Array substrate and display apparatus

Abstract

An array substrate, comprising a substrate, a first semiconductor layer, a first conductive layer and a plurality of touch leads. The first semiconductor layer is located on a side of the substrate; the first conductive layer is located on the side of the first semiconductor layer away from the substrate; the first conductive layer comprises a plurality of first signal lines; the plurality of touch leads are located on the side of the substrate close to the first semiconductor layer, the extension direction of the touch leads being parallel to the extension direction of the first signal lines; the orthographic projections of the touch leads on the substrate overlap the orthographic projections of the first signal lines on the substrate.

Description

Array substrate and display device

[0001] This application claims priority to Chinese patent application No. 202311625866.7, filed on November 30, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0003] With the continuous development of touch technology, its application in electronic products such as mobile phones, tablets, and laptops is becoming increasingly widespread. Generally, touch panels can be divided into capacitive, electromagnetic, resistive, and optical types. Capacitive touch panels can be divided into external touch panels (Add On Mode Touch Panel), on-cell touch panels (On Cell Touch Panel), and in-cell touch panels (In Cell Touch Panel). In-cell touch panels can integrate touch electrodes into the display screen, realizing both touch and display functions, thereby effectively reducing the thickness of the entire display device and simplifying the production process. Due to the characteristics of simple structure, light weight, and low cost, in-cell touch panels have gradually become the mainstream in the display field.

[0004] Summary of the Invention

[0005] In one aspect, an array substrate is provided. The array substrate comprises a substrate, a first semiconductor layer, a first conductive layer, and a plurality of touch leads. The first semiconductor layer is located on one side of the substrate. The first conductive layer is located on a side of the first semiconductor layer away from the substrate. The first conductive layer comprises a plurality of first signal lines. The plurality of touch leads are located on a side of the substrate closer to the first semiconductor layer. The touch leads extend in a direction parallel to the direction of the first signal lines. The orthographic projections of the touch leads on the substrate overlap with the orthographic projections of the first signal lines on the substrate.

[0006] In some embodiments, the array substrate also includes a second conductive layer, which is located between the substrate and the first semiconductor layer, and the touch lead is located in the second conductive layer; the first semiconductor layer also includes a plurality of active layer patterns, and the second conductive layer also includes a plurality of shading blocks, and the orthographic projection of the shading blocks on the substrate overlaps with the orthographic projection of the first active layer pattern on the substrate.

[0007] In some embodiments, the touch lead is connected to the light shielding block.

[0008] In some embodiments, the array substrate further comprises a plurality of touch electrodes. The plurality of touch electrodes are located on a side of the first conductive layer away from the substrate; the touch lead comprises a routing portion and a connecting portion connected to each other; the routing portion extends along a third direction, and the connecting portion is located on a side of the routing portion along a fourth direction; the third direction intersects the fourth direction; in an orthographic projection onto the substrate, the routing portion is located within the range of the first signal line, at least a portion of the connecting portion extends beyond the first signal line, and the touch electrode is connected to the portion of the connecting portion that extends beyond the first signal line.

[0009] In some embodiments, the array substrate further includes a first adapter block, at least one first insulating layer, and at least one second insulating layer. The first adapter block is located between the plurality of touch electrodes and the plurality of touch leads; the at least one first insulating layer is located between the touch electrodes and the first adapter block, and the at least one first insulating layer is provided with a second connection hole penetrating the at least one first insulating layer; the touch electrodes extend into the second connection hole and overlap with the first adapter block; the at least one second insulating layer is located between the first adapter block and the touch leads; the at least one second insulating layer is provided with a third connection hole penetrating the at least one second insulating layer, and the first adapter block extends into the third connection hole and overlaps with the portion of the connecting portion that extends beyond the first signal line.

[0010] In some embodiments, the first transfer block is located in the first conductive layer.

[0011] In some embodiments, the second conductive layer further includes a plurality of second gate lines; the array substrate further includes a second semiconductor layer, the second semiconductor layer being located between the second conductive layer and the substrate; the second semiconductor layer includes a plurality of second active layer patterns, the orthographic projection of the second active layer pattern on the substrate overlapping with the orthographic projection of the second gate lines on the substrate.

[0012] In some embodiments, the first semiconductor layer includes a plurality of first active layer patterns. The array substrate further includes a source driver circuit, a plurality of pixel electrodes, and a third conductive layer. The source driver circuit is located on a side of the substrate close to the first semiconductor layer; the first signal line is connected to the source driver circuit and the first active layer pattern; the plurality of pixel electrodes are located on a side of the first conductive layer away from the substrate; the third conductive layer is located between the first conductive layer and the plurality of pixel electrodes; the third conductive layer includes a plurality of second adapter blocks; the second adapter blocks are located between the pixel electrodes and the first active layer pattern and connect the pixel electrodes to the first active layer pattern; wherein the touch lead is located on the third conductive layer.

[0013] In some embodiments, the array substrate further includes a plurality of touch electrodes, which are located between the third conductive layer and the plurality of pixel electrodes; the orthographic projection of the touch lead on the substrate is located within the range of the orthographic projection of the first signal line on the substrate, and the touch lead is connected to the touch electrode.

[0014] In some embodiments, in an orthographic projection onto the substrate, at least one first signal line is provided between any two adjacent touch leads.

[0015] In some embodiments, in an orthographic projection onto the substrate, the plurality of first signal lines overlap with the plurality of touch leads in a one-to-one correspondence.

[0016] In some embodiments, a ratio of the resistivity of the touch wire to the thickness of the touch wire is less than or equal to 0.3.

[0017] In another aspect, a display device is provided. The display device comprises: an array substrate as described in any of the above embodiments, a color filter substrate, and a liquid crystal layer. The color filter substrate is disposed opposite the array substrate; the liquid crystal layer is located between the array substrate and the color filter substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0019] FIG1 is a structural diagram of a display device according to some embodiments;

[0020] FIG2 is a cross-sectional view along section line AA in FIG1 ;

[0021] FIG3 is a structural diagram of an array substrate according to some embodiments;

[0022] FIG4 is a partial enlarged view of B in FIG3 ;

[0023] FIG5 is a cross-sectional view along section line CC in FIG4 ;

[0024] FIG6 is another cross-sectional view along section line CC in FIG4 ;

[0025] FIG7 is another partial enlarged view of B in FIG3;

[0026] FIG8 is a cross-sectional view along section line DD in FIG7 ;

[0027] FIG9 is another partial enlarged view of B in FIG3 ;

[0028] FIG10 is a cross-sectional view along section line EE in FIG9 ;

[0029] FIG11 is another partial enlarged view of B in FIG3 ;

[0030] FIG12 is a cross-sectional view taken along section line FF in FIG11;

[0031] FIG. 13 is another structural diagram of an array substrate according to some embodiments. DETAILED DESCRIPTION

[0032] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0033] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0034] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0035] When describing some embodiments, the term "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the embodiments disclosed herein.

[0036] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0037] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0038] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0039] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0040] As used herein, “approximately” includes the stated value and an average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0041] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0042] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0043] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0044] An embodiment of the present disclosure provides a display device 1000. As shown in FIG1 , the display device 1000 can be any product or component with a display function, such as a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, or a car central control screen.

[0045] The display device 1000 may be a liquid crystal display (LCD), an organic light emitting display (OLED), a quantum dot light emitting display (QLED), a mini / micro light emitting display (MLED), or an active-matrix organic light emitting diode (AMOLED) display.

[0046] In the following embodiments, the display device 1000 is a liquid crystal display device as an example to schematically illustrate some embodiments of the present disclosure. However, the embodiments of the present disclosure are not limited thereto, and any other display device can also be considered as long as the same technical concept is applied.

[0047] As shown in FIG. 2 , the display device 1000 includes a housing 100 , a cover plate 200 , a liquid crystal display panel 300 , a backlight module 400 and a circuit board 500 .

[0048] As shown in FIG2 , the longitudinal cross-section of the housing 100 can be, for example, U-shaped. The liquid crystal display panel 300, the backlight module 400, and the circuit board 500 are located within the housing 100, and the cover plate 200 is disposed at the opening of the housing 100. The backlight module 400 is located on the side of the circuit board 500 that is close to the cover plate 200, and the liquid crystal display panel 300 is located on the side of the backlight module 400 that is close to the cover plate 200.

[0049] The backlight module 400 is used to provide backlight for the liquid crystal display panel 300 . The color of the backlight can be blue or white. The embodiment of the present disclosure does not impose any specific limitation on the color of the light emitted by the backlight module.

[0050] As shown in Figure 2, the liquid crystal display panel 300 includes an array substrate 10, a color filter substrate 20, a liquid crystal layer 30, and a sealant 40. The array substrate 10 and the color filter substrate 20 are arranged opposite each other, with the liquid crystal layer 30 located between them. The sealant 40 is located between the array substrate 10 and the color filter substrate 20 and surrounds the liquid crystal layer 30. The array substrate 10 and the color filter substrate 20 are bonded together by the sealant 40.

[0051] The color film substrate 20 may include a color filter. When the backlight provided by the backlight module 400 is blue light, the color filter may include a red filter portion, a green filter portion, and a blue filter portion. The red filter portion allows only red light in the incident light to pass through, the green filter portion allows only green light in the incident light to pass through, and the blue filter portion allows only blue light in the incident light to pass through. When the backlight provided by the backlight module 400 is blue light, the color filter may include a red filter portion and a green filter portion.

[0052] As shown in FIG3 , the array substrate 10 includes a display area AA and a peripheral area BB. The peripheral area BB is located on at least one side of the display area AA. FIG3 illustrates an example where the peripheral area BB surrounds the display area AA. The peripheral area BB can be used, for example, to provide a scan driver circuit, control signal lines (such as clock signal lines and power supply voltage signal lines), and a source driver circuit (SD). However, the functions of the peripheral area BB are not limited to these.

[0053] In some embodiments, as shown in FIG. 3 , FIG. 4 and FIG. 5 , the array substrate 10 includes a substrate 11 , a driving circuit stack 12 , and a plurality of touch electrodes 13 .

[0054] As shown in FIG5 , the substrate 11 may be a single-layer structure or a multi-layer structure. For example, in the case of a multi-layer structure, the substrate 11 may include a base 111 and a buffer layer 112 disposed on the base 111. The buffer layer 112 is disposed on the base 111. The material used for the buffer layer 112 may include inorganic insulating materials such as silicon nitride (SiNx, x>0), silicon oxynitride (SiON), and silicon oxide (SiOx, x>0). The buffer layer 112 is used to provide a good foundation for the formation of thin films when thin films are formed on the substrate 11. In the case of a single-layer structure, the material of the substrate 11 may include glass, sapphire, or silicon.

[0055] In some embodiments, as shown in Figures 3, 4, and 5, the driving circuit stack 12 includes a plurality of pixel circuits 121. As shown in Figure 3, the plurality of pixel circuits 121 are located in the display area AA. The plurality of pixel circuits 121 are arranged in multiple rows and columns. Each row of pixel circuits 121 includes a plurality of pixel circuits 121 spaced apart along a first direction X, and the plurality of rows of pixel circuits 121 are arranged along a second direction Y. Each column of pixel circuits 121 includes a plurality of pixel circuits 121 arranged along a second direction Y, and the plurality of columns of pixel circuits 121 are arranged along the first direction X. In other words, the first direction X is the row direction in which the plurality of pixel circuits 121 are arranged, and the second direction Y is the column direction in which the plurality of pixel circuits 121 are arranged. The first direction X and the second direction Y intersect with each other. For example, the first direction X and the second direction Y are perpendicular to each other.

[0056] As shown in FIG3 , the driving circuit stack 12 further includes a plurality of data lines 123 and a plurality of first gate lines 124. The plurality of data lines 123 and the plurality of first gate lines 124 are located in the display area AA. The plurality of data lines 123 extend along the second direction Y and are spaced apart along the first direction X. As shown in FIG5 , one data line 123 is connected to a row of pixel circuits 121.

[0057] As shown in FIG3 , the driver circuit stack 12 further includes a source driver circuit 125. The source driver circuit 125 is located in the peripheral area BB and on one side of the display area AA. For example, the source driver circuit 125 can be located above, below, to the left, or to the right of the display area AA. FIG3 illustrates an example where the source driver circuit 125 is located above the display area AA. Multiple data lines 123 (all data lines 123) are connected to the source driver circuit 125.

[0058] As shown in FIG3 , a plurality of first gate lines 124 extend along a first direction X and are arranged at intervals along a second direction Y. As shown in FIG5 , one first gate line 124 is connected to a column of pixel circuits 121 .

[0059] Based on the above structure, as shown in FIG. 3 , the plurality of data lines 123 and the plurality of first gate lines 124 divide the display area AA into a plurality of sub-pixel areas 110 .

[0060] As shown in FIG3 , multiple touch electrodes 13 are located in the display area AA and on the side of the drive circuit stack 12 away from the substrate 11. The multiple touch electrodes 13 are arranged in multiple rows and columns. Each row of touch electrodes 13 includes multiple touch electrodes 13 spaced apart in a first direction X, and the multiple rows of touch electrodes 13 are arranged along a second direction Y. Each column of touch electrodes 13 includes multiple touch electrodes 13 arranged along the second direction Y, and the multiple columns of touch electrodes 13 are arranged along the first direction X.

[0061] As shown in Figure 3, a plurality of sub-pixel regions 110 correspond to one touch electrode 13. For example, five, ten, or twenty pixel electrodes correspond to one touch electrode 13, which are not listed one by one in the embodiments of the present disclosure.

[0062] The correspondence between the plurality of sub-pixel regions 110 and one touch electrode 13 may mean that the plurality of sub-pixel regions 110 are located within the outer boundary of the orthographic projection of the touch electrode 13 on the substrate 11 .

[0063] As shown in FIG3 , the array substrate 10 further includes a touch chip 14. The touch chip 14 is disposed on the substrate 11 and is located in the peripheral area BB and on one side of the display area AA. The touch chip 14 can be located above, below, to the left, or to the right of the display area AA. FIG3 illustrates an example where the touch chip 14 is located below the display area AA.

[0064] The touch chip 14 is connected to the touch electrodes 13 (all touch electrodes 13). The touch chip 14 transmits touch drive signals to the touch electrodes 13 and receives feedback signals from the touch electrodes 13. The chip analyzes the feedback signals to determine whether the touch electrodes 13 are touched, thereby realizing the touch function.

[0065] As shown in Figure 3, the array substrate 10 also includes multiple touch leads 15, one end of the touch lead 15 is connected to a touch electrode 13, and the other end is connected to the touch chip 14. In this way, the touch chip can apply a touch drive signal to the touch electrode 13 through the touch lead 15.

[0066] The array substrate 10 further includes a first conductive layer 16. The first conductive layer 16 includes a plurality of first signal lines 161, which are configured to transmit signals (eg, data signals, scan signals, VDD signals, VSS signals).

[0067] In related art, the touch lead and the first signal line are made of the same material and are arranged in the same layer. When the first signal line is configured to transmit data signals or scan signals, the touch lead is located within the sub-pixel area, and the touch lead occupies part of the sub-pixel area, resulting in a reduction in the light-transmitting area of ​​the sub-pixel area, which in turn reduces the brightness of the liquid crystal display panel. When the first signal line is configured to transmit VDD or VSS signals, the touch lead and the first signal line are both located within the sub-pixel area, and both occupy part of the sub-pixel area, resulting in a reduction in the light-transmitting area of ​​the sub-pixel area.

[0068] To address the aforementioned technical issues, some embodiments of the present disclosure provide touch leads 15 disposed on a substrate 11, with the touch leads 15 extending parallel to the first signal lines 161. The orthographic projection of the touch leads 15 on the substrate 11 overlaps with the orthographic projection of the first signal lines 161 on the substrate 11.

[0069] In this manner, the overlapping portion of the touch lead 15 and the first signal line 161 does not repeatedly occupy or does not occupy the sub-pixel area 110 , thereby increasing the light-transmitting area of ​​the sub-pixel area 110 and further improving the brightness of the liquid crystal display panel 300 .

[0070] Exemplarily, the orthographic projection of the touch lead 15 on the substrate 11 is located within the range of the orthographic projection of the first signal line 161 on the substrate 11 .

[0071] In this manner, the touch leads 15 do not repeatedly occupy or do not occupy the sub-pixel area 110 , thereby increasing the light-transmitting area of ​​the sub-pixel area 110 and further improving the brightness of the liquid crystal display panel 300 .

[0072] In some embodiments, the driving circuit stack 12 includes a first semiconductor layer ACT1 , a first conductive layer 16 , and a first source-drain conductive layer SD1 , which are sequentially arranged in a direction perpendicular to the substrate 11 and away from the substrate 11 .

[0073] The first gate line 124 is located in the first conductive layer 16, that is, the first signal line 161 is the first gate line 124, and the data line 123 is located in the first source-drain conductive layer SD1. The touch lead 15 extends along the first direction X, and the orthographic projection of the touch lead 15 on the substrate 11 overlaps with the orthographic projection of the first gate line 124 on the substrate 11.

[0074] In this manner, the overlapping portion of the touch lead 15 and the first gate line 124 does not need to occupy the sub-pixel region 110 , thereby increasing the light-transmitting area of ​​the sub-pixel region 110 and further improving the brightness of the liquid crystal display panel 300 .

[0075] It can be understood that the driving circuit stack 12 also includes an insulating film layer located between the first semiconductor layer ACT1, the first conductive layer 16, the first source and drain conductive layer SD1 and the touch electrode 13. For example, the driving circuit stack 12 also includes a second gate insulating layer GI2 located between the first semiconductor layer ACT1 and the first conductive layer 16, a second interlayer dielectric layer ILD2 located between the first conductive layer 16 and the first source and drain conductive layer SD1, and a planarization layer PLN located between the first source and drain conductive layer SD1 and the touch electrode 13.

[0076] In other embodiments, as shown in FIG. 5 , the driving circuit stack 12 includes a first semiconductor layer ACT1 , a first gate conductive layer GT1 , and a first conductive layer 16 , which are sequentially arranged in a direction perpendicular to and away from the substrate 11 .

[0077] The first gate line 124 is located in the first gate conductive layer GT1, and the data line 123 is located in the first conductive layer 16, that is, the first signal line 161 is the data line 123, and the touch lead 15 extends along the second direction Y. The orthographic projection of the touch lead 15 on the substrate 11 overlaps with the orthographic projection of the data line 123 on the substrate 11.

[0078] In this manner, the portion overlapping with the orthographic projection of the data line 123 does not need to occupy the area of ​​the sub-pixel region 110 , thereby increasing the light-transmitting area of ​​the sub-pixel region 110 and further improving the brightness of the liquid crystal display panel 300 .

[0079] It can be understood that the driving circuit stack 12 also includes an insulating film layer located between the first semiconductor layer ACT1, the first gate conductive layer GT1, the first conductive layer 16 and the touch electrode 13. For example, the driving circuit stack 12 also includes a second gate insulating layer GI2 located between the first semiconductor layer ACT1 and the first gate conductive layer GT1, a second interlayer dielectric layer ILD2 located between the first gate conductive layer GT1 and the first conductive layer 16, and a planarization layer PLN located between the first conductive layer 16 and the touch electrode 13.

[0080] In the following embodiments, some embodiments of the present disclosure are schematically described by taking the first signal line 161 as the data line 123. However, the embodiments of the present disclosure are not limited thereto, and any other signal lines may also be considered as long as the same technical concept is applied.

[0081] In some embodiments, as shown in FIG5 , the array substrate 10 further includes a second conductive layer 17 . The second conductive layer 17 is located between the substrate 11 and the first semiconductor layer ACT1 . The touch wires 15 are located in the second conductive layer 17 .

[0082] In this way, the touch lead 15 and the first signal line 161 can be arranged in different layers, and the orthographic projection of the touch lead 15 on the substrate 11 overlaps with the orthographic projection of the first signal line 161 on the substrate 11. The part overlapping with the orthographic projection of the first signal line 161 does not need to occupy the area of ​​the sub-pixel area 110, thereby increasing the light-transmitting area of ​​the sub-pixel area 110, thereby improving the brightness of the liquid crystal display panel 300.

[0083] It is understandable that, in order to electrically insulate the second conductive layer 17 from the first gate conductive layer GT1 , the driving circuit stack 12 further includes a first interlayer dielectric layer ILD1 , which is located between the second conductive layer 17 and the first gate conductive layer GT1 .

[0084] In some examples, the first semiconductor layer ACT1 further includes a plurality of active layer patterns 1, which are active layer patterns of the pixel circuit 121. The second conductive layer 17 further includes a plurality of light shielding blocks 171, the orthographic projections of the light shielding blocks 171 on the substrate 11 overlapping with the orthographic projections of the first active layer patterns 1 on the substrate 11. This configuration can alleviate the problem of light from the substrate 11 striking the active layer patterns 1, causing the threshold voltage of the first thin film transistor 1211 to shift.

[0085] It will be understood that the pixel circuit 121 further includes a first gate electrode 2, a first source electrode 3, and a first drain electrode 4. The first source electrode 3 and the first drain electrode 4 may be structurally identical and thus interchangeable. A first gate line 124 orthographically overlaps with the first active layer pattern 1 in a row of first thin-film transistors 1211 on the substrate 11, and the portion of the first gate line 124 that orthographically overlaps with the first active layer pattern 1 forms the first gate electrode 2. A data line 123 orthographically overlaps with the first active layer pattern 1 in a column of first thin-film transistors 1211 on the substrate 11, and the portion of the data line 123 that orthographically overlaps with the first active layer pattern 1 forms the first source electrode 3.

[0086] Exemplarily, the first thin film transistor 1211 may be an oxide thin film transistor, i.e., the material of the active layer pattern 1 in the first thin film transistor 1211 includes an oxide material, for example, the material of the active layer pattern 1 includes indium gallium zinc oxide or indium gallium tin oxide. Alternatively, the first thin film transistor 1211 may be a low-temperature polysilicon thin film transistor, i.e., the material of the active layer pattern 1 in the first thin film transistor 1211 includes a low-temperature polysilicon material, for example, the material of the active layer pattern 1 includes oxygenated polysilicon.

[0087] In some embodiments, the touch lead 15 includes a connected routing portion 151 and a connecting portion 152. The routing portion 151 extends along the third direction, and the connecting portion 152 is located on one side of the routing portion 151 along the fourth direction. In an orthographic projection onto the substrate 11, the routing portion 151 is located within the range of the first signal line 161, and at least a portion of the connecting portion 152 extends beyond the first signal line 161. The third direction intersects the fourth direction. Exemplarily, the third direction and the fourth direction are perpendicular. As shown in FIG5 , the third direction is substantially parallel to the second direction Y, and the fourth direction is substantially parallel to the first direction X. That is, the routing portion 151 extends along the second direction Y, and the connecting portion 152 is located on one side of the routing portion 151 along the first direction X. Exemplarily, the connecting portion 152 is located on the left or right side of the routing portion 151. FIG5 illustrates the example of the connecting portion 152 being located on the left side of the routing portion 151.

[0088] Illustratively, in an orthographic projection onto the substrate 11 , the routing portion 151 completely overlaps with the first signal line 161 , and the connecting portion 152 completely extends beyond the first signal line 161 .

[0089] In some embodiments, as shown in FIG5 , the array substrate 10 further includes a first insulating laminate 101. The first insulating laminate 101 is located between the plurality of touch electrodes 13 and the plurality of touch leads 15. The first insulating laminate 101 is provided with a first connection hole 1011 that penetrates the first insulating laminate 101. The touch electrodes 13 extend into the first connection hole 1011 and overlap with the portion of the connecting portion 152 that extends beyond the first signal line 161. That is, the touch electrodes 13 and the touch leads 15 are connected through the first connection hole 1011.

[0090] When the driving circuit stack 12 includes a first interlayer dielectric layer ILD1, a second gate insulation layer GI2, a second interlayer dielectric layer ILD1 and a planarization layer PLN arranged in sequence perpendicular to the substrate 11 and away from the substrate 11, the first insulating stack 101 includes a first interlayer dielectric layer ILD1, a second gate insulation layer GI2, a second interlayer dielectric layer ILD2 and a planarization layer PLN arranged in a stacked manner.

[0091] It should be noted that the processes for forming vias in inorganic and organic insulating layers differ. The first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the second interlayer dielectric layer ILD2 are inorganic insulating layers, while the planarization layer PLN is an organic insulating layer. In other words, the first insulating layer stack 101 includes both organic and inorganic insulating film layers. Therefore, two drilling operations are required to form the first connection hole 1011 in the first insulating layer stack 101.

[0092] 6 , the array substrate 10 further includes a first adapter block 18 , at least one first insulating layer 102 , and at least one second insulating layer 103 . The first adapter block 18 is located between the touch electrodes 13 and the touch leads 15 .

[0093] At least one first insulating layer 102 (all first insulating layers 102 ) is located between the touch electrode 13 and the first adapter block 18 . At least one first insulating layer 102 is provided with a second connection hole 1021 penetrating at least one first insulating layer 102 . The touch electrode 13 extends into the second connection hole 1021 and overlaps with the first adapter block 18 .

[0094] At least one second insulating layer 103 (all second insulating layers 103) is located between the first adapter block 18 and the touch lead 15. At least one second insulating layer 103 is provided with a third connection hole 1031 that penetrates at least one second insulating layer 103. The first adapter block 18 extends into the third connection hole 1031 and overlaps with the portion of the connecting portion 152 that extends beyond the first signal line 161.

[0095] In this manner, the first adapter block 18 can reduce the depth of a single via hole when connecting the touch electrode 13 and the touch lead 15 , thereby improving the connection stability between the touch electrode 13 and the touch lead 15 and reducing the difficulty of manufacturing the via hole.

[0096] When the driving circuit stack 12 includes a second conductive layer 17, a first interlayer dielectric layer ILD1, a first semiconductor layer ACT1, a second gate insulation layer GI2, a first gate conductive layer GT1, a second interlayer dielectric layer ILD2, a first conductive layer 16 and a planarization layer PLN, which are arranged in sequence perpendicular to the substrate 11 and away from the substrate 11, the first transfer block 18 can be located in the first gate conductive layer GT1 or in the first conductive layer 16.

[0097] In some examples, the first transfer block 18 is located in the first gate conductive layer GT1. In this case, the at least one first insulating layer 102 includes a second interlayer dielectric layer ILD2 and a planarization layer PLN. The at least one second insulating layer 103 includes a first interlayer dielectric layer ILD1 and a second gate insulating layer GI2.

[0098] It should be noted that the processes for forming vias in inorganic and organic insulating layers differ. The first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the second interlayer dielectric layer ILD2 are inorganic insulating layers, while the planarization layer PLN is an organic insulating layer. In other words, at least one first insulating layer 102 comprises both an organic and an inorganic insulating film layer. Therefore, two drillings are required to form the second connection hole 1021 in the at least one first insulating layer 102. At least one second insulating layer 103 comprises only an inorganic insulating film layer. Therefore, a single drilling is required to form the third connection hole 1031 in the at least one second insulating layer 103.

[0099] 6 , the first transfer block 18 is located in the first conductive layer 16 , and the at least one first insulating layer 102 includes a planarization layer PLN. The at least one second insulating layer 103 includes a first interlayer dielectric layer ILD1 , a second gate insulating layer GI2 , and a second interlayer dielectric layer ILD2 .

[0100] It should be noted that the processes for forming vias in inorganic and organic insulating layers differ. The first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the second interlayer dielectric layer ILD2 are inorganic insulating layers, while the planarization layer PLN is an organic insulating layer. That is, at least one first insulating layer 102 comprises only an organic insulating film layer. Therefore, a single drilling operation can form the second connection hole 1021 in the at least one first insulating layer 102. At least one second insulating layer 103 comprises only an inorganic insulating film layer. Therefore, a single drilling operation can form the third connection hole 1031 in the at least one second insulating layer 103.

[0101] As shown in Figure 6, on the basis that the array substrate 10 includes the first adapter block 18, the second connection hole 1021 and the third connection hole 1031 are coaxially arranged. In this way, the size of the portion of the first adapter block 18 that exceeds the first signal line 161 can be reduced, thereby reducing the area occupied by the first adapter block 18 in the sub-pixel area 110, further increasing the light-transmitting area of ​​the sub-pixel area 110, thereby increasing the brightness of the liquid crystal display panel 300.

[0102] In some embodiments, the second conductive layer 17 includes the touch leads 15 and the light shielding block 171 , as shown in FIG. 7 and FIG. 8 , and the touch leads 15 and the light shielding block 171 are connected.

[0103] Setting it in this way can improve the problem that the light-shielding block 171 is a floating electrode, which leads to a large difference in parasitic capacitance between multiple light-shielding blocks 171 and the first active layer pattern 1, and reduce the risk of a large difference in threshold voltage shift of multiple first thin film transistors 1211 due to a large difference in parasitic capacitance between the first active layer patterns 1.

[0104] In some examples, as shown in Figures 7 and 8 , in an orthographic projection onto the substrate 11, the connection portion 152 is located to the left of the routing portion 151, and the pixel circuit 121 corresponding to the routing portion 151 is located to the right of the routing portion 151. Along the second direction Y, the connection portion 152 and the pixel circuit 121 corresponding to the routing portion 151 are arranged in pairs. The pixel circuit 121 corresponding to the routing portion 151 is the pixel circuit 121 connected to the data line 123 that overlaps with the orthographic projection of the routing portion 151.

[0105] In this case, the touch lead 15 is connected to the light shielding block 171, eliminating the gap between the touch lead 15 and the light shielding block 171, allowing the pixel circuit 121 to be closer to the data line 123. Without changing the distance between two adjacent data lines 123, the pixel circuit 121 being closer to the data line 123 can increase the spacing between the connection portion 152 and the pixel circuit 121 in the same sub-pixel region 110, thereby increasing the size of the connection portion 152. This, in turn, helps increase the facing area between the connection portion 152 and the touch electrode 13, increasing the contact area between the connection portion 152 and the touch electrode 13, and improving the reliability and stability of the connection between the connection portion 152 and the touch electrode 13. Alternatively, without changing the size of the connection portion 152, the pixel circuit 121 being closer to the data line can reduce the distance between two adjacent data lines 123, thereby reducing the size of the sub-pixel region 110 along the second direction Y, thereby improving the pixel resolution of the liquid crystal display panel 300.

[0106] In some embodiments, as shown in FIG. 3 and FIG. 5 , the driving circuit stack further includes a scan driving circuit 122 , and a plurality of first gate lines 124 (all first gate lines 124 ) are connected to the scan driving circuit 122 .

[0107] As shown in Figure 5 , the scan driver circuit 122 is located in the peripheral area BB and on one side of the display area AA. The scan driver circuit 122 can be located on at least one of the upper, lower, left, and right sides of the display area AA. Figure 3 illustrates the scan driver circuit 122 being located on the left side of the display area AA. The scan driver circuit 122 includes a second thin-film transistor 1221, which includes a second active layer pattern 5, a second gate 6, a second source electrode 7, and a second drain electrode 8. The second source electrode 7 and the second drain electrode 8 can be structurally identical and therefore interchangeable.

[0108] Exemplarily, the second conductive layer 17 further includes a plurality of second gate lines. The driving circuit stack 12 further includes a second semiconductor layer ACT2, which is located between the second conductive layer 17 and the substrate 11. The second semiconductor layer includes a plurality of second active layer patterns. The orthographic projections of the second active layer patterns on the substrate 11 overlap with the orthographic projections of the second gate lines on the substrate. The portion of the second gate lines that overlaps with the orthographic projections of the second active layer patterns 5 is the second gate 6.

[0109] In some embodiments, as shown in FIG5 , when the driving circuit stack 12 includes a first thin film transistor 1211 and a second thin film transistor 1221 , the first thin film transistor 1211 may be an oxide thin film transistor, and the second thin film transistor 1221 may be a low-temperature polysilicon thin film transistor.

[0110] Based on the advantages of low-temperature polysilicon thin-film transistors such as high mobility and fast charging, and the advantages of oxide thin-film transistors such as low leakage current, low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on an array substrate 10 to utilize the advantages of both, which can reduce the power consumption of the array substrate 10 and improve the display quality of the liquid crystal display panel 300.

[0111] In some embodiments, as shown in Figures 9, 10, 11, and 12, the driving circuit stack 12 further includes a third conductive layer 19, which is located between the first conductive layer 16 and the plurality of touch electrodes 13. The third conductive layer 19 includes a plurality of second adapter blocks 191. The orthographic projections of the second adapter blocks 191 on the substrate 11 overlap with the first active layer pattern 1 on the substrate 11, and the second adapter blocks 191 are connected to the first active layer pattern 1, that is, the second adapter blocks 191 form the first drain 4.

[0112] In this case, the distance between the orthographic projection of the second adapter block 191 on the substrate 11 and the orthographic projection of the data line 123 on the substrate 11 can be less than the minimum limit value of the exposure process (for example, the exposure accuracy value of the exposure machine, an example exposure accuracy value is 5μm), so that the size of the first active layer pattern 1 between the second adapter block 191 and the data line 123 can be smaller, the size of the first thin film transistor 1211 can be reduced, and the pixel resolution of the liquid crystal display panel 300 can be increased.

[0113] In some embodiments, as shown in FIG. 10 and FIG. 12 , the touch wires 15 are located in the third conductive layer 19 .

[0114] In this way, the touch lead 15 and the first signal line 161 can be arranged in different layers, and the orthographic projection of the touch lead 15 on the substrate 11 overlaps with the orthographic projection of the first signal line 161 on the substrate 11, thereby improving the brightness of the liquid crystal display panel 300.

[0115] In some embodiments, as shown in FIG12 , on the basis that the touch lead 15 is located in the third conductive layer 19 , the orthographic projection of the touch lead 15 on the substrate 11 is located within the range of the orthographic projection of the first signal line 161 on the substrate 11 , and the touch lead 15 is connected to the touch electrode 13 .

[0116] In this case, the touch lead 15 does not include the connecting portion 152 , which can further increase the light-transmitting area of ​​the sub-pixel region 110 and improve the brightness of the liquid crystal display panel 300 .

[0117] It is understandable that, in order to electrically insulate the first conductive layer 16 from the third conductive layer 19 , the driving circuit stack 12 further includes a third interlayer dielectric layer ILD3 , which is located between the first conductive layer 16 and the third conductive layer 19 .

[0118] In some embodiments, as shown in Figure 12, the array substrate 10 also includes at least one third insulating layer 104 (all third insulating layers 104), at least one third insulating layer 104 is located between the touch lead 15 and the touch electrode 13, and at least one third insulating layer 104 is provided with a fourth connection hole 1041 that penetrates at least one third insulating layer 104, and the touch electrode 13 extends into the fourth connection hole 1041 and is connected to the touch lead 15.

[0119] For example, when the driving circuit stack 12 includes the first conductive layer 16 , the third interlayer dielectric layer ILD2 , the third conductive layer 19 and the planarization layer PLN, the at least one third insulating layer 104 includes the planarization layer PLN.

[0120] It should be noted that the processes for forming vias in inorganic and organic insulating layers differ. The planarization layer PLN is an organic insulating layer, meaning that at least one third insulating layer 104 comprises only an organic insulating layer. Therefore, the fourth connection hole 1041 can be formed by drilling the at least one third insulating layer 104 in a single pass.

[0121] In some embodiments, one touch electrode 13 may be connected to a plurality of touch leads 15 or may be connected to one touch lead 15 .

[0122] In some examples, a touch electrode 13 is connected to multiple touch leads 15. In this way, even if one of the multiple touch leads 15 connected to a touch electrode 13 fails, the touch chip 14 can still transmit touch signals to the touch electrode 13 through other touch leads 15, which can increase the stability of the touch chip 14 transmitting touch signals to the touch electrode 13.

[0123] In other examples, one touch electrode 13 is connected to one touch lead 15. This arrangement can increase the number of touch electrodes 13 and reduce the size of the touch electrodes 13, thereby improving the touch performance of the liquid crystal display device.

[0124] In some embodiments, as shown in FIG3 , at least one first signal line 161 is provided between any two adjacent touch leads 15 in an orthographic projection onto the substrate 11. For example, one, three, or five first signal lines 161 may be provided between any two adjacent touch leads 15, and these are not listed in detail in the embodiments of the present disclosure.

[0125] Illustratively, in an orthographic projection onto the substrate 11 , two first signal lines 161 are provided between any two adjacent touch leads 15 .

[0126] In some other implementations, as shown in FIG. 13 , in an orthographic projection onto the substrate 11 , the plurality of first signal lines 161 overlap with the plurality of touch leads in a one-to-one correspondence.

[0127] In this way, the number of touch leads 15 and the number of first signal lines 161 can increase the number of touch electrodes 13 , reduce the size of the touch electrodes 13 , and further improve the touch performance of the display device 1000 .

[0128] In some embodiments, the ratio of the resistivity of the touch wire 15 to the thickness of the touch wire 15 is less than or equal to 0.3. This configuration can reduce the resistance of the touch wire 15 and thereby reduce the voltage drop across the touch wire 15.

[0129] In some embodiments, the touch electrodes 13 are multiplexed as common electrodes, and in this case, the touch leads 15 are multiplexed as common electrode leads. The touch chip 14 may be a touch and display driver integration (TDDI) chip.

[0130] On this basis, as shown in Figures 3 and 5, the array substrate 10 further includes a plurality of pixel electrodes 22. The plurality of pixel electrodes 22 are located in the display area AA and on the side of the touch electrode 13 away from the substrate 11. The plurality of pixel electrodes 22 are arranged in multiple rows and columns. Each row of pixel electrodes 22 includes a plurality of pixel electrodes 22 arranged at intervals in a first direction X, and the plurality of rows of pixel electrodes 22 are arranged along a second direction Y. Each column of pixel electrodes 22 includes a plurality of pixel electrodes 22 arranged along the second direction Y, and the plurality of columns of pixel electrodes 22 are arranged along the first direction X.

[0131] A pixel electrode 22 is located in a sub-pixel region 110 and is connected to the drain of a first thin film transistor 1211 . In this way, the source driving circuit 125 is used to provide a data signal to the pixel electrode 22 through the data line 123 .

[0132] 5 , the array substrate 10 further includes a passivation layer PVX, which is located between the plurality of pixel electrodes 22 and the plurality of touch electrodes 13. In this manner, the passivation layer PVX can insulate the touch electrodes 13 from the pixel electrodes 22.

[0133] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0134] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: substrate; A first semiconductor layer, located on one side of the substrate; A first conductive layer is located on a side of the first semiconductor layer away from the substrate; the first conductive layer includes a plurality of first signal lines; A plurality of touch control leads are located on a side of the substrate close to the first semiconductor layer; an extending direction of the touch control leads is parallel to an extending direction of the first signal lines; The orthographic projection of the touch lead on the substrate overlaps with the orthographic projection of the first signal line on the substrate.

2. The array substrate according to claim 1, further comprising: A second conductive layer, located between the substrate and the first semiconductor layer, wherein the touch control lead is located in the second conductive layer; The first semiconductor layer further includes a plurality of active layer patterns, and the second conductive layer further includes a plurality of light shielding blocks, wherein the orthographic projections of the light shielding blocks on the substrate overlap with the orthographic projections of the first active layer patterns on the substrate.

3. The array substrate according to claim 2, wherein: The touch lead is connected to the light shielding block.

4. The array substrate according to claim 1, further comprising: A plurality of touch electrodes are located on a side of the first conductive layer away from the substrate; The touch lead comprises a wiring portion and a connecting portion connected to each other; the wiring portion extends along a third direction, and the connecting portion is located at one side of the wiring portion along a fourth direction; the third direction intersects with the fourth direction; In an orthographic projection onto the substrate, the routing portion is located within the range of the first signal line, at least a portion of the connecting portion exceeds the first signal line, and the touch electrode is connected to a portion of the connecting portion exceeding the first signal line.

5. The array substrate according to claim 4, further comprising: The first insulating layer is located between the plurality of touch electrodes and the plurality of touch leads. The first insulating layer is provided with a first connecting hole penetrating the first insulating layer. The touch electrode extends into the first connecting hole and overlaps with a portion of the connecting portion that exceeds the first signal line.

6. The array substrate according to claim 5, further comprising: A first adapter block is located between the plurality of touch electrodes and the plurality of touch leads; At least one first insulating layer is located between the touch electrode and the first adapter block, and the at least one first insulating layer is provided with a second connecting hole penetrating the at least one first insulating layer; the touch electrode extends into the second connecting hole and overlaps with the first adapter block; At least one second insulating layer is located between the first adapter block and the touch lead; the at least one second insulating layer is provided with a third connecting hole penetrating the at least one second insulating layer, and the first adapter block extends into the third connecting hole and overlaps with the portion of the connecting portion that exceeds the first signal line. 7 . The array substrate according to claim 6 , wherein the first adapter block is located on the first conductive layer.

8. The array substrate according to any one of claims 1 to 7, wherein: The second conductive layer further comprises a plurality of second gate lines; The array substrate further includes: The second semiconductor layer is located between the second conductive layer and the substrate; the second semiconductor layer includes a plurality of second active layer patterns, and the orthographic projection of the second active layer patterns on the substrate overlaps with the orthographic projection of the second gate line on the substrate.

9. The array substrate according to claim 1, wherein: The first semiconductor layer includes a plurality of first active layer patterns; The array substrate further includes: A source driving circuit is located on a side of the substrate close to the first semiconductor layer; the first signal line is connected to the source driving circuit and the first active layer pattern; A plurality of pixel electrodes are located on a side of the first conductive layer away from the substrate; The third conductive layer is located between the first conductive layer and the plurality of pixel electrodes; the touch lead is located in the third conductive layer, and the third conductive layer includes a plurality of second adapter blocks; the second adapter block is located between the pixel electrode and the first active layer pattern, and connects the pixel electrode and the first active layer pattern.

10. The array substrate according to claim 9, further comprising: A plurality of touch electrodes, located between the third conductive layer and the plurality of pixel electrodes; The orthographic projection of the touch control lead on the substrate is located within the range of the orthographic projection of the first signal line on the substrate, and the touch control lead is connected to the touch control electrode.

11. The array substrate according to any one of claims 1 to 10, wherein: In the orthographic projection onto the substrate, at least one first signal line is disposed between any two adjacent touch control leads.

12. The array substrate according to claim 11, wherein: In the orthographic projection onto the substrate, two first signal lines are disposed between any two adjacent touch control leads.

13. The array substrate according to any one of claims 1 to 10, wherein: In an orthographic projection onto the substrate, the plurality of first signal lines overlap with the plurality of touch control leads in a one-to-one correspondence.

14. The array substrate according to any one of claims 1 to 13, wherein: A ratio of the resistivity of the touch wire to the thickness of the touch wire is less than or equal to 0.

3.

15. A display device, comprising: The array substrate according to any one of claims 1 to 14; A color filter substrate, arranged opposite to the array substrate; The liquid crystal layer is located between the array substrate and the color filter substrate.

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