Resolver processing circuit and method, and chip and electronic device

Abstract

A resolver processing circuit (200), comprising: an adjustment module (201), which is used for adjusting a first symbol and outputting a first codeword, wherein the first symbol is a symbol of a digital codeword corresponding to a sensing signal, and the sensing signal is generated by secondary windings (1022, 1023) of a resolver module on the basis of a sinusoidal excitation signal; an accumulation module (202), which is used for performing accumulation on the first codeword and determining a second codeword corresponding to an envelope signal; and an angle calculation module (203), which is used for determining angle information on the basis of the second codeword. Angle information can be accurately estimated with relatively low hardware costs and relatively low calculation capability requirements. Further disclosed are a resolver processing method, a chip and an electronic device.

Description

Resolver processing circuit, method, chip and electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 30, 2023, with application number 202311635641.X and invention name “Resolutionary Transformer Processing Circuit, Method, Chip and Electronic Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic technology, and in particular to a resolver processing circuit, method, chip, and electronic device. Background Art

[0003] A resolver is an electromagnetic sensor used to measure the angular displacement and angular velocity of a rotating object. It can be used in a variety of position and velocity feedback applications. In industrial applications, resolvers are widely used in servo control systems, industrial robots, and AC variable frequency drives. In automotive applications, resolvers are widely used in traction inverters and power steering systems in electric and hybrid vehicles.

[0004] A resolver has a primary side and a secondary side. A sinusoidal alternating voltage is applied to the primary side, generating an AC voltage of the same frequency on the secondary side. Angle information is obtained by decoding the AC voltage on the secondary side. A resolver decoder that provides accurate angle estimation with low hardware cost and / or low computing power requirements is needed in the art. Technical issues

[0005] Embodiments of the present application provide a resolver processing circuit, method, chip, and electronic device, which provide a resolver decoder for accurately estimating angles with lower hardware cost and / or lower computing power requirements. Technical Solutions

[0006] The technical solution of this application is as follows:

[0007] In a first aspect, an embodiment of the present application provides a resolver processing circuit, including:

[0008] An adjustment module is configured to adjust a first symbol and output a first codeword, wherein the first symbol is a digital codeword corresponding to a sensing signal generated by a secondary winding of a rotary transformer module according to a sinusoidal excitation signal; an accumulation module is configured to accumulate the first codeword and determine a second codeword corresponding to an envelope signal; and an angle calculation module is configured to determine angle information based on the second codeword.

[0009] In a second aspect, an embodiment of the present application further provides a chip comprising the above-mentioned resolver processing circuit.

[0010] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a device body and a chip as described above disposed in the device body.

[0011] In a fourth aspect, an embodiment of the present application also provides a resolver processing method, including: adjusting a first symbol and outputting a first codeword, wherein the first symbol is a symbol of a digital codeword corresponding to an induction signal, and the induction signal is generated by the secondary winding of the resolver module according to a sinusoidal excitation signal; accumulating the first codeword and determining a second codeword corresponding to the envelope signal; and determining angle information based on the second codeword. Beneficial effects

[0012] The resolver processing circuit, method, chip, and electronic device provided in the embodiments of the present application adjust the sign of the digital codeword corresponding to the sensing signal to obtain a first codeword, accumulate this first codeword, and determine a second codeword corresponding to the envelope signal. This is equivalent to accumulating multiple digital samples of the sensing signal from the secondary winding to obtain the second codeword corresponding to the envelope signal, and determining angle information based on this second codeword. This resolver processing circuit eliminates the need for complex electronic components and accurately estimates angle information with low hardware cost and computing power requirements.

[0013] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0015] FIG1 shows a schematic block diagram of a motor system provided in an embodiment of the present application.

[0016] FIG2 shows a schematic block diagram of an exemplary rotary transformer provided in an embodiment of the present application.

[0017] FIG3 shows a schematic block diagram of a resolver processing circuit provided in an embodiment of the present application.

[0018] FIG4A shows a schematic diagram of symbol adjustment (method 1) provided in an embodiment of the present application.

[0019] FIG4B shows a schematic diagram of the symbol adjustment (method 2) provided in an embodiment of the present application.

[0020] FIG5 shows a schematic block diagram of a portion of a motor system provided in an embodiment of the present application.

[0021] FIG6 shows a schematic block diagram of a resolver processing circuit provided in an embodiment of the present application.

[0022] 7A and 7B respectively show a schematic block diagram of an analog-to-digital conversion module and an analog-to-digital conversion module.

[0023] FIG8 shows an exemplary timing diagram for performing analog-to-digital conversion.

[0024] FIG9 shows a schematic block diagram of a differential amplifier module provided in an embodiment of the present application.

[0025] FIG10 is a schematic diagram showing signal waveforms of various nodes of the differential amplification provided in an embodiment of the present application.

[0026] FIG11 shows a schematic block diagram of a differential amplification module provided in an embodiment of the present application.

[0027] FIG12 shows a schematic diagram of an excitation PWM signal.

[0028] FIG13 shows a schematic block diagram of a circuit for generating the first control signal SIGN-C.

[0029] FIG. 14 shows the relationship between the generation of the first control signal SIGN-C and the PWM pulses and their counts.

[0030] FIG15 shows a flow chart of a resolver processing method provided in an embodiment of the present application.

[0031] Implementation Methods of the Application

[0032] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0033] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0034] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0035] Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0036] In the description of the embodiments of this application, words such as "example" or "for example" are used to indicate an example, illustration, or description. Any embodiment or design described as "for example" or "for example" in the embodiments of this application is not to be construed as being preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to clearly present relative concepts.

[0037] In addition, in the embodiments of the present application, "plurality" refers to two or more. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two, or more. For example, "including at least one" means including one, two, or more, and does not limit which ones are included. For example, "including at least one of A, B, and C" means including A, B, C, A and B, A and C, B and C, or A, B, and C.

[0038] It should be noted that in the embodiments of the present application, "and / or" describes the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects are in an "or" relationship.

[0039] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0040] The first electrode / first end of each transistor used in the embodiments of the present application is one of the source and the drain, and the second electrode / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable, that is, the first electrode / first end and the second electrode / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode / first end of the transistor is the source, and the second electrode / second end is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode / first end of the transistor is the drain, and the second electrode / second end is the source.

[0041] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual components, but represent the junction points of related couplings in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0042] A resolver is an electromagnetic sensor used to measure the angular displacement and angular velocity of a rotating object. It can be used in a variety of position and velocity feedback applications. In industrial applications, resolvers are widely used in servo control systems, industrial robots, and AC variable frequency drives. In automotive applications, resolvers are widely used in traction inverters and power steering systems in electric and hybrid vehicles.

[0043] The resolver processing circuit of the embodiment of the present application can be applied to the motor system 100 shown in FIG1 . As shown in FIG1 , the motor system 100 may include a motor 101 , a resolver 102 , an excitation circuit 103 , a motor drive circuit 106 , and a resolver processing circuit 200 .

[0044] For example, the motor 101 may be a three-phase motor. The motor 101 may be driven by a motor drive circuit 106, which may include a drive circuit that provides a drive voltage to the motor 101. For example, the motor drive circuit 106 may include three parallel drive circuits, each drive circuit being configured to drive one of the three phases of the motor 101. The motor drive circuit 106 may be controlled by a central processing unit (CPU) 105.

[0045] In some embodiments, the rotary transformer 102 may include a primary winding and a secondary winding. For example, as shown in FIG2 , the rotary transformer 102 may include a primary winding 1021 and a first secondary winding 1022 and a second secondary winding 1023. The primary winding 1021 may include an excitation coil, and the first secondary winding 1022 and the second secondary winding 1023 may include two secondary coils perpendicular to each other. As shown in FIG2 , the primary winding 1021 includes a positive phase input terminal exc+ and a negative phase input terminal exc-. For example, in the case where the first secondary winding 1022 generates a sinusoidal induction signal and the second secondary winding generates a cosine induction signal, the first secondary winding 1022 includes a positive phase output terminal sin+ and a negative phase output terminal sin-, and the second secondary winding 1023 includes a positive phase output terminal cos+ and a negative phase output terminal cos-.

[0046] In some embodiments, as shown in FIG1 , motor system 100 may include an excitation circuit 103 connected to a rotary transformer 102. Excitation circuit 103 generates a sinusoidal excitation signal, and a secondary winding of rotary transformer 102 generates an induction signal based on the sinusoidal excitation signal. Exemplarily, excitation circuit 103 may include an H-bridge.

[0047] As shown in Figures 1 and 2 , primary winding 1021 is connected to excitation circuit 103. When a sinusoidal excitation signal generated by excitation circuit 103 is applied to primary winding 1021, a first induction signal 107A is induced in first secondary winding 1022, and a second induction signal 107B is induced in second secondary winding 1023. First induction signal 107A and second induction signal 107B vary as the shaft of motor 101 rotates.

[0048] In this embodiment, the outer envelope of the first sensing signal 107A (i.e., the first envelope signal) and the outer envelope of the second sensing signal 107B (i.e., the second envelope signal) can be extracted, and the angle information of the rotating shaft of the motor 101 can be determined based on the extracted first envelope signal and second envelope signal. The derivation process is as follows:

[0049] Assuming the sinusoidal excitation signal is: V = Vs * sin(ωt), then the first sensing signal 107A can be expressed as: Vα = Vs * sin(ωt) * sin(θ), and the second sensing signal 107B can be expressed as: Vβ = Vs * sin(ωt) * cos(θ), where θ is the angle of the rotating shaft. Since Vβ / Vɑ = tan(θ), θ = arctan(Vβ / Vɑ).

[0050] An embodiment of the present application provides a resolver processing circuit, which is described in this specification in conjunction with a motor system 100 .

[0051] As shown in Figure 3, resolver processing circuit 200 includes an adjustment module 201, an accumulation module 202, and an angle calculation module 203. Adjustment module 201 adjusts a first symbol and outputs a first codeword. The first symbol is a digital codeword corresponding to a sensing signal generated by the resolver module's secondary winding in response to a sinusoidal excitation signal. Accumulation module 202 accumulates the first codeword output by adjustment module 201 and determines a second codeword corresponding to the envelope signal. Angle calculation module 203 determines angle information based on this second codeword.

[0052] Through the embodiments of the present application, the sign of the digital codeword corresponding to the sensing signal is adjusted to obtain a first codeword, which is then accumulated to determine a second codeword corresponding to the envelope signal. This is equivalent to accumulating multiple digital samples of the sensing signal from the secondary winding to obtain the second codeword corresponding to the envelope signal, and then determining the angle information based on the second codeword. This eliminates the need for complex electronic components and allows for accurate angle estimation with low hardware cost and computing power requirements.

[0053] An exemplary implementation of adjusting the first symbol and outputting the first codeword is described below.

[0054] In the first approach, the adjustment module 201 can adjust the first symbol and obtain the first codeword based on the first control signal SING-C and the second control signal SING-S. The first control signal SIGN-C is used to indicate the positive and negative cycle information of the induced signal corresponding to the sinusoidal excitation signal, and the second control signal SING-S is used to indicate the positive and negative information of the second symbol of the envelope signal.

[0055] For example, as shown in FIG4A , when the second sign is positive, the second control signal SING-S is at a first level (shown as a high level in FIG4A ); when the second sign is negative, the second control signal SING-S is at a second level (shown as a low level in FIG4A ). When the sensing signal corresponds to the positive half-cycle of the sinusoidal excitation signal, the first control signal SIGN-C is at a first level (shown as a high level in FIG4A ); when the sensing signal corresponds to the negative half-cycle of the sinusoidal excitation signal, the first control signal SIGN-C is at a second level (shown as a low level in FIG4A ).

[0056] As an embodiment, adjusting the sign of the digital signal according to the first control signal SING-C and the second control signal SING-S to obtain a digital output may include:

[0057] If the sensing signal corresponds to the positive half-cycle of the sinusoidal excitation signal (the first control signal SIGN-C is high) and the second sign is negative (the second control signal SING-S is low), the first sign is flipped. As shown in Figure 4A, for the sensing signal in interval a, the first sign of the digital codeword corresponding to the sensing signal before flipping is positive, and the first sign of the digital codeword corresponding to the sensing signal after flipping is negative, and the sign of the output first codeword is negative.

[0058] If the sensing signal corresponds to the positive half-cycle of the sinusoidal excitation signal (the first control signal SIGN-C is high) and the second sign is positive (the second control signal SING-S is high), the first sign remains unchanged. As shown in Figure 4A, for the sensing signal in interval b, the first sign remains positive, and the sign of the output first codeword is positive.

[0059] If the sensing signal corresponds to the negative half-cycle of the sinusoidal excitation signal (the first control signal SIGN-C is low) and the second sign is positive (the second control signal SING-S is high), the first sign is flipped. As shown in Figure 4A, for the sensing signal in interval c, the first sign of the digital codeword corresponding to the sensing signal before the flip is negative, and the first sign of the digital codeword corresponding to the sensing signal after the flip is positive, and the sign of the output first codeword is positive.

[0060] If the sensing signal corresponds to the negative half-cycle of the sinusoidal excitation signal (the first control signal SIGN-C is at a low level) and the second sign is negative (the second control signal SING-S is at a low level), the first sign corresponding to the sensing signal remains unchanged. As shown in Figure 4A, for the sensing signal within interval d, the first sign of the digital codeword corresponding to the sensing signal remains negative, and the sign of the output first codeword is negative.

[0061] Through method 1, the first sign of the adjusted first codeword is consistent with the second sign of the second codeword corresponding to the envelope signal. The sign of the second codeword determined by accumulating the first codeword is the second sign corresponding to the envelope signal. As shown in Figure 4A, in intervals b and c, the sign of the actual outer envelope is positive, and the sign of the extracted outer envelope (second codeword) is also positive, that is, the sign of the second codeword is consistent with the second sign corresponding to the envelope signal.

[0062] Exemplarily, as shown in FIG4A , the first codewords (with positive signs) in interval b and / or interval c are accumulated to determine that the sign of the obtained second codeword is positive, and the sign of the second codeword is consistent with the second sign corresponding to the envelope signal. For example, as shown in FIG4A , the sensing signals in area b and area c are sampled and converted to obtain 8 digital codewords, 4 digital codewords in area b and 4 digital codewords in area c. Before adjustment: the first signs of the 4 digital codewords b1, b2, b3 and b4 in area b are positive, and the first signs of the two digital codewords c1, c2, c3 and c4 in area c are negative. After adjustment according to method 1: the signs of the 4 first codewords Db1, Db2, Db3 and Db4 corresponding to area b are positive, and the signs of the 4 first codewords Dc1, Dc2, Dc3 and Dc4 corresponding to area c are positive. Accumulate the first codewords Db1, Db2, Db3, and Db4 and at least some of the first codewords Dc1, Dc2, Dc3, and Dc4 to determine that the sign of the obtained second codeword is positive. The sign of the second codeword is consistent with the second sign corresponding to the envelope signal, that is, the signs of the second codeword and the envelope signal are both positive.

[0063] Exemplarily, the first codewords (with negative signs) in interval d and / or interval a are accumulated, and the sign of the determined second codeword is negative, and the sign of the second codeword is consistent with the second sign corresponding to the envelope signal. For example, as shown in FIG4A , the sensing signals in area d and area a are sampled and converted to obtain 8 digital codewords, 4 digital codewords in area d and 4 digital codewords in area a. Before adjustment: the first signs of the 4 digital codewords d1, d2, d3 and d4 in area d are negative, and the first signs of the 4 digital codewords a1, a2, a3 and a4 in area a are positive. After adjustment according to method 1: the signs of the 4 first codewords Dd1, Dd2, Dd3 and Dd4 corresponding to area d are negative, and the signs of the 4 first codewords Da1, Da2, Da1 and Da2 corresponding to area a are negative. Accumulate at least some of the first code words Da1, Da2, Da1 and Da2, and Dd1, Dd2, Dd3 and Dd4, and determine that the sign of the obtained second code word is negative. The sign of the second code word is consistent with the second sign of the envelope signal, that is, the signs of the second code word and the envelope signal are both negative.

[0064] In the first approach, the angle calculation module 203 may use the symbol of the second codeword as the second symbol of the envelope signal.

[0065] It should be understood that FIG4A shows the case of a sinusoidal sensing signal, and the cosine sensing signal is similar to this, which will not be described in detail in the embodiment of the present application.

[0066] In the second approach, the adjustment module 201 may adjust the first symbol according to the first control signal SIGN-C and obtain the first codeword.

[0067] Exemplarily, adjusting the first symbol and outputting the first codeword according to the first control signal SIGN-C includes:

[0068] If the sensing signal corresponds to the positive half-cycle of the sinusoidal excitation signal (the first control signal SIGN-C is at a high level), the first sign remains unchanged. For example, as shown in FIG4B , for the sensing signal in interval b, the first control signal SIGN-C is at a high level, the first sign remains positive, and the sign of the output first codeword is positive.

[0069] If the sensing signal corresponds to the negative half-cycle of the sinusoidal excitation signal (the first control signal SIGN-C is at a low level), the first sign is flipped. For example, as shown in FIG4B , for the sensing signal within interval c, the first control signal SIGN-C is at a low level. The first sign of the digital codeword corresponding to the sensing signal before the flip is negative, and the sign of the first codeword output after the flip is positive.

[0070] Unlike Method 1, Method 2 uses the same adjustment method as for intervals b and c for the sensing signals within intervals a and d. Specifically, as shown in FIG4B , for the sensing signal within interval d, which corresponds to the negative half-cycle of the sinusoidal excitation signal (the first control signal SIGN-C is at a low level), the first sign of the digital codeword corresponding to the sensing signal before flipping is negative, and the sign of the first codeword output after flipping is positive. For the sensing signal within interval a, the first sign remains unchanged, and the output first codeword remains positive. As shown in FIG4B , when the actual outer envelope is positive, the extracted outer envelope is positive; when the actual outer envelope is negative, the extracted outer envelope is positive. That is, the outer envelope extracted by Method 2 is a steamed bun wave.

[0071] In the second method, the accumulation module 201 accumulates the first codewords and determines the second codeword. The sign of the second codeword does not represent the second sign of the envelope signal. For example, the signs of the second codewords determined by accumulating the first codewords in interval a and / or interval d are all positive, while the second signs of the envelope signals in intervals a and d are negative. To this end, in the second method, the angle calculation module 203 can determine the second sign corresponding to the envelope signal based on the second control signal SING-S and determine the angle information based on the second codeword and the second sign.

[0072] 5 , the resolver processing circuit 200 may further include a second control module 204. The second control module 204 is configured to flip the second symbol of the envelope signal based on the second codeword and generate a second control signal SING-S based on the second symbol.

[0073] 5 , in the aforementioned approach 1, the second control module 204 may send the second control signal SIGN-S to the accumulation module 202 ; in the aforementioned approach 2, the second control module 204 may send the second control signal SIGN-S to the angle calculation module 203 .

[0074] As an implementation, the second control module 204 may flip the second symbol when the absolute value of the second codeword changes from greater than a preset flip threshold to less than the preset flip threshold, and from less than the preset flip threshold to greater than the preset flip threshold.

[0075] For example, as shown in FIG4A , for one cycle of the sinusoidal sensing signal (first sensing signal 107A), the second sign of the envelope signal is positive when the angle is from 0 to π, and negative when the angle is from π to 2π. The second sign is initialized to positive, and the second control signal SING-S is initialized to a high level. During the angle change from 0 to π, the second codeword is greater than 0 and first increases and then decreases. When the absolute value of the second codeword changes from greater than a preset flip threshold to less than the preset flip threshold, it can be considered that the angle is about to reach π. The second sign is flipped, that is, the second sign flips from positive to negative, and the second control signal SING-S flips from a high level to a low level, forming a falling edge. During the angle change from π to 2π, the second codeword is less than 0 and first decreases and then increases. When the absolute value of the second codeword changes from less than the preset flip threshold to greater than the preset flip threshold, it can be considered that the angle is about to reach 2π. The second sign is flipped, that is, the second sign flips from negative to positive, and the second control signal SING-S flips from a low level to a high level, forming a rising edge.

[0076] As an embodiment, the accumulation module 202 can accumulate the first codewords corresponding to N half-waves of the sinusoidal excitation signal and determine the second codeword corresponding to the envelope signal, where N is a positive integer. Exemplarily, N can be 1, that is, the first codeword corresponding to one half-wave is accumulated. With reference to Figures 4A and 4B, the first codeword corresponding to intervals a, b, c, or d is accumulated. Exemplarily, N can be 2, that is, the first codeword corresponding to two half-waves (i.e., one full-wave) is accumulated. With reference to Figures 4A and 4B, the first codeword corresponding to intervals a and d is accumulated, or the first codeword corresponding to intervals b and c is accumulated.

[0077] In one embodiment, accumulation module 202 is configured to output a second codeword based on a third control signal, where the third control signal is configured to indicate the start and end information of N half-waves. The second codeword is the accumulated value of the first codewords corresponding to the N half-waves. As an example, the third control signal can be generated based on the first control signal SIGN-C. For example, as shown in Figures 4A and 4B, when N is 1, the third control signal is consistent with the first control signal SIGN-C, and the rising and falling edges of the first control signal SIGN-C indicate the start and end information of a half-wave. When N is 2, the rising edge of the first control signal SIGN-C indicates the start and end information of two half-waves. Similar behavior occurs for other values ​​of N.

[0078] As an embodiment, the angle calculation module 203 may include an inverse tangent module, which may perform an inverse tangent operation and determine the angle based on the tangent value. The inverse tangent operation is sign-dependent, and the second codeword and the second sign of its envelope signal serve as inputs to the inverse tangent operation. The period of the tangent function is π, and the inverse tangent operation can determine -π / 2 to π / 2. Optionally, the angle information may be further determined by combining the second sign of the sine sensing signal and the second sign of the cosine sensing signal. When determining the second sign of the envelope signal and the amplitude of the envelope signal, the angle may be determined using methods in related art, which will not be described in detail in this embodiment.

[0079] In some embodiments, as shown in FIG5 , the resolver processing circuit 200 may further include a first control module 205. The first control module 205 is configured to generate a first control signal SIGN-C based on a count of generated PWM pulses in a PWM pulse sequence, wherein the PWM pulse sequence is configured to generate a sinusoidal excitation signal.

[0080] For example, one sinusoidal excitation signal cycle corresponds to a PWM pulse sequence consisting of 18 PWM pulses, each PWM pulse having a specific different duty cycle. Sequentially generating the PWM pulses in the PWM pulse sequence can generate a sinusoidal excitation signal cycle. When nine PWM pulses have been generated, the positive half of the sinusoidal excitation signal cycle ends. Thus, a second control signal, SIGN-C, can be generated based on the number of PWM pulses generated in the PWM pulse sequence. For example, when the first PWM pulse in the PWM pulse sequence begins to be generated, the second control signal, SIGN-C, can be at a first level (e.g., a high level). After nine PWM pulses have been generated, the second control signal, SIGN-C, flips to a second level (e.g., a low level).

[0081] In some embodiments, as shown in FIG5 , the resolver processing circuit 200 may further include an analog-to-digital conversion module 207. The analog-to-digital conversion module 207 may perform analog-to-digital conversion on the sensing signal of the secondary winding of the resolver 102 to obtain a corresponding digital codeword. The output of the analog-to-digital conversion module 207 is a digital signal, including a first digital codeword 108A corresponding to the first sensing signal 107A (first secondary winding 1022 ) and a second digital codeword 108B corresponding to the second sensing signal 107B (second secondary winding 1023 ).

[0082] In this embodiment, the analog-to-digital conversion module 207 may include various types of analog-to-digital converters, for example, a SAR ADC. The SAR ADC has the characteristics of low power consumption, high resolution, high precision, and small size, and can be integrated with other larger functions.

[0083] The adjustment module 201 may adjust the first sign of the first digital codeword 108A and output the first codeword 109A corresponding to the first sensing signal 107A, and adjust the first sign of the second digital codeword 108B and output the first codeword 109B corresponding to the second sensing signal 107B.

[0084] The accumulation module 202 may accumulate the first codeword 109A corresponding to the first sensing signal 107A and determine the second codeword 110A corresponding to the first envelope signal corresponding to the first sensing signal 107A, and accumulate a preset number of second first codewords 109B and determine the second codeword 110B corresponding to the second envelope signal corresponding to the second sensing signal 107B.

[0085] FIG6 illustrates a resolver processing circuit according to an embodiment of the present application. As shown in FIG6 , the analog-to-digital conversion module 207 may include a first analog-to-digital conversion module 207A and a second analog-to-digital conversion module 207B. The first analog-to-digital conversion module 207A is configured to perform analog-to-digital conversion on a first sensing signal 107A from a first secondary winding 1022 of the resolver 102 and output a first digital codeword 108A. The second analog-to-digital conversion module 207B is configured to perform analog-to-digital conversion on a second sensing signal 107B from a second secondary winding 1023 of the resolver 102 and output a second digital codeword 108B.

[0086] As an implementation manner, the first analog-to-digital conversion module 207A and the second analog-to-digital conversion module 207B perform analog-to-digital conversion on the positive phase and negative phase of the sensing signal respectively to obtain a positive phase result and a negative phase result, and determine a digital codeword of the sensing signal based on the positive phase result and the negative phase result.

[0087] 7A and 7B respectively show exemplary structures of the first analog-to-digital conversion module 207A and the second analog-to-digital conversion module 207B.

[0088] As shown in FIG7A , the first analog-to-digital conversion module 207A includes: a first analog-to-digital conversion unit 610A, configured to perform analog-to-digital conversion on the positive phase of the first sensing signal 107A during a first period, and write the converted positive phase result into a first register DR61; perform analog-to-digital conversion on the negative phase of the first sensing signal 107A during a second period, and write the converted negative phase result into a second register DR62, thereby generating a first trigger signal; and a first calculation unit 620A, configured to read the positive phase result and the negative phase result from the first register DR61 and the second register DR62 according to the first trigger signal, and determine a first digital codeword of the first sensing signal 107A based on the positive phase result and the negative phase result, thereby obtaining the first digital codeword. For example, the first calculation unit 620A may be a subtractor.

[0089] As shown in FIG7B , the second analog-to-digital conversion module 207B includes: a second analog-to-digital conversion unit 610B, configured to perform analog-to-digital conversion on the positive phase of the second sensing signal 107B during a first period, and write the converted positive phase result into the third register DR63; perform analog-to-digital conversion on the negative phase of the second sensing signal 107B during a second period, and write the converted negative phase result into the fourth register DR64, and generate a second trigger signal; and a second calculation unit 620B, configured to read the positive phase result and the negative phase result from the third register DR63 and the fourth register DR64 according to the second trigger signal, and determine the second digital codeword of the second sensing signal 107B based on the positive phase result and the negative phase result, thereby obtaining the second digital codeword. For example, the second calculation unit 620B may be a subtractor.

[0090] As an implementation, the first analog-to-digital conversion module 207A and the second analog-to-digital conversion module 207B may start analog-to-digital conversion at the zero point of a PWM pulse, wherein the PWM pulse belongs to a PWM pulse sequence for generating a sinusoidal excitation signal.

[0091] For example, FIG8 illustrates an exemplary timing sequence for analog-to-digital conversion performed by the first analog-to-digital conversion module 207A and the second analog-to-digital conversion module 207B. As shown in FIG8 , at the zero point of the PWM pulse, a rising edge signal (shown as the rising edge of signal ADC_START in FIG8 ) is generated. During period 1, analog-to-digital conversion is performed on the positive phase, and the converted positive phase result is stored in register DR0. During period 2, analog-to-digital conversion is performed on the negative phase, and the converted negative phase result is stored in register DR1. After the conversion is completed, a falling edge signal (shown as the falling edge of signal ADC_START in FIG8 ) is generated, which serves as a trigger signal, trigger. In response to this trigger signal, a subtractor, subtractor sub, reads the positive phase result from register DR0 and the negative phase result from register DR1, and performs a subtraction operation on the positive and negative phase results to obtain the digital codeword of the sensing signal.

[0092] As an embodiment, as shown in FIG7A , the first analog-to-digital conversion module 207A may further include: a first multiplexing unit 630A, connected to the first analog-to-digital conversion unit 610A, configured to output a positive phase of the first sensing signal 107A during the first period, and output a negative phase of the first sensing signal 107A during the second period.

[0093] For example, the first multiplexer 630A can be controlled to perform multiplexing. For example, during a first period, the first channel of the first multiplexer 630A can be enabled to output the positive phase of the first sensing signal 107A to the first analog-to-digital conversion unit 610A. During or after the analog-to-digital conversion of the positive phase of the first sensing signal 107A, the second channel of the first multiplexer 630A can be enabled to output the negative phase of the first sensing signal 107A to the first analog-to-digital conversion unit 610A.

[0094] As an embodiment, as shown in FIG7B , the second analog-to-digital conversion module 207B may further include: a second multiplexer 630B connected to the second analog-to-digital conversion unit 610B, configured to output a positive phase of the second sensing signal 107B during the first period, and output a negative phase of the second sensing signal 107B during the second period.

[0095] Exemplarily, the second multiplexer 630B can be controlled to perform multiplexing. For example, during the first period, the first channel of the second multiplexer 630B can be enabled to output the positive phase of the second sensing signal 107B to the second analog-to-digital conversion unit 610B. During or after the analog-to-digital conversion of the positive phase of the second sensing signal 107B, the second channel of the second multiplexer 630B can be enabled to output the negative phase of the received second sensing signal 107B to the second analog-to-digital conversion unit 610B.

[0096] In some embodiments, as shown in FIG5 , the resolver processing circuit 200 may further include a differential amplifier module 208. The differential amplifier module 208 is connected to the analog-to-digital conversion module 207 and is configured to differentially amplify the positive and negative phases of the sensing signal, and to ensure that the median values ​​of the positive and negative phases of the sensing signal are both a preset voltage.

[0097] As an embodiment, as shown in FIG6 , the differential amplifier module 208 may include a first differential amplifier module 208A and a second differential amplifier module 208B. The first differential amplifier module 208A is connected to the first analog-to-digital conversion module 207A and is configured to differentially amplify the positive and negative phases of the first sensing signal 107A, and to ensure that the median values ​​of the positive and negative phases of the first sensing signal 107A are both a first preset voltage. The second differential amplifier module 208B is connected to the second analog-to-digital conversion module 207B and is configured to differentially amplify the positive and negative phases of the second sensing signal 107B, and to ensure that the median values ​​of the positive and negative phases of the second sensing signal 107B are both a second preset voltage. Exemplarily, the first differential amplifier module 208A and the second differential amplifier module 208B may include programmable gain amplifiers or operational amplifiers.

[0098] For example, taking the first sensing signal 107A as a sinusoidal sensing signal, the first differential amplifier module 208A differentially amplifies the positive phase (Vsin+) and the negative phase (Vsin-) of the first sensing signal 107A, and makes the median values ​​of the positive phase and the negative phase of the first sensing signal 107A both equal to the first preset voltage.

[0099] The voltage value of the first sensing signal 107A is the difference between the positive phase and the negative phase. The first differential amplifier module 208A differentially amplifies the positive phase (Vsin+) and the negative phase (Vsin-) of the first sensing signal 107A, that is, amplifies the voltage value of the first sensing signal 107A. The second sensing signal 107B is similar to the first sensing signal 107A.

[0100] As an implementation, the first differential amplifier module 208A and the second differential amplifier module 208B can employ the circuit structure shown in FIG9 . As shown in FIG9 , the operational amplifier (OPA) acts as a voltage follower and can output a voltage of 1 / 2*VDD, which serves as the DC bias voltage for the positive and negative inputs of the fully differential programmable gain amplifier (PGA). The fully differential programmable gain amplifier (PGA) amplifies the input differential signal. As shown in FIG9 , the signal received at the positive input of the fully differential programmable gain amplifier (PGA) is represented as Vin_p, the signal received at the negative input is represented as Vin_n, the signal at the positive output is represented as Vop_diff, and the signal at the negative output is represented as Von_diff. Assuming the input signal is a sinusoidal wave with an amplitude of A and the gain of the fully differential programmable gain amplifier (PGA) is G, the output voltage waveforms at various points of the fully differential programmable gain amplifier (PGA) are shown in FIG10 .

[0101] As shown in FIG9 , the signal Vop_diff at the positive output terminal and the signal Von_diff at the negative output terminal of the fully differential programmable gain amplifier PGA enter a multiplexer (MUX). The multiplexer MUX is connected to an analog-to-digital converter (ADC). The analog-to-digital converter performs analog-to-digital conversion on the signal Vop_diff at the positive output terminal and the signal Von_diff at the negative output terminal.

[0102] As an embodiment, as shown in FIG6 , the resolver processing circuit 200 may include: a first adjustment module 201A (also referred to as a first adjustment unit) and a second adjustment module 201B (also referred to as a second adjustment unit). The first adjustment module 201A may perform sign adjustment on the first digital codeword output by the first analog-to-digital conversion module 207A, and output a first codeword 109A corresponding to the first sensing signal. Exemplarily, the first adjustment module 201A may perform sign adjustment using the aforementioned method 1 or method 2. The second adjustment module 201B may perform sign adjustment on the second digital codeword output by the second analog-to-digital conversion module 207B, and output a first codeword 109B corresponding to the second sensing signal. Exemplarily, the second adjustment module 201B may perform sign adjustment using the aforementioned method 1 or method 2.

[0103] As an embodiment, as shown in FIG6 , the resolver processing circuit 200 may include a first accumulation module 202A (also referred to as a first accumulation unit) and a second accumulation module 202B (also referred to as a second accumulation unit). The first accumulation module 202A is connected to the first adjustment module 201A and can accumulate the first codeword 109A corresponding to the first sensing signal and determine the second codeword 110A corresponding to the first envelope signal corresponding to the first sensing signal. The second accumulation module 202B is connected to the second adjustment module 201A and can accumulate the first codeword 109B corresponding to the second sensing signal and determine the second codeword 110B corresponding to the second envelope signal corresponding to the second sensing signal.

[0104] For example, taking the first sensing signal 107A as a sinusoidal sensing signal, the first differential amplifier module 208A amplifies the positive and negative phases of the sinusoidal sensing signal, and sets the median of the positive and negative phases of the sinusoidal sensing signal to a preset voltage. The first analog-to-digital conversion module 207A performs analog-to-digital conversion on the positive and negative phases of the amplified sinusoidal sensing signal to obtain positive and negative phase results, and calculates a first digital codeword based on the positive and negative phase results. The first adjustment module 201A performs sign adjustment on the first digital codeword to obtain a first codeword. The first accumulation module 202A accumulates the first codeword and determines a second codeword corresponding to the sinusoidal envelope signal corresponding to the sinusoidal sensing signal.

[0105] For example, taking the second sensing signal 107B as a cosine sensing signal, the second differential amplification module 208B amplifies the positive and negative phases of the cosine sensing signal, and sets the median of the positive and negative phases of the cosine sensing signal to a preset voltage. The second analog-to-digital conversion module 207B performs analog-to-digital conversion on the amplified positive and negative phases of the cosine sensing signal to obtain positive and negative phase results, and calculates a second digital codeword based on the positive and negative phase results. The second adjustment module 201B performs sign adjustment on the second digital codeword to obtain a first codeword. The second accumulation module 202B accumulates the first codeword and determines a second codeword corresponding to the cosine envelope signal corresponding to the cosine sensing signal.

[0106] In some embodiments, as shown in FIG5 , the resolver processing circuit 200 may further include a resolver drive module 206. As an implementation, the resolver drive module 206 may generate an excitation PWM signal, and the excitation circuit 103 shown in FIG1 may generate a sinusoidal excitation signal based on the excitation PWM signal. Exemplarily, the excitation PWM signal includes a PWM pulse sequence, and the excitation circuit 103 may generate a sinusoidal excitation signal based on the PWM pulse sequence, with one PWM pulse sequence corresponding to one period of the sinusoidal excitation signal.

[0107] As an embodiment, as shown in FIG10 , the resolver drive module 206 may include a storage unit 2061, a direct memory access unit (DMA) 2062, and a signal generating unit 2063. The storage unit 2061 is used to store the duty cycle data of each PWM pulse in the PWM pulse sequence. The direct memory access unit 2062 is used to transmit the duty cycle data of each PWM pulse from the storage unit 2061 to the signal generating unit 2063. The signal generating unit 2063 is used to generate a PWM pulse based on the duty cycle data of the PWM pulse. This embodiment can load the duty cycle data stored in the storage unit into the signal generating unit 2063 without the involvement of the CPU, so that the signal generating unit 2063 forms PWM pulses with different duty cycles.

[0108] Optionally, the zero point of the PWM counter serves as a trigger signal for data transmission of the direct memory access unit 2062 . When the zero point of the PWM counter arrives, the direct memory access unit 2062 loads the next duty cycle data in the storage unit 2061 into the signal generating unit 2063 .

[0109] For example, taking the resolver drive module 206 driving the H-bridge (excitation circuit 103) as an example, as shown in Figure 12, the resolver drive module 206 can generate 4 PWM pulses, namely PWM0, PWM1, PWM2 and PWM3. As shown in Figure 12, PWM0 and PWM1 are complementary and symmetrical, and PWM2 and PWM3 are complementary and symmetrical.

[0110] For example, the resolver drive module 206 can generate two complementary PWM pulses without dead zones, and the excitation circuit 103 can convert one PWM output into two complementary symmetrical PWM pulses with dead zones, thereby converting the two PWM pulses generated by the resolver drive module 206 into four PWM pulses as shown in FIG12 .

[0111] As an embodiment, the first control module 205 shown in Figure 4 can generate the first control signal SIGN-C according to the count of the generated PWM pulses in the PWM pulse sequence.

[0112] As shown in Figure 13, the first control module 205 may include: a first comparison unit 2051, used to receive the count value DMACNT of the generated PWM pulse, compare the count value DMACNT with a first counting threshold and output a first comparison output, wherein the first counting threshold corresponds to half a cycle of the sinusoidal excitation signal; a second comparison unit 2052, used to receive the count value DMACNT of the generated PWM pulse, compare the count value DMACNT with a second counting threshold to obtain a second comparison output, wherein the second counting threshold corresponds to one cycle of the sinusoidal excitation signal; and an output unit 2053, used to generate a first control signal SIGN-C based on the first comparison output and the second comparison output.

[0113] As an implementation, the output unit 2053 may flip the first control signal SIGN-C when the first comparison output indicates that the count value DMACNT is equal to the first count threshold, or when the second comparison output indicates that the count value DMACNT is equal to the second count threshold.

[0114] As an implementation manner, as shown in FIG. 11 , the direct memory access unit 2062 may count the duty cycle data and output the count value DMACNT.

[0115] As an example, as shown in FIG13 , the direct memory access unit 2062 is configured in a cyclic mode, and the initial value of the DMA counter is the number of PWM pulses corresponding to a period of a sinusoidal excitation signal. Each time a DMA transfer occurs, the value of the DMA counter is reduced by 1. When the value of the DMA counter is reduced to 0, it is automatically loaded to the initial value, and this cycle repeats.

[0116] As an example, the PWM counter's zero point serves as a trigger condition for DMA transfer. That is, when the PWM counter reaches zero point, the direct memory access unit 2062 loads the next duty cycle data from the storage unit 2061 into the signal generation unit 2063 (the PWM duty cycle register in FIG13 ). The PWM counter can be set to either edge counting mode or center-aligned mode. In this embodiment, the edge counting mode is used as an example.

[0117] The first counting threshold of the first comparing unit 2051 and the second counting threshold of the second comparing unit 2052 can be configured according to the number of PWM pulses corresponding to a period of a sinusoidal excitation signal.

[0118] For example, assuming that a sinusoidal excitation signal consists of 18 PWM pulses, with 9 PWM pulses in the positive half cycle and 9 PWM pulses in the negative half cycle, then duty cycle data for a total of 18 PWM pulses is stored in the storage unit 2061 (shown as duty 1 to duty 18 stored in the RAM in FIG13 ). The first counting threshold and the second counting threshold are 7 and 16, respectively.

[0119] As shown in Figure 14, the initial value of the count value DMACNT (stored in the transfer count register in Figure 13) is 18. When the PWM counter reaches zero, duty1 is passed to the signal generation unit, and the count value DMACNT becomes 17. After the next PWM zero point arrives, duty2 is passed to the signal generation unit (the PWM duty cycle register in Figure 13), and the count value DMACNT becomes 16. At this time, the PWM corresponding to duty1 begins to take effect and is output.

[0120] When the count value DMACNT is equal to 7, the two input signals of the first comparison unit 2051 (count value DMACNTA1, first count threshold B1) match, and the output signal of the first comparison unit 2051 is pulled high. At this time, the output signal of the second comparison unit 2052 is still low, and is pulled high to a high level after the output of the OR gate, thereby triggering the flip circuit to flip the level of the first control signal SIGN-C (high level to low level), indicating the start of the negative half cycle of the sinusoidal excitation signal.

[0121] When the count value DMACNT is equal to 6, the two input signals (A1, B1) of the first comparison unit 2051 do not match, and the output signal of the first comparison unit 2051 becomes low. At this time, the output signal of the second comparison unit 2052 is still low, and the output becomes low after passing through the OR gate. The level of the first control signal SIGN-C remains unchanged.

[0122] When the count value DMACNT is equal to 16, the two input signals of the second comparison unit 2052 (count value DMACNTA2, second count threshold B2) match, and the output signal of the second comparison unit 2052 is pulled high, and the output is pulled high to a high level through the OR gate, thereby triggering the flip circuit to flip the level of the first control signal SIGN-C (low level to high level), indicating the start of the positive half cycle of the sinusoidal excitation signal.

[0123] When the count value DMACNT is equal to 15, the two input signals (A2, B2) of the second comparison unit 2052 do not match, and the output signal of the second comparison unit 2052 becomes low. At this time, the output signal of the first comparison unit 2051 is still low, and the output becomes low after passing through the OR gate. The level of the first control signal SIGN-C remains unchanged.

[0124] In some embodiments, the resolver processing circuit 200 of the present invention is integrated into a microcontroller (MCU). For example, the resolver processing circuit 200 shown in Figures 3, 5, and 6, or any of the embodiments of the present invention, can be integrated into the MCU. This MCU can replace an external hardware decoding chip to decode the resolver signal. Most of the submodules are available in conventional MCUs. By integrating the accumulator and inverse tangent module into the MCU, the external resolver decoding chip can be replaced, reducing resolver decoding costs and improving the MCU's competitiveness.

[0125] An embodiment of the present application also provides a resolver processing method, which can be implemented by the motor system, resolver processing circuit, and MCU of this specification.

[0126] As shown in FIG. 15 , the resolver processing method may include steps S1501 to S1503 .

[0127] Step S1501: adjust the first symbol and output a first codeword.

[0128] The first symbol is a symbol of a digital codeword corresponding to an induction signal, and the induction signal is generated by a secondary winding of the rotary transformer module according to a sinusoidal excitation signal.

[0129] Step S1502: Accumulate the first codeword and determine the second codeword.

[0130] Step S1503: Determine angle information according to the second codeword.

[0131] Through this embodiment, accurate estimation of angles can be provided with lower hardware cost and lower computing power requirement.

[0132] An exemplary embodiment of adjusting the sign of a digital signal to obtain a digital output is described below.

[0133] In the first approach, the adjustment module 201 can adjust the first symbol and obtain the first codeword based on the first control signal SING-C and the second control signal SING-S. The first control signal SIGN-C is used to indicate the positive and negative cycle information of the induced signal corresponding to the sinusoidal excitation signal, and the second control signal SING-S is used to indicate the positive and negative information of the second symbol of the envelope signal.

[0134] For example, as shown in FIG4A , when the second sign is positive, the second control signal SING-S is at a first level (shown as a high level in FIG4A ); when the second sign is negative, the second control signal SING-S is at a second level (shown as a low level in FIG4A ). When the sensing signal corresponds to the positive half-cycle of the sinusoidal excitation signal, the first control signal SIGN-C is at a first level (shown as a high level in FIG4A ); when the sensing signal corresponds to the negative half-cycle of the sinusoidal excitation signal, the first control signal SIGN-C is at a second level (shown as a low level in FIG4A ).

[0135] As an embodiment, adjusting the sign of the digital signal according to the first control signal SING-C and the second control signal SING-S to obtain a digital output may include:

[0136] If the sensing signal corresponds to the positive half-cycle of the sinusoidal excitation signal (the first control signal SIGN-C is high) and the second sign is negative (the second control signal SING-S is low), the first sign is flipped. As shown in Figure 4A, for the sensing signal in interval a, the first sign of the digital codeword corresponding to the sensing signal before flipping is positive, and the first sign of the digital codeword corresponding to the sensing signal after flipping is negative, and the sign of the output first codeword is negative.

[0137] If the sensing signal corresponds to the positive half-cycle of the sinusoidal excitation signal (the first control signal SIGN-C is high) and the second sign is positive (the second control signal SING-S is high), the first sign remains unchanged. As shown in Figure 4A, for the sensing signal in interval b, the first sign remains positive, and the sign of the output first codeword is positive.

[0138] If the sensing signal corresponds to the negative half-cycle of the sinusoidal excitation signal (the first control signal SIGN-C is low) and the second sign is positive (the second control signal SING-S is high), the first sign is flipped. As shown in Figure 4A, for the sensing signal in interval c, the first sign of the digital codeword corresponding to the sensing signal before the flip is negative, and the first sign of the digital codeword corresponding to the sensing signal after the flip is positive, and the sign of the output first codeword is positive.

[0139] If the sensing signal corresponds to the negative half-cycle of the sinusoidal excitation signal (the first control signal SIGN-C is at a low level) and the second sign is negative (the second control signal SING-S is at a low level), the first sign corresponding to the sensing signal remains unchanged. As shown in Figure 4A, for the sensing signal within interval d, the first sign of the digital codeword corresponding to the sensing signal remains negative, and the sign of the output first codeword is negative.

[0140] Through method 1, the first sign of the adjusted first codeword is consistent with the second sign of the second codeword corresponding to the envelope signal. The sign of the second codeword determined by accumulating the first codeword is the second sign corresponding to the envelope signal. As shown in Figure 4A, in intervals b and c, the sign of the actual outer envelope is positive, and the sign of the extracted outer envelope (second codeword) is also positive, that is, the sign of the second codeword is consistent with the second sign corresponding to the envelope signal.

[0141] Exemplarily, as shown in FIG4A , the first codewords (with positive signs) in interval b and / or interval c are accumulated to determine that the sign of the obtained second codeword is positive, and the sign of the second codeword is consistent with the second sign corresponding to the envelope signal. For example, as shown in FIG4A , the sensing signals in area b and area c are sampled and converted to obtain 8 digital codewords, 4 digital codewords in area b and 4 digital codewords in area c. Before adjustment: the first signs of the 4 digital codewords b1, b2, b3 and b4 in area b are positive, and the first signs of the two digital codewords c1, c2, c3 and c4 in area c are negative. After adjustment according to method 1: the signs of the 4 first codewords Db1, Db2, Db3 and Db4 corresponding to area b are positive, and the signs of the 4 first codewords Dc1, Dc2, Dc3 and Dc4 corresponding to area c are positive. Accumulate the first codewords Db1, Db2, Db3, and Db4 and at least some of the first codewords Dc1, Dc2, Dc3, and Dc4 to determine that the sign of the obtained second codeword is positive. The sign of the second codeword is consistent with the second sign corresponding to the envelope signal, that is, the signs of the second codeword and the envelope signal are both positive.

[0142] Exemplarily, the first codewords (with negative signs) in interval d and / or interval a are accumulated, and the sign of the determined second codeword is negative, and the sign of the second codeword is consistent with the second sign corresponding to the envelope signal. For example, as shown in FIG4A , the sensing signals in area d and area a are sampled and converted to obtain 8 digital codewords, 4 digital codewords in area d and 4 digital codewords in area a. Before adjustment: the first signs of the 4 digital codewords d1, d2, d3 and d4 in area d are negative, and the first signs of the 4 digital codewords a1, a2, a3 and a4 in area a are positive. After adjustment according to method 1: the signs of the 4 first codewords Dd1, Dd2, Dd3 and Dd4 corresponding to area d are negative, and the signs of the 4 first codewords Da1, Da2, Da1 and Da2 corresponding to area a are negative. Accumulate at least some of the first code words Da1, Da2, Da1 and Da2, and Dd1, Dd2, Dd3 and Dd4, and determine that the sign of the obtained second code word is negative. The sign of the second code word is consistent with the second sign of the envelope signal, that is, the signs of the second code word and the envelope signal are both negative.

[0143] In the first approach, when the technical angle information is obtained, the symbol of the second codeword can be used as the second symbol of the envelope signal.

[0144] It should be understood that FIG4A shows the case of a sinusoidal sensing signal, and the cosine sensing signal is similar to this, which will not be described in detail in the embodiment of the present application.

[0145] In the second approach, the first symbol may be adjusted according to the first control signal SIGN-C to obtain a first codeword.

[0146] Exemplarily, adjusting the first symbol and outputting the first codeword according to the first control signal SIGN-C includes:

[0147] If the sensing signal corresponds to the positive half-cycle of the sinusoidal excitation signal (the first control signal SIGN-C is at a high level), the first sign remains unchanged. For example, as shown in FIG4B , for the sensing signal in interval b, the first control signal SIGN-C is at a high level, the first sign remains positive, and the sign of the output first codeword is positive.

[0148] If the sensing signal corresponds to the negative half-cycle of the sinusoidal excitation signal (the first control signal SIGN-C is at a low level), the first sign is flipped. For example, as shown in FIG4B , for the sensing signal within interval c, the first control signal SIGN-C is at a low level. The first sign of the digital codeword corresponding to the sensing signal before the flip is negative, and the sign of the first codeword output after the flip is positive.

[0149] Unlike Method 1, Method 2 uses the same adjustment method as for intervals b and c for the sensing signals within intervals a and d. Specifically, as shown in FIG4B , for the sensing signal within interval d, which corresponds to the negative half-cycle of the sinusoidal excitation signal (the first control signal SIGN-C is at a low level), the first sign of the digital codeword corresponding to the sensing signal before flipping is negative, and the sign of the first codeword output after flipping is positive. For the sensing signal within interval a, the first sign remains unchanged, and the output first codeword remains positive. As shown in FIG4B , when the actual outer envelope is positive, the extracted outer envelope is positive; when the actual outer envelope is negative, the extracted outer envelope is positive. That is, the outer envelope extracted by Method 2 is a steamed bun wave.

[0150] In the second method, the first codewords are accumulated and the second codeword is determined. The sign of the second codeword does not represent the second sign of the envelope signal. For example, the signs of the second codewords determined by accumulating the first codewords in interval a and / or interval d are all positive, while the second signs of the envelope signals in intervals a and d are negative. To this end, in the second method, the second sign corresponding to the envelope signal can be determined based on the second control signal SING-S, and the angle information can be determined based on the second codeword and the second sign.

[0151] The embodiment of the present application also provides a chip, which includes the above-mentioned resolver processing circuit. The chip is also called an integrated circuit (IC), and the chip can be, but is not limited to, a SOC (System on Chip) chip or a SIP (system in package) chip. The chip adjusts the first symbol of the digital codeword corresponding to the induction signal of the secondary winding of the resolver and outputs the first codeword, accumulates the first codeword and determines the second codeword corresponding to the envelope signal, which is equivalent to accumulating multiple digital samples of the induction signal of the secondary winding to obtain the second codeword, and determining the angle information according to the second codeword. The resolver processing circuit does not require complex electronic devices and provides accurate angle estimation with lower hardware cost and lower computing power requirements.

[0152] An embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above provided in the device body. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablet computers, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights. This electronic device adjusts the first sign of a digital codeword corresponding to the induced signal from the secondary winding of a resolver and outputs the first codeword. This codeword is then accumulated to determine a second codeword corresponding to the envelope signal. This is equivalent to accumulating multiple digital samples of the induced signal from the secondary winding to obtain a second codeword, which is then used to determine angle information. The resolver processing circuit eliminates the need for complex electronic components, providing accurate angle estimation with low hardware cost and computing power requirements.

[0153] The above is only a preferred embodiment of the present application and does not constitute any form of limitation to the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A resolver processing circuit, characterized in that: include: An adjustment module, configured to adjust a first symbol and output a first codeword, wherein the first symbol is a symbol of a digital codeword corresponding to an induction signal, and the induction signal is generated by a secondary winding of a rotary transformer module according to a sinusoidal excitation signal; An accumulation module, used for accumulating the first codeword and determining a second codeword corresponding to the envelope signal; An angle calculation module is used to determine angle information according to the second codeword.

2. The circuit according to claim 1, characterized in that The adjustment module is also used for: According to a first control signal and a second control signal, adjusting the first symbol and outputting the first codeword; The first control signal is used to indicate the positive and negative period information of the induction signal corresponding to the sinusoidal excitation signal, and the second control signal is used to indicate the positive and negative information of the second sign of the envelope signal.

3. The circuit according to claim 2, characterized in that The adjustment module is also used for: If the induced signal corresponds to the positive half cycle of the sinusoidal excitation signal and the second sign is negative, flipping the first sign; If the induced signal corresponds to the positive half cycle of the sinusoidal excitation signal and the second sign is positive, keeping the first sign unchanged; If the induced signal corresponds to the negative half cycle of the sinusoidal excitation signal and the second sign is positive, flipping the first sign; If the induced signal corresponds to the negative half cycle of the sinusoidal excitation signal and the second sign is negative, the first sign is kept unchanged.

4. The circuit according to claim 1, characterized in that The adjustment module is further used to: adjust the first symbol according to a first control signal and output the first codeword; wherein the first control signal is used to indicate the positive and negative cycle information of the induced signal corresponding to the sinusoidal excitation signal; The angle calculation module is used to determine the second symbol corresponding to the envelope signal according to a second control signal, and determine the angle information according to the second codeword and the second symbol, wherein the second control signal is used to indicate the positive and negative information of the second symbol of the envelope signal.

5. The circuit according to claim 4, characterized in that The adjustment module is also used for: If the induced signal corresponds to the positive half cycle of the sinusoidal excitation signal, keeping the first sign unchanged; If the induced signal corresponds to a negative half cycle of the sinusoidal excitation signal, the first sign is flipped.

6. A circuit as claimed in claim 1, 2 or 4, characterized in that Also includes: A second control module is used to flip the second symbol based on the second codeword, and generate a second control signal based on the second symbol, wherein the second control signal is used to indicate positive and negative information of the second symbol of the envelope signal.

7. The circuit according to claim 6, characterized in that The second control module is used to flip the second symbol when the absolute value of the second codeword changes from greater than a preset flip threshold to less than the preset flip threshold, and changes from less than the preset flip threshold to greater than the preset flip threshold.

8. The circuit according to claim 1, characterized in that Also includes: A first analog-to-digital conversion module, configured to perform analog-to-digital conversion on a first sensing signal of a first secondary winding of a rotary transformer module, and output a first digital codeword corresponding to the first sensing signal; The second analog-to-digital conversion module is used to perform analog-to-digital conversion on a second sensing signal of a second secondary winding of the rotary transformer module, and output a second digital codeword corresponding to the second sensing signal.

9. The circuit according to claim 8, characterized in that The first analog-to-digital conversion module comprises: A first analog-to-digital conversion unit is used to perform analog-to-digital conversion on a positive phase of a first sensing signal during a first period, and write the converted positive phase result into a first register; perform analog-to-digital conversion on a negative phase of the first sensing signal during a second period, and write the converted negative phase result into a second register, and generate a first trigger signal; The first calculation unit is used to read the positive phase result and the negative phase result from the first register and the second register according to the first trigger signal, and determine the first digital codeword according to the positive phase result and the negative phase result.

10. The circuit according to claim 8, characterized in that The second analog-to-digital conversion module comprises: a second analog-to-digital conversion unit, configured to perform analog-to-digital conversion on the positive phase of the second sensing signal during a first period, and write the converted positive phase result into a third register; perform analog-to-digital conversion on the negative phase of the second sensing signal during a second period, and write the converted negative phase result into a fourth register, and generate a second trigger signal; The second calculation unit is used to read the positive phase result and the negative phase result from the third register and the fourth register according to the second trigger signal, and determine the second digital codeword according to the positive phase result and the negative phase result.

11. The circuit according to claim 9, characterized in that The first analog-to-digital conversion module further includes: The first multiplexer is connected to the first analog-to-digital conversion unit, and is used to output the positive phase of the first sensing signal during the first period, and to output the negative phase of the first sensing signal during the second period.

12. The circuit according to claim 10, characterized in that The second analog-to-digital conversion module further includes: The second multiplexer is connected to the second analog-to-digital conversion unit, and is used to output the positive phase of the second sensing signal during the first period, and output the negative phase of the second sensing signal during the second period.

13. The circuit according to claim 8, characterized in that The first analog-to-digital conversion module and the second analog-to-digital conversion module start analog-to-digital conversion at the zero point of the PWM pulse, wherein the PWM pulse belongs to a PWM pulse sequence for generating the sinusoidal excitation signal.

14. The circuit according to claim 8, characterized in that Also includes: a first differential amplification module, connected to the first analog-to-digital conversion module, and configured to differentially amplify the positive phase and the negative phase of the first sensing signal, and to make the median of the positive phase and the negative phase of the first sensing signal both be a first preset voltage; The second differential amplification module is connected to the second analog-to-digital conversion module and is used to differentially amplify the positive phase and the negative phase of the second sensing signal, and make the median of the positive phase and the negative phase of the second sensing signal both be a second preset voltage.

15. The circuit according to claim 2 or 4, characterized in that Also includes: A first control module, configured to generate the first control signal according to a count value of PWM pulses generated in a PWM pulse sequence; The PWM pulse sequence is used to generate the sinusoidal excitation signal, and the first control signal is used to indicate that the induction signal corresponds to positive and negative cycle information of the sinusoidal excitation signal.

16. The circuit according to claim 15, characterized in that The first control module comprises: a first comparison unit, configured to receive the count value, compare the count value with a first count threshold and output a first comparison output, wherein the first count threshold corresponds to a half period of the sinusoidal excitation signal; a second comparison unit, configured to receive the count value, compare the count value with a second count threshold and output a second comparison output, wherein the second count threshold corresponds to one cycle of the sinusoidal excitation signal; An output unit is used to generate the first control signal based on the first comparison output and the second comparison output.

17. The circuit according to claim 15, characterized in that It also includes a rotary drive module, the rotary drive module including: A storage unit, used for storing duty cycle data of each PWM pulse in the PWM pulse sequence; a direct memory access unit, configured to transmit the duty cycle data from the storage unit to the signal generating unit; The signal generating unit is used to generate PWM pulses according to the duty cycle data of the PWM pulses.

18. The circuit according to claim 17, characterized in that The direct memory access unit is also used to count the transmitted PWM pulses and output the count value.

19. The circuit of claim 1, wherein: The accumulation module is used to accumulate the first code words corresponding to N half waves of the sinusoidal excitation signal and determine the second code word corresponding to the envelope signal, wherein N is a positive integer.

20. The circuit of claim 19, wherein: The accumulation module is also used to output the second code word according to a third control signal, wherein the third control signal is used to indicate the start and end information of the N half waves, and the second code word is the accumulated value of the first code words corresponding to the N half waves.

21. The circuit of claim 1, 19 or 20, wherein: The accumulation module comprises: a first accumulating unit, configured to accumulate a first code word corresponding to a first sensing signal, and determine a second code word corresponding to a first envelope signal corresponding to the first sensing signal, wherein the first sensing signal is a sensing signal of a first secondary winding of the rotary transformer module; The second accumulating unit is used to accumulate the first codeword corresponding to the second sensing signal and determine the second codeword corresponding to the second envelope signal corresponding to the second sensing signal, wherein the second sensing signal is the sensing signal of the second secondary winding of the rotary transformer module.

22. A chip, characterized in that: It includes the resolver processing circuit described in claims 1 to 21 above.

23. An electronic device, characterized in that: The invention comprises a device body and the chip as claimed in claim 22 arranged in the device body.

24. A rotational processing method, characterized in that: include: Adjusting a first symbol and outputting a first codeword, wherein the first symbol is a symbol of a digital codeword corresponding to an induction signal, and the induction signal is generated by a secondary winding of a rotary transformer module according to a sinusoidal excitation signal; Accumulating the first codewords and determining a second codeword corresponding to the envelope signal; Angle information is determined according to the second codeword.

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