A carrier substrate and a method for producing a carrier substrate

Abstract

The present invention relates to a carrier substrate (100) for electrically interconnecting at least one substrate (104,105) of a sub-layer (103) comprising a first substrate (101) comprising traces (106) for electrical interconnection. The carrier substrate (100) further comprises an intermediate layer (102) adhered to the first substrate (101), and a sub-layer (103) adhered to the intermediate layer (102).The sub-layer comprises at least a second substrate (104) and a third substrate (105) arranged side-by-side. The at least one substrate (104, 105) of the sub-layer (103) is electrically connected to the first substrate (101).

Description

[0001] A CARRIER SUBSTRATE AND A METHOD FOR PRODUCING A CARRIER SUBSTRATE

[0002] TECHNICAL FIELD

[0003] The present disclosure generally relates to the field of substrates and printed circuit boards and more specifically to the field of carrier substrates that integrates further substrates with different properties.

[0004] BACKGROUND

[0005] The constantly increasing density of circuits in modern electronic systems causes many problems to overcome. For example, if a circuit comprises both an optical system and a RF circuit there are problems with integration. Since, the optical substrate on which the optical system is formed on has different electrical and optical properties compared to the RF substrate on which the RF circuit is formed. Furthermore, the substrates may have very different coefficients of thermal expansion, CTE, causing CTE mismatch. This CTE mismatch causes problems with built-in stress in the carrier substrate. This may cause problems with cracking, due to the formation of temperature-induced cracks. Furthermore, if layers with CTE mismatch are stacked on top of each other, the carrier substrate may bend during use in elevated temperatures.

[0006] In Y. Ren, M. Yin, C. Ye and X. Ye, "Application of hybrid PCB stackup," 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), Haining, China, 2017, pp. 1-3, doi: 10.1109 / EDAPS.2017.8277046. a hybrid PCB is designed with different layers with different CTE. The PCB suggested in this article most likely suffers from the above-discussed problem as well as built-in stress due to CTE mismatch.

[0007] Thus, there is a large interest in a carrier substrate that allows integration of different substrates with CTE mismatch. That is not prone to cracking, and / or bending, at elevated temperatures and with a reduced amount of built-in stress. SUMMARY

[0008] An object of the present disclosure is to provide a carrier substrate which seeks to mitigate, alleviate, or eliminate one or more of the above-identified deficiencies in the art and disadvantages singly or in any combination and to provide an improved carrier substrate.

[0009] This object is obtained by a carrier substrate for electrically interconnecting electronic components, comprising: a first substrate comprising traces for electrical interconnection, an intermediate layer adhered to the first substrate, and a sub-layer adhered to the intermediate layer. The sub-layer comprises at least a second substrate and a third substrate arranged side- by-side. The at least one substrate of the sub-layer is electrically connected to the first substrate.

[0010] The object is also obtained by a method for producing a carrier substrate wherein the method comprises the steps of providing a first substrate, providing a second substrate of a sub-layer, providing a third substrate of a sub-layer. The method further comprises applying an intermediate layer to the first substrate, placing the second substrate and the third substrate of the sub-layer on the intermediate layer side-by-side, laminating the first substrate, the second substrate and the third substrate, and forming vias in the sub-layer and the first substrate.

[0011] This way, the thermal expansion of the different substrates of the carrier substrates are alleviated by the intermediate layer so that the terminal stress transferred to the first substrate is reduced.

[0012] BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The foregoing will be apparent from the following more particular description of the example embodiments, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the example embodiments.

[0014] Figure 1 is a schematic cross section of a carrier substrate according to one embodiment of the present disclosure; Figure 2 is a schematic cross section of a carrier substrate and an electronic component according to one embodiment of the present disclosure; and

[0015] Figure 3 is a flowchart illustrating a method of producing a carrier substrate according to one embodiment of the present disclosure.

[0016] DETAILED DESCRIPTION

[0017] Aspects of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. The apparatus and method disclosed herein can, however, be realized in many different forms and should not be construed as being limited to the aspects set forth herein. Like numbers in the drawings refer to like elements throughout.

[0018] The terminology used herein is for the purpose of describing particular aspects of the disclosure only, and is not intended to limit the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0019] In this disclosure, the term 'via' should be interpreted as a structure provided for electrically connecting different layers of a carrier substrate. The term "via", short for "via hole," is a fundamental component in a printed circuit board (PCB). Vias are used to establish electrical connections between different layers of a multi-layer PCB, allowing signals and power to flow from one layer to another.

[0020] In this disclosure, the term "prepreg" should be interpreted as a material in PCB manufacturing that helps insulate and separate conductive copper layers, allowing for the creation of multilayer PCBs with complex circuitry while preventing electrical shorts between the layers. Prepreg materials vary in terms of thickness, resin type, and glass fabric type, depending on the specific requirements of the PCB design. The choice of prepreg affects factors such as the dielectric constant, thermal properties, and overall performance of the PCB.

[0021] Some of the example embodiments presented herein are directed towards a carrier substrate.

[0022] As part of the development of the example embodiments presented herein, a problem will first be identified and discussed. A carrier board comprising several different sub-layers with different CTE in a multi-layer structure will possibly experience bending and possibly formation of cracks due to the difference in CTE, upon experiencing elevated temperatures.

[0023] The present inventors realized that these problems might be minimized or even eliminated by forming a sub-layer of these different substrates arranged side-by-side arranged on an intermediate layer of prepreg, or adhesive, on a first carrier substrate. The intermediate layer may be dimensioned to absorb the expansion and contraction due to different CTE of the substrates in the sub-layer. This is further illustrated in Figure 1.

[0024] Figure 1 shows a carrier substrate, generally designated 100, for electrically interconnecting electronic components. The carrier substrate comprises a first substrate 101 comprising traces 106 for electrical interconnection. The traces are often embedded metallic traces in the first substrate. The carrier substrate further comprises an intermediate layer 102 adhered to the first substrate 101, and a sub-layer 103 adhered to the intermediate layer 102. The sub-layer 103 comprises at least a second substrate 104 and a third substrate 105 arranged side-by-side, wherein at least one substrate 104, 105 of the sub-layer 103 is electrically connected to the first substrate 101.

[0025] The intermediate layer 102 may fill regions 108 between opposing faces of the second substrate 104 and the third substrate 105 of the sub-layer 103. This way, thermal expansion of the second and third substrate is alleviated by the intermediate layer so that less thermal stress is transferred to the first substrate.

[0026] The at least one of the first substrate 104, or the second substrate 105 of the sub-layer 103 may be electrically connected to the first substrate 101 by means of a via 107 as shown in Figure 1.

[0027] The intermediate layer 102 may comprise prepreg or an adhesive.

[0028] The second substrate 104 and the third substrate 105 may have different coefficients of thermal expansion, CTE or other electrical and thermal properties.

[0029] The carrier substrate 100 may in one embodiment further comprise a fourth substrate 109 adhered to the second substrate 104 and / or the third substrate 105 of the sub-layer 103. Now with reference made to Figure 2 in which an electronic component 201 is connected to the second substrate 104 and / or the third substrate 105.

[0030] The second substrate 104 may be a RF substrate and the third substrate 105 may be an optical substrate. The electronic component 201 comprises a RF circuit 202 being connected to the second substrate 104 , and an optoelectronic circuit 203 being connected to the third substrate 105.

[0031] Now with reference made to Figure 3 in which a method, generally designated 300, for producing a carrier substrate 100 is disclosed. The method comprises the steps of:

[0032] Providing S10 a first substrate 101. This first substrate may be a conventional substrate for a printed circuit board (PCB) made of for example reinforced fiberglass.

[0033] Providing S20 a second substrate 104 of a sub-layer 103. This second substrate may be a special substrate for RF circuits.

[0034] Providing S30 a third substrate 105 of a sub-layer 103. The third substrate may be a substrate for optical components.

[0035] Applying S40 an intermediate layer 102 to the first substrate 101.

[0036] Placing S50 the second substrate 104 and the third substrate 105 of the sub-layer 103 on the intermediate layer 102 side-by-side. The intermediate layer may not be fully cured in order to allow the second and third substrate to be placed on the intermediate layer such that the top side of these substrates are in level with the top side of the intermediate level. This way no subtractive machining is required to embed these substrates in the intermediate layer.

[0037] Laminating S60 the first substrate 102, the second substrate 104 and the third substrate 105.

[0038] Forming S70 vias 107 in the sub-layer 103 and the first substrate 101. Optionally, the step of applying S40 an intermediate layer further comprises filling regions 108 between opposing faces of the second substrate 104 and the third substrate 105 of the sublayer 103.

[0039] Optionally, the method further comprises forming a via 107 for electrically connecting at least one of the first substrate 104, or the second substrate 105, of the sub-layer 103 to the first substrate 101.

[0040] The step of applying S40 an intermediate layer 102 may comprise distributing prepreg, or an adhesive, on the first substrate 101.

[0041] Optionally, the method further comprises a step of placing S45 the second substrate 104 and the third substrate 105 in a frame prior to placing S50 the second and third substrates. The frame provides fixed positions relative the first substrate 101.

[0042] Optionally, the step of placing S50 the second substrate 104 and the third substrate 105, further comprises using fiducial marks and / or dowel pins for aligning the second substrate 104 and third substrate 105 with the first substrate 101.

[0043] Optionally, the method further comprises adhering a fourth substrate 109 to the second substrate 104 and / or the third substrate 105 of the sub-layer 102.

[0044] The disclosure relates to a carrier substrate for electrically interconnecting at least one substrate of a sub-layer comprising a first substrate comprising traces for electrical interconnection, an intermediate layer adhered to the first substrate, and a sub-layer adhered to the intermediate layer, wherein the sub-layer comprises at least a second substrate and a third substrate arranged side-by-side, wherein at least one substrate of the sub-layer is electrically connected to the first substrate.

[0045] According to some embodiments, the intermediate layer fills regions between opposing faces of the second substrate and the third substrate of the sub-layer.

[0046] According to some embodiments, the at least one of the first substrate, or the second substrate of the sub-layer is electrically connected to the first substrate by means of a via. According to some embodiments, the intermediate layer comprises prepreg or an adhesive.

[0047] According to some embodiments, the second substrate and the third substrate have different coefficients of thermal expansion, CTE.

[0048] According to some embodiments, the method further comprises a fourth substrate adhered to the second substrate and / or the third substrate of the sub-layer.

[0049] According to some embodiments, an electronic component being connected to the second substrate and / or the third substrate.

[0050] According to some embodiments, the second substrate is a RF substrate and the third substrate is an optical substrate, wherein the electronic component comprises a RF circuit connected to the second substrate, and an optoelectronic circuit connected to the third substrate.

[0051] The disclosure also relates to a method for producing a carrier substrate wherein the method comprises the steps of providing a first substrate, providing a second substrate of a sub-layer, providing a third substrate of a sub-layer, applying an intermediate layer to the first substrate, placing the second substrate and the third substrate of the sub-layer on the intermediate layer side-by-side, laminating the first substrate, the second substrate and the third substrate, and forming vias in the sub-layer and the first substrate.

[0052] According to some embodiments, the step of applying an intermediate layer further comprises filling regions between opposing faces of the second substrate and the third substrate of the sub-layer.

[0053] According to some embodiments, the method further comprises forming a via for electrically connecting at least one of the first substrate, or the second substrate, of the sub-layer to the first substrate.

[0054] According to some embodiments, the step of applying an intermediate layer comprises distributing prepreg, or an adhesive, on the first substrate. According to some embodiments, the method further comprises a step of placing the second substrate and the third substrate in a frame prior to placing the second and third substrates, wherein the frame provides fixed positions relative the first substrate.

[0055] According to some embodiments, the step of placing the second substrate and the third substrate, further comprises using fiducial marks and / or dowel pins for aligning the second substrate and third substrate with the first substrate.

[0056] According to some embodiments, the method further comprises adhering a fourth substrate to the second substrate and / or the third substrate of the sub-layer.

[0057] In the drawings and specification, there have been disclosed exemplary embodiments. However, many variations and modifications can be made to these embodiments. Accordingly, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the embodiments being defined by the following claims.

[0058] The description of the example embodiments provided herein have been presented for purposes of illustration. The description is not intended to be exhaustive or to limit example embodiments to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of various alternatives to the provided embodiments. The examples discussed herein were chosen and described in order to explain the principles and the nature of various example embodiments and its practical application to enable one skilled in the art to utilize the example embodiments in various manners and with various modifications as are suited to the particular use contemplated. The features of the embodiments described herein may be combined in all possible combinations of methods, apparatus, modules, systems, and computer program products.

[0059] It should be appreciated that the example embodiments presented herein may be practiced in any combination with each other. It should be noted that the word "comprising" does not necessarily exclude the presence of other elements or steps than those listed and the words "a" or "an" preceding an element do not exclude the presence of a plurality of such elements. It should further be noted that any reference signs do not limit the scope of the claims, that the example embodiments may be implemented at least in part by means of both hardware and software, and that several "means", "units" or "devices" may be represented by the same item of hardware.

Claims

CLAIMS1. A carrier substrate (100) for electrically interconnecting electronic components, comprising: a first substrate (101) comprising traces (106) for electrical interconnection; an intermediate layer (102) adhered to the first substrate (101); and a sub-layer (103) adhered to the intermediate layer (102), wherein the sub-layer comprises at least a second substrate (104) and a third substrate (105) arranged side-by-side, wherein at least one substrate (104, 105) of the sub-layer (103) is electrically connected to the first substrate (101).

2. The carrier substrate (100) according to claim 1, wherein the intermediate layer (102) fills regions (108) between opposing faces of the second substrate (104) and the third substrate (105) of the sub-layer (103).

3. The carrier substrate (100) according to any one of the preceding claims, wherein the at least one of the first substrate (104), or the second substrate (105) of the sub-layer (103) is electrically connected to the first substrate (101) by means of a via (107).

4. The carrier substrate (100) according to any one of the preceding claims, wherein the intermediate layer (102) comprises prepreg or an adhesive.

5. The carrier substrate (100) according to any one of the preceding claims, wherein the second substrate (104) and the third substrate (105) have different coefficients of thermal expansion, CTE.

6. The carrier substrate (100) according to any one of the preceding claims, further comprising a fourth substrate (109) adhered to the second substrate (104) and / or the third substrate (105) of the sub-layer (103).

7. An electronic assembly (200), comprising: a carrier substrate (100) according to any one of the preceding claims; an electronic component (201) being connected to the second substrate (104) and / or the third substrate (105).

8. The electronic assembly (200) according to claim 7, wherein the second substrate (104) is a RF substrate and the third substrate (105) is an optical substrate, wherein the electronic component (201) comprises: a RF circuit (202) connected to the second substrate (104); and an optoelectronic circuit (203) connected to the third substrate (105).

9. A method (300) for producing a carrier substrate (100), wherein the method comprises the steps of: providing (S10) a first substrate (101); providing (S20) a second substrate (104) of a sub-layer (103); providing (S30) a third substrate (105) of a sub-layer (103); applying (S40) an intermediate layer (102) to the first substrate (101); placing (S50) the second substrate (104) and the third substrate (105) of the sub-layer (103) on the intermediate layer (102) side-by-side; laminating (S60) the first substrate (101), the second substrate (104) and the third substrate (105); and forming (S70) vias (107) in the sub-layer (103) and the first substrate (101).

10. The method according to claim 10, wherein the step of applying (S40) an intermediate layer further comprises filling regions (108) between opposing faces of the second substrate (104) and the third substrate (105) of the sub-layer (103).

11. The method according to any one of claims 10 or 11, further comprising forming a via (107) for electrically connecting at least one of the first substrate (104), or the second substrate (105), of the sub-layer (103) to the first substrate (101).

12. The method (300) according to any one of claim 10 to 12, wherein the step of applying (S40) an intermediate layer (102) comprises distributing prepreg, or an adhesive, on the first substrate (101).

13. The method (300) according to any one of claim 10 or 13, further comprising a step of placing (S45) the second substrate (104) and the third substrate (105) in a frame prior to placing (S5) the second and third substrates, wherein the frame provides fixed positions relative the first substrate (101).

14. The method (300) according to any one of claim 10 to 14, wherein the step of placing (S50) the second substrate (104) and the third substrate (105), further comprises using fiducial marks and / or dowel pins for aligning the second substrate (104) and third substrate (105) with the first substrate (101).

15. The method (300) according to any one of claim 10 to 15, further comprises adhering a fourth substrate (109) to the second substrate (104) and / or the third substrate (105) of the sublayer (103).

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