Chip packaging structure and electronic device

Abstract

Disclosed in the present application are a chip packaging structure and an electronic device. The chip packaging structure comprises a main substrate, a first chip, a transition substrate and a second chip, wherein the first chip is arranged on one side of the main substrate; the transition substrate is arranged on the side of the first chip that is away from the main substrate; and the second chip is arranged on the side of the transition substrate that is away from the first chip. Compared with the related art, the chip packaging structure provided in the present application eliminates at least one layer of substrate and a gap formed along with the substrate, such that either mechanical interconnection paths or electrical interconnection paths between the second chip and the first chip are reduced, thereby making the chip packaging structure as a whole achieve benefits in terms of thickness, heat dissipation, signal transmission, etc.

Description

Chip packaging structure and electronic equipment Technical Field

[0001] The present application relates to the field of chip technology, and more specifically, to a chip packaging structure and electronic equipment. Background Art

[0002] Stacked chips, also known as three-dimensional chips or multi-layer chips, are different from traditional planar chips. Stacked chips use a vertical stacking method to package multiple chips with different functions into one, thereby achieving higher integration and smaller size.

[0003] The system on chip (SoC) of a smartphone is a typical stacked chip, which mainly includes a memory chip on the upper layer and a logic chip on the lower layer.

[0004] The current technology used in the industry to manufacture SoC chips is to package the memory chip and logic chip separately into two parts, then stack them together and perform a secondary packaging process using package-on-package (PoP) technology. However, this technology makes the final SoC chip thicker, which is not conducive to meeting the development trend of thinner and lighter smartphones. It also leads to a longer heat dissipation path for the logic chip, which is not conducive to heat dissipation and full performance.

[0005] Summary of the Invention

[0006] The purpose of this application is to provide a chip packaging structure and an electronic device, in which the paths of mechanical and electrical interconnection between the second chip and the first chip are reduced, so that the overall chip packaging structure gains benefits in thickness, heat dissipation, signal transmission, etc.

[0007] In a first aspect, the present application provides a chip packaging structure, including a main substrate, a first chip, a transition substrate and a second chip.

[0008] The first chip is arranged on one side of the main substrate, the transition substrate is arranged on a side of the first chip away from the main substrate, and the second chip is arranged on a side of the transition substrate away from the first chip.

[0009] Compared with the related art, the chip packaging structure provided in the present application eliminates a layer of substrate and the gap formed by the substrate, so that the mechanical interconnection path between the second chip and the first chip is shortened, thereby achieving the effect of reducing the overall thickness of the chip structure, so that the chip packaging structure in the present application can meet the development needs of lightweight smartphones; at the same time, since a layer of substrate is eliminated, the path for the first chip to dissipate heat to the outside is also shortened, ensuring the heat dissipation effect of the first chip. More importantly, the gap formed by the substrate layer also disappears, so that the air thermal resistance on the heat dissipation path is reduced, which is more conducive to the first chip to dissipate heat to the outside without easily triggering temperature control protection, so that the working performance of the first chip can be fully released; in addition, the electrical interconnection path between the second chip and the first chip is also shortened, which is conducive to high-speed signal transmission and power network distribution, thereby reducing signal transmission loss and overall chip power consumption. Overall, the chip performance is ultimately improved.

[0010] In one possible design, the first chip includes a logic chip, and the second chip includes a storage chip.

[0011] Optionally, the first chip includes but is not limited to logic chips such as a central processing chip, a graphics processing chip, a digital signal processing chip, an application chip, and a baseband processing chip.

[0012] Optionally, the second chip includes but is not limited to a memory chip of a dynamic random access memory, a static random access memory, a synchronous dynamic random access memory, or the like.

[0013] In one possible design, the second chip includes multiple chip unit groups, and the chip unit groups include multiple chip units arranged in a stacked manner.

[0014] Optionally, the ends of the multiple chip units toward the edge of the transition substrate are successively retracted; or, the ends of the multiple chip units toward the edge of the transition substrate are successively extended; or, the side surfaces of the ends of the multiple chip units toward the edge of the transition substrate are in the same plane.

[0015] In a possible design, a dummy die is also provided on the side of the transition substrate where the second chip is provided.

[0016] The added dummy die can absorb the stress between chip units due to thermal expansion and contraction or external force, thereby improving the reliability of the second chip. In addition, the added dummy die can quickly transfer the heat generated by the first chip to the external environment, which has a good heat dissipation effect on the entire chip packaging structure.

[0017] In a possible design, the virtual die includes a first die, and the first die is located between the plurality of chip unit groups.

[0018] In this way, the heat conduction path passes between the chip unit groups, preventing the heat emitted by the first chip from affecting the chip unit group, thereby ensuring that the performance of the second chip can be fully released.

[0019] In a possible design, an orthographic projection of the first die toward the main substrate at least partially falls on the first chip.

[0020] The specific location of the virtual die is further limited, so that the heat emitted by the first chip can be vertically conducted upward to the virtual die. This short heat conduction path further ensures the heat dissipation effect of the entire chip packaging structure.

[0021] In a possible design, the virtual die includes a second die, and the second die is located outside the plurality of chip unit groups.

[0022] A second die is added to the original first die, located in the peripheral area of ​​the transition substrate, so that the heat conducted from the first chip to the transition substrate can be evenly dispersed and dissipated from multiple directions: one is to dissipate heat in the vertical direction through the first die, and the other is to dissipate heat in all directions through the second die.

[0023] In addition, the area on the transition substrate where the second chip is not mounted is utilized to mount dummy die, making the overall structure of the chip more uniform, further improving the structural stability during thermal expansion and contraction, and ensuring the overall service life of the chip.

[0024] In a possible design, a heat sink is provided inside the transition substrate.

[0025] By embedding a heat sink inside the transition substrate, the heat conduction efficiency of the transition substrate is improved, which can further improve the heat dissipation effect of the first chip to the outside, and is conducive to fully releasing the working performance of the first chip.

[0026] In a possible design, an orthographic projection of the heat sink toward the main substrate at least partially falls on the first chip.

[0027] The positional relationship between the heat sink and the first chip is further limited, so that the heat dissipated by the first chip in the vertical direction can be fully and quickly conducted to the heat sink, which can further improve the outward heat dissipation effect of the first chip.

[0028] In a possible design, the heat sink is made of metal and is used to achieve electrical connection between the second chip and the main substrate.

[0029] The metal heat sink has a "dual-purpose" effect. In addition to its basic heat dissipation function, it also serves as a conductive connector.

[0030] In a possible design, the distance between the first chip and the opposing surfaces of the transition substrate is 5% to 10% of the distance between the opposing surfaces of the main substrate and the transition substrate.

[0031] The distance between the first chip and the transition substrate, as well as the distance between the main substrate and the transition substrate, is restricted, so that the heat transfer path of the first chip to the outside is reduced as much as possible while ensuring a safe distance during assembly.

[0032] In a possible design, thermal conductive adhesive is provided between the first chip and the transition substrate.

[0033] The first chip is thermally connected to the transition substrate, thereby improving the efficiency of heat transfer from the first chip to the transition substrate.

[0034] In a possible design, the outer surface of the first chip is coated with thermal conductive adhesive.

[0035] The periphery and bottom of the first chip are also wrapped with thermal conductive adhesive, so that the thermal conductive adhesive can also protect the first chip and the electrical connection between the first chip and the main substrate.

[0036] In a possible design, a receiving groove is provided on a side of the transition substrate facing the first chip, and thermal conductive adhesive is provided in the receiving groove.

[0037] A receiving groove is provided on the side of the transition substrate facing the first chip, so that the relative position between the transition substrate and the first chip is thinned, thereby shortening the heat conduction path on the transition substrate, and filling the receiving groove with thermal conductive glue, so that the heat emitted by the first chip can be more easily conducted upward through the transition substrate after passing through the thermal conductive glue, thereby reducing the thermal resistance of the entire heat transfer path of the first chip to the outside, thereby being more conducive to the heat dissipation of the first chip.

[0038] In a possible design, the surface area of ​​the first chip facing the transition substrate is smaller than the opening area of ​​the accommodating groove.

[0039] By further limiting the relationship between the opening area of ​​the accommodating groove and the surface area of ​​the first chip, that is, the first chip is smaller than the accommodating groove, the first chip can partially extend into the accommodating groove. In this way, when the intermediate substrate is assembled above the first chip, the accommodating groove can avoid the first chip, preventing interference between the intermediate substrate and the first chip, thereby achieving smooth assembly of the two. This in turn reduces the difficulty of processing and assembling related components.

[0040] In one possible design, the periphery of the transition substrate has a first connection portion extending from the edge of the first chip, and the periphery of the main substrate has a second connection portion extending from the edge of the first chip. Solder pads are respectively provided on opposite surfaces of the first connection portion and the second connection portion, and a support member is welded between the solder pad of the first connection portion and the solder pad of the second connection portion.

[0041] The support member is not only used to support the transition substrate above the main substrate and realize the mechanical interconnection between the transition substrate and the main substrate, but also realizes the electrical interconnection between the transition substrate and the main substrate through the support member. This can eliminate the electrical connector specifically used to electrically connect the transition substrate and the main substrate, making the chip packaging structure more compact.

[0042] In a possible design, the outer surface of the support member is covered with protective glue.

[0043] The protective glue is wrapped around the outside of the support member and the pad, thereby ensuring the connection strength between the support member and the pad and preventing the electrical connection from being disconnected.

[0044] In a possible design, the chip packaging structure further includes a packaging component, which is coated on the outer surface of the second chip.

[0045] The package plays a protective role for the second chip.

[0046] In a second aspect, the present application also provides a chip packaging structure, including a main substrate, a logic chip, a memory chip and a packaging component.

[0047] The logic chip is arranged on one side of the main substrate, the memory chip is arranged on the side of the logic chip away from the main substrate, and the packaging component covers the outer surfaces of the logic chip and the memory chip.

[0048] The chip packaging structure provided by the present application completely abandons the method of separately packaging the second chip and the first chip and then packaging them again in the related art, so that the chip packaging structure only undergoes one packaging step during processing. In the final chip packaging structure, compared with the related art, the two layers of substrates and the gap formed by the two layers of substrates are omitted, so that the mechanical interconnection path between the second chip and the first chip is shortened, thereby achieving the effect of reducing the overall thickness of the chip structure; at the same time, since the two layers of substrates are omitted and the gap is completely eliminated, the air thermal resistance on the heat dissipation path completely disappears, which is more conducive to the outward heat dissipation of the first chip; the electrical interconnection path between the second chip and the first chip is also shortened, which is conducive to high-speed signal transmission and power network distribution.

[0049] In one possible design, the memory chip includes multiple chip unit groups, and the chip unit group includes multiple chip units arranged in a stacked manner.

[0050] In a possible design, in a direction away from the main substrate, for each chip unit group, multiple chip units sequentially extend toward the end portion of the edge of the main substrate, and the end portion of each chip unit is connected to the main substrate via a support member.

[0051] The ends of the multiple chip units extend sequentially toward the edge of the main substrate, allowing them to avoid each other and leave a portion of the substrate, thereby facilitating the connection of support members, such as metal pillars, to the main substrate via flip-chip bonding. Furthermore, the support members in this embodiment serve two primary functions: first, to achieve electrical connection between the chip units and the main substrate, and second, to mechanically support the chip units, thereby ensuring their stability during the encapsulation process and facilitating manufacturing.

[0052] In one possible design, a dummy die is provided on one side of the logic chip where the memory chip is provided.

[0053] The added dummy die can absorb the stress between the second chip due to thermal expansion and contraction or external force, thereby improving the reliability of the second chip. In addition, the added dummy die can quickly transfer the heat generated by the first chip to the external environment, which has a good heat dissipation effect on the entire chip packaging structure.

[0054] In one possible design, a dummy die is located between multiple chip unit groups.

[0055] In this way, the heat conduction path passes between the chip unit groups, preventing the heat emitted by the first chip from affecting the chip unit groups, thereby ensuring that the performance of the memory chip can be fully released.

[0056] In a third aspect, the present application also provides an electronic device comprising any of the above chip packaging structures.

[0057] The electronic device provided in this application also has the above-mentioned beneficial effects because it includes the above-mentioned chip packaging structure, which will not be described in detail here.

[0058] In a fourth aspect, the present application further provides a chip packaging method, comprising:

[0059] Mounting a second chip on the transition substrate, and covering an outer surface of the second chip with a package;

[0060] mounting a first chip on the main substrate;

[0061] The transition substrate is fixed to one side of the main substrate having the first chip through a supporting member in an interval manner, and the transition substrate is electrically connected to the main substrate.

[0062] The chip packaging method provided in the embodiments of this application can reduce one packaging step compared to related technologies, thereby reducing chip packaging costs. The chip structure manufactured using this chip packaging method achieves the effect of reducing the overall thickness of the chip structure, ensuring effective heat dissipation of the first chip, and reducing signal transmission loss and overall chip power consumption.

[0063] In one possible design, the step of fixing the transition substrate to the side of the main substrate having the first chip by a support member and electrically connecting the transition substrate to the main substrate includes:

[0064] Solder pads are respectively provided on opposite surfaces of the transition substrate and the main substrate;

[0065] The support members are welded between the welding pads of the transition substrate and the welding pads of the main substrate.

[0066] The support member is not only used to realize the mechanical interconnection between the transition substrate and the main substrate, but also realizes the electrical interconnection between the transition substrate and the main substrate through the support member. This can eliminate the electrical connector specifically used to electrically connect the transition substrate and the main substrate, making the chip packaging structure more compact.

[0067] In one possible design, the step of mounting the second chip on the transition substrate and covering the outer surface of the second chip with a package further includes:

[0068] The second chip and the dummy die are mounted on the transition substrate, and the outer surfaces of the second chip and the dummy die are covered with a package.

[0069] The added dummy grains can absorb the stress between the second chip due to thermal expansion and contraction or external force. At the same time, the added dummy grains can quickly conduct the heat generated by the first chip to the external environment, which has a good heat dissipation effect on the entire chip packaging structure.

[0070] In a possible design, before the step of mounting the second chip on the transition substrate, the method further includes:

[0071] A heat sink is mounted inside the transition base plate.

[0072] By installing a heat sink inside the transition substrate, the heat conduction efficiency of the transition substrate is improved, which can further improve the heat dissipation effect of the first chip to the outside, and is conducive to fully releasing the working performance of the first chip.

[0073] In a possible design, before the step of fixing the transition substrate to the side of the main substrate having the first chip by the support member, the method further includes:

[0074] Filling the area adjacent to the first chip on the main substrate with thermal conductive glue.

[0075] The thermal conductive adhesive is used to establish a thermal conductive connection path between the first chip and the transition substrate, and can improve the outward heat transfer efficiency of the first chip.

[0076] In a possible design, after the step of welding the support member between the welding pad of the transition substrate and the welding pad of the main substrate, the method further includes:

[0077] The area between the transition substrate and the main substrate and adjacent to the support member is filled with protective glue.

[0078] The protective glue is used to protect the electrical connection between the transition substrate and the main substrate to prevent it from breaking and causing electrical connection failure.

[0079] In a fifth aspect, the present application further provides a chip packaging method, comprising:

[0080] mounting a first chip on the main substrate;

[0081] bonding a second chip onto the first chip and connecting the second chip to the main substrate;

[0082] A package is wrapped around the second chip and the first chip.

[0083] The chip packaging method provided in this application completely abandons the related art practice of separately packaging the second chip and the first chip and then repackaging them. This allows the chip packaging structure to undergo only a single packaging step during processing, thereby reducing chip packaging costs. The chip structure manufactured using this chip packaging method eliminates the need for two substrates and the gap formed by them, achieving an overall reduction in chip thickness, ensuring effective heat dissipation for the first chip, and reducing signal transmission loss and overall chip power consumption.

[0084] In a possible design, the second chip and the main substrate can be connected by wire bonding, adhesive bonding, flip-chip bonding, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] FIG1 is a schematic diagram of a SoC chip in the related art;

[0086] FIG2 is a schematic diagram of a packaging method of a SoC chip in the related art;

[0087] FIG3 is a schematic diagram of a smart phone provided in an embodiment of the present application;

[0088] FIG4 is a schematic diagram of a first example of a chip packaging structure provided in an embodiment of the present application;

[0089] FIG5 is a schematic diagram of temperature distribution of a SoC chip in the related art;

[0090] FIG6 is a schematic diagram of temperature distribution of a chip packaging structure in an embodiment of the present application;

[0091] FIG7 is a schematic diagram of a second example of a chip packaging structure provided in an embodiment of the present application;

[0092] FIG8 is a schematic diagram of a third example of a chip packaging structure provided in an embodiment of the present application;

[0093] FIG9 is a schematic diagram of a fourth example of a chip packaging structure provided in an embodiment of the present application;

[0094] FIG10 is a schematic diagram of a fifth example of a chip packaging structure provided in an embodiment of the present application;

[0095] FIG11 is a schematic diagram of a sixth example of a chip packaging structure provided in an embodiment of the present application;

[0096] FIG12 is a top view of a transition substrate provided in an embodiment of the present application;

[0097] FIG13 is a partial cross-sectional view of a transition substrate provided in an embodiment of the present application;

[0098] FIG14 is a schematic diagram of a seventh example of a chip packaging structure provided in an embodiment of the present application;

[0099] FIG15 is a schematic diagram of an eighth example of a chip packaging structure provided in an embodiment of the present application;

[0100] FIG16 is a schematic diagram of a ninth example of a chip packaging structure provided in an embodiment of the present application;

[0101] FIG17 is a schematic diagram of a tenth example of a chip packaging structure provided in an embodiment of the present application;

[0102] FIG18 is a schematic diagram of an eleventh example of a chip packaging structure provided in an embodiment of the present application;

[0103] FIG19 is a schematic diagram of a twelfth example of a chip packaging structure provided in an embodiment of the present application;

[0104] FIG20 is a schematic diagram of a thirteenth example of a chip packaging structure provided in an embodiment of the present application;

[0105] FIG21 is a schematic diagram of a fourteenth example of a chip packaging structure provided in an embodiment of the present application;

[0106] FIG22 is a schematic diagram of a fifteenth example of a chip packaging structure provided in an embodiment of the present application;

[0107] FIG23 is a schematic diagram of a sixteenth example of a chip packaging structure provided in an embodiment of the present application;

[0108] FIG24 is a schematic diagram of a first example of a chip packaging method provided in an embodiment of the present application;

[0109] FIG25 is a schematic diagram of a second example of a chip packaging method provided in an embodiment of the present application;

[0110] FIG26 is a schematic diagram of a third example of a chip packaging method provided in an embodiment of the present application;

[0111] FIG27 is a schematic diagram of a fourth example of a chip packaging method provided in an embodiment of the present application;

[0112] FIG28 is a schematic diagram of a fifth example of a chip packaging method provided in an embodiment of the present application;

[0113] FIG29 is a schematic diagram of a sixth example of a chip packaging method provided in an embodiment of the present application;

[0114] Figure 30 is a schematic diagram of the seventh example of the chip packaging method provided in an embodiment of the present application.

[0115] Figure numerals: 1. memory chip; 2. first substrate; 3. logic chip; 4. second substrate; 5. third substrate; 10. second chip; 11. chip unit group; 111. chip unit; 10a. memory chip; 20. transition substrate; 21. gap; 22. first connecting portion; 231. first area; 232. second area; 24. virtual grain; 241. first grain; 242. second grain; 25. first middle portion; 26. heat sink; 27. receiving groove; 28. via; 30. first chip; 30a. logic chip; 40. main substrate; 41. second connecting portion; 42. second middle portion; 50. packaging component; 60. supporting component; 70. wire; 80. thermal conductive adhesive; 90. protective adhesive; 100. chip packaging structure; 200. housing; 300. display screen. DETAILED DESCRIPTION

[0116] The following is an illustrative introduction to the relevant contents that may be involved in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments.

[0117] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0118] In the description of this application, it should be understood that the terms "upper", "lower", "side", "inside", "outside", "top", "bottom", etc. indicate orientations or positional relationships based on the installation, and are only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on this application.

[0119] It should also be noted that, in the embodiments of the present application, the same figure mark is used to represent the same component or the same part. For the same parts in the embodiments of the present application, the figure may only mark the figure with one of the parts or parts as an example. It should be understood that the figure mark is also applicable to other identical parts or parts.

[0120] In the description of this application, it should be noted that the term "and / or" is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0121] Figure 1 is a schematic diagram of a SoC chip in the related art. As shown in Figure 1, the SoC chip of a smartphone is a typical stacked chip, which mainly includes a memory chip 1 on the upper layer and a logic chip 4 on the lower layer.

[0122] Figure 2 is a schematic diagram of a packaging method for a SoC chip in the related art. Figure 2 (a) shows a schematic diagram of a memory chip 1 and a logic chip 4 after being packaged separately, and Figure 2 (b) shows a schematic diagram of a memory chip 1 and a logic chip 4 after being packaged as a whole.

[0123] Currently, the industry uses three main technical routes when manufacturing SoC chips: separately packaging the memory chip 1 to form the upper part A; separately packaging the logic chip 4 to form the lower part B; and interconnecting the upper part A and the lower part B into one.

[0124] Specifically, as shown in (a) in Figure 2, the upper part A after separate packaging mainly includes a memory chip 1 and a first substrate 2, and a solder pad is set at the bottom of the first substrate 2 according to the unified standard interface formulated by the Joint Electron Device Engineering Council (JEDEC); the lower part B after separate packaging mainly includes a second substrate 3, a logic chip 4 and a third substrate 5, and a solder pad is also set on the top of the second substrate 3 according to the unified standard interface formulated by JEDEC; as shown in (b) in Figure 2, the upper part A and the lower part B are stacked and then secondary packaged using PoP technology, that is, the first substrate 2 and the second substrate 3 are welded together by solder balls to achieve mechanical and electrical interconnection between the memory chip 1 and the logic chip 4, thereby obtaining the final SoC chip product.

[0125] As can be seen, before manufacturing the SoC chip, the manufacturer of memory chip 1 will separately package memory chip 1, and the manufacturer of logic chip 4 will separately package logic chip 4. These chips are then smoothly combined according to the standards set by JEDEC. This flexible configuration of memory chip 1 and logic chip 4 facilitates industrial division of labor. This collaborative approach is particularly beneficial for the semiconductor industry, which requires substantial investment in R&D and production. Manufacturers of memory chip 1 and logic chip 4 can accumulate deep technical expertise in their respective fields, ultimately providing end customers with technologically innovative products.

[0126] However, although the current SoC chip manufacturing method is conducive to industrial division of labor, its many defects cannot be ignored: First, the overall thickness is too thick. As shown in Figure 1, the first substrate 2, the second substrate 3 and the solder balls between the two occupy a large thickness space, making the final SoC chip too thick as a whole, which is not conducive to meeting the development needs of thin and light smartphones; second, it is not conducive to heat dissipation. The logic chip 4 has an extremely high power density when working at high frequency. When dissipating heat upward, it must pass through the second substrate 3, the first substrate 2, the packaging components and other components. The heat dissipation path is long, and there are many gaps in the heat dissipation path, such as the gap between the logic chip 4 and the second substrate 3, and the gap between the second substrate 3 and the first substrate 2. The air thermal resistance in these gaps is very high. The first substrate 2 and the second substrate 3 are larger, which is not conducive to the heat dissipation of the logic chip 4 and the full release of the working performance; the second substrate 3 and the third substrate 5 are larger, which is not conducive to the heat dissipation of the logic chip 4 and the full release of the working performance; the third is that the interconnection path between the memory chip 1 and the logic chip 4 is longer, and at least the first substrate 2, the second substrate 3 and the third substrate 5 are required to realize electrical interconnection, which is not conducive to high-speed signal transmission and power network distribution, thereby increasing signal transmission loss and overall power consumption of the chip; the fourth is the high cost. In order to achieve a unified standard electrical interface, the memory chip 1 and the logic chip 4 must be packaged separately, and then repackaged through PoP technology to mechanically and electrically interconnect the memory chip 1 and the logic chip 4. This causes the problem of repeated packaging of the memory chip 1 and the logic chip 4, which is not conducive to reducing the manufacturing cost of the chip.

[0127] Therefore, in order to solve the above technical problems, the present application provides a chip packaging structure and an electronic device. In the chip packaging structure, the paths of mechanical and electrical interconnection between the second chip and the first chip are reduced, so that the overall chip packaging structure gains benefits in thickness, heat dissipation, signal transmission, etc.

[0128] The present application first provides an electronic device, which may also be referred to as a mobile device, a terminal device, a mobile terminal, or a terminal. The electronic device includes but is not limited to a handheld device, an in-vehicle device, a wearable device, a computing device, or other processing device connected to a wireless modem. For example, the electronic device may include a smart watch, a smart wristband, a smart phone, an earphone, a personal digital assistant (PDA), a tablet computer, a laptop computer, an in-vehicle computer, smart glasses, a pedometer, a two-way radio, and other electronic devices having a chip packaging structure and requiring a thin and lightweight chip structure and heat dissipation design.

[0129] In order to more conveniently explain the electronic device provided in the embodiment of the present application, as an example rather than a limitation, the following will take the electronic device being a smart phone as an example to explain in detail the technical solution of the present application.

[0130] FIG3 is a schematic diagram of a smart phone provided in an embodiment of the present application.

[0131] As shown in Figure 3, the smartphone provided in an embodiment of the present application includes a display screen 300 and a housing 200, which further includes a middle frame and a back cover. The middle frame is a hollow, ring-shaped structure, with the display screen 300 fixed to the front end and the back cover fixed to the rear end. The display screen 300, the middle frame, and the back cover together define a housing for the smartphone, which is used to house the various functional components of the smartphone, such as the chip packaging structure 100 described in the embodiments below, as well as other functional components such as a battery, microphone, and speaker.

[0132] In the embodiment of the present application, the cross-sectional shape of the middle frame (corresponding to the shape of the display screen 300 and the back cover) is rectangular, square, racetrack-shaped, or oval, etc. The middle frame provides mechanical support and protection for the entire smartphone and is made of a material with sufficient hardness. The material constituting the middle frame may be stainless steel, ceramic, titanium alloy, aluminum alloy, copper alloy, or hard plastic, etc. The back cover is attached to the rear end surface of the middle frame and may be made of stainless steel, titanium alloy, glass, ceramic, aluminum alloy, copper alloy, plastic, etc.

[0133] Optionally, the back cover can be screwed or snapped onto the middle frame, and a sealing ring can be provided between the back cover and the middle frame to improve the sealing and waterproof effect of the joint between the back cover and the middle frame. The sealing ring can be made of a highly elastic material such as silicone or rubber.

[0134] Optionally, the back cover and the middle frame may be bonded together by a sealant such as double-sided tape, curing adhesive, etc., so that the back cover and the middle frame are bonded together while also achieving a sealing and waterproof effect.

[0135] In addition, a smartphone may also include functional components such as a universal serial bus (USB) interface, a charging management module, a power management module, a battery, a microphone, a mobile communication module, an antenna, a wireless communication module, an audio module, a headphone jack, a sensor module, buttons, a camera, and a subscriber identification module (SIM) card interface.

[0136] These functional elements can be changed according to user needs. It can be understood that the specific embodiment introduced above is only a specific implementation method of the present application. Other ways to implement the solution of the present application are also within the scope of protection of the present application and will not be described in detail here.

[0137] The chip packaging structure 100 provided in this application will now be described in detail with reference to the accompanying drawings.

[0138] FIG4 is a schematic diagram of a first example of a chip packaging structure 100 provided in an embodiment of the present application.

[0139] As shown in FIG. 4 , an embodiment of the present application provides a chip packaging structure 100 , which includes a main substrate 40 , a first chip 30 , a transition substrate 20 , and a second chip 10 .

[0140] In addition, the chip package structure 100 may further include a package 50, which is disposed on the transition substrate 20 and is used to cover the second chip 10 to provide protection for the second chip 10. The material of the package 50 includes, but is not limited to, silicone, polyolefin resin, epoxy resin, modified epoxy resin, silicone resin, modified silicone resin, etc.

[0141] The first chip 30 is disposed on one side of the main substrate 40. The first chip 30 may be a logic chip, and the pins of the first chip 30 are connected to the pads of the transition substrate 20 by welding or conductive adhesive, so as to achieve mechanical and electrical interconnection between the first chip 30 and the transition substrate 20.

[0142] The transition substrate 20 is disposed on a side of the first chip 30 away from the main substrate 40 . The transition substrate 20 is fixed to one side of the main substrate 40 via a support member 60 and forms a gap 21 with the main substrate 40 . The first chip 30 is located in the gap 21 .

[0143] The second chip 10 is disposed on a side of the transition substrate 20 away from the first chip 30. The second chip 10 may be a storage chip, and the pins of the second chip 10 are connected to pads on the transition substrate 20 by welding or conductive adhesive to achieve mechanical and electrical interconnection between the second chip 10 and the transition substrate 20. Alternatively, the second chip 10 may be electrically interconnected with the transition substrate 20 via wires 70 (for detailed description, see the embodiments described below), and mechanically interconnected by encapsulating the second chip 10 on the transition substrate 20 using a package 50.

[0144] The transition substrate 20 is also connected to the main substrate 40. When connecting the transition substrate 20 to the main substrate 40, the transition substrate 20 can be directly welded via the support member 60. This allows the support member 60 to serve two purposes: it not only mechanically interconnects the transition substrate 20 and the main substrate 40, but also electrically interconnects them. Alternatively, the transition substrate 20 and the main substrate 40 can be mechanically interconnected via the support member 60, and additional electrical connectors such as wires and connectors can be added to electrically interconnect the transition substrate 20 and the main substrate 40.

[0145] As can be seen, the chip package structure 100 provided in the embodiment of the present application, from a mechanical perspective, only requires one transition substrate 20 to pass between the first chip 30 and the second chip 10; and from an electrical connection perspective, only two substrates, the transition substrate 20 and the main substrate 40, are required. This results in overall improvements in thickness, heat dissipation, and signal transmission for the chip package structure 100, as detailed below. The overall thickness of the chip package structure 100 can be understood as the length of the chip package structure 100 in the Z direction as shown in Figure 4 .

[0146] The overall thickness of the SoC chip structure in the related art is approximately 1.1 mm. The chip packaging structure 100 in the embodiment of the present application, while having the second chip 10, the first chip 30, the substrate, the package 50 and other components being the same as those in the related art, has an overall thickness of about 0.9 mm due to the reduction of a layer of substrate and the gap formed by the substrate, which can achieve a 20% thickness reduction.

[0147] Furthermore, the chip package structure 100 in the embodiment of the present application also achieves significant heat dissipation benefits, as detailed in the comparative experiments described below. In these comparative experiments, the second chip 10, first chip 30, substrate, package 50, and other components are identical to those in the related art, and the operating power of the first chip 30 is also the same.

[0148] Figure 5 is a schematic diagram of the temperature distribution of a SoC chip in the related art. The color depth of each area in the figure is related to the heat level. The darker the color of the area, the higher the temperature of the area. Correspondingly, the lighter the color of the area, the lower the temperature of the area. It can be clearly seen from Figure 5 that the color near the logic chip 4 is darker than other areas, and the temperature there is the highest. As the distance from the logic chip 4 increases, the color of the area gradually becomes lighter until it reaches the dotted area indicated by G.

[0149] FIG6 is a schematic diagram of the temperature distribution of the chip packaging structure 100 in the embodiment of the present application. FIG6 shows that the color near the first chip 30 is darker than other areas, indicating the highest temperature there. As the area moves away from the first chip 30, the color gradually becomes lighter, all the way to the dotted area indicated by G'. Compared to the dotted area indicated by G in FIG5 , the dotted area indicated by G' in FIG6 is significantly smaller. Therefore, it can be seen that the chip packaging structure 100 in the embodiment of the present application is more conducive to transferring the heat generated by the first chip 30 to the surrounding environment, and is less likely to cause heat to concentrate near the first chip 30.

[0150] Furthermore, testing revealed that in operating scenario 1, the junction temperature (junction temperature refers to the actual operating temperature of an electronic component) of the logic chip 4 in the related art was 63.14°C, while the junction temperature of the first chip 30 in the embodiment of the present application was 57.35°C. In operating scenario 2, the junction temperature of the logic chip 4 in the related art was 88.9°C, while the junction temperature of the first chip 30 in the embodiment of the present application was 79.4°C. This indicates that, under the same operating scenario, the chip package structure 100 in the embodiment of the present application can reduce the junction temperature of the first chip 30 by approximately 5°C-10°C, demonstrating significant heat dissipation benefits.

[0151] In summary, the chip packaging structure 100 provided in the embodiment of the present application eliminates a layer of substrate and the gap formed by the substrate compared to the related art, so that the mechanical interconnection path between the second chip 10 and the first chip 30 is shortened, thereby achieving the effect of reducing the overall thickness of the chip structure, so that the chip packaging structure 100 in the embodiment of the present application can meet the development needs of lightweight smartphones; at the same time, since a layer of substrate is omitted, the path for the first chip 30 to dissipate heat to the outside is also shortened, ensuring the heat dissipation effect of the first chip 30. More importantly, the gap formed by the layer of substrate also disappears, so that the air thermal resistance on the heat dissipation path is reduced, which is more conducive to the first chip 30 to dissipate heat to the outside without easily triggering temperature control protection, so that the working performance of the first chip 30 can be fully released; in addition, the electrical interconnection path between the second chip 10 and the first chip 30 is also shortened, which is conducive to high-speed signal transmission and power network distribution, thereby reducing signal transmission loss and the overall power consumption of the chip. Overall, the chip performance is ultimately improved.

[0152] Optionally, when the support member 60 is only used to achieve the purpose of mechanical interconnection between the transition substrate 20 and the main substrate 40, there are multiple schemes for fixing the support member 60 to the transition substrate 20 and the main substrate 40 respectively, which can be bonded with adhesives, locked with screws, plugged in with a socket structure, or snapped in with a snap-fit ​​structure.

[0153] Optionally, when the first chip 30 is a logic chip, it includes but is not limited to one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processing chip (DSP), an application processor (AP), and a baseband processing chip (BP), or it can also be a combination of multiple chips.

[0154] Optionally, when the second chip 10 is a memory chip, it includes but is not limited to one of dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), or a combination of multiple memories.

[0155] As mentioned above, when the transition substrate 20 is connected to the main substrate 40 , it can be directly welded through the support member 60 , which is the case described in the following embodiment.

[0156] As shown in Figure 4, in an embodiment provided in the present application, the periphery of the transition substrate 20 has a first connection portion 22 extending out from the edge of the first chip 30, and the transition substrate 20 also has a first middle portion 25 corresponding to the shape of the first chip 30; the periphery of the main substrate 40 has a second connection portion 41 extending out from the edge of the first chip 30, and the main substrate 40 also has a second middle portion 42 corresponding to the shape of the first chip 30; solder pads are respectively provided on the opposite surfaces of the first connection portion 22 and the second connection portion 41, and a support member 60 is welded between the solder pads of the first connection portion 22 and the solder pads of the second connection portion 41.

[0157] In this embodiment, the support member 60 is not only used to support the transition substrate 20 above the main substrate 40 and realize the mechanical interconnection between the transition substrate 20 and the main substrate 40, but also realizes the electrical interconnection between the transition substrate 20 and the main substrate 40 through the support member 60. This can eliminate the need for electrical connectors specifically used to electrically connect the transition substrate 20 and the main substrate 40, making the chip packaging structure 100 more compact.

[0158] Optionally, the support member 60 can be a plurality of metal balls, or a plurality of metal pillars, each metal ball or metal pillar corresponds to a group of upper pads and lower pads; or, the support member 60 can also be a metal ring structure, which connects the multiple upper pads and the multiple lower pads together.

[0159] Optionally, the material of the support member 60 can be a tin (Sn) alloy, and the elements added to form the tin alloy can be lead (Pb), copper (Cu), silver (Ag), nickel (Ni), etc., thereby improving the key performance indicators of the support member 60 such as electrical conductivity, solder resistance, and corrosion resistance.

[0160] In an embodiment provided in the present application, the second chip 10 includes a plurality of chip unit groups 11 distributed along the surface of the transition substrate 20 , and the chip unit group 11 includes a plurality of chip units 111 arranged in a stacked manner.

[0161] Optionally, the stacked chip units 111 may be bonded together using a die attach film (DAF), which is an ultra-thin film adhesive used to connect semiconductor chips to packaging substrates and chips to chips during semiconductor packaging.

[0162] Optionally, the ends of the multiple chip units 111 toward the edge of the transition substrate 20 are successively retracted; or, the ends of the multiple chip units 111 toward the edge of the transition substrate 20 are successively extended; or, the side surfaces of the ends of the multiple chip units 111 toward the edge of the transition substrate 20 are in the same plane.

[0163] FIG7 is a schematic diagram of a second example of a chip packaging structure 100 provided in an embodiment of the present application.

[0164] As shown in Figure 7, in an embodiment provided by the present application, the multiple chip units 111 of each chip unit group 11 are stacked in sequence, and the end side surfaces of the multiple chip units 111 facing the edge of the main substrate 40 are roughly in the same plane; the chip units 111 at the bottom layer of the stacked chip units 111, or the chip units 111 adjacent to the transition substrate 20, are connected to the transition substrate 20 by welding or conductive adhesive bonding; except for the chip units 111 at the bottom layer of the stacked chip units 111, the remaining chip units 111 can be electrically connected to the transition substrate 20 through wires 70.

[0165] FIG8 is a schematic diagram of a third example of a chip packaging structure 100 provided in an embodiment of the present application.

[0166] As shown in FIG8 , in an embodiment provided in the present application, in a direction away from the transition substrate 20 , the ends of multiple chip units 111 toward the edge of the transition substrate 20 are successively retracted, and the end of each chip unit 111 is connected to the main substrate 40 via a wire 70 .

[0167] It should be noted that the ends of the multiple chip units 111 toward the edge of the transition substrate 20, i.e., the position shown in the enlarged view at point C in FIG8 , are successively retracted, which can be understood as a stepped arrangement, or can also be understood as extending one section from top to bottom.

[0168] In this embodiment, the ends of the plurality of chip units 111 toward the edge of the transition substrate 20 are successively retracted, so that a portion of the substrate can be avoided from each other to facilitate the arrangement of the wires 70 .

[0169] FIG9 is a schematic diagram of a fourth example of a chip packaging structure 100 provided in an embodiment of the present application.

[0170] As shown in FIG. 9 , in an embodiment provided in the present application, a dummy die 24 is also provided on one side of the transition substrate 20 where the second chip 10 is provided.

[0171] The dummy die, also known as a fake chip, a dummy wafer, or a blank wafer, is a silicon wafer without circuits or functions, and its material is the same as that of a conventional chip. The dummy die 24 can be bonded to the transition substrate 20 using DAF adhesive.

[0172] In this embodiment, the added virtual die 24 can absorb the stress between the chip units 111 due to thermal expansion and contraction or external force, thereby improving the reliability of the second chip 10; in addition, the main raw material of the virtual die 24 is silicon, and its thermal conductivity is approximately 150W / mK, which is much greater than that of the package 50 made of air and resin. Therefore, the added virtual die 24 can quickly conduct the heat emitted by the first chip 30 to the external environment, thereby achieving a good heat dissipation effect for the entire chip packaging structure 100.

[0173] 9 , in one embodiment provided by the present application, the virtual die 24 includes a first die 241, and the first die 241 is located between the plurality of chip unit groups 11. The number of the first die 241 is not limited and can be one or more.

[0174] Specifically, a first region 231 where the second chip 10 is not mounted is defined above the middle portion of the transition substrate 20 , and the first die 241 is located in the first region 231 .

[0175] In this embodiment, the specific setting position of the virtual grain 24 (first grain 241) is further limited, that is, the virtual grain 24 is located between multiple chip unit groups 11, so that the heat conduction path passes between the chip unit groups 11, avoiding the heat emitted by the first chip 30 from affecting the chip unit group 11, thereby ensuring that the performance of the second chip 10 can be fully released.

[0176] In an embodiment provided in the present application, an orthographic projection of the first die 241 toward the main substrate 40 at least partially falls on the first chip 30 .

[0177] In this embodiment, the relative positions of the virtual die 24 (first die 241) and the first chip 30 are further limited, that is, the positive projection of the first die 241 toward the main substrate 40 at least partially falls on the first chip 30, so that the heat emitted by the first chip 30 can be conducted vertically upward to the virtual die 24. Such a heat conduction path is shorter, thereby further ensuring the heat dissipation effect of the entire chip packaging structure 100.

[0178] FIG10 is a schematic diagram of a fifth example of a chip packaging structure 100 provided in an embodiment of the present application.

[0179] As shown in Figure 10, in one embodiment provided by the present application, the virtual die 24 includes a second die 242, and the second die 242 is located at the periphery of the plurality of chip unit groups 11. The number of the second die 242 is not limited and can be one or more.

[0180] Specifically, the transition substrate 20 has a second region 232 on its periphery where the second chip 10 is not mounted, and the second die 242 is located in the second region 232 .

[0181] In this embodiment, a second die 242 located in the peripheral area of ​​the transition substrate 20 is added on the basis of the original first die 241, so that the heat conducted from the first chip 30 to the transition substrate 20 can be evenly dispersed and dissipated from multiple directions: one is to dissipate heat in the vertical direction through the first die 241, and the other is to dissipate heat in the surrounding directions through the second die 242.

[0182] In addition, in this embodiment, the area on the transition substrate 20 where the second chip 10 is not installed is utilized to install virtual grains 24 (first grain 241 and second grain 242), so that the overall structure of the chip is relatively uniform, which can further improve the structural stability during thermal expansion and contraction, and ensure the overall service life of the chip.

[0183] In order to understand the above technical effects, we need to introduce some background knowledge: As mentioned above, the chip packaging structure 100 also includes a package 50 for encapsulating the second chip 10. The material of the package 50 is resin. Since the linear expansion coefficients (sometimes also called linear elastic coefficient (linear expansivity), which indicates the degree of expansion or contraction of the material, specifically defined as the elongation per unit length of a solid substance when its temperature rises by 1°C) of resin and silicon are different, the package 50 and the second chip 10 will have different deformation amounts when they expand due to heat or contract due to cold. This will cause the second chip 10 itself and the electrical connection between the second chip 10 and the transition substrate 20 to be subjected to stress and torn in multiple directions. After long-term use, the second chip 10 will inevitably be prone to failure or the reliability of the electrical connection will be affected, thereby reducing the overall service life of the chip. In this embodiment, the area in the package 50 where the second chip 10 is not installed is filled with virtual grains 24, so that the second chip 10 and the virtual grains 24 in the package 50 are evenly dispersed. In this way, when the chip expands due to heat or contracts due to cold, the virtual grains 24 can resist or absorb part of the stress from the package 50, thereby avoiding excessive tearing effect of the package 50 on the second chip 10, thereby ensuring the structural stability of the second chip 10 itself and the electrical connection between the second chip 10 and the transition substrate 20, thereby improving the overall service life of the chip.

[0184] FIG11 is a schematic diagram of a sixth example of a chip packaging structure 100 provided in an embodiment of the present application.

[0185] As shown in FIG. 11 , in an embodiment provided in the present application, a heat sink 26 is provided inside the transition substrate 20 .

[0186] In this embodiment, a heat sink 26 is provided inside the transition substrate 20 to improve the thermal conductivity of the transition substrate 20 , which can further improve the heat dissipation effect of the first chip 30 , thereby facilitating the full release of the working performance of the first chip 30 .

[0187] Optionally, the heat sink 26 is a sheet-like body, which can be embedded in the interior of the transition substrate 20, that is, completely covered by the base material of the transition substrate 20; or, a through groove is opened in the middle of the transition substrate 20, and the heat sink 26 is fixed in the through groove by bonding, clamping, etc.

[0188] Optionally, the heat sink 26 may be made of metal or non-metal.

[0189] Specifically, when the heat sink 26 is made of non-metallic material, it can be graphite or ceramic. The thermal conductivity of the graphite sheet varies depending on the microstructure of the graphite, temperature, pressure, oxygen content and other factors. Under normal pressure, the thermal conductivity of the graphite sheet is about 130W / mK~200W / mK. In comparison, the thermal conductivity of the ceramic sheet is weaker, but it is also much greater than the thermal conductivity of resin or air. The thermal conductivity of the ceramic sheet is 2W / mK~3W / mK.

[0190] FIG12 is a top view of the transition substrate 20 provided in an embodiment of the present application.

[0191] As shown in FIG. 12 , in an embodiment provided in the present application, the orthographic projection of the heat sink 26 toward the main substrate 40 at least partially falls on the first chip 30 .

[0192] In this embodiment, the positional relationship between the heat sink 26 and the first chip 30 is further limited, that is, the positive projection of the heat sink 26 toward the main substrate 40 at least partially falls on the first chip 30, so that the heat dissipated by the first chip 30 in the vertical direction can be fully and quickly conducted to the heat sink 26, which can further improve the outward heat dissipation effect of the first chip 30.

[0193] In one embodiment provided herein, the heat sink 26 is made of metal and is used to electrically connect the second chip 10 to the main substrate 40. The metal heat sink 26 can be a single-layer or multi-layer structure. If it is a multi-layer structure, the heat sinks 26 of two adjacent layers are electrically connected through copper-plated vias 28 in the hole walls.

[0194] The metal heat sink 26 in this embodiment can be etched into a circuit pattern and embedded within the transition substrate 20. This serves to form a circuit network within the transition substrate 20 and connect the circuits between various components, effectively transmitting electrical signals and ensuring proper circuit operation. Therefore, the metal heat sink 26 in this embodiment not only dissipates heat but also constructs circuits to achieve signal transmission.

[0195] The technical principle of the heat sink 26 will now be described in detail with reference to the accompanying drawings, taking the multi-layered metal heat sink 26 as an example.

[0196] Figure 13 is a partial cross-sectional view of a transition substrate 20 provided in an embodiment of the present application. As shown in Figure 13, the transition substrate 20 is embedded with multiple layers of metal heat sinks 26. The metal heat sinks 26 of two adjacent layers are electrically connected through copper-plated vias 28 in the hole walls. The surface of the transition substrate 20 facing the second chip 10 is provided with solder pads, and these solder pads are also electrically connected to the topmost metal heat sink 26 through vias 28. The surface of the transition substrate 20 facing the main substrate 40 is also provided with solder pads, and these solder pads are also electrically connected to the bottommost metal heat sink 26 through vias 28. As a result, the solder pads on the upper and lower sides of the transition substrate 20 are electrically connected through the metal heat sink 26. The solder pads on the upper and lower sides are then electrically connected to the second chip 10 and the main substrate 40, respectively, thus achieving a sequential electrical connection between the second chip 10, the metal heat sink 26, and the main substrate 40.

[0197] In addition, the interior of the main substrate 40 also has a circuit composed of conductive metal parts such as copper sheets. The solder pads on the main substrate 40 facing the first chip 30 and the solder pads facing the transition substrate 20 are respectively electrically connected to the copper sheets, thereby achieving electrical conductivity between the solder pads. The corresponding solder pads are then electrically connected to the first chip 30 and the transition substrate 20 respectively, so that the second chip 10, the metal heat sink 26, the copper sheet, and the first chip 30 can be electrically connected in sequence, thereby realizing signal transmission between the second chip 10 and the first chip 30.

[0198] Since the metal material selected for the heat sink 26 needs to have electrical conductivity and thermal conductivity, the heat sink 26 can optionally be made of a single metal or alloy such as gold, silver, copper, iron, or aluminum.

[0199] In addition to being electrically conductive, the above-mentioned metal materials also have excellent thermal conductivity. The thermal conductivity coefficients of various metal materials are summarized as follows: the thermal conductivity coefficient of silver is 400W / mK~420W / mK; the thermal conductivity coefficient of copper is 390W / mK~400W / mK; the thermal conductivity coefficient of gold is 310W / mK~320W / mK; the thermal conductivity coefficient of aluminum is 230W / mK~240W / mK; the thermal conductivity coefficient of iron is 54W / mK~60W / mK; the thermal conductivity coefficient of aluminum alloy is 155W / mK~226W / mK; the thermal conductivity coefficient of 1050 aluminum alloy is 209W / mK; and the thermal conductivity coefficient of 6063 aluminum alloy is 201W / mK.

[0200] Silver and gold have relatively good electrical and thermal conductivity, but they are expensive, making them difficult to reduce the production cost of chip products. Iron is inexpensive, but its electrical and thermal conductivity are relatively weak, and its density is high, making it difficult to achieve thinner and lighter chip products. Aluminum is inexpensive and has a low density, but its electrical and thermal conductivity are poorer than copper. Copper offers a good balance of electrical and thermal conductivity, light weight, and low cost, so copper is the preferred material for the heat sink 26 in the embodiments of the present application.

[0201] As shown in Figure 4 , in one embodiment provided herein, the distance d between the opposing surfaces of the first chip 30 and the transition substrate 20 is 5% to 10% of the distance L between the opposing surfaces of the main substrate 40 and the transition substrate 20. For example, when the distance L = 5 mm, the distance d = 0.25 mm to 0.5 mm; when the distance L = 6 mm, the distance d = 0.3 mm to 0.6 mm. It should be noted that the distance d includes the endpoints of the aforementioned numerical range.

[0202] Due to limitations in machining accuracy, errors may occur during the manufacturing and assembly of the first chip 30, the transition substrate 20, and the main substrate 40. This requires maintaining a certain safe distance between the first chip 30 and the transition substrate 20 to prevent the transition substrate 20 from squeezing the first chip 30 during mechanical interconnection between the transition substrate 20 and the main substrate 40. However, an excessively large safe distance increases the heat transfer path, affecting the outward heat dissipation of the first chip 30. Therefore, in this embodiment, the ratio of the distance d between the first chip 30 and the transition substrate 20 to the distance L between the main substrate 40 and the transition substrate 20 is restricted. This minimizes the outward heat transfer path of the first chip 30 while maintaining a safe distance during assembly.

[0203] FIG14 is a schematic diagram of a seventh example of a chip packaging structure 100 provided in an embodiment of the present application.

[0204] As shown in FIG14 , in one embodiment provided herein, a dummy die 24 is mounted on the transition substrate 20 opposite the first chip 30. A heat sink 26 is embedded within the transition substrate 20 opposite the first chip 30. Furthermore, the top of the first chip 30 is positioned as close as possible to the bottom of the transition substrate 20. This design effectively conducts heat away from the first chip 30.

[0205] In an embodiment provided in the present application, a thermal conductive adhesive 80 is provided between the first chip 30 and the transition substrate 20 .

[0206] As mentioned above, the thermal resistance of air is extremely large, which is not conducive to heat conduction. Therefore, in this embodiment, a thermal conductive adhesive 80 is filled between the first chip 30 and the transition substrate 20 to expel the air and achieve a thermal connection between the first chip 30 and the transition substrate 20, which can improve the efficiency of heat transfer from the first chip 30 to the transition substrate 20.

[0207] Thermally conductive adhesive 80 comprises a liquid polymer matrix and a large amount of thermally conductive fillers. Liquid matrix materials include, but are not limited to, silicone resins, polyurethanes, acrylic polymers, hot melt adhesives, pressure-sensitive adhesives, and the like. Fillers include, but are not limited to, aluminum oxide, aluminum nitride, boron nitride, zinc oxide, silicon carbide, aluminum powder, and the like.

[0208] Alternatively, thermally conductive adhesive 80 may be silver paste, which primarily includes silver powder, an organic solvent, a gelling agent, and a stabilizer. Silver powder is one of the main components of silver paste, typically nano-sized silver particles, which exhibit high electrical and thermal conductivity. The thermal conductivity of silver paste is 160 W / mK.

[0209] Optionally, when insulation protection of the first chip 30 and the transition substrate 20 is ensured, liquid gallium-based alloy may be used to replace the thermal conductive adhesive 80 .

[0210] Optionally, in some other embodiments provided in the present application, the gap 21 may not be filled with the thermally conductive adhesive 80 , but a thermally conductive gasket may be provided between the first chip 30 and the transition substrate 20 .

[0211] Among them, the composition of thermal gaskets is similar to that of thermal paste. The only difference lies in the shape of the matrix. The matrix of thermal gaskets is silicone elastomer, which has weaker fluidity than liquid matrix. The fillers are the same, and aluminum oxide, aluminum nitride, boron nitride, zinc oxide, silicon carbide, aluminum powder, etc. can also be used.

[0212] FIG15 is a schematic diagram of an eighth example of a chip packaging structure 100 provided in an embodiment of the present application.

[0213] As shown in FIG. 15 , in an embodiment provided in the present application, the outer surface of the first chip 30 is coated with thermal conductive adhesive 80 .

[0214] In this embodiment, not only is the thermal conductive adhesive 80 filled between the first chip 30 and the transition substrate 20, that is, the top of the first chip 30, but the first chip 30 is also wrapped around and on the bottom by the thermal conductive adhesive 80, so that the thermal conductive adhesive 80 can also play a protective role for the first chip 30 and the electrical connection between the first chip 30 and the main substrate 40.

[0215] FIG16 is a schematic diagram of a ninth example of a chip packaging structure 100 provided in an embodiment of the present application.

[0216] As shown in FIG. 16 , in an embodiment provided in the present application, a receiving groove 27 is provided on a side of the transition substrate 20 facing the first chip 30 , and a thermal conductive adhesive 80 is provided in the receiving groove 27 .

[0217] In this embodiment, a receiving groove 27 is provided on the side of the transition substrate 20 facing the first chip 30, so that the relative position between the transition substrate 20 and the first chip 30 is thinned, thereby shortening the heat conduction path on the transition substrate 20, and filling the receiving groove 27 with thermal conductive adhesive 80, so that the heat emitted by the first chip 30 can be more easily conducted upward through the transition substrate 20 after passing through the thermal conductive adhesive 80, thereby reducing the thermal resistance of the entire heat transfer path of the first chip 30 to the outside, thereby being more conducive to heat dissipation of the first chip 30.

[0218] In one embodiment provided herein, the surface area of ​​the first chip 30 facing the transition substrate 20 is smaller than the opening area of ​​the accommodating groove 27, so that the first chip 30 can extend into the accommodating groove 27. The opening area of ​​the accommodating groove 27 can be understood as the cross-sectional area or projected outline area of ​​the accommodating groove 27.

[0219] As previously mentioned, the relationship between the distance d between the first chip 30 and the transition substrate 20 and the distance L between the main substrate 40 and the transition substrate 20 requires constraints to ensure a safe distance between the first chip 30 and the transition substrate 20 during assembly. In this embodiment, by further limiting the relationship between the opening area of ​​the accommodating recess 27 and the surface area of ​​the first chip 30, that is, by making the first chip 30 smaller than the accommodating recess 27, the first chip 30 can partially extend into the accommodating recess 27. This allows the transition substrate 20 to be assembled above the first chip 30, and the accommodating recess 27 to provide clearance for the first chip 30, preventing interference between the transition substrate 20 and the first chip 30, thereby enabling smooth assembly of the two. Therefore, this embodiment eliminates the need for specific constraints on the relationship between the distance d and the distance L, thereby reducing the difficulty of processing and assembling related components.

[0220] FIG17 is a schematic diagram of a tenth example of a chip packaging structure 100 provided in an embodiment of the present application.

[0221] As shown in FIG. 17 , in one embodiment provided in the present application, the outer surface of the support member 60 is covered with a protective adhesive 90 .

[0222] When the first chip 30 generates heat during operation, the first chip 30 conducts a large amount of heat upward to the transition substrate 20, while also conducting a small amount of heat downward to the main substrate 40. Furthermore, the linear elastic coefficients of the two are not exactly the same. This causes displacement between the solder pads of the transition substrate 20 and the solder pads of the main substrate 40 when the transition substrate 20 and the main substrate 40 expand due to heat. Furthermore, package warping occurs, i.e., the transition substrate 20 or the main substrate 40 bends, which can cause the electrical connection between the support member 60 and the transition substrate 20 and the main substrate 40 to become disconnected and ineffective. In this embodiment, the protective glue 90 is infiltrated into the area adjacent to the support member 60 within the gap 21 using the principle of capillary action, and then gradually solidifies through thermal curing. The protective glue 90 wraps around the outside of the support member 60 and the solder pad, thereby ensuring the connection strength between the support member 60 and the solder pad and preventing the electrical connection from becoming disconnected.

[0223] In summary, in this embodiment, the protective glue 90 is used to fill the area adjacent to the support member 60 in the gap 21, which can reduce the adverse effects caused by thermal expansion between the transition substrate 20 and the main substrate 40. At the same time, it can also protect the support member 60 and the pad from the influence of harmful use environments such as mechanical stretching, shearing, twisting, and vibration, thereby improving the overall reliability and service life of the chip.

[0224] Optionally, the protective glue 90 is an insulating protective glue, which can be polypropylene, polyoxymethylene, polyurethane, silicone, polyolefin resin, epoxy resin, modified epoxy resin, silicone resin, modified silicone resin, etc.

[0225] FIG18 is a schematic diagram of the eleventh example of the chip packaging structure 100 provided in an embodiment of the present application.

[0226] As shown in FIG. 18 , in an embodiment provided in the present application, the outer surface of the first chip 30 is covered with a thermal conductive adhesive 80 , and the outer surface of the support member 60 is covered with a protective adhesive 90 .

[0227] In this embodiment, there is both thermal conductive glue 80 and protective glue 90 between the transition substrate 20 and the main substrate 40, which can improve the outward heat dissipation effect of the first chip 30, facilitate the complete release of the working performance of the first chip 30, and at the same time ensure the connection strength between the support member 60 and the pad, thereby improving the overall reliability and service life of the chip.

[0228] FIG19 is a schematic diagram of the twelfth example of the chip packaging structure 100 provided in an embodiment of the present application.

[0229] As shown in FIG19 , in one embodiment provided by the present application, a dummy die 24 is installed on the transition substrate 20 at a position facing the first chip 30, and a heat sink 26 is embedded in the transition substrate 20 at a position facing the first chip 30. In addition, the top of the first chip 30 is as close to the bottom surface of the transition substrate 20 as possible, and the area adjacent to the first chip 30 in the gap 21 is filled with thermally conductive adhesive 80, and the area adjacent to the support member 60 in the gap 21 is filled with protective adhesive 90. This design can further improve the effect of heat dissipation from the first chip 30, facilitate the full release of the working performance of the first chip 30, and at the same time ensure the connection strength between the support member 60 and the pad, thereby improving the overall reliability and service life of the chip.

[0230] FIG20 is a schematic diagram of the thirteenth example of the chip packaging structure 100 provided in an embodiment of the present application.

[0231] As shown in FIG. 20 , an embodiment of the present application further provides a chip packaging structure 100 , which includes a memory chip 10 a , a logic chip 30 a , a main substrate 40 , and a packaging component 50 .

[0232] The logic chip 30a is disposed on one side of the main substrate 40. The logic chip 30a can be mounted on the transition substrate 20 by welding or conductive adhesive bonding to achieve mechanical and electrical interconnection between the memory chip 10a and the transition substrate 20.

[0233] The memory chip 10a is disposed on a side of the logic chip 30a away from the main substrate 40. The memory chip 10a can be bonded to the logic chip 30a and electrically connected to the main substrate 40. In this way, the memory chip 10a is mechanically interconnected with the main substrate 40 through the logic chip 30a, and is directly electrically interconnected with the main substrate 40.

[0234] The package 50 covers the outer surfaces of the logic chip 30 a and the memory chip 10 a , thereby protecting the logic chip 30 a and the memory chip 10 a .

[0235] The chip packaging structure 100 provided in this embodiment completely abandons the method of separately packaging the memory chip 10a and the logic chip 30a and then re-packaging them in the related art, so that the chip packaging structure 100 only undergoes one packaging step during processing. In the final chip packaging structure 100, compared with the related art, the two layers of substrates and the gap formed by the two layers of substrates are omitted, so that the mechanical interconnection path between the memory chip 10a and the logic chip 30a is shortened, thereby achieving the effect of reducing the thickness of the entire chip structure, so that the chip packaging structure 100 of the embodiment of the present application can meet the development demand of lightweight and thin smartphones; Since two layers of substrates are omitted, the path for the logic chip 30a to dissipate heat outward is also shortened, ensuring the heat dissipation effect of the logic chip 30a. More importantly, the gap is completely eliminated, so that the air thermal resistance on the heat dissipation path completely disappears, which is more conducive to the logic chip 30a to dissipate heat outward without easily triggering temperature control protection, so that the working performance of the logic chip 30a can be fully released; in addition, the electrical interconnection path between the memory chip 10a and the logic chip 30a is also shortened, which is conducive to high-speed signal transmission and power network distribution, thereby reducing signal transmission loss and the overall power consumption of the chip. Overall, the chip performance is ultimately improved.

[0236] Optionally, the logic chip 30a includes but is not limited to a central processing chip, a graphics processing chip, a digital signal processing chip, an application chip, a baseband processing chip, etc.

[0237] Optionally, the memory chip 10a includes but is not limited to a dynamic random access memory, a static random access memory, a synchronous dynamic random access memory, etc.

[0238] Optionally, the memory chip 10a and the logic chip 30a may be bonded together using DAF glue. In addition, the plurality of chip units 111 may also be bonded together using DAF glue.

[0239] Optionally, the memory chip 10 a includes a plurality of chip unit groups 11 distributed along the surface of the transition substrate 20 . The chip unit group 11 includes a plurality of stacked chip units 111 . The chip units 111 are electrically connected to the transition substrate 20 .

[0240] As shown in Figure 20, in an embodiment provided in the present application, multiple chip units 111 of each chip unit group 11 are stacked in sequence, and the outward ends are roughly on the same vertical line; the chip unit 111 at the bottom layer of the stacked chip units 111, or the chip unit 111 adjacent to the transition substrate 20, is electrically connected to the transition substrate 20 through the support member 60; except for the chip unit 111 at the bottom layer of the stacked chip units 111, the remaining chip units 111 can be electrically connected to the transition substrate 20 through the wire 70.

[0241] FIG21 is a schematic diagram of the fourteenth example of the chip packaging structure 100 provided in an embodiment of the present application.

[0242] As shown in Figure 21, in an embodiment provided in the present application, in the direction away from the main substrate 40, the ends of multiple chip units 111 toward the edge of the main substrate 40 are successively retracted, and each chip unit 111 is electrically connected to the main substrate 40 through a wire 70.

[0243] It should be noted that the ends of the plurality of chip units 111 in this embodiment facing the edge of the main substrate 40 are successively retracted, which is the same as the above-mentioned form.

[0244] In this embodiment, the ends of the plurality of chip units 111 toward the edge of the main substrate 40 are successively retracted, so that a portion of the substrate can be avoided from each other to facilitate the arrangement of the wires 70 .

[0245] FIG22 is a schematic diagram of the fifteenth example of the chip packaging structure 100 provided in an embodiment of the present application.

[0246] As shown in Figure 22, in an embodiment provided in the present application, in the direction away from the main substrate 40, for each chip unit group 11, multiple chip units 111 extend in sequence toward the end of the edge of the main substrate 40, and the end of each chip unit 111 is connected to the main substrate 40 through a support member 60.

[0247] It should be noted that the multiple chip units 111 extend out in sequence toward the end portion of the edge of the main substrate 40, which is the position shown in the enlarged view at D in Figure 20. It can be understood that the chip units 111 extend out in sequence from bottom to top, which is exactly the opposite of the sequential retraction mentioned above.

[0248] In this embodiment, multiple chip units 111 extend sequentially toward the ends of the edge of the main substrate 40, so that a portion of the base can be avoided from each other, thereby facilitating the connection of support members 60 such as metal columns to the main substrate 40 through flip-chip bonding.

[0249] In addition, the support member 60 in this embodiment has two main functions: one is to realize the electrical connection between the chip unit 111 and the main substrate 40, and the other is to provide mechanical support for the chip unit 111, thereby ensuring the stability of the chip unit 111 during the process of wrapping the package 50 to facilitate manufacturing.

[0250] FIG23 is a schematic diagram of the sixteenth example of the chip packaging structure 100 provided in an embodiment of the present application.

[0251] As shown in FIG. 23 , in an embodiment provided in the present application, a logic chip 30 a is provided with a dummy die 24 on one side of the memory chip 10 a .

[0252] In this embodiment, the added dummy die 24 can absorb the stress between the memory chips 10a due to thermal expansion and contraction or external forces, thereby improving the reliability of the memory chip 10a. In addition, the main raw material of the dummy die 24 is silicon, and its thermal conductivity or thermal conductivity is much greater than that of the package 50 made of air and resin. Therefore, the added dummy die 24 can quickly conduct the heat generated by the logic chip 30a to the external environment, thereby achieving a good heat dissipation effect for the entire chip packaging structure 100.

[0253] In one embodiment provided herein, the dummy die 24 is located between multiple chip unit groups 11. This allows the heat conduction path to pass between the chip unit groups 11, preventing the heat generated by the first chip 30 from affecting the chip unit groups 11, thereby ensuring that the performance of the memory chip 10a can be fully unleashed.

[0254] The packaging method of the chip packaging structure 100 will be described in detail below with reference to the accompanying drawings.

[0255] Figure 24 is a schematic diagram of a first example of a chip packaging method provided by an embodiment of the present application. Figure 24 (a) is a schematic diagram of a second chip 10 mounted on a transition substrate 20; Figure 24 (b) is a schematic diagram of a package 50 covering the outer surface of the second chip 10; Figure 24 (c) is a schematic diagram of a first chip 30 mounted on a main substrate 40; Figure 24 (d) is a schematic diagram of the transition substrate 20 and the main substrate 40 after being welded to the support member 60; and Figure 24 (e) is a schematic diagram of the bottom of the main substrate 40 after ball implantation.

[0256] As shown in FIG. 24 , in one embodiment provided in the present application, the chip packaging method includes the following steps.

[0257] In step 201 , as shown in (a) and (b) of FIG. 24 , a second chip 10 is mounted on a transition substrate 20 , and a package 50 is coated on the outer surface of the second chip 10 .

[0258] In step 202 , as shown in FIG. 24 ( c ), the first chip 30 is mounted on the main substrate 40 .

[0259] Step 203 : providing pads on the opposite surfaces of the transition substrate 20 and the main substrate 40 .

[0260] In step 204 , as shown in FIG. 24 ( d ), the support member 60 is welded between the pads of the transition substrate 20 and the pads of the main substrate 40 .

[0261] Optionally, as shown in (e) of FIG. 24 , balls may be planted on the bottom of the main substrate 40 to prepare for mounting the main substrate 40 on the main board in subsequent steps.

[0262] The chip packaging method provided in the embodiment of the present application can reduce one packaging step compared to the related art method of separately packaging the second chip 10 and the first chip 30 and then repackaging them, thereby reducing the cost of chip packaging. Compared to the related art, the chip structure manufactured using this chip packaging method eliminates a layer of substrate and the gap formed by the substrate, thereby shortening the mechanical interconnection path between the second chip 10 and the first chip 30, thereby achieving the effect of reducing the overall thickness of the chip structure; at the same time, the path for the first chip 30 to dissipate heat outward is also shortened, ensuring the heat dissipation effect of the first chip 30; in addition, the electrical interconnection path between the second chip 10 and the first chip 30 is also shortened, which is conducive to high-speed signal transmission and power network distribution, thereby reducing signal transmission loss and overall chip power consumption.

[0263] In addition, in this embodiment, the support member 60 is not only used to realize the mechanical interconnection between the transition substrate 20 and the main substrate 40, but also realizes the electrical interconnection between the transition substrate 20 and the main substrate 40 through the support member 60. This can eliminate the need for electrical connectors specifically used to electrically connect the transition substrate 20 and the main substrate 40, making the chip packaging structure 100 more compact.

[0264] Figure 25 is a schematic diagram of a second example of a chip packaging method provided by an embodiment of the present application. Figure 25 (a) is a schematic diagram of the second chip 10 and dummy die 24 mounted on the transition substrate 20; Figure 25 (b) is a schematic diagram of the outer surface of the second chip 10 and dummy die 24 covered with the package 50; Figure 25 (c) is a schematic diagram of the first chip 30 mounted on the main substrate 40; Figure 25 (d) is a schematic diagram of the transition substrate 20 and the main substrate 40 after being welded to the support member 60; and Figure 25 (e) is a schematic diagram of the bottom of the main substrate 40 after ball implantation.

[0265] As shown in FIG. 25 , in one embodiment provided in the present application, the chip packaging method includes the following steps.

[0266] In step 301 , as shown in (a) and (b) of FIG. 25 , a second chip 10 and a dummy die 24 are mounted on a transition substrate 20 , and a package 50 is coated on the outer surfaces of the second chip 10 and the dummy die 24 .

[0267] In step 302 , as shown in FIG. 25 ( c ), the first chip 30 is mounted on the main substrate 40 .

[0268] Step 303 : providing solder pads on the opposite surfaces of the transition substrate 20 and the main substrate 40 .

[0269] In step 304 , as shown in FIG. 25 ( d ), the support member 60 is welded between the pads of the transition substrate 20 and the pads of the main substrate 40 .

[0270] Optionally, as shown in (e) of FIG. 25 , balls may be planted on the bottom of the main substrate 40 to prepare for mounting the main substrate 40 on the main board in subsequent steps.

[0271] In this embodiment, the added virtual grain 24 can absorb the stress between the second chip 10 due to thermal expansion and contraction or external force. At the same time, the added virtual grain 24 can quickly conduct the heat emitted by the first chip 30 to the external environment, which has a good heat dissipation effect on the entire chip packaging structure 100.

[0272] Figure 26 is a schematic diagram of a third example of a chip packaging method provided by an embodiment of the present application. Figure 26 (a) is a schematic diagram of a heat sink 26 embedded in a transition substrate 20; Figure 26 (b) is a schematic diagram of a second chip 10 mounted on the transition substrate 20; Figure 26 (c) is a schematic diagram of a package 50 covering the outer surface of the second chip 10; Figure 26 (d) is a schematic diagram of a first chip 30 mounted on a main substrate 40; Figure 26 (e) is a schematic diagram of the transition substrate 20 and the main substrate 40 after being welded to a support member 60; and Figure 26 (f) is a schematic diagram of a bottom ball implanted on the main substrate 40.

[0273] As shown in FIG. 26 , in one embodiment provided in the present application, the chip packaging method includes the following steps.

[0274] In step 401 , as shown in FIG. 26 ( a ), a heat sink 26 is installed inside the transition substrate 20 .

[0275] In step 402 , as shown in (b) and (c) of FIG. 26 , a second chip 10 is mounted on the transition substrate 20 , and a package 50 is coated on the outer surface of the second chip 10 .

[0276] In step 403 , as shown in FIG. 26 ( d ), the first chip 30 is mounted on the main substrate 40 .

[0277] Step 404 : providing pads on the opposite surfaces of the transition substrate 20 and the main substrate 40 .

[0278] In step 405 , as shown in FIG. 26 ( e ), the support member 60 is welded between the pads of the transition substrate 20 and the pads of the main substrate 40 .

[0279] Optionally, as shown in (f) in FIG. 26 , balls may be planted on the bottom of the main substrate 40 to prepare for mounting the main substrate 40 on the main board in a subsequent process.

[0280] In this embodiment, by installing a heat sink 26 inside the transition substrate 20 , the thermal conductivity of the transition substrate 20 is improved, which can further improve the heat dissipation effect of the first chip 30 , and is conducive to fully releasing the working performance of the first chip 30 .

[0281] Optionally, when the heat sink 26 is made of metal, in addition to having a basic heat dissipation function, it also serves as a conductive connector and is used to construct an internal circuit of the transition substrate 20 .

[0282] FIG27 is a schematic diagram of a fourth example of a chip packaging method provided by an embodiment of the present application. FIG27(a) is a schematic diagram of a second chip 10 mounted on a transition substrate 20; FIG27(b) is a schematic diagram of a package 50 covering the outer surface of the second chip 10; FIG27(c) is a schematic diagram of a first chip 30 mounted on a main substrate 40; FIG27(d) is a schematic diagram of a region adjacent to the first chip 30 filled with thermally conductive adhesive 80; FIG27(e) is a schematic diagram of the transition substrate 20 and the main substrate 40 after being welded to the support member 60; FIG27(f) is a schematic diagram of a region adjacent to the support member 60 filled with protective adhesive 90; and FIG27(g) is a schematic diagram of a bottom ball implanted on the main substrate 40.

[0283] As shown in FIG. 27 , in one embodiment provided in the present application, the chip packaging method includes the following steps.

[0284] In step 501 , as shown in (a) and (b) of FIG. 27 , a second chip 10 is mounted on a transition substrate 20 , and a package 50 is coated on the outer surface of the second chip 10 .

[0285] In step 502 , as shown in FIG. 27 ( c ), the first chip 30 is mounted on the main substrate 40 .

[0286] Step 503 : Solder pads are respectively provided on the opposite surfaces of the transition substrate 20 and the main substrate 40 .

[0287] In step 504 , as shown in FIG. 27 ( d ), a thermal conductive adhesive 80 is filled in the area adjacent to the first chip 30 on the main substrate 40 .

[0288] In step 505 , as shown in FIG. 27 ( e ), the support member 60 is welded between the pads of the transition substrate 20 and the pads of the main substrate 40 .

[0289] In step 506 , as shown in FIG. 27 ( f ), a protective glue 90 is filled in the area between the transition substrate 20 and the main substrate 40 adjacent to the support member 60 .

[0290] Optionally, as shown in (g) of FIG. 27 , after the balls are planted on the bottom of the main substrate 40 , preparations can be made for mounting the main substrate 40 on the main board in subsequent steps.

[0291] In this embodiment, the heat dissipation effect of the first chip 30 can be further improved, which is conducive to the complete release of the working performance of the first chip 30. At the same time, it can also ensure the connection strength between the support member 60 and the pad, and improve the overall reliability and service life of the chip.

[0292] FIG28 is a schematic diagram of a fifth example of a chip packaging method provided by an embodiment of the present application. FIG28(a) is a schematic diagram of a heat sink 26 embedded in a transition substrate 20; FIG28(b) is a schematic diagram of a second chip 10 and a dummy die 24 mounted on the transition substrate 20; FIG28(c) is a schematic diagram of a package 50 covering the outer surface of the second chip 10 and the dummy die 24; FIG28(d) is a schematic diagram of a first chip 30 mounted on a main substrate 40; FIG28(e) is a schematic diagram of a region adjacent to the first chip 30 filled with thermally conductive adhesive 80; FIG28(f) is a schematic diagram of the transition substrate 20 and the main substrate 40 after being welded to the support member 60; FIG28(g) is a schematic diagram of a region adjacent to the support member 60 filled with protective adhesive 90; and FIG28(h) is a schematic diagram of a bottom bump on the main substrate 40 after the bump is implanted.

[0293] As shown in FIG. 28 , in one embodiment provided in the present application, the chip packaging method includes the following steps.

[0294] In step 601 , as shown in FIG. 28 ( a ), a heat sink 26 is installed inside the transition substrate 20 .

[0295] In step 602 , as shown in (b) and (c) of FIG. 28 , the second chip 10 and the dummy die 24 are mounted on the transition substrate 20 , and the outer surfaces of the second chip 10 and the dummy die 24 are covered with a package 50 .

[0296] In step 603 , as shown in FIG. 28 ( d ), the first chip 30 is mounted on the main substrate 40 .

[0297] Step 604 : Solder pads are respectively provided on the opposite surfaces of the transition substrate 20 and the main substrate 40 .

[0298] In step 605 , as shown in FIG. 28 ( e ), a thermal conductive adhesive 80 is filled in the area adjacent to the first chip 30 on the main substrate 40 .

[0299] In step 606 , as shown in FIG. 28 ( f ), the support member 60 is welded between the pads of the transition substrate 20 and the pads of the main substrate 40 .

[0300] In step 607 , as shown in FIG. 28 ( g ), a protective glue 90 is filled in the area between the transition substrate 20 and the main substrate 40 adjacent to the support member 60 .

[0301] Optionally, as shown in (h) of FIG. 28 , after the balls are planted on the bottom of the main substrate 40 , preparations can be made for mounting the main substrate 40 on the main board in subsequent steps.

[0302] In this embodiment, structures such as the heat sink 26, the thermal adhesive 80, and the virtual grain 24 can further improve the effect of dissipating heat from the first chip 30 to the outside, which is beneficial to the complete release of the working performance of the first chip 30; the virtual grain 24 can absorb the stress between the second chip 10 due to thermal expansion and contraction or external force, thereby improving the reliability of the second chip 10, and the protective adhesive 90 can ensure the connection strength between the support member 60 and the pad, thereby improving the overall reliability and service life of the chip.

[0303] Figure 29 is a schematic diagram of a sixth example of a chip packaging method provided by an embodiment of the present application. Figure 29 (a) shows a logic chip 30a mounted on a main substrate 40; Figure 29 (b) shows a memory chip 10a bonded to the logic chip 30a; Figure 29 (c) shows a memory chip 10a electrically connected to the main substrate 40 via a wire 70; Figure 29 (d) shows a package 50 externally encapsulating the memory chip 10a; and Figure 29 (e) shows a schematic diagram of the bottom of the main substrate 40 after ball implantation.

[0304] As shown in FIG. 29 , in one embodiment provided in the present application, the chip packaging method includes the following steps.

[0305] In step 701 , as shown in FIG. 29 ( a ), a logic chip 30 a is mounted on a main substrate 40 .

[0306] In step 702 , as shown in (b) and (c) of FIG. 29 , the memory chip 10 a is bonded onto the logic chip 30 a , and the memory chip 10 a is electrically connected to the main substrate 40 by wire bonding.

[0307] In step 703 , as shown in FIG. 29 ( d ), the outer surfaces of the memory chip 10 a and the logic chip 30 a are covered with a package 50 .

[0308] Optionally, as shown in (e) of FIG. 29 , after the balls are planted on the bottom of the main substrate 40 , preparations can be made for mounting the main substrate 40 on the main board in subsequent steps.

[0309] Wire bonding uses thin metal wires (conductors 70) and utilizes heat, pressure, and ultrasonic energy to tightly weld the two ends of the metal wires to the memory chip 10a and the main substrate 40, respectively.

[0310] The chip packaging method provided in the embodiments of the present application completely abandons the method of separately packaging the memory chip 10a and the logic chip 30a and then repackaging them in the related art. This method allows the chip packaging structure 100 to undergo only one packaging step during processing, thereby reducing the cost of chip packaging. Compared with the related art, the chip structure manufactured using this chip packaging method eliminates the two-layer substrate and the gap formed by the substrate. This shortens the mechanical interconnection path between the memory chip 10a and the logic chip 30a, thereby achieving the effect of reducing the overall thickness of the chip structure. At the same time, the path for the logic chip 30a to dissipate heat outward is also shortened, ensuring the heat dissipation effect of the logic chip 30a. In addition, the electrical interconnection path between the memory chip 10a and the logic chip 30a is also shortened, which is conducive to high-speed signal transmission and power network distribution, thereby reducing signal transmission loss and overall chip power consumption.

[0311] Figure 30 is a schematic diagram of the seventh example of the chip packaging method provided in an embodiment of the present application. Figure 30 (a) is a schematic diagram of a logic chip 30a mounted on a main substrate 40; Figure 30 (b) is a schematic diagram of a memory chip 10a bonded to the logic chip 30a; Figure 30 (c) is a schematic diagram of the memory chip 10a connected to the main substrate 40 via a support member 60; Figure 30 (d) is a schematic diagram of the external package 50 covering the memory chip 10a; and Figure 30 (e) is a schematic diagram of the bottom of the main substrate 40 after ball implantation.

[0312] As shown in FIG30 , in one embodiment provided in the present application, the chip packaging method includes the following steps.

[0313] In step 801 , as shown in FIG. 30 ( a ), a logic chip 30 a is mounted on a main substrate 40 .

[0314] Step 802 , as shown in FIG30( b ), a support member 60 is installed on the memory chip 10 a .

[0315] In step 803 , as shown in (c) of FIG. 30 , the memory chip 10 a is bonded to the logic chip 30 a , and the support member 60 is connected to the main substrate 40 by flip-chip bonding.

[0316] In step 804 , as shown in FIG. 30 ( d ), a package 50 is wrapped around the memory chip 10 a and the logic chip 30 a .

[0317] Optionally, as shown in (e) of FIG. 30 , after the balls are planted on the bottom of the main substrate 40 , preparations can be made for mounting the main substrate 40 on the main board in subsequent steps.

[0318] Optionally, the memory chip 10 a may be electrically connected to the main substrate 40 by adhesive bonding.

[0319] The adhesive bonding is to adhere the support member 60 between the memory chip 10 a and the main substrate 40 by means of a conductive adhesive, so as to achieve electrical connection between the memory chip 10 a and the main substrate 40 .

[0320] The flip-chip bonding is to prefabricate connection bumps on the main substrate 40 or the support member 60, and then heat the memory chip 10a face down to melt the bumps so that the main substrate 40 and the support member 60 are interconnected.

[0321] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A chip packaging structure, characterized in that, it includes: a main substrate (40); a first chip (30), disposed on one side of the main substrate (40); a transition substrate (20), disposed on the side of the first chip (30) away from the main substrate (40); and a second chip (10), disposed on the side of the transition substrate (20) away from the first chip (30).

2. The chip packaging structure according to claim 1, characterized in that, the first chip (30) includes a logic chip, and the second chip (10) includes a storage chip.

3. The chip packaging structure according to claim 1 or 2, characterized in that, the second chip (10) includes a plurality of chip unit groups (11), and the chip unit group (11) includes a plurality of chip units (111) arranged in a stacked manner.

4. The chip packaging structure according to claim 3, characterized in that, a dummy die (24) is further provided on the side of the transition substrate (20) where the second chip (10) is disposed.

5. The chip packaging structure according to claim 4, characterized in that, the dummy die (24) includes a first die (241), and the first die (241) is located between the plurality of chip unit groups (11).

6. The chip packaging structure according to claim 5, characterized in that, the orthographic projection of the first die (241) towards the main substrate (40) at least partially falls on the first chip (30).

7. The chip packaging structure according to any one of claims 4 - 6, characterized in that, the dummy die (24) includes a second die (242), and the second die (242) is located on the outer periphery of the plurality of chip unit groups (11).

8. The chip packaging structure according to any one of claims 1 - 7, characterized in that, a heat dissipation member (26) is disposed inside the transition substrate (20).

9. The chip packaging structure according to claim 8, characterized in that, the orthographic projection of the heat dissipation member (26) towards the main substrate (40) at least partially falls on the first chip (30).

10. The chip packaging structure according to claim 8 or 9, characterized in that, the heat dissipation member (26) is made of a metal material and is used to electrically connect the second chip (10) and the main substrate (40).

11. The chip packaging structure according to any one of claims 1 - 10, characterized in that, the distance (d) between the opposing surfaces of the first chip (30) and the transition substrate (20) is 5% - 10% of the distance (L) between the opposing surfaces of the main substrate (40) and the transition substrate (20).

12. The chip packaging structure according to any one of claims 1 - 11, characterized in that, a thermal conductive adhesive (80) is disposed between the first chip (30) and the transition substrate (20).

13. The chip packaging structure according to claim 12, characterized in that, the outer surface of the first chip (30) is coated with the thermal conductive adhesive (80).

14. The chip packaging structure according to claim 12 or 13, characterized in that, a receiving groove (27) is provided on one side of the transition substrate (20) facing the first chip (30), and the thermal conductive adhesive (80) is provided in the receiving groove (27).

15. The chip packaging structure according to claim 14, characterized in that, the surface area of one side of the first chip (30) facing the transition substrate (20) is smaller than the opening area of the receiving groove (27).

16. The chip packaging structure according to any one of claims 1-15, characterized in that, a first connecting portion (22) extending beyond the edge of the first chip (30) is provided on the periphery of the transition substrate (20), a second connecting portion (41) extending beyond the edge of the first chip (30) is provided on the periphery of the main substrate (40), pads are respectively provided on the opposite surfaces of the first connecting portion (22) and the second connecting portion (41), and a support member (60) is welded between the pad of the first connecting portion (22) and the pad of the second connecting portion (41).

17. The chip packaging structure according to claim 16, characterized in that, a protective adhesive (90) is coated on the outer surface of the support member (60).

18. The chip packaging structure according to any one of claims 1-17, characterized in that, further comprising: a packaging member (50) coated on the outer surface of the second chip (10).

19. A chip packaging structure, characterized in that, comprising: a main substrate (40); a logic chip (30a) provided on one side of the main substrate (40); a memory chip (10a) provided on the side of the logic chip (30a) away from the main substrate (40); and a packaging member (50) coated on the outer surfaces of the logic chip (30a) and the memory chip (10a).

20. The chip packaging structure according to claim 19, characterized in that, the memory chip (10a) includes a plurality of chip unit groups (11), and each chip unit group (11) includes a plurality of chip units (111) arranged in a stacked manner.

21. The chip packaging structure according to claim 20, characterized in that, in the direction away from the main substrate (40), for each chip unit group (11), the ends of the plurality of chip units (111) facing the edge of the main substrate (40) extend out in sequence, and the end of each chip unit (111) is connected to the main substrate (40) through a support member (60).

22. The chip packaging structure according to claim 20 or 21, characterized in that, a virtual die (24) is further provided on the side of the logic chip (30a) where the memory chip (10a) is provided.

23. The chip packaging structure according to claim 22, characterized in that, the virtual die (24) is located between the plurality of chip unit groups (11).

24. An electronic device, characterized in that, comprising the chip packaging structure (100) according to any one of claims 1-23.

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