Silicon carbide planar MOS device and manufacturing method therefor

Abstract

The present invention provides a silicon carbide planar MOS device and a manufacturing method therefor. According to the silicon carbide planar MOS device, at a gap, the gap on the inner side of a passivation layer is filled with a metal capping layer instead of a PI layer, such that the structure increases the effective area of a cell region and prevents the PI layer from applying a large stress to the passivation layer at the gap. That is, the stress on the passivation layer at the side wall of the gap is reduced, protecting the passivation layer and mitigating the phenomenon of cracking of the passivation layer at the side wall of the gap, thereby improving the reliability of the silicon carbide planar MOS device.

Description

A silicon carbide planar MOS device and its preparation method Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a silicon carbide planar MOS device and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC) is a representative of third-generation semiconductor materials and one of the most mature and widely used wide-bandgap semiconductor materials in terms of crystal growth technology and device manufacturing. Compared to silicon, it boasts a wider bandgap, higher thermal conductivity, higher electron saturation drift velocity, and a critical breakdown electric field 10 times that of silicon, making it an ideal semiconductor material for high-temperature, high-frequency, high-power, and radiation-resistant applications.

[0003] As shown in FIG1 , the current silicon carbide planar MOS device includes a gate structure 20 located on a silicon carbide substrate 10, a source region S located in the silicon carbide substrate 10, a dielectric layer 30 covering the gate structure 20 and the silicon carbide substrate 10, a gate metal layer 40 and a source metal layer 50 covering the dielectric layer 30, wherein the gate structure 20 exposes the source region S, the source metal layer 50 penetrates the dielectric layer 30 and contacts the source region S, and the gate metal layer 40 penetrates the dielectric layer 30 and contacts the source region S. The gate structure 20 is in contact with the gate structure 20, wherein the gate metal layer 40 and the source metal layer 50 are spaced apart and there is an etched through hole between the two. The silicon carbide planar MOS device also includes a PA layer (passivation layer) 60 and a PI (polyimide) layer 70. The PA layer 60 covers part of the source metal layer 50, covers the gate metal layer 40, and also covers the sidewalls of the etched through hole. The PI layer 70 is located on the PA layer 60 and fills the etched through hole. In the above structure, there is a weak point at the interface between the PI layer 70 and the PA layer 60 at the sidewall of the etched through hole. It is easy for the PA layer 60 to crack and generate cracks 60a, thereby affecting the reliability of the silicon carbide planar MOS device. In addition, due to the distribution of the source metal layer 50 and the gate metal layer 40, the source pad leading out of the source metal layer 50 and the gate pad leading out of the gate metal layer 40 are relatively dispersed.

[0004] Summary of the Invention

[0005] The object of the present invention is to provide a silicon carbide planar MOS device and a preparation method thereof, which can improve the cracking of the PA layer.

[0006] In order to solve the above problems, the present invention provides a silicon carbide planar MOS device, comprising:

[0007] a gate structure, located on the silicon carbide substrate;

[0008] A source region is located in the silicon carbide substrate and between two adjacent gate structures;

[0009] a dielectric layer, covering the gate structure and the silicon carbide substrate;

[0010] a gate metal layer, disposed on the dielectric layer, the gate metal layer penetrating the dielectric layer and in contact with the gate structure;

[0011] a source metal layer, disposed on the dielectric layer, the source metal layer penetrating the dielectric layer and contacting the source region, wherein a gap is provided between the gate metal layer and the source metal layer;

[0012] a passivation layer covering the gate metal layer, an inner wall of the gap, and the source metal layer near the gap;

[0013] a metal covering layer, covering the passivation layer and filling the gap;

[0014] The PI layer covers the metal covering layer.

[0015] Optionally, the thickness of the source metal layer and the gate metal layer are both 2 μm to 10 μm.

[0016] Optionally, the thickness of the metal covering layer is 2 μm to 10 μm.

[0017] Optionally, the material of the metal covering layer is selected from at least one of Al, AlCu, and AlSiCu.

[0018] Optionally, the gate structure includes a first gate structure and a second gate structure.

[0019] The first gate structure includes a gate oxide layer and a polysilicon gate, the gate oxide layer is located on the silicon carbide substrate, and the polysilicon gate is located on the gate oxide layer;

[0020] The second gate structure includes a gate oxide layer, a field oxide layer and a field plate. The gate oxide layer and the field oxide layer are adjacent to and in contact with each other and are arranged on the silicon carbide substrate. The field plate is located on the gate oxide layer and at least a portion of the field oxide layer.

[0021] Furthermore, the gate metal layer is located above the second gate structure, passes through the dielectric layer, and contacts the field plate; the source metal layer is located above the first gate structure and the source region, passes through the dielectric layer, and contacts the silicon carbide substrate of the source region;

[0022] Wherein, the gap is located above the second gate structure.

[0023] Furthermore, the metal covering layer also covers the source metal layer near the second gate structure, so that the metal covering layer is connected to the source metal layer outside the passivation layer.

[0024] On the other hand, the present invention also provides a method for preparing a silicon carbide planar MOS device, comprising the following steps:

[0025] Providing a silicon carbide substrate, wherein an active region is formed in the silicon carbide substrate, a gate structure is formed on the silicon carbide substrate, and a dielectric layer covering the gate structure and the silicon carbide substrate, wherein a first through hole and a second through hole are formed in the dielectric layer, wherein the first through hole exposes the gate structure, and the second through hole exposes the silicon carbide substrate of the source region;

[0026] Simultaneously forming a gate metal layer and a source metal layer, wherein both the gate metal layer and the source metal layer are located on the dielectric layer, and the gate metal layer fills the first through hole and contacts the gate structure, and the source metal layer fills the second through hole and contacts the source region, wherein a gap is provided between the gate metal layer and the source metal layer;

[0027] forming a passivation layer and forming a third through hole in the passivation layer, wherein the passivation layer covers the gate metal layer, an inner wall of the gap, and the source metal layer near the gap, and the third through hole is located inside the gap;

[0028] A metal covering layer and a PI layer are formed in sequence, wherein the metal covering layer covers the passivation layer and fills the third through hole, and the PI layer covers the metal covering layer.

[0029] Optionally, the method of simultaneously forming the gate metal layer and the source metal layer includes:

[0030] forming a metal film layer on the dielectric layer, wherein the metal film layer covers the dielectric layer and fills the first through hole and the second through hole;

[0031] The metal film layer is etched by an etching process to form a gate metal layer and a source metal layer, wherein the gate metal layer contacts the gate structure and the source metal layer contacts the source region; at the same time, a gap is formed to separate the gate metal layer and the source metal layer.

[0032] Optionally, a first distance exists between the side wall of the third through hole and the side wall of the gap, and a second distance exists between the bottom wall of the third through hole and the bottom wall of the gap.

[0033] Optionally, the thickness of the source metal layer and the gate metal layer are both 2 μm to 10 μm.

[0034] Optionally, the thickness of the metal covering layer is 2 μm to 10 μm.

[0035] Optionally, the material of the metal covering layer is selected from at least one of Al, AlCu, and AlSiCu.

[0036] Optionally, the metal covering layer further covers the source metal layer near the passivation layer, so that the metal covering layer is connected to the source metal layer outside the passivation layer.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] The present invention provides a silicon carbide planar MOS device and a preparation method thereof. The silicon carbide planar MOS device includes a silicon carbide substrate, a source region, a gate structure, a dielectric layer, a gate metal layer, a source metal layer, a passivation layer, a metal covering layer and a PI layer. The source region is located in the silicon carbide substrate, the gate structure is located on the silicon carbide substrate, and the source region is located between two adjacent gate structures. The dielectric layer covers the gate structure and the silicon carbide substrate. The gate metal layer and the source metal layer are simultaneously arranged on the dielectric layer, and a gap is provided between the gate metal layer and the source metal layer. The gate metal layer passes through the dielectric layer and contacts the gate structure. The source metal layer passes through the dielectric layer and contacts the source region. The passivation layer covers the gate metal layer, the inner wall (i.e., the side wall and the bottom wall) of the gap, and the source metal layer near the gap. The metal covering layer covers the passivation layer and fills the gap. The PI layer covers the metal covering layer. The present invention fills the gap inside the passivation layer with a metal covering layer at the gap instead of using a PI layer to fill the gap inside the passivation layer. This structure increases the effective area of ​​the cell region and avoids the PI layer applying a large stress to the passivation layer at the gap, that is, reduces the stress of the passivation layer on the side wall of the gap, protects the passivation layer, improves the phenomenon of cracking of the passivation layer on the side wall of the gap, and thus optimizes the reliability of the silicon carbide planar MOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] FIG1 is a schematic diagram of the cross-sectional structure of a silicon carbide planar MOS device.

[0040] FIG2 is a schematic cross-sectional view of a silicon carbide planar MOS device according to an embodiment of the present invention.

[0041] FIG3 is a schematic flow chart of a method for fabricating a silicon carbide planar MOS device according to an embodiment of the present invention.

[0042] FIG4 is a schematic diagram of the cross-sectional structure of a silicon carbide substrate provided in one embodiment of the present invention.

[0043] FIG5 is a schematic cross-sectional view of the structure after forming a gate metal layer and a source metal layer according to an embodiment of the present invention.

[0044] FIG6 is a schematic diagram of a cross-sectional structure after forming a passivation layer according to an embodiment of the present invention.

[0045] FIG7 is a schematic diagram of a cross-sectional structure after forming a metal covering layer and a PI layer according to an embodiment of the present invention.

[0046] In FIG1 , 10 is a silicon carbide substrate; 20 is a gate structure; 30 is a dielectric layer; 40 is a gate metal layer; 50 is a source metal layer; 60 is a PA layer; 60a is a crack; 70 is a PI layer;

[0047] In Figures 2 to 7: 100 - silicon carbide substrate; 110 - source region; 210 - field oxide layer; 220 - gate oxide layer; 230 - polysilicon gate; 240 - field plate; 300 - dielectric layer; 310 - first through hole; 320 - second through hole; 410 - source metal layer; 420 - gate metal layer; 430 - gap; 500 - passivation layer; 510 - third through hole; 600 - metal covering layer; 700 - PI layer. DETAILED DESCRIPTION

[0048] The following is a further detailed description of a silicon carbide planar MOS device and its fabrication method according to the present invention. The present invention will be described in more detail below with reference to the accompanying drawings, which illustrate preferred embodiments of the present invention. It should be understood that those skilled in the art may modify the present invention described herein while still achieving the beneficial effects of the present invention. Therefore, the following description should be understood as being generally known to those skilled in the art and not intended to limit the present invention.

[0049] For the sake of clarity, not all features of actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would obscure the present invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as adapting from one embodiment to another to accommodate system or business constraints. Furthermore, it should be understood that such development work may be complex and time-consuming, but is nevertheless a routine undertaking for those skilled in the art.

[0050] In order to make the purpose and features of the present invention more obvious and easy to understand, the specific embodiments of the present invention are further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0051] As shown in FIG2 , this embodiment provides a silicon carbide planar MOS device, which includes a silicon carbide substrate 100, a source region 110, a gate structure, a dielectric layer 300, a gate metal layer 420, a source metal layer 410, a passivation layer 500, a metal capping layer 600, and a PI layer 700. The source region 110 is located in the silicon carbide substrate 100, the gate structure is located on the silicon carbide substrate 100, and the source region 110 is located between two adjacent gate structures. The dielectric layer 300 covers the gate structure and the silicon carbide substrate 100. The gate metal layer 420 and the source metal layer 410 are simultaneously provided on the dielectric layer 300, and a gap 430 is provided between the gate metal layer 420 and the source metal layer 410. The gate metal layer 420 The passivation layer 500 penetrates the dielectric layer 300 and contacts the gate structure, the source metal layer 410 penetrates the dielectric layer 300 and contacts the source region 110, the passivation layer 500 covers the gate metal layer 420, the inner wall (i.e., the side wall and the bottom wall) of the gap 430, and the source metal layer 410 near the gap 430, the metal covering layer 600 covers the passivation layer 500 and fills the gap 430, and the PI layer 700 covers the metal covering layer 600.

[0052] In the silicon carbide planar MOS device of this embodiment, the gap 430 inside the passivation layer 500 is filled by the metal covering layer 600 at the gap 430, rather than the PI layer 700 filling the gap 430 inside the passivation layer 500. This structure increases the effective area of ​​the cell region and avoids the PI layer 700 applying a large stress to the passivation layer 500 at the gap 430, that is, reduces the stress of the passivation layer 500 on the side wall of the gap 430, protects the passivation layer 500, and improves the phenomenon of cracking of the passivation layer 500 on the side wall of the gap 430, thereby optimizing the reliability of the silicon carbide planar MOS device.

[0053] Specifically:

[0054] The silicon carbide substrate 100 includes a front surface and a back surface. A plurality of spaced-apart source regions 110 are provided in the front surface of the silicon carbide substrate 100. The source regions 110 may extend from the front surface of the silicon carbide substrate 100 toward the interior of the silicon carbide substrate 100. The conductivity type of the source regions 110 is N-type.

[0055] A plurality of gate structures are spaced apart on the front surface, and the gate structures are located on the silicon carbide substrate 100 , and each source region 110 is located between two adjacent gate structures. In this embodiment, the source regions 110 and gate structures are all parallel and arranged in strips.

[0056] The gate structure may include a first gate structure and a second gate structure. The first gate structure includes a gate oxide layer 220 and a polysilicon gate 230. The gate oxide layer 220 is located on the silicon carbide substrate 100, and the polysilicon gate 230 is located on the gate oxide layer 220. The second gate structure includes a gate oxide layer 220, a field oxide layer 210, and a field plate 240. The gate oxide layer 220 and the field oxide layer 210 are adjacent to and in contact with each other and are disposed on the silicon carbide substrate 100. The field plate 240 is located on the gate oxide layer 220 and at least a portion of the field oxide layer 210. The material of the field plate 240 is polysilicon. The thickness of the field oxide layer 210 is greater than the thickness of the gate oxide layer 220.

[0057] The dielectric layer 300 covers the gate structure and the silicon carbide substrate 100 between adjacent gate structures. The dielectric layer 300 is made of, for example, oxide, such as silicon dioxide.

[0058] The gate metal layer 420 and the source metal layer 410 are disposed in the same layer and are both located on the dielectric layer 300. The gate metal layer 420 is located above the second gate structure, penetrates the dielectric layer 300, and contacts the field plate 240. The source metal layer 410 is located above the first gate structure and the source region 110, penetrates the dielectric layer 300, and contacts the silicon carbide substrate 100 of the source region 110.

[0059] The gate metal layer 420 and the source metal layer 410 can both be primarily made of metal, and their materials can be selected from at least one of Al, AlCu, and AlSiCu. The gate metal layer 420 and the source metal layer 410 located on the dielectric layer 300 each have a thickness of 2 μm to 10 μm. Compared to the thickness of the gate metal layer 40 and the source metal layer 50 in the prior art, the gate metal layer 420 and the source metal layer 410 of this embodiment are thinner, reducing the height of the gap 430 and thereby reducing the stress of the passivation layer 500 at the gap 430.

[0060] The width of the gap 430 between the gate metal layer 420 and the source metal layer 410 is 5 μm to 10 μm, and the gap 430 prevents electrical connection between the gate metal layer 420 and the source metal layer 410. In this embodiment, the gap 430 is located above the second gate structure.

[0061] The passivation layer 500 covers the inner wall of the gap 430, and also covers the dielectric layer 300 near the gap 430, the gate metal layer 420, and a portion of the source metal layer 410 near the gap 430. The thickness of the passivation layer 500 on the sidewall of the gap 430 is 0.1 μm to 2 μm.

[0062] In this embodiment, the passivation layer 500 is located above the second gate structure and covers the sidewalls and bottom walls of the gap 430 , and also covers the gate metal layer 420 and the dielectric layer 300 on the gate structure, as well as the source metal layer 410 near the gap 430 .

[0063] The metal cover layer 600 covers the passivation layer 500 and also covers a portion of the source metal layer 410 near the second gate structure, so that the metal cover layer 600 is connected to the source metal layer 410 outside the passivation layer 500. The metal cover layer 600 also fills the gap 430 to protect the gap 430. Compared with the prior art, since the thickness of the gate metal layer 420 and the source metal layer 410 is thinner (i.e., the height of the gap 430 is reduced), the step height of the passivation layer 500 at the gap 430 can be reduced, thereby reducing the stress of the passivation layer 500 at the gap 430, and further improving the cracking phenomenon of the passivation layer 500 at the sidewall of the gap 430.

[0064] The thickness of the metal cover layer 600 located on the passivation layer 500 is 2 μm to 10 μm. The metal cover layer 600 can be primarily made of metal, and its material can be selected from at least one of Al, AlCu, and AlSiCu. Because the hardness of the metal cover layer 600 is lower than that of the PI layer 700, the stress of the passivation layer 500 at the gap 430 can be further reduced when the metal cover layer 600 fills the gap 430, thereby further improving the cracking phenomenon of the passivation layer 500 at the sidewall of the gap 430.

[0065] The silicon carbide planar MOS device of this embodiment further includes a gate pad and a source pad. The gate lead pad is connected to the gate metal layer 420 from above the gate metal layer 420, and the source pad is indirectly connected to the source metal layer 410 from above the metal covering layer 600. In this way, the gate pad and the source pad are concentrated above the second gate structure, that is, the gate pad and the source pad are concentrated, thereby increasing the effective area of ​​the cell region.

[0066] The silicon carbide planar MOS device further includes a drain metal layer, and the drain metal layer is located on the back side.

[0067] As shown in FIG3 , this embodiment further provides a method for preparing a silicon carbide planar MOS device, comprising the following steps:

[0068] Step S10: providing a silicon carbide substrate, wherein an active region is formed in the silicon carbide substrate, a gate structure is formed on the silicon carbide substrate, and a dielectric layer covering the gate structure and the silicon carbide substrate is formed, wherein a first through hole and a second through hole are formed in the dielectric layer, wherein the first through hole exposes the gate structure, and the second through hole exposes the silicon carbide substrate of the source region;

[0069] Step S20: Simultaneously forming a gate metal layer and a source metal layer, wherein both the gate metal layer and the source metal layer are located on the dielectric layer, and the gate metal layer fills the first through hole and contacts the gate structure, and the source metal layer fills the second through hole and contacts the source region, wherein a gap is formed between the gate metal layer and the source metal layer;

[0070] Step S30: forming a passivation layer and forming a third through hole in the passivation layer, wherein the passivation layer covers the gate metal layer, the inner wall of the gap, and the source metal layer near the gap, and the third through hole is located inside the gap;

[0071] Step S40: forming a metal covering layer and a PI layer in sequence, wherein the metal covering layer covers the passivation layer and fills the third through hole, and the PI layer covers the metal covering layer.

[0072] As shown in FIG4 , in step S10, the first through-hole 310 exposes the field plate 240 of the second gate structure, and the second through-hole 320 exposes the silicon carbide substrate 100 in the source region 110 between two adjacent gate structures. Specifically, the second through-hole 320 exposes the silicon carbide substrate 100 in the source region 110 between two adjacent first gate structures, as well as the silicon carbide substrate 100 in the source region 110 between the first and second gate structures.

[0073] As shown in FIG5 , step S20 specifically includes:

[0074] First, a metal film layer is formed on the dielectric layer 300 , the metal film layer covers the dielectric layer 300 , and the metal film layer also fills the first through hole 310 and the second through hole 320 , so that the metal film layer contacts the source region 110 and the field plate 240 of the second gate structure respectively.

[0075] Next, the metal film layer is etched through an etching process to form a gate metal layer 420 and a source metal layer 410. At this time, the gate metal layer 420 is in contact with the field plate 240 of the second gate structure, and the source metal layer 410 is in contact with the source region 110. At the same time, a gap 430 is formed on the second gate structure to separate the gate metal layer 420 and the source metal layer 410.

[0076] As shown in FIG6 , step S30 includes:

[0077] First, a passivation layer 500 is formed. The passivation layer 500 covers the gate metal layer 420 , the inner wall of the gap 430 , and the source metal layer 410 near the gap 430 .

[0078] Next, a third through hole 510 is formed in the passivation layer 500 through an etching process. The third through hole 510 is located inside the gap 430, and a first spacing is formed between the sidewalls of the third through hole 510 and the sidewalls of the gap 430, and a second spacing is formed between the bottom wall of the third through hole 510 and the bottom wall of the gap 430, so that the passivation layer 500 on the bottom inner wall of the third through hole 510 covers the inner wall and bottom wall of the gap 430. The first spacing may be equal to the second spacing, or may not be equal to the second spacing. Preferably, the first spacing may be equal to the second spacing.

[0079] Step S40 includes:

[0080] As shown in Figure 7, first, a metal covering layer 600 is formed. The metal covering layer 600 fills the third through hole 510 and covers the passivation layer 500. At the same time, it also covers part of the source metal layer 410 near the second gate structure, so that the metal covering layer 600 is connected to the source metal layer 410 outside the passivation layer 500.

[0081] As shown in FIG. 2 , a PI layer 700 is formed, and the PI layer 700 covers the metal cover layer 600 .

[0082] In summary, the present invention provides a silicon carbide planar MOS device and a method for manufacturing the same. The silicon carbide planar MOS device includes a silicon carbide substrate, a source region, a gate structure, a dielectric layer, a gate metal layer, a source metal layer, a passivation layer, a metal capping layer, and a PI layer. The source region is located in the silicon carbide substrate, the gate structure is located on the silicon carbide substrate, and the source region is located between two adjacent gate structures. The dielectric layer covers the gate structure and the silicon carbide substrate. The gate metal layer and the source metal layer are simultaneously arranged on the dielectric layer, and a gap is provided between the gate metal layer and the source metal layer. The gate metal layer passes through the dielectric layer and contacts the gate structure. The source metal layer passes through the dielectric layer and contacts the source region. The passivation layer covers the gate metal layer, the inner walls (i.e., side walls and bottom walls) of the gap, and the source metal layer near the gap. The metal capping layer covers the passivation layer and fills the gap. The PI layer covers the metal capping layer. The present invention fills the gap inside the passivation layer with a metal covering layer at the gap instead of using a PI layer to fill the gap inside the passivation layer. This structure increases the effective area of ​​the cell region and avoids the PI layer applying a large stress to the passivation layer at the gap, that is, reduces the stress of the passivation layer on the side wall of the gap, protects the passivation layer, improves the phenomenon of cracking of the passivation layer on the side wall of the gap, and thus optimizes the reliability of the silicon carbide planar MOS device.

[0083] In addition, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0084] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A silicon carbide planar MOS device, characterized in that: include: A gate structure located on a silicon carbide substrate; A source region, located in the silicon carbide substrate and between two adjacent gate structures; A dielectric layer, covering the gate structure and the silicon carbide substrate; A gate metal layer is disposed on the dielectric layer, the gate metal layer penetrates the dielectric layer and contacts the gate structure; A source metal layer is disposed on the dielectric layer, the source metal layer penetrates the dielectric layer and contacts the source region, wherein a gap exists between the gate metal layer and the source metal layer; a passivation layer covering the gate metal layer, an inner wall of the gap, and the source metal layer near the gap; a metal covering layer, covering the passivation layer and filling the gap; and The PI layer covers the metal covering layer.

2. The silicon carbide planar MOS device according to claim 1, characterized in that: The thickness of the source metal layer and the gate metal layer are both 2 μm to 10 μm.

3. The silicon carbide planar MOS device according to claim 1, characterized in that: The thickness of the metal covering layer is 2 μm to 10 μm.

4. The silicon carbide planar MOS device according to claim 1, characterized in that: The material of the metal covering layer is selected from at least one of Al, AlCu and AlSiCu.

5. The silicon carbide planar MOS device according to claim 1, characterized in that: The gate structure includes a first gate structure and a second gate structure, The first gate structure comprises a gate oxide layer and a polysilicon gate, the gate oxide layer is located on the silicon carbide substrate, and the polysilicon gate is located on the gate oxide layer; The second gate structure includes a gate oxide layer, a field oxide layer and a field plate. The gate oxide layer and the field oxide layer are adjacent to and in contact with each other on the silicon carbide substrate. The field plate is located on the gate oxide layer and at least a portion of the field oxide layer.

6. The silicon carbide planar MOS device according to claim 5, characterized in that: The gate metal layer is located above the second gate structure, the gate metal layer passes through the dielectric layer, and contacts the field plate; the source metal layer is located above the first gate structure and the source region, the source metal layer passes through the dielectric layer, and contacts the silicon carbide substrate of the source region; Wherein, the gap is located above the second gate structure.

7. The silicon carbide planar MOS device according to claim 5, characterized in that: The metal cover layer also covers the source metal layer near the second gate structure, so that the metal cover layer is connected to the source metal layer outside the passivation layer.

8. A method for preparing a silicon carbide planar MOS device, characterized in that: The following steps are involved: A silicon carbide substrate is provided, wherein an active region is formed in the silicon carbide substrate, a gate structure is formed on the silicon carbide substrate, and a dielectric layer covering the gate structure and the silicon carbide substrate is formed, wherein a first through hole and a second through hole are formed in the dielectric layer, wherein the first through hole exposes the gate structure, and the second through hole exposes the silicon carbide substrate of the source region; Simultaneously forming a gate metal layer and a source metal layer, wherein both the gate metal layer and the source metal layer are located on the dielectric layer, and the gate metal layer fills the first through hole and contacts the gate structure, and the source metal layer fills the second through hole and contacts the source region, wherein a gap exists between the gate metal layer and the source metal layer; forming a passivation layer, and forming a third through hole in the passivation layer, wherein the passivation layer covers the gate metal layer, the inner wall of the gap, and the source metal layer near the gap, and the third through hole is located inside the gap; A metal covering layer and a PI layer are formed in sequence, wherein the metal covering layer covers the passivation layer and fills the third through hole, and the PI layer covers the metal covering layer.

9. The method for preparing a silicon carbide planar MOS device according to claim 8, characterized in that: The method of simultaneously forming a gate metal layer and a source metal layer comprises: forming a metal film layer on the dielectric layer, wherein the metal film layer covers the dielectric layer and fills the first through hole and the second through hole; The metal film layer is etched by an etching process to form a gate metal layer and a source metal layer, wherein the gate metal layer contacts the gate structure and the source metal layer contacts the source region; at the same time, a gap is formed to separate the gate metal layer and the source metal layer.

10. The method for preparing a silicon carbide planar MOS device according to claim 8, characterized in that: A first distance exists between the side wall of the third through hole and the side wall of the gap, and a second distance exists between the bottom wall of the third through hole and the bottom wall of the gap.

11. The method for preparing a silicon carbide planar MOS device according to claim 8, characterized in that: The thickness of the source metal layer and the gate metal layer are both 2 μm to 10 μm.

12. The method for preparing a silicon carbide planar MOS device according to claim 8, characterized in that: The thickness of the metal covering layer is 2 μm to 10 μm.

13. The method for preparing a silicon carbide planar MOS device according to claim 8, characterized in that: The material of the metal covering layer is selected from at least one of Al, AlCu and AlSiCu.

14. The method for preparing a silicon carbide planar MOS device according to claim 8, characterized in that: The metal cover layer further covers the source metal layer near the passivation layer, so that the metal cover layer is connected to the source metal layer outside the passivation layer.

15. The method for preparing a silicon carbide planar MOS device according to claim 10, characterized in that: The first interval is equal to the second interval.

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