Display panel and display apparatus

Abstract

A display panel and a display apparatus, which belong to the technical field of displays. The display panel comprises: a first display area and at least one second display area; a plurality of first sub-pixels, which are located in the first display area; and a plurality of second sub-pixels, which are located in the second display area, wherein each of the first sub-pixels and second sub-pixels comprises a pixel circuit, each pixel circuit comprises a first-type transistor, and each second sub-pixel comprises a first sub-area and a second sub-area; and the display panel further comprises a first semiconductor layer, which comprises active portions of the first-type transistors, wherein the orthographic projection, on a substrate of the display panel, of the portion of the first semiconductor layer which is located in the second display area at least falls within the first sub-areas, the pixel circuits of the second sub-pixels are configured to allow light transmission, and the transmittance of the first sub-areas is less than that of the second sub-areas.

Description

Display panel and display device

[0001] This disclosure claims priority to the Chinese patent application filed with the Patent Office of China on December 4, 2023, with application number 202311650046.3, titled “A display panel, its preparation method, and display device,” and the Chinese patent application filed with the Patent Office of China on December 4, 2023, with application number 202323294367.2, titled “A display panel, display device,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] For mobile phone display products, improving the screen-to-body ratio has become one of the core themes of mobile phone product innovation. At present, in order to increase the screen-to-body ratio, designs such as bangs screen, widow's peak, water drop screen, and hole screen have emerged. These designs all place the camera in the non-display area and are not full screens.

[0004] In related technologies, external pixel circuits can be used to place the camera below the display area, significantly increasing the screen-to-body ratio. However, for products with facial recognition capabilities, the facial recognition sensor or infrared projector occupies a large amount of space. When the facial recognition sensor or infrared projector is placed below the display area, the limited design space no longer allows for the arrangement of the external pixel circuits. This makes placement of the facial recognition sensor or infrared projector below the display area particularly difficult.

[0005] Overview

[0006] A first aspect of the present disclosure provides a display panel, comprising:

[0007] a substrate comprising a first display area and at least one second display area, wherein the first display area at least partially surrounds the at least one second display area;

[0008] a plurality of first sub-pixels, located in the first display area;

[0009] a plurality of second sub-pixels located in the second display area, wherein the first sub-pixels and the second sub-pixels each include a pixel circuit including a first-type transistor, and the pixel circuit of the second sub-pixel includes a first sub-area and a second sub-area excluding the first sub-area;

[0010] Furthermore, the display panel further comprises:

[0011] a first semiconductor layer, located on one side of the substrate, comprising an active portion of the first type transistor;

[0012] The orthographic projection of the portion of the first semiconductor layer located in the second display area on the substrate falls on at least the first sub-area, the pixel circuit of the second sub-pixel is configured to allow light to pass through, and the transmittance of the first sub-area is less than the transmittance of the second sub-area.

[0013] Exemplarily, the second sub-pixel includes a light-emitting device, the light-emitting device includes a light-emitting area and a non-light-emitting area, the first sub-area falls within the light-emitting area, and the second sub-area includes a first sub-area falling within the light-emitting area and a second sub-area falling within the non-light-emitting area;

[0014] The transmittance of the first sub-region is smaller than the transmittance of the first sub-region, and the transmittance of the first sub-region is smaller than the transmittance of the second sub-region.

[0015] Exemplarily, the display panel includes a plurality of signal lines, and the plurality of signal lines include at least one of a gate line, a light emitting control signal line, a reset signal line, an initialization signal line, a data signal line, and a first power signal line;

[0016] The display panel further includes:

[0017] a plurality of electrode layers, comprising a source, a drain and a gate of the first type transistor, wherein the plurality of signal lines are located in the plurality of electrode layers;

[0018] Among them, the transmittance of the portion of the multiple electrode layers located in the first sub-region is lower than the transmittance of the portion located in the first sub-region; and the transmittance of the portion of the electrode layer located in the first sub-region is lower than the transmittance of the portion located in the second sub-region.

[0019] Exemplarily, the portions of the multiple electrode layers located in the first sub-region include metal, at least some of the portions of the electrode layers located in the first sub-region include light-transmitting conductive material and metal, and the portions of the multiple electrode layers located in the second sub-region include light-transmitting conductive material.

[0020] Exemplarily, the pixel circuit further includes a second type transistor, and the display panel further includes:

[0021] a second semiconductor layer, comprising an active portion of the second type transistor, wherein an orthographic projection of a portion of the second semiconductor layer located in the second display area on the substrate falls on at least the second sub-area, and the second semiconductor layer comprises a channel region and a non-channel region;

[0022] The transmittance of the second sub-region in the area where the channel area is located is smaller than the transmittance of the second sub-region in the area where the non-channel area is located.

[0023] Exemplarily, the plurality of electrode layers located in the second sub-region in the area where the channel region is located include metal and light-transmitting conductive material, and the plurality of electrode layers located in the second sub-region in the area where the non-channel region is located include light-transmitting conductive material.

[0024] Exemplarily, the plurality of electrode layers include:

[0025] a first gate layer, located on a side of the first semiconductor layer away from the substrate, comprising a gate of the first type transistor and a first electrode of a storage capacitor;

[0026] a second gate layer, located on a side of the first gate layer away from the substrate, comprising a first gate of the second type transistor and a second electrode of the storage capacitor, and the second semiconductor layer comprising an active portion of the second type transistor;

[0027] a third gate layer, located on a side of the second semiconductor layer away from the substrate, comprising at least a portion of the second gate of the second-type transistor, and the second semiconductor layer is also located on a side of the second gate layer away from the substrate;

[0028] a first source-drain conductive layer, located on a side of the second gate layer away from the substrate, comprising at least the source and drain of the first type transistor and at least part of the second type transistor;

[0029] a second source-drain conductive layer, located on a side of the first source-drain conductive layer facing away from the substrate, and including at least a portion of the source and drain of the second-type transistor;

[0030] The gate line, the light emitting control signal line, the reset signal line, and the initialization signal line are located on at least one layer of the first gate layer, the second gate layer, and the third gate layer, and the first power signal line and the data line are located on at least one layer of the first source-drain conductive layer and the second source-drain conductive layer.

[0031] Exemplarily, portions of the first gate layer, the second gate layer, and the third gate layer located in the first sub-region include metal, portions of the second sub-region located in the area where the non-channel region is located include a light-transmitting conductive material, and portions of the second gate layer and / or the third gate layer located in the second sub-region in the area where the channel region is located include a light-transmitting conductive material and metal;

[0032] The first source-drain conductive layer and the second source-drain conductive layer include metal in the first sub-region, include the light-transmitting conductive material and metal in the first sub-region, and include light-transmitting conductive material in the second sub-region.

[0033] Exemplarily, the third gate layer located in the second sub-region in the area where the channel region is located includes a first sub-layer and a second sub-layer, the material of the first sub-layer includes the metal, and the material of the second sub-layer includes the light-transmitting conductive material;

[0034] The first sub-layer is located on a side of the second sub-layer facing away from the substrate, and the orthographic projection of the first sub-layer on the substrate covers the orthographic projection of the second sub-layer on the substrate.

[0035] Exemplarily, the thickness of the light-transmitting conductive material included in the portion of the first source-drain conductive layer and the second source-drain conductive layer located in the second sub-region is greater than the thickness of the light-transmitting conductive material in the first gate layer, the second gate layer and the third gate layer located in the second sub-region.

[0036] Exemplarily, the first source-drain conductive layer further includes a connection layer connected to the second semiconductor layer, and the connection layer includes metal.

[0037] Exemplarily, the portions of the first source-drain conductive layer and the second source-drain conductive layer located in the first sub-region each include a first sub-layer and a second sub-layer, the material of the first sub-layer includes the metal, and the material of the second sub-layer includes the light-transmitting conductive material;

[0038] The second sub-layer is located on a side of the first sub-layer facing away from the substrate.

[0039] Exemplarily, the portion of the first gate layer located in the first sub-region further includes the light-transmitting conductive material.

[0040] Exemplarily, the display panel further includes:

[0041] a third source-drain conductive layer, located between the first source-drain conductive layer and the second source-drain conductive layer in the thickness direction of the substrate, the third source-drain conductive layer including at least part of the source and part of the drain of the second-type transistor;

[0042] The orthographic projection of the third source-drain conductive layer on the substrate is located in the non-light-emitting sub-region, and the third source-drain conductive layer includes a light-transmitting conductive material.

[0043] Exemplarily, the gate portion of the second type transistor in the second display area in the second gate layer and / or the third gate layer includes a first sublayer and a second sublayer, the material of the first sublayer includes the metal, and the material of the second sublayer includes the light-transmitting conductive material;

[0044] The orthographic projection of the first sublayer on the substrate and the orthographic projection of the channel region of the second semiconductor layer on the substrate have a first overlapping area, and the orthographic projection of the second sublayer on the substrate and the orthographic projection of the channel region of the second semiconductor layer on the substrate have a second overlapping area,

[0045] A size of the first overlapping region in a first direction is greater than a size of the second overlapping region in the first direction, where the first direction is a direction from the channel region to the non-channel region.

[0046] Exemplarily, portions of the second gate layer and the third gate layer serving as gates of the second-type transistors in the first display area include a metal conductive layer; an orthographic projection of the metal conductive layer on the substrate and an orthographic projection of the channel region of the second semiconductor layer on the substrate have a third overlapping area;

[0047] The size of the third overlapping region in the first direction is equal to the size of the first overlapping region in the first direction.

[0048] Exemplarily, the second display area includes a middle display area and a transition area from the middle display area to the first display area;

[0049] Part or all of the signal lines located in the transition region include metal and light-transmitting conductive material.

[0050] Exemplarily, the display panel further includes:

[0051] a light shielding layer, located on a side of the first semiconductor layer close to the substrate;

[0052] The portion of the light shielding layer located in the first sub-region includes metal and light-transmitting conductive material, and the portion of the light shielding layer located in the second sub-region includes light-transmitting conductive material.

[0053] A second aspect of the present disclosure provides a display device, comprising the display panel described in any one of the embodiments in the first aspect.

[0054] A third aspect of the present disclosure provides a method for manufacturing a display panel as described in the first aspect, wherein the method comprises:

[0055] forming a first semiconductor layer on a substrate;

[0056] forming a first gate layer on a side of the first semiconductor layer facing away from the substrate;

[0057] forming a second gate layer on a side of the first gate layer facing away from the substrate;

[0058] forming a second semiconductor layer on a side of the second gate layer facing away from the substrate;

[0059] forming a third gate layer on a side of the second semiconductor layer facing away from the substrate;

[0060] forming a first source-drain conductive layer on a side of the third gate layer facing away from the substrate;

[0061] forming a second source-drain conductive layer on a side of the first source-drain conductive layer facing away from the substrate;

[0062] The transmittance of the first gate layer, the second gate layer, and the third gate layer located in the first display area and the first sub-area is lower than the transmittance of the first gate layer, the second gate layer, and the third gate layer located in the second sub-area.

[0063] The transmittance of a portion of the first source-drain conductive layer located in the first sub-region is lower than the transmittance of a portion located in the second sub-region.

[0064] Exemplarily, the method further includes:

[0065] forming an insulating layer on a side of the first gate layer facing away from the substrate;

[0066] A first source-drain conductive layer is formed on a side of the first gate layer facing away from the substrate, comprising:

[0067] forming a first via hole in the insulating layer;

[0068] A metal layer is patterned in the first display area and the first sub-area, wherein the metal layer is overlapped with the active portion of the first type transistor and part of the active portion of the second type transistor through the first via hole;

[0069] forming a second via hole in the insulating layer;

[0070] A transparent conductive layer is patterned in the second sub-area, and the transparent conductive layer is overlapped with a part of the active portion of the second type transistor through the second via hole. The material of the transparent conductive layer includes a light-transmitting conductive material

[0071] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below.

[0072] BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for the description of the embodiments or related technologies. Obviously, the drawings described below are some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. It should be noted that the scales in the drawings are for illustration only and do not represent the actual scale.

[0074] FIG1A is a schematic cross-sectional view of a display panel according to an embodiment of the present application;

[0075] 1B and 1C are diagrams illustrating the characteristics of a low-temperature polysilicon transistor and an oxide transistor, respectively;

[0076] FIG. 2A (1), FIG. 2A (2), FIG. 2B (1), and FIG. 2B (2) are schematic top views of four display panels provided in embodiments of the present application;

[0077] FIG3 is a schematic diagram illustrating the arrangement of pixel circuits in a first display area and a second display area of ​​a display panel provided by an embodiment of the present application;

[0078] 4A-5C show circuit structure diagrams of several pixel circuits in embodiments of the present disclosure;

[0079] FIG6A schematically shows a light transmittance diagram of a first sub-pixel and a second sub-pixel in an embodiment of the present disclosure;

[0080] FIG6B shows a schematic diagram of a planar area division of the area where the second sub-pixel and the first sub-pixel are located in an embodiment of the present disclosure;

[0081] 7A , 9 , and 8A respectively illustrate schematic cross-sectional structures of several regions AA22 in the second display region in an embodiment of the present disclosure;

[0082] FIG7B shows a schematic diagram of the layout of the electrode layer in FIG7A ;

[0083] FIG8B shows a schematic diagram of the layout of the electrode layer in FIG8A ;

[0084] FIG10 shows a schematic cross-sectional structure diagram of the AA11 area in the first display area in an embodiment of the present disclosure;

[0085] 11A-12B are schematic cross-sectional views of several display panels according to embodiments of the present disclosure;

[0086] FIG13 is a partial schematic diagram showing the region where the second type transistor T5 is located in the diagram shown in FIG11A ;

[0087] FIG14 shows a schematic diagram of the distribution of the electrode layer in FIG11A ;

[0088] FIG15 shows a schematic diagram of the distribution of the electrode layer in FIG11B ;

[0089] FIG16 shows a schematic diagram of the distribution of the electrode layer in FIG11C ;

[0090] FIG17 shows a schematic diagram of the distribution of the electrode layer in FIG11D ;

[0091] FIG18 shows a schematic diagram of the distribution of the electrode layer in FIG11E ;

[0092] FIG19 shows a schematic diagram of the distribution of the electrode layer in FIG12A ;

[0093] 20A and 21 are schematic top views of the active portion and gate of two second-type transistors, respectively;

[0094] FIG20B shows an enlarged schematic diagram of the channel region in FIG20A ;

[0095] FIG. 22 is an enlarged schematic diagram showing the area where the second display area AA2 and the first display area AA1 in FIG. 3 intersect.

[0096] Detailed description

[0097] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0098] In this specification, the terms "electrically connected" and "coupled" include components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0099] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0100] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, that is, meaning "including, but not limited to."

[0101] In the embodiments of this application, "same layer" refers to the relationship between multiple film layers formed from the same material after the same step (e.g., a one-step patterning process). "Same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same. Polygons in this specification are not strictly defined and can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, etc., and some small deformations due to tolerances may exist.

[0102] In the embodiment of the present application, the source and drain of the transistor can be interchanged. In the embodiment of the present application, one of the source and drain of the transistor can also be referred to as the first electrode, and the other of the source and drain can be referred to as the second electrode.

[0103] Figure 1A provides a schematic diagram of the cross-sectional structure of a display panel in a related art. In Figure 1A, it can be seen that a pixel circuit is provided in the display area of ​​the display panel. Since the overall transmittance of the pixel circuit and the wiring between the pixel circuits is very low, it is impossible to set sensors (such as ambient light sensors, distance sensors, face recognition sensors), cameras and other devices below the display area (the side of the substrate away from the pixel circuit in Figure 1A); for this reason, for smaller sensors, the related art adopts the method of relocating the pixel circuit in the display area above the sensor (for example, the pixel circuit in the area corresponding to the sensor is externalized to the display area outside the area corresponding to the sensor) to improve the transmittance of the area corresponding to the sensor, thereby increasing the screen-to-body ratio of the display product, and improving the aesthetics and user experience of the display product.

[0104] However, for products with facial recognition functions, since the facial recognition sensor or infrared projector occupies a large space, when the facial recognition sensor or infrared projector is set below the display area, the arrangement of the external pixel circuit can no longer meet the requirements of the design space, and it is difficult to increase the transmittance of the local area of ​​the display area corresponding to the facial recognition sensor or infrared projector, which makes it particularly difficult to set the facial recognition sensor or infrared projector below the display area.

[0105] Based on this, an embodiment of the present application provides a display panel, a preparation method thereof, and a display device. The display panel, as shown in Figure 3, includes a first display area AA1 and at least one second display area AA2; the first display area AA1 includes a plurality of first sub-pixels P1; the second display area AA2 includes a plurality of second sub-pixels P2, and the first sub-pixel P1 and the second sub-pixel P2 both include pixel circuits and light-emitting devices. In the following embodiments, the pixel circuit in the first sub-pixel P1 is referred to as a first pixel circuit Pc1, and the pixel circuit in the second sub-pixel P1 is referred to as a second pixel circuit Pc2.

[0106] In which, the pixel circuits of the first sub-pixel P1 and the second sub-pixel P2 both include a first-type transistor T3, and the pixel circuit of the second sub-pixel P2 includes a first sub-area AK1 and a second sub-area AK2; and, the display panel also includes a first semiconductor layer 4, and the first semiconductor layer 4 includes an active portion of the first-type transistor T3; wherein, the orthographic projection of the portion of the first semiconductor layer 4 located in the second display area AA2 on the substrate 1 of the display panel falls on at least the first sub-area AK1, and the pixel circuit of the second sub-pixel P2 is configured to allow light to pass through, and the transmittance of the first sub-area AK1 is less than the transmittance of the second sub-area AK2.

[0107] Among them, sub-pixels are arranged in the first display area AA1 and the second display area AA2. Specifically, the sub-pixel located in the first display area AA1 can be a first sub-pixel P1, and the sub-pixel located in the second display area AA2 can be called a second sub-pixel P2. The first sub-pixel P1 and the second sub-pixel P2 both include pixel circuits and light-emitting devices Q, and the circuit structures of the pixel circuits of the first sub-pixel P1 and the second sub-pixel P2 can be the same.

[0108] Among them, the pixel circuit of the second sub-pixel P2 is configured to allow light to pass through, so that the entire second display area AA2 is light-transmissive, and sensors (such as ambient light sensors, distance sensors, face recognition sensors), cameras and other devices can be set in the area below the second display area AA2 of the display panel, thereby not affecting the use of the sensor below the display screen, and there is no need for the pixel circuit to bypass the sensor setting, so that the sensor setting is no longer limited by the design space.

[0109] Furthermore, the first semiconductor layer 4 in the second display area AA2 can be located in the first sub-area AK1 of the pixel circuit of the second sub-pixel P2. The transmittance of the first sub-area AK1 is less than the transmittance of the second sub-area AK2. Thus, in the second display area AA2, a first sub-area AK1 with smaller transmittance can be provided to ensure light shielding of the active part of the first type transistor T3 to a certain extent, thereby ensuring the performance of the first type transistor T3, so that the second display area AA2 has light transmittance without affecting the use of the sensor, while ensuring the driving performance of the second sub-pixel P2 in the second display area AA2.

[0110] Hereinafter, the display panel and its manufacturing method, and the display device provided by the embodiments of the present application will be specifically described and introduced with reference to the accompanying drawings.

[0111] An embodiment of the present application provides a display panel, as shown in FIG. 2A (1) and FIG. 2B (1) and FIG. 2B (2), FIG. 2A and FIG. 2B respectively show top views of four display panels, and the display panel includes:

[0112] Substrate 1 includes a first display area AA1 and at least one second display area AA2. For example, the at least one second display area AA2 may include one, two, or three second display areas AA2. The second display area AA2 may be circular, racetrack-shaped, or polygonal in shape. As shown in FIG3 , FIG3 illustrates the arrangement of pixel circuits in the first and second display areas. The first display area AA1 includes a plurality of first sub-pixels P1 arranged in an array, and the second display area AA2 includes a plurality of second sub-pixels P2 arranged in an array.

[0113] 7A and 7B , FIG. 7A shows a schematic cross-sectional structure diagram of the AA22 region in FIG. 3 , and FIG. 7B shows a schematic cross-sectional structure diagram of the electrode layer in FIG. 7A . The first subpixel P1 and the second subpixel P2 both include pixel circuits, each including a first-type transistor T3 . The pixel circuit of the second subpixel P2 includes a first sub-area AK1 and a second sub-area AK2 .

[0114] And, the display panel further includes:

[0115] a first semiconductor layer 4 including an active portion of the first type transistor T3;

[0116] Among them, the orthographic projection of the portion of the first semiconductor layer 4 located in the second display area AA2 on the substrate 1 of the display panel falls on at least the first sub-area AK1, the pixel circuit of the second sub-pixel P2 is configured to allow light to pass through, and the transmittance of the first sub-area AK1 is less than the transmittance of the second sub-area AK2.

[0117] In this embodiment, the transmittance of the second display area AA2 may be greater than that of the first display area AA1. Thus, the transmittance of the pixel circuit of the second sub-pixel P2 may be greater than that of the pixel circuit of the first sub-pixel P1.

[0118] The transmittance may refer to light transmittance, including infrared light transmittance and visible light transmittance.

[0119] In this embodiment, as shown in Figure 3, the pixel circuit of the first sub-pixel P1 is called the first pixel circuit Pc1, and the pixel circuit of the second sub-pixel P2 is called the second pixel circuit Pc2. The circuit structures of the first pixel circuit Pc1 and the second pixel circuit Pc2 can be the same. Exemplarily, the structures of the equivalent circuits of the first pixel circuit Pc1 and the second pixel circuit Pc2 are the same.

[0120] In this embodiment, the shape of the plane figure of the above-mentioned second display area AA2 is not limited. For example, the shape of the plane figure of the above-mentioned second display area AA2 may include a polygon, an arc, or a combination of a polygon and an arc, wherein the combination of a polygon and an arc refers to a figure of a spliced ​​shape of a polygon and an arc, or a figure formed by removing a local area on a polygon or an arc.

[0121] In some embodiments, the first display area AA1 may surround the second display area AA2; in other embodiments, the first display area AA1 may partially surround the second display area AA2, that is, a portion of the outer contour of the second display area AA2 is surrounded by the first display area AA1.

[0122] The display area AA includes a first display area AA1 and a second display area AA2 , and both the first display area AA1 and the second display area AA2 can emit display light.

[0123] As shown in FIG2A , a second display area AA2 may be included. As shown in (1) in FIG2A , the second display area AA2 may be located in the middle position of one side of the display area, for example, in the middle position of the uppermost side of the display area; or, in some examples, as shown in (2) in FIG2A , the second display area AA2 may be located at a position other than the middle position of one side of the display area, such as an area to the left of the upper edge of the display area AA1, for example, the upper left corner of the entire display area.

[0124] As shown in FIG2B , a plurality of second display areas AA2 may be included, for example, three second display areas AA2 or two second display areas AA2 may be included, wherein the shapes of the plurality of second display areas AA2 may be consistent, as shown in FIG2B (1), the three second display areas AA2 are all circular; or, in some examples, the shapes of the plurality of second display areas AA2 are not completely consistent, for example, the shapes of the plurality of second display areas AA2 are different, as shown in FIG2B (2), one of the two second display areas AA2 is a rounded rectangle, and the other second display area is a circle.

[0125] In the case of including multiple second display areas AA2 , when the multiple second display areas AA2 have the same shape, the sizes of the multiple second display areas AA2 may not be completely consistent, and the size refers to the plane area of ​​the second display area AA2 .

[0126] In some embodiments, the display colors of the light-emitting devices Q of each sub-pixel in the above-mentioned display panel can be the same; in some embodiments, the above-mentioned display panel simultaneously includes multiple sub-pixels displaying different colors, for example, simultaneously including red sub-pixels, green sub-pixels and blue sub-pixels, so that multiple first sub-pixels P1 simultaneously include red sub-pixels, green sub-pixels and blue sub-pixels, and multiple second sub-pixels P2 simultaneously include red sub-pixels, green sub-pixels and blue sub-pixels.

[0127] In some embodiments, the number of the second sub-pixels P2 is less than the number of the first sub-pixels P1.

[0128] In some embodiments, the density of the second sub-pixels P2 can be smaller than that of the first sub-pixels P1, where density refers to the number of sub-pixels per unit area. This can provide a larger area and a higher light-transmitting area for the pixel circuit of each second sub-pixel P2.

[0129] In an exemplary embodiment, the display panel may be an organic light emitting diode (OLED) display panel, or a WOLED display panel. Each sub-pixel includes a pixel circuit (including a first pixel circuit Pc1 and a second pixel circuit Pc2) and a light-emitting device Q connected to the pixel circuit, for example, a light-emitting device Q1 connected to the first pixel circuit Pc1 and a light-emitting device Q2 connected to the second pixel circuit Pc2.

[0130] The light-emitting device (including Q1 and Q2) may include a light-emitting functional layer and an anode 18 and a cathode 22 located on opposite sides of the light-emitting functional layer. The anode 18 may be located on a side of the light-emitting functional layer close to the substrate 1, and the cathode 22 may be located on a side of the light-emitting functional layer facing away from the substrate 1. The pixel circuit of the sub-pixel (including a first pixel circuit Pc1 and a second pixel circuit Pc2) may be connected to the anode 18 of the light-emitting device (including Q1 and Q2), thereby driving the light-emitting device to emit light.

[0131] Among them, the luminous colors of all light-emitting devices can be the same, for example, all light-emitting devices emit blue light; for another example, all light-emitting devices emit white light; in this case, when used as a display, a color conversion layer needs to be set on the light-emitting side of the light-emitting device, for example, a color filter (Color Filter) can be set on the light-emitting side of the light-emitting device, such as a red filter, a green filter and a blue filter; for another example, different color quantum dot layers (QD Film) can be set on the light-emitting side of the light-emitting device, such as a red quantum dot layer, a green quantum dot layer and a white resin layer, the blue light emitted by the light-emitting functional layer passes through the red quantum dot layer and then emits red light, the blue light emitted by the light-emitting functional layer passes through the green quantum dot layer and then emits green light, and the blue light emitted by the light-emitting functional layer passes through the white resin layer and then emits blue light, thereby realizing a colored display.

[0132] In an exemplary embodiment, the display panel includes a plurality of light-emitting devices emitting different colors, for example, a red light-emitting device, a green light-emitting device, and a blue light-emitting device.

[0133] In this embodiment, as shown in FIG3 , the display panel further includes a plurality of data lines DL and a plurality of gate lines GL. The data lines and the gate lines intersect to define a plurality of sub-pixel areas PA. The pixel circuits and light-emitting devices of the sub-pixels may all be located in the sub-pixel areas PA.

[0134] In this embodiment, the pixel circuit structures of the first pixel circuit Pc1 and the second pixel circuit Pc2 may be the same. For example, the first pixel circuit Pc1 and / or the second pixel circuit Pc2 may include two transistors and one capacitor (2T1C); or, the first pixel circuit Pc1 and / or the second pixel circuit Pc2 may include four transistors and two capacitors (4T2C); or, the first pixel circuit Pc1 and / or the second pixel circuit Pc2 may include five transistors and two capacitors (5T2C); or, the first pixel circuit Pc1 and / or the second pixel circuit Pc2 may include six transistors and two capacitors (6T1C); or, the first pixel circuit Pc1 and / or the second pixel circuit Pc2 may include seven transistors and one capacitor (7T1C); or, the first pixel circuit Pc1 and / or the second pixel circuit Pc2 may include eight transistors and one capacitor (8T1C).

[0135] In this display panel, the pixel circuits of all sub-pixels may include a first-type transistor T3, wherein the first-type transistor T3 may be a driving transistor of the pixel circuit, used to drive the light-emitting device to emit light. Please refer to Figures 4A-4B and 5A-5C, which respectively show schematic diagrams of circuit structures of various pixel circuits. As shown in Figures 4A-5C, the first-type transistor T3 may be the transistor T3 in Figures 4A-5C. The first-type transistor T3 may be a polysilicon transistor or an oxide transistor. Different types of driving transistors may have slightly different circuit structures of pixel circuits. For example, Figures 4A and 4B show pixel circuits when the first-type transistor T3 is a polysilicon transistor, and Figures 5A-5C show pixel circuits when the first-type transistor T3 is an oxide transistor.

[0136] In an example of the display panel provided in this embodiment, the first pixel circuit Pc1 and the second pixel circuit Pc2 may also include a second type transistor. In an exemplary embodiment, the first type transistor T3 may be a driving transistor, and the second transistor may be at least one of a light emitting control transistor, a reset transistor, and an initialization transistor.

[0137] Among them, the first type transistor T3 can be a polysilicon transistor, and the second type transistor is an oxide transistor; or, the first type transistor T3 and the second type transistor are both oxide transistors; in an exemplary embodiment, the polysilicon transistor may include a low-temperature polysilicon transistor (LTPS); and the oxide transistor may include a metal oxide transistor (MOS).

[0138] 1B and 1C provide diagrams illustrating transistor characteristics of a polysilicon transistor and an oxide transistor, wherein the oxide transistor has better light transmittance than the polysilicon transistor.

[0139] For example, if the first-type transistor T3 is a polysilicon transistor, its pixel circuit can be shown in Figures 4A-4B ; for example, if the first-type transistor T3 is an oxide transistor, its pixel circuit can be shown in Figures 5A-5C . It can be seen that when the type of the first-type transistor T3 is different, the pixel circuit has certain differences.

[0140] Among them, some of the multiple second-type transistors can be connected to the first-type transistor T3. In the first pixel circuit Pc1 and the second pixel circuit Pc2, the transistors other than the first-type transistor T3 can be called second-type transistors. As shown in Figures 4A to 5A, the second-type transistors include transistor T1, transistor T2, transistor T4, transistor T5, transistor T6 and transistor T7; among them, transistor T5 and transistor T6 are directly connected to the first-type transistor T3.

[0141] 5B to 5C , the second type transistors include transistor T1 , transistor T2 , transistor T4 , transistor T5 , and transistor T6 , wherein transistors T4 , T5 , and transistor T6 are directly connected to the first type transistor T3 .

[0142] It should be noted that the subsequent FIG. 7A to FIG. 12B only show the cross-sectional structural schematic diagrams of the first type transistor 3 and the second type transistors T4 , T5 and T6 directly connected thereto, and the other cross-sectional schematic diagrams are not shown in this embodiment.

[0143] Please refer to Figures 7A to 10. Figures 7A to 9 show schematic cross-sectional structural diagrams of the AA22 area in the second display area AA2 in Figure 3, and Figure 10 shows a schematic cross-sectional structural diagram of the AA11 area in the first display area AA1 in Figure 3. The second pixel circuit Pc2 shown in Figures 7A and 9 is the circuit structure shown in Figures 4A to 4B. The second pixel circuit Pc2 includes seven transistors and a capacitor (7T1C). The first type transistor T3 can be connected to the second type transistor T5 and the second type transistor T6.

[0144] The second pixel circuit Pc2 shown in Figure 8A is the circuit structure shown in Figures 5B-5C, and Figure 8B shows a schematic diagram of the electrode layer in Figure 8A. As shown in Figures 8A and 8B, the second pixel circuit Pc2 includes 6 transistors and 1 capacitor (6T1C), and the first type transistor T3 can be connected to the second type transistor T4 and the second type transistor T6.

[0145] The first pixel circuit Pc1 shown in FIG. 10 has the circuit structure shown in FIG. 4A-FIG . 4B .

[0146] The circuit structure of the first pixel circuit Pc1 and / or the second pixel circuit Pc2 is described in detail at the end of this document.

[0147] In this display panel, the second pixel circuit Pc2 of the second subpixel P2 is configured to allow light to pass through, thereby making the second display area AA2 light-transmissive and ensuring the normal operation of the sensor below the second display area AA2. Specifically, the transmittance of the first pixel circuit Pc1 of the first subpixel P1 can be lower than the transmittance of the second pixel circuit Pc2 of the second subpixel P2. As shown in Figure 6A, the amount of light passing through the first pixel circuit Pc1 is lower than the amount of light passing through the second pixel circuit Pc2, thereby ensuring the quality of the display image of the display panel.

[0148] Among them, the transmittance of the first pixel circuit Pc1 can be made smaller than the transmittance of the second pixel circuit Pc2 by setting the materials and / or sizes of the wiring and devices in the first pixel circuit Pc1. For example, materials with different transmittances can be selected as wiring and devices for the first pixel circuit Pc1 and the second pixel circuit Pc2, so that the transmittance of the first pixel circuit Pc1 can be smaller than the transmittance of the second pixel circuit Pc2 of the second sub-pixel P2; for another example, wiring and devices of different sizes (including thickness and width) can be selected for the first pixel circuit Pc1 and the second pixel circuit Pc2, so that the transmittance of the first pixel circuit Pc1 can be smaller than the transmittance of the second pixel circuit Pc2 of the second sub-pixel P2.

[0149] In this embodiment, please refer to Figures 11A-12B, where Figures 11A-11D and Figure 12A show schematic cross-sectional structures of the AA22 region in the second display area AA2, and Figures 11E and 12B show schematic cross-sectional structures of the AA11 region in the first display area AA1.

[0150] As shown in Figures 11A-12B, taking the case where the circuit structures of the first pixel circuit Pc1 and the second pixel circuit Pc2 are the same as an example, the display panel may include a first semiconductor layer 4, and the first semiconductor layer 4 may include at least an active portion of a first-type transistor T3, wherein the first semiconductor layer 4 includes a portion located in the first display area AA1 and a portion located in the second display area AA2. More specifically, the first semiconductor layer 4 includes the active portion of the first-type transistor T3 of the first pixel circuit Pc1 of the multiple first sub-pixels P1 located in the first display area AA1, and the active portion of the first-type transistor T3 of the second pixel circuit Pc2 of the multiple second sub-pixels P2 located in the second display area AA2.

[0151] The intersection of the gate and data lines of the display panel forms a sub-pixel area PA, which includes the sub-pixel's light-emitting device and pixel circuit. The light-emitting device includes an anode 18, a cathode 22, and a light-emitting functional layer 21 located between the anode 18 and the cathode 22.

[0152] In some examples, please continue to combine with Figures 7A, 8A and 10, the orthographic projection of the pixel circuit on the substrate 1 may overlap with the orthographic projection of the anode 18 on the substrate 1. For example, the orthographic projection of the second pixel circuit Pc2 on the substrate 1 may overlap with the orthographic projection of the anode 18 of the light-emitting device Q2 on the substrate 1. In this case, the orthographic projection of the active part of the first-type transistor T3 of the second pixel circuit Pc2 on the substrate 1 may overlap with the orthographic projection of the anode 18 on the substrate 1. For example, the orthographic projection of the active part of the first-type transistor T3 of the second pixel circuit Pc2 on the substrate 1 is located within the orthographic projection of the anode 18 on the substrate 1, or the orthographic projection of the active part of the first-type transistor T3 of the second pixel circuit Pc2 on the substrate 1 partially overlaps with the orthographic projection of the anode 18 on the substrate 1.

[0153] In some other examples, please refer to Figure 9, the orthographic projection of the pixel circuit on the substrate 1 may overlap with the orthographic projection of the anode 18 on the substrate 1. For example, the orthographic projection of the second pixel circuit Pc2 on the substrate 1 may overlap with the orthographic projection of the anode 18 of the light-emitting device Q2 on the substrate 1. In this case, the orthographic projection of the active part of the first type transistor T3 of the second pixel circuit Pc2 on the substrate 1 may not overlap with the orthographic projection of the anode 18 on the substrate 1.

[0154] Similarly, the overlapping relationship between the first pixel circuit Pc1 and the anode 18 , and the overlapping relationship between the active portion of the first type transistor T3 of the first pixel circuit Pc1 and the anode 18 , can refer to the overlapping relationship between the second pixel circuit Pc2 and the anode 18 .

[0155] As shown in FIG6B , a planar schematic diagram of a second sub-pixel P2 in the AA22 area in the second display area AA2 is shown. For the second sub-pixel P2, the second pixel circuit Pc2 of the second sub-pixel P2 may include a first sub-area AK1 and a second sub-area AK2. The second sub-area AK2 may be an area other than the first sub-area AK1 in the second pixel circuit Pc2 of the second sub-pixel. Specifically, the orthographic projection of the portion of the first semiconductor layer 4 located in the second display area AA2 on the substrate 1 of the display panel falls at least on the first sub-area AK1.

[0156] Among them, the positive projection of the part of the first semiconductor layer 4 located in the second display area AA2 on the substrate 1 of the display panel falls on at least the first sub-area AK1, which may mean that: the positive projection of the active part of the first type transistor T3 in the second pixel circuit in the first semiconductor layer 4 on the substrate 1 of the display panel falls on the first sub-area AK1.

[0157] As shown in Figure 11A, the first sub-region AK1 can be understood as the area of ​​the positive projection of the active part of the first semiconductor layer 4 of the first type transistor T3 in the second pixel circuit Pc2 on the substrate 1 of the display panel; in this way, the first sub-region AK1 can coincide with the positive projection of the part of the active part of the first semiconductor layer 4 located in the second display area AA2 on the substrate 1 of the display panel.

[0158] In this display panel, when the transmittance of the second display area AA2 is greater than the transmittance of the first display area AA1, the transmittance of the first sub-area AK1 within the second display area AA2 may be lower than the transmittance of the second sub-area AK2. In an exemplary embodiment, the transmittance of the first sub-area AK1 may be higher than the transmittance of the first display area AA1 and lower than the transmittance of the second sub-area AK2.

[0159] Among them, when the transmittance of the first sub-area AK1 is relatively low, the transmittance of infrared light or visible light in this area is slightly low, thereby having a shading effect on the first type transistor T3 of the second pixel circuit Pc2 in the second sub-pixel P2, thereby ensuring the performance of the first type transistor T3. At the same time, by setting the second sub-area AK2 with a relatively large transmittance, the overall transmittance of the second display area AA2 can be guaranteed so as not to affect the use of the sensor SE set under the screen.

[0160] The sensor SE may be an infrared sensor and / or a camera. The number of the sensor SE may be one or more.

[0161] In one example, the second pixel circuit Pc2 of the second sub-pixel P2 may include a circuit structure located in the first sub-area AK1 (hereinafter referred to as the first circuit portion) and a circuit structure located in the second sub-area AK2 (hereinafter referred to as the second circuit portion), wherein the transmittance of the first sub-area AK1 is lower than the transmittance of the second sub-area AK2, which can be achieved in the following manner:

[0162] Method 1: The transmittance of the materials of the wiring and the components in the first circuit portion may be set so that the transmittance of the first circuit portion is smaller than the transmittance of the second circuit portion.

[0163] Method 2: By setting the thickness and / or line width of the routing in the first circuit portion, the routing in the first circuit portion and the routing in the second circuit portion are made to have a transmittance of less than that of the second circuit portion while maintaining electrical properties; for example, the thickness of the routing in the first circuit portion is greater than the thickness of the routing in the second circuit portion; generally, the smaller the thickness of the film layer, the higher the transmittance.

[0164] In the display panel provided by the embodiments of the present application, the first display area AA1 includes a plurality of first sub-pixels P1 arranged in an array, and the second display area AA2 includes a plurality of second sub-pixels P2 arranged in an array; the second pixel circuit Pc2 of the second sub-pixel P2 is configured to allow light to pass through, so that the second display area AA2 can be transparent or translucent, so that sensors (such as ambient light sensors, distance sensors, sensors for face recognition, fingerprint sensors, etc.), cameras and other devices can be set in the area below the second display area AA2 in the display panel, thereby enabling the display panel to be manufactured as a full screen. And on this basis, in the second sub-pixel P2, the transmittance of the first sub-area AK1 where the active part of the first type transistor T3 of the second pixel circuit Pc2 is located can be lower than the transmittance of the second sub-area AK2 outside the first sub-area AK1. Thus, the light shielding property of the active part of the first type transistor T3 of the second pixel circuit Pc2 can be ensured, thereby maintaining the electrical performance of the driving element (first type transistor T3) in the second pixel circuit Pc2, so as to ensure the normal driving of the second sub-pixel P2 and improve the display quality of the display panel.

[0165] In at least one display panel provided in an embodiment of the present application, please refer to Figure 6B and Figures 11A-12B, the second sub-pixel P2 located in the second display area AA2 includes a light-emitting device Q2, and the light-emitting device Q2 includes a light-emitting area KK2 and a non-light-emitting area FKK2. The orthographic projection of the first sub-area AK1 on the substrate 1 is located within the orthographic projection of the light-emitting area KK2 on the substrate 1, and the second sub-area AK2 includes a first sub-area AK21 falling into the light-emitting area KK2 and a second sub-area AK22 falling into the non-light-emitting area FKK2; wherein, the transmittance of the first sub-area AK1 is less than the transmittance of the first sub-area AK21, and the transmittance of the first sub-area AK21 is less than the transmittance of the second sub-area AK22.

[0166] In this exemplary embodiment, the light-emitting region KK2 may be a pixel opening defined by the pixel definition layer 19. Referring to FIG. 7A , the light-emitting device Q2 of the second sub-pixel P2 includes an anode 18, a cathode 22, and a light-emitting functional layer 21. The orthographic projection of the anode 18 on the substrate may overlap the orthographic projection of the light-emitting functional layer 21 on the substrate, and the orthographic projection of the cathode on the substrate may overlap the orthographic projection of the light-emitting functional layer 21 on the substrate. The light-emitting region KK2 refers to the region where the light-emitting functional layer 21 emits light when driven by the current between the anode 18 and the cathode 22. Generally speaking, the light-emitting region is the overlapping region of the orthographic projections of the anode 18, the light-emitting functional layer 21, and the cathode 22 on the substrate. Therefore, the light-emitting device Q2 includes the light-emitting region KK2 and the non-light-emitting region FKK2.

[0167] In this way, the luminous area refers to the area in the first sub-pixel P1 and / or the second sub-pixel P2 that can emit display light, and the non-luminous area refers to the area in the light-emitting device that cannot emit display light (including the area where circuits and wiring are set).

[0168] For example, as shown in conjunction with Figures 6B and 11A-11D, the light-emitting device Q2 in the second display area includes a light-emitting area KK2 and a non-light-emitting area FKK2. As shown in Figures 6B, 11E, and 12B, the light-emitting device Q1 in the first display area includes a light-emitting area KK1 and a non-light-emitting area FKK1. As described above, the areas of the light-emitting areas of the light-emitting devices Q2 and Q1 can be consistent with the area occupied by the 19-pixel opening in the pixel definition layer, or smaller than the area occupied by the pixel opening, and the light-emitting functional layer 21 is disposed in the pixel opening.

[0169] Among them, the luminous area refers to the area in the first sub-pixel P1 and / or the second sub-pixel P2 that can emit display light, and the non-luminous area refers to the area in the light-emitting device that cannot emit display light (including the area where circuits and wiring are set).

[0170] For example, as shown in Figure 6B, the light-emitting area KK2 refers to the area covered by the orthographic projection of the second anode layer 18b on the substrate 1, and the non-light-emitting area FKK2 refers to the area in the sub-pixel area PA except the area covered by the orthographic projection of the second anode layer 18b on the substrate 1.

[0171] As shown in the above embodiment, the orthographic projection of the second pixel circuit Pc2 on the substrate 1 may overlap with the orthographic projection of the anode 18 on the substrate 1 , and the second pixel circuit Pc2 may include a portion located in the light-emitting area KK2 and a portion located in the non-light-emitting area FKK2 .

[0172] As shown in Figure 6B, the second pixel circuit Pc2 and the first pixel circuit Pc1 can also include a portion that is not located in the light-emitting area KK2 and a portion that is not located in the non-light-emitting area FKK2. For example, the second pixel circuit Pc2 includes a portion that is neither located in the light-emitting area KK2 nor in the non-light-emitting area FKK2.

[0173] As shown in Figure 11A, the first sub-area AK1 where the active portion 4 of the first type transistor T3 in the second pixel circuit Pc2 is located can fall into the light-emitting area KK2. In this way, the part of the first semiconductor layer 4 used as the active portion 4 of the first type transistor T3 in the second pixel circuit Pc2, the orthographic projection on the substrate 1 can fall into the light-emitting area KK2, that is, the orthographic projection of the active portion of the first type transistor T3 in the second pixel circuit Pc2 on the substrate 1 can be covered by the orthographic projection of the anode 18 on the substrate 1.

[0174] In the following exemplary embodiments, it is described as an example that the first sub-area AK1 where the active portion of the first-type transistor T3 in the second pixel circuit Pc2 is located may fall into the light-emitting area KK2 .

[0175] As shown in Figure 6B and Figures 11A-12B, the sub-pixel area PA of the second sub-pixel P2 can be divided into a light-emitting area KK2 and a non-light-emitting area FKK2 as a whole, wherein the first sub-area AK1 is located in the light-emitting area KK2, and the second sub-area AK2 may include an area in the second pixel circuit Pc2 except the first sub-area AK1, wherein the portion of the second sub-area AK2 located in the light-emitting area KK2 is called a first sub-area AK21, and the portion located in the non-light-emitting area FKK2 is called a second sub-area AK22.

[0176] In this display panel, the transmittance of the first sub-area AK1 is lower than that of the first sub-area AK21, and the transmittance of the first sub-area AK21 is lower than that of the second sub-area AK22. Thus, the transmittance of the second pixel circuit Pc2 located below the light-emitting device of the second sub-pixel P2 can gradually increase from the active portion of the first-type transistor T3 outward.

[0177] In one embodiment, the transmittance of the first sub-area AK21 is greater than the transmittance of the first sub-area AK1, which means that the overall transmittance of the circuit structure located in the first sub-area AK21 is greater than the overall transmittance of the circuit structure located in the first sub-area AK1; the transmittance of the second sub-area AK22 is greater than the transmittance of the first sub-area AK21, which means that the overall transmittance of the circuit structure located in the second sub-area AK22 is greater than the overall transmittance of the circuit structure located in the first sub-area AK21.

[0178] In one example, the transmittance of the first sub-area AK21 can be greater than the transmittance of the first sub-area AK1 by: the transmittance of the material of some or all traces (including components) in the circuit structure located in the first sub-area AK21 is greater than the transmittance of the material of some or all traces (including components) in the circuit structure located in the first sub-area AK1. Alternatively, the dimensions of some or all traces (including components) in the circuit structure located in the first sub-area AK21 are smaller than the dimensions of some or all traces (including components) in the circuit structure located in the first sub-area AK1, and such dimensions may include thickness and / or line width.

[0179] In one example, the transmittance of the second sub-area AK22 can be greater than the transmittance of the first sub-area AK21 by: the transmittance of the material of some or all traces (including components) in the circuit structure located in the second sub-area AK22 is greater than the transmittance of the material of some or all traces (including components) in the circuit structure located in the first sub-area AK21. Alternatively, the dimensions of some or all traces (including components) in the circuit structure located in the second sub-area AK22 are smaller than the dimensions of some or all traces (including components) in the circuit structure located in the first sub-area AK21, and these dimensions may include thickness and / or line width.

[0180] In this embodiment, please continue to combine with Figures 6B and 12B. For the first sub-pixel P1 in the first display area AA1, the first sub-pixel P1 may also include a light-emitting device Q1. The light-emitting device Q1 includes a light-emitting area KK1 and a non-light-emitting area FKK1. Similarly, the light-emitting area KK1 in the first sub-pixel P1 is the positive projection part of the anode 18 in the light-emitting device Q1 in the first sub-pixel P1 on the substrate 1; the non-light-emitting area FKK1 may refer to the part of the sub-pixel area PA where the first sub-pixel P1 is located except for the positive projection of the anode 18 in the light-emitting device Q1 on the substrate 1.

[0181] Among them, the transmittance of the light-emitting area KK1 in the first display area AA1 can be lower than the transmittance of the light-emitting area KK2 in the second display area AA2. At the same time, the transmittance of the non-light-emitting area FKK1 in the first display area AA1 can be lower than the transmittance of the non-light-emitting area FKK2 in the second display area AA2, which will not be elaborated here.

[0182] In this embodiment, in the second pixel circuit Pc2, the active portion of the first type transistor T3 of the second pixel circuit Pc2 faces outward, and the transmittance of the second pixel circuit Pc2 can gradually increase. As a result, the electrical connection performance of the components and wiring in the second pixel circuit Pc2, such as ensuring sufficient resistivity, can be guaranteed, and the electrical performance of the components in the second pixel circuit Pc2 (such as the first type transistor T3) can be guaranteed, and the light transmittance of the area where the second sub-pixel P2 is located can be guaranteed.

[0183] As described above, the first pixel circuit Pc1 and the second pixel circuit Pc2 may include a first type transistor T3 and a second type transistor. In conjunction with FIG. 7B and FIG. 11A-12B , a display panel in an exemplary embodiment may further include the following structure:

[0184] The second semiconductor layer 10 includes an active portion of a second type transistor; wherein, the orthographic projection of a portion of the second semiconductor layer 10 located in the second display area AA2 on the substrate 1 at least partially falls on the second sub-area AK2, and the second semiconductor layer 10 includes a channel area H1 and a non-channel area H2; wherein, the transmittance of the second sub-area AK2 in the area H1 where the channel area is located may be less than the transmittance of the second sub-area AK2 in the area H2 where the non-channel area is located.

[0185] The first semiconductor layer 4 and the second semiconductor layer 10 may be arranged in different layers.

[0186] The pixel circuit may include a first-type transistor T3 and multiple second-type transistors, and the second semiconductor layer 10 may include active portions of the multiple second-type transistors. The portion of the second semiconductor layer 10 located in the second display area AA2 may fall within the second sub-area AK2 and may not overlap with the first sub-area AK1. Specifically, as shown in FIG11A , the second semiconductor layer 10 (including 10A and 10B) in the second pixel circuit Pc2 may include a portion located in the first sub-area AK21 and a portion located in the second sub-area AK22.

[0187] As shown in FIG13 , FIG13 shows a local schematic diagram of the area where the second-type transistor T5 is located in the figure shown in FIG11A . As shown in FIG13 , the portion of the second semiconductor layer serving as the active portion of the second-type transistor T5 may include a channel region and a non-channel region. The channel region may be a region overlapping with the second gate 12A and the first gate 8A of the second-type transistor. The non-channel region refers to a region other than the channel region in the active portion of the second-type transistor T5.

[0188] Among them, the area H1 where the channel region is located refers to: the part of the channel region in the active part of the second type transistor T5 in the second pixel circuit that falls within the orthographic projection of the channel region on the substrate; the area H2 where the non-channel region is located refers to the part of the non-channel region in the active part of the second type transistor T5 in the second pixel circuit that falls within the orthographic projection of the substrate.

[0189] The region H2 where the non-channel region is located may include the source 14A of the second type transistor T5 , and the region H1 where the channel region is located may be a region overlapping with the second gate 12A and the first gate 8A of the second type transistor.

[0190] Specifically, within the second sub-area AK2, the transmittance of the second sub-area AK2 in the region H1 where the channel region is located is lower than the transmittance of the second sub-area AK2 in the region H2 where the non-channel region is located. Thus, the transmittance of the regions above and below the channel region of the second semiconductor layer 10 in the second pixel circuit Pc2 can be slightly lower than that of the regions outside the second sub-area AK2. This improves the light shielding of the second semiconductor layer 10, thereby ensuring the electrical performance of the second-type transistor and maintaining the performance of the switching element in the second pixel circuit Pc2.

[0191] The upper area of ​​the channel region of the second semiconductor layer 10 refers to the area of ​​the channel region of the second semiconductor layer 10 facing away from the substrate 1 , and the lower area of ​​the channel region of the second semiconductor layer 10 refers to the area of ​​the channel region of the second semiconductor layer 10 close to the substrate 1 .

[0192] The area outside the second sub-area AK2 may refer to an area in the second sub-area AK2 excluding the orthographic projection of the channel area of ​​the second semiconductor layer 10 on the substrate 1 , also referred to as a non-channel area H2 .

[0193] Among them, the setting of the second semiconductor layer 10 of other second-type transistors in the second pixel circuit Pc2 can be the same as the setting of the above-mentioned second semiconductor layer 10. For example, the structure of the area where the second-type transistor T6 in Figure 11A is located can be shown in Figure 13, which will not be repeated here.

[0194] The transmittance of the second sub-area AK2 in the region H1 where the channel region is located is lower than the transmittance of the second sub-area AK2 in the region H2 where the non-channel region is located can be achieved as follows:

[0195] Implementation method one: set the transmittance of the material of the wiring and components in the channel region of the second semiconductor layer 10 of the second pixel circuit Pc2 away from the side of the substrate 1 to be lower than the transmittance of the material of the wiring and components in the area other than the channel region in the second sub-area AK2; and / or, the transmittance of the material of the wiring and components in the channel region of the second semiconductor layer 10 of the second pixel circuit Pc2 close to the side of the substrate 1 is lower than the transmittance of the material of the wiring and components in the second sub-area AK2 except the channel region.

[0196] Similarly, the area outside the second sub-area AK2 may refer to an area H2 in the second sub-area AK2 excluding the orthographic projection H1 of the channel region of the second semiconductor layer 10 on the substrate 1 .

[0197] Implementation method two: set the size of the routing of the channel region of the second semiconductor layer 10 of the second pixel circuit Pc2 away from the side of the substrate 1 to be greater than the thickness of the routing in the second sub-area AK2 except the area H1 where the channel region is located; and / or, the size of the routing of the channel region of the second semiconductor layer 10 of the second pixel circuit Pc2 close to the side of the substrate 1 is greater than the thickness of the routing in the second sub-area AK2 except the area H1 where the channel region is located.

[0198] Implementation method three is a combination of implementation method one and implementation method two.

[0199] In a display panel provided in one embodiment, as shown in Figures 11A-12B , the various components of the pixel circuit (first-type transistor T3, second-type transistor, and storage capacitor) and wiring (wires connecting the various components) can be fabricated on various film layers of the display panel. The film layer fabricated with the wiring and some components can be referred to as an electrode layer. The display panel can include multiple signal lines connected to the first sub-pixel P1 and the second sub-pixel P2, the multiple signal lines including at least a gate line, a light-emitting control signal line, a reset signal line, an initialization signal line, a data signal line, and a first power signal line. The display panel can also include:

[0200] a plurality of electrode layers, including a source, a drain and a gate of each transistor, wherein a plurality of signal lines are located in the plurality of electrode layers;

[0201] The transmittance of the electrode layers in the first sub-area AK1 is lower than that in the first sub-area AK21 ; and the transmittance of the electrode layers in the first sub-area AK21 is lower than that in the second sub-area AK22 .

[0202] In this embodiment, FIG14 shows a schematic diagram of the distribution of the electrode layers in FIG11A . As shown in FIG14 , the multiple electrode layers can be provided in different layers and can be provided in different layers from the first semiconductor layer 4. The multiple electrode layers can include the source, drain, and gate of each transistor, and each transistor can include a first-type transistor T3 and a second-type transistor.

[0203] In some examples, the plurality of electrode layers may also be different from the second semiconductor layer 10 ( 10A and 10B).

[0204] For example, taking Figures 7A and 7B as an example, the electrode layer may include the gate 6B of the first type transistor T3, the active portion 10A of the second type transistor T5, the active portion 10B of the second type transistor T6, the first gate 8A and the second gate 12A of the second type transistor T5, the first gate 8C and the second gate 12B of the second type transistor T6, the first electrode 14A and the second electrode 14B of the second type transistor T5, and the first electrode 14C and the second electrode 14D of the second type transistor T6, as well as the electrode 17B connected to the second electrode 14D of the second type transistor T6, and the electrode 17A connected to the first electrode 14A of the second type transistor T5.

[0205] 11A-12B , the transmittance of the electrode layer in the first sub-area AK1 is lower than that in the first sub-area AK21 , and the transmittance of the electrode layer in the first sub-area AK21 is lower than that in the second sub-area AK22 .

[0206] The portion of the electrode layer located in the first sub-area AK1 may refer to a portion of the electrode layer whose orthographic projection on the substrate 1 falls into the first sub-area AK1 .

[0207] As described above, the desired transmittance can be achieved by configuring the components and materials of the pixel circuit. In a further embodiment, the portions of the multiple electrode layers located in the first sub-area AK1 include metal, at least some of the electrode layers located in the first sub-area AK21 include a light-transmitting conductive material and metal, and the portions of the multiple electrode layers located in the second sub-area AK22 include a light-transmitting conductive material.

[0208] In this embodiment, for each electrode layer, the portion thereof located in the first sub-area AK1 may include metal, and the portion thereof located in the second sub-area AK22 may include a light-transmitting conductive material.

[0209] For example, as shown in FIG14 , in the film layer where the electrode layer 14A is located (hereinafter referred to as the first source-drain conductive layer), the portion located in the first sub-area AK1 includes the second electrode 14B of the second-type transistor T5 and the first electrode 14C of the second-type transistor T6. Electrodes 14B and 14C may be made of metal. The portion located in the second sub-area AK2 includes the first electrode 14A of the second-type transistor T5 and the second electrode 14D of the second-type transistor T6. Electrodes 14A and 14D may be made of a light-transmitting conductive material.

[0210] In some examples, for part of the electrode layer or each electrode layer, the portion located in the first sub-region AK21 may include light-transmitting conductive material and metal, for example, the electrode layer connected to the second type transistor and the electrode layer belonging to the source, gate and drain of the second type transistor, these electrode layers may include light-transmitting conductive material and metal in the portion of the first sub-region AK21, and the remaining electrode layers may include light-transmitting conductive material.

[0211] For example, the portion of the gate 12B of the second-type transistor T6 located in the first sub-region AK21 may include a light-transmitting conductive material and metal, while the portion of the gate 12B located in the second sub-region AK21 may also include a light-transmitting conductive material and metal. The portion of the second electrode 14D of the second-type transistor T6 located in the second sub-region AK22 may also include a light-transmitting conductive material. In this way, the active portion 10B of the second-type transistor T6 can be partially shielded from light by the mixed-metal gate, thereby ensuring the electrical characteristics of the second-type transistor T6.

[0212] As described above, when the pixel circuit of the sub-pixel includes a second-type transistor and the display panel includes a second semiconductor layer 10 (10A, 10B), as shown in FIG13 , the transmittance of the second sub-area AK2 in the region H1 where the channel region of the second semiconductor layer 10 (10A, 10B) is located is lower than the transmittance of the second sub-area AK2 in the region H2 where the non-channel region of the second semiconductor layer 10 (10A, 10B) is located. Thus, in another display panel provided in one embodiment, a portion of the plurality of electrode layers located in the region H1 where the channel region of the second sub-area AK2 is located in the second semiconductor layer 10 (10A, 10B) includes metal, and a portion of the second sub-area AK2 located in the region H2 where the non-channel region is located, excluding the region H1 where the channel region is located, includes a light-transmitting conductive material.

[0213] In the display panel of this embodiment, for an electrode layer, the electrode layer includes a portion located in the second sub-area AK2. If it further includes a portion located in the area H1 where the channel region of the second semiconductor layer 10 (10A, 10B) is located (8A, 12A, 8C and 12B in Figure 11A), then the electrode layer of this portion includes metal.

[0214] If the portion of the electrode layer including the second sub-region AK2 also includes a portion of the area H2 where the non-channel region is located (for example, 14A, 14D, 17A and 17B in FIG11A ), the electrode layer of this portion includes a light-transmitting conductive material.

[0215] The metal may be an opaque metal, such as any one or more of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), nickel (Ni) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb).

[0216] Among them, the light-transmitting conductive material may refer to a light-transmitting conductive material, such as but not limited to indium tin oxide (ITO), indium zinc oxide (IZO), graphene, PEDOT [polymer of EDOT (3,4-ethylenedioxythiophene monomer)], metal grid, carbon nanotubes, carbon nanorods (carbon nanobuds), silver nanowires (SNW, silver nanowire), etc.

[0217] In this embodiment, the electrode layer is located in the region H1 where the channel region of the second semiconductor layer 10 (10A, 10B) in the second sub-region AK2 is located, and the portion includes metal, which can improve the shielding of the channel region H1 in the second semiconductor layer 10 (10A, 10B), thereby reducing the exposure of the channel region to light (visible light and infrared light), thereby ensuring the electrical performance of the second type transistors (T5 and T6).

[0218] In a display panel provided in one embodiment, referring to FIG. 7B to FIG. 10 , the plurality of electrode layers may include the following structure:

[0219] a first gate layer 6 , located on a side of the first semiconductor layer 4 away from the substrate 1 , comprising a gate 6B of the first type transistor T3 and a first electrode 6A of the storage capacitor as shown in FIG8A ;

[0220] The first source-drain conductive layer 14 - 1 is located on a side of the first gate layer 6 away from the substrate 1 and includes at least the source and drain of the first type transistor T3 and part of the source and drain of the second type transistor;

[0221] The second gate layer 8 is located on the side of the second semiconductor layer 10 close to the substrate 1, as shown in FIG7B , and includes a portion of the first gate of the second type transistor. The second semiconductor layer 10 includes the active portion of the second type transistor and the second electrode 8B of the storage capacitor.

[0222] The third gate layer 12 is located on a side of the second semiconductor layer 10 away from the substrate 1 and includes at least part of the second gate of the second type transistor; the first source-drain conductive layer 14-1 is located on a side of the third gate layer 12 away from the substrate 1;

[0223] The second source-drain conductive layer 17 is located on a side of the first source-drain conductive layer 14 - 1 facing away from the substrate 1 , and includes at least a portion of the source and drain of the second type transistor;

[0224] The gate line, light emitting control signal line, reset signal line, and initialization signal line are located on at least one layer of the first gate layer 6, the second gate layer 8, and the third gate layer 12, and the first power signal line and the data line are located on at least one layer of the first source-drain conductive layer 14-1 and the second source-drain conductive layer 17.

[0225] In this embodiment, referring to Figures 7A, 7B, 9, and 10, wherein Figure 7B shows a schematic diagram of the electrode layer in Figure 7A, the display panel may include a substrate 1, a first semiconductor layer 4 located on one side of the substrate 1, a first gate insulating layer 5 located on a side of the first semiconductor layer 4 facing away from the substrate 1, a first gate layer 6 located on a side of the first gate insulating layer 5 facing away from the substrate 1, and a second gate insulating layer 7 located on a side of the first gate layer 6 facing away from the substrate 1; the first gate layer 6 includes a gate 6B of a first-type transistor T3; the first semiconductor layer 4 includes an active portion of the first-type transistor T3;

[0226] a second gate layer 8 located on the side of the second gate insulating layer 7 facing away from the substrate 1 , the second gate layer 8 including a second electrode 8B of the storage capacitor, a first gate 8A of the second type transistor T5 , and a first gate 8C of the second type transistor T6 ;

[0227] a third gate insulating layer 9 located on a side of the second gate layer 8 facing away from the substrate 1 , and a second semiconductor layer 10 located on a side of the third gate insulating layer 9 facing away from the substrate 1 , wherein the second semiconductor layer 10 includes an active portion 10A of the second type transistor T5 and an active portion 10B of the second type transistor T6 ;

[0228] a fourth gate insulating layer 11 located on a side of the second semiconductor layer 10 facing away from the substrate 1 , and a third gate layer 12 located on a side of the fourth gate insulating layer 11 facing away from the substrate 1 , wherein the third gate layer 12 includes a second gate 12A of the second-type transistor T5 and a second gate 12B of the second-type transistor T6 ;

[0229] As shown in FIG7B , the fifth gate insulating layer 13 is located on the side of the third gate layer 12 facing away from the substrate 1, and the first source-drain conductive layer 14 - 1 is located on the side of the fifth gate insulating layer 13 facing away from the substrate 1. The first source-drain conductive layer 14 - 1 includes the second electrode 14B of the second-type transistor T5 and the first electrode 14C of the second-type transistor T6.

[0230] a passivation layer 15 located on a side of the first source-drain conductive layer 14-1 facing away from the substrate 1, and a second source-drain conductive layer 17 located on a side of the passivation layer 15 facing away from the substrate 1, wherein the second source-drain conductive layer 17 includes an electrode 17A connected to the first electrode 14A of the second-type transistor T5, and an electrode 17B connected to the second electrode 14D of the second-type transistor T6;

[0231] A second flat layer 16-2 is located on the side of the second source-drain conductive layer 17 facing away from the substrate 1, an anode 18 (including a first anode 18 layer 18a and a second anode layer 18b) is located on the side of the second flat layer facing away from the substrate 1, and a pixel definition layer 19 is located on the side of the anode 18 facing away from the substrate 1. The pixel definition layer 19 includes an opening area, a light-emitting functional layer 21 is included in the opening area, and a cathode 22 is located on the side of the light-emitting functional layer 21 facing away from the substrate 1; the orthographic projections of the anode 18 and the cathode 22 on the substrate 1 can respectively cover the orthographic projections of the opening on the substrate 1.

[0232] In this embodiment, as shown in Figures 7A, 9 and 10, a third source-drain conductive layer 14-2 may be further included between the first source-drain conductive layer 14-1 and the second source-drain conductive layer 17. The third source-drain conductive layer 14-2 includes a first electrode 14A of the second type transistor T5 and a second electrode 14D of the second type transistor T6.

[0233] A first planarization layer 16 - 1 is further included between the third source-drain conductive layer 14 - 2 and the second source-drain conductive layer 17 .

[0234] The anode 18 may include a first anode layer 18A and a second anode layer 18b located on the side of the first anode layer 18A facing away from the substrate 1 , and the orthographic projection of the first anode layer 18A on the substrate 1 may overlap with the orthographic projection of the second anode layer 18b on the substrate 1 .

[0235] In this embodiment, please refer to Figure 8A. Unlike Figure 7A, Figure 9 and Figure 10, the first gate layer 6 can also include a first electrode 6A of the storage capacitor, and the fifth gate insulation layer 13 further includes a passivation layer 15A on the side facing away from the substrate 1. The first source-drain conductive layer 14-1 is located on the side of the passivation layer 15A facing away from the substrate 1. The first source-drain conductive layer 14-1 includes a first electrode 14A of the second type transistor T5, a first electrode 14C of the second type transistor T4, and a second electrode 14D of the second type transistor T6.

[0236] In this embodiment, as shown in Figures 11A-11C , unlike Figures 7A , 9 , and 10 , the source and drain electrodes of the first-type transistor T3 and the second-type transistor connected to the first-type transistor T3 can both be located in the first source-drain conductive layer 14-1, which does not include the third source-drain conductive layer 14-2. In this case, the first source-drain conductive layer 14-1 includes the first electrode 14A and the second electrode 14B of the second-type transistor T5, and the first electrode 14C and the second electrode 14D of the second-type transistor T6.

[0237] Among them, the gate 6B in the first gate layer 6, the portion of the second electrode 14B and the portion of the first electrode 14C in the first source-drain conductive layer 14-1, and the first semiconductor layer 4 can serve as the structure of the first-type transistor T3. The orthographic projection of the portion of the first gate layer 6 serving as the gate 6B of the first-type transistor T3 on the substrate 1 can overlap with the orthographic projection of the first semiconductor layer 4 on the substrate 1, as shown in Figures 11A-12B for the gate 6B. Of course, as shown in Figures 8A and 12A, the first gate layer 6 can also include a first electrode 6A of a storage capacitor, for example, the first electrode 6A shown in Figure 12A.

[0238] As shown in Figures 7A, 9, and 10, the first source-drain conductive layer 14-1 may include the source and drain of the first-type transistor T3 and may also include the source and drain of the second-type transistor. The first source-drain conductive layer 14-1 may overlap the source and drain of the first-type transistor T3 and a portion of the second-type transistor. For example, as shown in Figures 7A, 9, and 10, the first source-drain conductive layer 14-1 may include an electrode 14B and an electrode 14C overlapping the active portion 4 of the first-type transistor T3. The electrode 14B serves as the second electrode 14B of the second-type transistor T5, and the electrode 14C serves as the first electrode 14C of the second-type transistor T6.

[0239] The first electrode may be a drain electrode, and the second electrode may be a source electrode, or the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0240] Likewise, the first source-drain conductive layer 14 - 1 may include a portion overlapping with the orthographic projection of the active portion 4 of the first type transistor T3 on the substrate 1 , and a portion not overlapping with the orthographic projection of the active portion 4 of the first type transistor T3 on the substrate 1 .

[0241] The second gate layer 8 and the third gate layer 12 can be located on opposite sides of the second semiconductor layer 10. For example, the gate 8A in the second gate layer 8 and the gate 12A in the third gate layer 12 can be located on opposite sides of the active portion 10A of the second-type transistor T5. Thus, the second-type transistor T5 is a dual-gate transistor. Similarly, the second-type transistor T6 can also be a dual-gate transistor.

[0242] In some embodiments, the first gate layer 6 may further include a gate line Scan (marked as gate in FIG. 5A to FIG. 5C ), a light emitting control signal line EM, a reset signal line Reset, and an initialization signal line Vinit (not shown in the figure).

[0243] In some embodiments, the second gate layer 8 may also include one of the gate line Scan, the light emitting control signal line EM, the reset signal line Reset, and the initialization signal line Vinit (not shown in the figure).

[0244] In an exemplary embodiment, the third gate layer 12 may also include one of the gate line Scan, the emission control signal line EM, the reset signal line Reset, and the initialization signal line Vinit (not shown in the figure).

[0245] In at least one display panel provided by an embodiment of the present application, as shown in FIG11A , portions of the first gate layer 6, the second gate layer 8, and the third gate layer 12 located in the first sub-area AK1 include metal, portions located in the region H2 of the second sub-area AK2 where the non-channel region is located include a light-transmitting conductive material, and portions of the second gate layer 8 and / or the third gate layer 12 located in the region H1 of the second sub-area AK2 where the channel region is located include a light-transmitting conductive material and metal.

[0246] The first source-drain conductive layer 14 - 1 and the second source-drain conductive layer 17 include metal in the first sub-area AK1 , light-transmitting conductive material in the second sub-area AK22 , and light-transmitting conductive material and metal in the first sub-area AK21 .

[0247] For example, in combination with Figures 11A-11E, the first gate layer 6 may include a gate 6B of a first-type transistor T3 and a first electrode 6A of a storage capacitor, wherein the portion of the first gate layer 6 serving as the gate 6B of the first-type transistor T3 may be located in the first sub-region AK1, and the portion serving as the first electrode 6A of the storage capacitor may also be located in the first sub-region AK1 (the first electrode 6A is not shown in Figure 11A).

[0248] For example, as shown in FIG12A , the portion of the first gate layer 6 serving as the gate 6B of the first type transistor T3 may be located in the first sub-region AK1 , and the portion serving as the first electrode 6A of the storage capacitor may be located in the second sub-region AK2 .

[0249] The second gate layer 8 may include the first gate of the second-type transistor, and the third gate layer 12 may include the second gate of the second-type transistor. For example, as shown in Figures 11A-12A, the second gate layer 8 includes the first gate 8A of the second-type transistor T5 and the first gate 8C of the second-type transistor T6, and the third gate layer 12 includes the second gate 12A of the second-type transistor T5 and the second gate 12B of the second-type transistor T6. Thus, gates are provided on both the side of the active portion of the second-type transistor facing away from the substrate 1 and the side close to the substrate 1, making the second-type transistor a dual-gate transistor.

[0250] The portion of the second gate layer 8 and the third gate layer 12 serving as the gate of the second type transistor may be located in the second sub-region AK2, specifically, in the first sub-region AK21, or in the second sub-region AK22, or in both the first sub-region AK21 and the second sub-region AK22.

[0251] For example, as shown in Figures 11A-12A, the second gate layer 8 includes a first gate 8A of the second-type transistor T5, and the third gate layer 12 includes a second gate 12A of the second-type transistor T5. The first gate 8A and the second gate 12A of the second-type transistor T5 are both located in the second sub-area AK2 and in the second sub-area AK22. The second gate layer 8 also includes a first gate 8C of the second-type transistor T6, and the third gate layer 12 includes a second gate 12B of the second-type transistor T6. The first gate 8C and the second gate 12B of the second-type transistor T6 are both located in the second sub-area AK2, including a portion located in the first sub-area AK21 and a portion located in the second sub-area AK22.

[0252] In addition to the above-mentioned second-type transistors T5 and T6, other second-type transistors may also be included, such as second-type transistors T1, T2, T4, and T7. These second-type transistors may be dual-gate transistors or single-gate transistors. In the case of dual-gate transistors, the two gates of the second-type transistors T1, T2, T4, and T7 may be located on the second gate layer 8 and the third gate layer 12, respectively. In the case of single-gate transistors, the gates of the second-type transistors T1, T2, T4, and T7 may be located on the second gate layer 8 or the third gate layer 12. In this case, it is not ruled out that the gates of some of the second-type transistors T1, T2, T4, and T7 are all located in the first sub-region AK21.

[0253] Among them, for the first gate layer 6, the second gate layer 8 and the third gate layer 12, the parts thereof located in the first sub-area AK1 include metal, the parts located in the area H2 where the non-channel area is located in the second sub-area AK2 include light-transmitting conductive material, and the parts of the second gate layer 8 and / or the third gate layer 12 located in the area H1 where the channel area is located in the second sub-area AK2 include light-transmitting conductive material and metal.

[0254] For example, as shown in Figures 11A, 11C and 11D, the portion of the first gate layer 6 located in the first sub-area AK1 may include the gate 6B of the first type transistor T3, which gate 6B may include a non-light-transmitting metal, and the portion of the active portion 10A of the second type transistor located in the second sub-area AK2 in the area where the channel region H21 is located in the second gate layer 8 includes the first gate 8A of the second type transistor T5 and the first gate 8C of the second type transistor T6, and the gates 8A and 8C include light-transmitting conductive materials and metals.

[0255] As shown in Figures 11A, 11B and 11D, the active portion 10A of the second type transistor located in the second sub-area AK2 in the third gate layer 12 is in the portion of the region H1 where the channel region is located, including the second gate 12A of the second type transistor T5 and the second gate 12B of the second type transistor T6, and the second gate 12A and the second gate 12B include light-transmitting conductive material and metal.

[0256] For example, as shown in FIG12A , the portion of the first gate layer 6 located in the first sub-region AK1 may include the gate 6B of the first type transistor T3, which may include a non-light-transmitting metal, and the portion of the first gate layer 6 located in the second sub-region AK2 and in the area H2 where the non-channel region is located includes a first electrode 6A of the storage capacitor, which may include a light-transmitting conductive material.

[0257] As shown in Figure 12A, a portion of the second gate layer 8 located in the second sub-area AK2 and in the area H2 where the non-channel region is located includes the second electrode 8B of the storage capacitor, and the second electrode 8B includes a light-transmitting conductive material; a portion of the third gate layer 12 located in the area H1 where the channel region is located in the second sub-area AK2 includes the second gate 12A of the second-type transistor T5, the second gate 12B of the second-type transistor T6, and the second gate 12C of the second-type transistor T4, and the second gate 12A, the second gate 12B, and the second gate 12C include a light-transmitting conductive material and a metal.

[0258] Among them, the first gate layer 6, the second gate layer 8 and the third gate layer 12 include at least a light-transmitting conductive material in the portion of the second sub-area AK2. For the second gate layer 8 and the third gate layer 12, the portion of the second sub-area AK2 distinguishes between the channel region and the non-channel region. The portion located in the non-channel region includes a light-transmitting conductive material to ensure the light transmittance of the second sub-area AK2. The portion located in the channel region may include a light-transmitting conductive material and metal to ensure the shielding of the channel region of the second semiconductor layer 10.

[0259] In some exemplary embodiments, in the second gate layer 8 and / or the third gate layer 12, a portion of the second sub-region AK2 in the region H1 where the channel region (i.e., the channel region of the active portion of the second type transistor) is located includes a light-transmitting conductive material and a metal; in the second gate layer 8 and the third gate layer 12, a portion of the second sub-region AK2 in the region H2 where the non-channel region is located includes a light-transmitting conductive material.

[0260] In an example of this embodiment, portions of the third gate layer 12 and the second gate layer 8 located in the region H1 of the second sub-region AK2 where the channel region is located may both include light-transmitting conductive material and metal.

[0261] For example, portions of the third gate layer 12 and the second gate layer 8 located in the region H1 of the second sub-area AK2 where the channel region is located may both include the first sub-layer A1 and the second sub-layer A2.

[0262] As shown in Figures 11A and 14, Figure 14 shows a schematic structural diagram of the electrode layer in Figure 11A in the display panel. As shown in Figures 11A and 14, a portion of the second gate layer 8 located in the area H1 where the channel region in the second sub-area AK2 is located includes a first gate 8A of the second-type transistor T5 and a first gate 8C of the second-type transistor T6, wherein the gate 8A and the gate 8C both include light-transmitting conductive material and metal; a portion of the third gate layer 12 located in the area where the channel region in the second sub-area AK2 is located includes a second gate 12A of the second-type transistor T5 and a second gate 12B of the second-type transistor T6, and the second gate 12A and the second gate 12B include both light-transmitting conductive material and metal.

[0263] The light-transmitting conductive material forms the second sub-layer A2, and the metal forms the first sub-layer A1.

[0264] In another example of this embodiment, as shown in Figures 11B and 15, Figure 15 shows a schematic structural diagram of the electrode layer in Figure 11B in the display panel, the third gate layer 12 is located in the area of ​​the second sub-area AK2 where the channel area is located, which may include a light-transmitting conductive material and a metal, and the second gate layer 8 is located in the area of ​​the second sub-area AK2 where the channel area is located, which may include a light-transmitting conductive material.

[0265] For example, as shown in Figures 11B and 12A, a portion of the second gate layer 8 in the area where the channel region in the second sub-area AK2 is located includes the first gate 8A of the second type transistor T5 and the first gate 8C of the second type transistor T6. As shown in Figure 15, the gate 8A and the gate 8C only include light-transmitting conductive material, that is, include the second sub-layer A2; a portion of the third gate layer 12 in the area H1 where the channel region in the second sub-area AK2 is located includes the second gate 12A of the second type transistor T5 and the second gate 12B of the second type transistor T6, and the second gate 12A and the second gate 12B include both light-transmitting conductive material and metal.

[0266] The light-transmitting conductive material forms the second sub-layer A2, and the metal forms the first sub-layer A1.

[0267] In another example of this embodiment, as shown in FIG11C and FIG16 , FIG16 shows a schematic structural diagram of the electrode layer in FIG11C in the display panel. The second gate layer 8 located in the region H1 of the second sub-area AK2 where the channel region is located may include a light-transmitting conductive material and metal, and the third gate layer 12 located in the region H1 of the second sub-area AK2 where the channel region is located may include a light-transmitting conductive material.

[0268] For example, as shown in Figures 11C and 16, a portion of the second gate layer 8 located in the area H1 where the channel region in the second sub-area AK2 is located includes the first gate 8A of the second type transistor T5 and the first gate 8C of the second type transistor T6, and the first gate 8A and the first gate 8C both include light-transmitting conductive material and metal; a portion of the third gate layer 12 located in the area H1 where the channel region in the second sub-area AK2 is located includes the second gate 12A of the second type transistor T5 and the second gate 12B of the second type transistor T6, and the second gate 12A and the second gate 12B include only light-transmitting conductive material.

[0269] The light-transmitting conductive material forms the second sub-layer A2, and the metal forms the first sub-layer A1.

[0270] When the third gate layer 12 and the second gate layer 8 located in the region H1 of the second sub-area AK2 where the channel region is located both include a light-transmitting conductive material and a metal, that is, both include a first sub-layer A1 and a second sub-layer A2. In one example, the first sub-layer A1 in the second gate layer 8 can be located on a side of the second sub-layer A2 facing away from the substrate 1, and the first sub-layer A1 in the third gate layer 12 can be located on a side of the second sub-layer A2 facing away from the substrate 1.

[0271] For example, as shown in Figures 11A and 14, the light-transmitting conductive material layer (second sub-layer A2) in the first gate electrode 8A in the second gate layer 8 is located on the side of the metal (first sub-layer A1) close to the substrate 1, and the conductive material layer (second sub-layer A2) in the second gate electrode 12A in the third gate layer 12 is located on the side of the metal (first sub-layer A1) close to the substrate 1; the light-transmitting conductive material layer (second sub-layer A2) in the first gate electrode 8C in the second gate layer 8 is located on the side of the metal (first sub-layer A1) close to the substrate 1, and the conductive material layer (second sub-layer A2) in the second gate electrode 12B in the third gate layer 12 is located on the side of the metal (first sub-layer A1) close to the substrate 1.

[0272] In a further example, the orthographic projection of the first sublayer A1 of the portion of the third gate layer 12 located in the region H1 where the channel region of the second sub-region AK2 is located on the substrate 1 can cover the second sublayer A2, and the first sublayer A1 is located on the side of the second sublayer A2 facing away from the substrate 1.

[0273] Continuing with reference to Figures 11A and 14 , the orthographic projection of the second gate 12B in the third gate layer 12 and the light-transmitting conductive material layer (second sub-layer A2) in the second gate 12A on the substrate 1 falls within the orthographic projection of the metal (first sub-layer A1) on the substrate 1 .

[0274] In this embodiment, the orthographic projection of the second sub-layer A2 on the substrate 1 falls within the orthographic projection of the first sub-layer A1 on the substrate 1, which may mean that in the width direction of the active portion, the orthographic projection of the second sub-layer A2 on the substrate 1 falls within the orthographic projection of the first sub-layer A1 on the substrate 1.

[0275] The width direction is the direction from the channel region of the active portion to the non-channel region.

[0276] In this case, the third gate layer 12 located on the side of the channel region of the active part of the second type transistor facing away from the substrate 1 can be a conductive layer formed by two materials, namely the first sublayer A1 and the second sublayer A2, and the transparent conductive material is covered with a metal material, which can avoid cracks and damage to the passivation layer when etching vias when forming the first source-drain conductive layer 14-1 connected to the active part of the second type transistor.

[0277] In another example, when the third gate layer 12 and the second gate layer 8 located in the region H1 of the second sub-area AK2 where the channel region is located both include a light-transmitting conductive material and a metal, that is, both include a first sub-layer A1 and a second sub-layer A2. The first sub-layer A1 in the second gate layer 8 can be located on the side of the second sub-layer A2 facing away from the substrate 1, and the first sub-layer A1 in the third gate layer 12 is located on the side of the second sub-layer A2 close to the substrate 1.

[0278] For example, as shown in Figures 11D and 17, Figure 17 shows a schematic structural diagram of the electrode layer in Figure 11D in a display panel. In particular, the portion of the second gate layer 8 located in the second sub-area AK2 in the channel region includes the first gates of the second-type transistors (including the first gate 8A of the second-type transistor T5 and the first gate 8B of the second-type transistor T6), and the metal (first sub-layer A1) in the first gates 8A and 8B is located on the side of the transparent conductive material (second sub-layer A2) facing away from the substrate 1. The portion of the third gate layer 12 located in the second sub-area AK2 in the channel region includes the second gates of the second-type transistors (including the second gate 12A of the second-type transistor T5 and the second gate 12B of the second-type transistor T6), and the metal (first sub-layer A1) in the second gates 12A and 12B is located on the side of the transparent conductive material (second sub-layer A2) close to the substrate 1.

[0279] In a further embodiment, in the portion of the second gate layer 8 located in the region H1 where the channel region is located in the second sub-area AK2, the outer contour of the orthographic projection of the first sub-layer A1 on the substrate 1 may coincide with the outer contour of the orthographic projection of the second sub-layer A2 on the substrate 1. For example, as shown in Figures 11A, 11C, and 11D, and as shown in Figures 14, 16, and 17, the metal (first sub-layer A1) in the first gate 8A of the second gate layer 8 is located on the side of the transparent conductive material (second sub-layer A2) facing away from the substrate 1, and the outer contour of the orthographic projection of the first sub-layer A1 on the substrate 1 coincides with the outer contour of the orthographic projection of the second sub-layer A2 on the substrate 1, and the metal (first sub-layer A1) in the first gate 8B is located on the side of the transparent conductive material (second sub-layer A2) facing away from the substrate 1, and the outer contour of the orthographic projection of the first sub-layer A1 on the substrate 1 coincides with the outer contour of the orthographic projection of the second sub-layer A2 on the substrate 1.

[0280] As shown in FIG11A and FIG11B , and as shown in FIG14 and FIG15 , the metal (first sublayer A1) in the second gate electrode 12A in the third gate layer 12 is located on the side of the transparent conductive material (second sublayer A2) facing away from the substrate 1, and the outer contour of the orthographic projection of the first sublayer A1 on the substrate 1 covers the outer contour of the orthographic projection of the second sublayer A2 on the substrate 1;

[0281] As shown in FIG11D and FIG17 , the metal (first sublayer A1) in the second gate electrode 12A in the third gate layer 12 is located on the side of the transparent conductive material (second sublayer A2) close to the substrate 1, and the outer contour of the orthographic projection of the first sublayer A1 on the substrate 1 overlaps the outer contour of the orthographic projection of the second sublayer A2 on the substrate 1. The metal (first sublayer A1) in the second gate electrode 12B in the third gate layer 12 is located on the side of the transparent conductive material (second sublayer A2) close to the substrate 1, and the outer contour of the orthographic projection of the first sublayer A1 on the substrate 1 overlaps the outer contour of the orthographic projection of the second sublayer A2 on the substrate 1.

[0282] As shown in Figures 12A and 19, Figure 19 shows a schematic diagram of the electrode layers in Figure 12A in a display panel. The metal (first sublayer A1) in the second gate electrode 12A, the second gate electrode 12B, and the second gate electrode 12C in the third gate layer 12 is located on the side of the transparent conductive material (second sublayer A2) facing away from the substrate 1, and the outer contour of the orthographic projection of the first sublayer A1 on the substrate 1 coincides with the outer contour of the orthographic projection of the second sublayer A2 on the substrate 1.

[0283] In the display panel provided in some embodiments, the portion of the first gate layer 6 located in the first sub-area AK1 may further include a light-transmitting conductive material. In this case, the first-type transistor T3 is an oxide-type transistor, which exhibits stable transistor characteristics under infrared light. This increases the transmittance of the first sub-area AK1 without affecting its electrical performance.

[0284] Taking Figures 12A and 19 as examples, the first gate layer 6 may include a portion serving as the gate 6B of the first-type transistor T3. The gate 6B of the first-type transistor T3 may include a light-transmitting conductive material and a metal. The light-transmitting conductive material in the first gate layer 6 may be referred to as a light-transmitting sublayer B2, and the metal in the first gate layer 6 may be referred to as a light-shielding sublayer B1. The light-shielding sublayer B1 may be located on the side of the light-transmitting sublayer B2 facing away from the substrate 1. This improves the transmittance in the first sub-area AK1.

[0285] In which, the orthographic projection of the light-shielding sub-layer B1 on the substrate 1 overlaps with the orthographic projection of the light-transmitting sub-layer B2 on the substrate 1, or the orthographic projection of the light-shielding sub-layer B1 on the substrate 1 covers the orthographic projection of the light-transmitting sub-layer B2 on the substrate 1, or the orthographic projection of the light-shielding sub-layer B1 on the substrate 1 falls within the orthographic projection of the light-transmitting sub-layer B2 on the substrate 1.

[0286] In some embodiments, the first type transistor T3 is a polysilicon transistor, the first gate layer 6 includes a first electrode 6A of the storage capacitor, and the second gate layer 8 includes a second electrode 8B of the storage capacitor.

[0287] As shown in FIG12A , the first type transistor T3 is an oxide type transistor. The first electrode 6A and the second electrode 8B of the storage capacitor are located in the second sub-area AK2 . When located in the second sub-area AK2 , the first electrode 6A and the second electrode 8B include a light-transmitting conductive material.

[0288] In some embodiments, the first electrode 6A and the second electrode 8B of the storage capacitor may also be located in the first sub-area AK1. The situation where the second electrode 8B is located in the first sub-area AK1 can be shown in Figures 11A-11E. The first electrode 6A cannot be seen in Figures 11A-11E. When located in the first sub-area AK1, the first electrode 6A and the second electrode 8B both include metal.

[0289] In particular, for the first source-drain conductive layer 14-1 and the second source-drain conductive layer 17, the portion of the first source-drain conductive layer 14-1 and the second source-drain conductive layer 17 located in the first sub-area AK1 includes metal, the portion located in the first sub-area AK21 includes a light-transmitting conductive material and metal, and the portion located in the second sub-area AK22 includes a light-transmitting conductive material. As a result, the transmittance of the first sub-area AK1, the first sub-area AK21, and the second sub-area AK22 increases in sequence.

[0290] The first source-drain conductive layer 14 - 1 and the second source-drain conductive layer 17 may include the same or different metals, and the first source-drain conductive layer 14 - 1 and the second source-drain conductive layer 17 may include the same or different light-transmitting conductive materials.

[0291] For example, as shown in Figures 11A-11C, the first source-drain conductive layer 14-1 includes a first electrode 14A and a second electrode 14B of the second type transistor T5, a first electrode 14C and a second electrode 14D of the second type transistor T6, and the second source-drain conductive layer 17 includes an electrode 17A connected to the first electrode 14A of the second type transistor T5, and an electrode 17B connected to the second electrode 14D of the second type transistor T6.

[0292] The electrode 17A can be understood as an auxiliary electrode of the first electrode 14A, and the electrode 17B can be understood as an auxiliary electrode of the second electrode 14D.

[0293] The second electrode 14B of the second type transistor T5 is connected to the first electrode of the first type transistor T3 , and the first electrode 14C of the second type transistor T6 is connected to the second electrode of the first type transistor T3 .

[0294] The first electrode 14A and the second electrode 14D of the second-type transistor T5 are located in the second sub-area AK22. The second electrode 14B of the second-type transistor T5 includes a portion located in the first sub-area AK21, a portion located in the first sub-area AK1, and a portion located in the second sub-area AK22. The first electrode 14C of the second-type transistor T6 includes a portion located in the first sub-area AK21, a portion located in the first sub-area AK1, and a portion located in the second sub-area AK22. The first metal layer 17A and the second metal layer 17B are both located in the second sub-area AK22.

[0295] The first electrode 14A and the second electrode 14D of the second type transistor T5 located in the second sub-region AK22 only include light-transmitting conductive material, and the first metal layer 17A and the second metal layer 17B only include light-transmitting conductive material.

[0296] Parts of the second electrode 14B of the second-type transistor T5 and the first electrode 14C of the second-type transistor T6 located in the first sub-area AK1 include metal.

[0297] In some examples, since the second-type transistors T5 and T6 are connected to the first-type transistor T3 , to simplify the process, the second electrode 14B of the second-type transistor T5 and the first electrode 14C of the second-type transistor T6 can be formed of full metal.

[0298] In some examples, since Figure 11A only shows a cross-sectional schematic diagram of the second-type transistors T5 and T6 and the first-type transistor T3, which also includes second-type transistors T1, T2, T4, and T7, the first source-drain conductive layer 14-1 and the second source-drain conductive layer 17 may include the first and second electrodes of the second-type transistors T1, T2, T4, and T7, then the portions of the first and second electrodes of the second-type transistors T1, T2, T4, and T7 located in the first sub-region AK21 may include light-transmitting conductive materials and metals.

[0299] As another example, as shown in Figure 11D, different from Figures 11A to 11C, the first electrode 14A of the second-type transistor T5 and the second electrode 14D of the second-type transistor T6 are located in the second source-drain conductive layer 17, and the second electrode 14B of the second-type transistor T5 and the first electrode 14C of the second-type transistor T6 are located in the first source-drain conductive layer 14-1. This example is the same as Figures 11A to 11C, that is, the auxiliary electrode 17A of the first electrode 14A of the second-type transistor T5 and the auxiliary electrode 17B of the second electrode 14D of the second-type transistor T6 in the second source-drain conductive layer 17, wherein the portion located in the second sub-region AK22 only includes light-transmitting conductive material, and the portion of the second electrode 14B of the second-type transistor T5 and the first electrode 14C of the second-type transistor T6 in the first source-drain conductive layer 14-1 located in the first sub-region AK1 includes metal.

[0300] In one example, the light-transmitting conductive material and metal in the first sub-region AK21 of the first source-drain conductive layer 14-1 and the second source-drain conductive layer 17 can be stacked in a normal direction to the substrate 1. As shown in FIG18 , a portion 14B2 of the electrode 14B and a portion 14C2 of the electrode 14C in the first source-drain conductive layer 14-1 include a light-transmitting conductive material and metal, with the light-transmitting conductive material located on the side of the metal facing away from the substrate 1.

[0301] In a further example, when the portions of the first source-drain conductive layer 14-1 and the second source-drain conductive layer 17 located in the first sub-region AK21 both include metal and light-transmitting conductive material, they may include a first sublayer A1 and a second sublayer A2, the material of the first sublayer A1 includes metal, and the material of the second sublayer A2 includes light-transmitting conductive material; wherein the second sublayer A2 is located on the side of the first sublayer A1 facing away from the substrate 1.

[0302] Thus, for the first source-drain conductive layer 14-1 and the second source-drain conductive layer 17 located in the first sub-area AK21, the light-transmitting conductive material included therein is arranged closer to the light-emitting side, thereby ensuring electrical connectivity between the first source-drain conductive layer 14-1 and the semiconductor layer located thereunder in the transistor.

[0303] In the display panel provided in some embodiments, the first source-drain conductive layer 14 - 1 further includes a connection layer connected to the second semiconductor layer 10 , and a portion of the connection layer located in the second display area AA2 may include metal.

[0304] Taking Figures 11A and 18 as examples, the electrode 14B in the first source-drain conductive layer 14-1 needs to simultaneously connect the source of the first type transistor T3 and the drain of the second type transistor T5, and the electrode 14C in the first source-drain conductive layer 14-1 needs to simultaneously connect the drain of the first type transistor T3 and the source of the second type transistor T6. For the connection layer in the first source-drain conductive layer 14-1 located in the second sub-area AK2 and connected to the active part of the first type transistor T3 and the source and drain part of the second type transistor T5, the connection layer may include metal to ensure the electrical connection performance between the first type transistor T3 and the second type transistor. As shown in Figure 18, the connection layer of the first source-drain conductive layer 14-1 may include the portion 14B2 of the electrode 14B located in the second sub-area AK2 and the portion 14C2 of the electrode 14C located in the second sub-area AK2.

[0305] In one example, the portion of the first source-drain conductive layer 14 - 1 connected to the first semiconductor layer 4 may include metal. For example, the portion connected to the first semiconductor layer 4 in FIG. 18 may include 14B1 and 14C1 , which may include metal.

[0306] In one example, the portion of the first source-drain conductive layer 14-1 connected to the second type transistor may include metal and light-transmitting conductive material, such as the connecting layers 14B2 and 14C2 in Figure 18. The connecting layer may include metal and light-transmitting conductive material, the metal forms the first sublayer A1, and the light-transmitting conductive material forms the second sublayer A2, wherein the first sublayer A1 is located on the side of the second sublayer A2 close to the substrate 1.

[0307] In another display panel provided by an embodiment, the thickness of the light-transmitting conductive material contained in the first source-drain conductive layer 14-1 and the second source-drain conductive layer 17 may be greater than the thickness of the light-transmitting conductive material located in the second sub-area AK2 in the first gate layer 6, the second gate layer 8 and the third gate layer 12.

[0308] In an example of this embodiment, the thickness of the light-transmitting conductive material of the first source-drain conductive layer 14-1 and the second source-drain conductive layer 17 located in the first sub-region AK21 and the second sub-region AK22 may be greater than the thickness of the light-transmitting conductive material of the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the second sub-region AK2.

[0309] In one example, the thickness of the light-transmitting conductive material of the first source-drain conductive layer 14-1 and the second source-drain conductive layer 17 located in the second sub-region AK22 may be greater than the thickness of the light-transmitting conductive material of the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the second sub-region AK2.

[0310] In one example, the thickness of the light-transmitting conductive material of the first source-drain conductive layer 14-1 and the second source-drain conductive layer 17 located in the first sub-region AK21 may be greater than the thickness of the light-transmitting conductive material of the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the second sub-region AK2.

[0311] In the display panel provided in some embodiments, the second-type transistor may be a dual-gate transistor, and at least one gate of the second-type transistor located in the second display area AA2 may include a first sublayer A1 and a second sublayer A2. The orthographic projections of the first sublayer A1 and the second sublayer A2 on the substrate 1 may overlap, and the orthographic projections of the first sublayer A1 and the second sublayer A2 on the substrate 1 both overlap with the orthographic projection of the second semiconductor layer 10 on the substrate 1. The overlapping dimensions of the orthographic projections of the first sublayer A1 and the second sublayer A2 on the substrate 1 and the orthographic projection of the second semiconductor layer 10 on the substrate 1 may differ.

[0312] Exemplarily, the gate portion of the second type transistor used as the second display area AA2 in the second gate layer 8 and / or the third gate layer 12 includes a first sublayer A1 and a second sublayer A2, the material of the first sublayer A1 includes metal, and the material of the second sublayer A2 includes a light-transmitting conductive material;

[0313] The orthographic projection of the first sublayer A1 on the substrate 1 and the orthographic projection of the channel region of the second semiconductor layer 10 on the substrate 1 have a first overlapping region, and the orthographic projection of the second sublayer A2 on the substrate 1 and the orthographic projection of the channel region of the second semiconductor layer 10 on the substrate 1 have a second overlapping region C2. The dimension L1 of the first overlapping region in the first direction is greater than the dimension L2 of the second overlapping region C2 in the first direction.

[0314] The first direction y is a direction from a channel region of the active portion of the second type transistor to a non-channel region of the active portion of the second type transistor.

[0315] Please refer to FIG. 20A and FIG. 21 , which respectively show top views of the active portions and gates of two types of second-type transistors. As shown in FIG. 21 and FIG. 20A , at least one gate (the first gate and / or the second gate) of the second-type transistor in the second display area AA2 has the following structural features:

[0316] It includes a first sublayer A1 and a second sublayer A2, the first sublayer A1 and the second sublayer A2 have overlapping orthographic projections on the substrate 1, and both overlap with the channel region H1 of the active portion 10A of the second type transistor, and a size L1 of a first overlapping area C1 between the first sublayer A1 and the channel region H1 in the first direction y is greater than a size L2 of a second overlapping area C2 between the second sublayer A2 and the channel region in the first direction y.

[0317] In one example, the second gate layer 8 and the third gate layer 12 located in the second display area AA2, which serve as the gate of the second type transistor, both have the above-mentioned structural characteristics. In this case, the first sublayer A1 of the third gate layer 12 can be located on the side of the second sublayer A2 facing away from the substrate 1, and the first sublayer A1 in the second gate layer 8 can be located on the side of the second sublayer A2 close to the substrate 1.

[0318] In one example, the portion of the third gate layer 12 located in the second display area AA2 that serves as the gate of the second type transistor has the above-mentioned structural characteristics. In this case, the first sublayer A1 of the third gate layer 12 can be located on the side of the second sublayer A2 facing away from the substrate 1.

[0319] In another example, the portion of the second gate layer 8 located in the second display area AA2 that serves as the gate of the second type transistor has the above-mentioned structural characteristics. In this case, the first sublayer A1 of the second gate layer 8 can be located on the side of the second sublayer A2 close to the substrate 1.

[0320] In one example, as shown in Figures 19 and 20A, the orthographic projections of the first sublayer A1 and the second sublayer A2 on the substrate 1 can be orthogonal, and the orthogonal region can be located in the channel region H1 of the active portion 10A of the second type transistor in the second semiconductor layer 10.

[0321] In one example, as shown in Figures 20A and 21, the shapes and sizes of the orthographic projections of the first sublayer A1 and the second sublayer A2 on the substrate 1 may be different. For example, the size L1 of the orthographic projection of the first sublayer A1 on the substrate 1 in the first direction y is larger than the size L2 of the partial area of ​​the orthographic projection of the second sublayer A2 on the substrate 1 in the first direction y, and the size W2 of the orthographic projection of the first sublayer A1 on the substrate 1 in the second direction x is smaller than the size of the partial area of ​​the orthographic projection of the second sublayer A2 on the substrate 1 in the second direction x.

[0322] The second direction x is orthogonal to the first direction y.

[0323] In one example, as shown in Figure 20A, for the second sublayer A2, the second sublayer A2 may include a first area A21 and a second area A22 located on two opposite sides of the first area A21 (on two opposite sides in the second direction x), wherein the second overlapping area C2 falls into the first area A21, and the size of the first area A21 in the first direction y is smaller than the size of the second area A22 in the first direction y.

[0324] In one exemplary embodiment, the orthographic projection of the first area A21 on the substrate 1 may be a rectangle.

[0325] In another embodiment, as shown in Figure 21, for the second sub-layer A2, the second sub-layer A2 may include a first area A21, a third area A23 and a second area A22 located between the first area A21 and the third area A23, such as including one first area A21, two second areas A22 and two third areas A23, wherein the two second areas A22 are located on opposite sides of the first area A21 (on opposite sides in the second direction x), and the two third areas A23 are respectively located on the side of the second area A22 away from the first area A21.

[0326] In which, the channel region of the second semiconductor layer 10 serving as the active part of the second type transistor can cover the first area A21 and overlap with the second area A22. In this way, the second overlapping area C2 is composed of the first area A21 and part of the second area A22. The orthographic projection of the first sub-layer A1 on the substrate 1 covers the first area A21 and overlaps with the second area A22, and the orthographic projection of the third area A23 on the substrate 1 does not overlap with the first sub-layer A1.

[0327] In which, the size of the first area A21 in the first direction y is smaller than the size of the third area A23 in the first direction y, and in the direction from the first area A21 to the third area A23, the size of the second area A22 in the first direction y gradually increases to be the same as the size of the third area A23 in the first direction y. For example, the orthographic projection of the second area A22 on the substrate 1 can be an isosceles trapezoid, and the orthographic projection of the first area A21 on the substrate 1 can be a rectangle.

[0328] In this example, the gate of the second type transistor in the second display area AA2 can have the above-mentioned structural characteristics, so that the size L1 of the first sublayer A1 in the first direction y is larger than the size L2 of the second sublayer A2 in the first direction y, thereby avoiding the influence of Overlay on the W / L of the channel region of the second semiconductor layer 10.

[0329] Wherein, L represents the distance between the source and drain of the thin film transistor, also known as the length of the channel region, and W represents the width of the channel region of the thin film transistor. The first direction y mentioned above can also be understood as the length L of the channel region.

[0330] In a further example of the display panel of this embodiment, portions of the second gate layer 8 and the third gate layer 12 serving as gates of the second type transistors in the first display area AA1 include a metal conductive layer; an orthographic projection of the metal conductive layer on the substrate 1 and an orthographic projection of the channel region of the second semiconductor layer 10 on the substrate 1 have a third overlapping region C3;

[0331] The size of the third overlapping region C3 in the first direction y is equal to the size of the first overlapping region in the first direction x.

[0332] In this embodiment, as shown in Figures 11E and 18, the portion of the second gate layer 8 in the first display area AA1 includes the first gate 8A of the second type transistor T5 and the first gate 8C of the second type transistor T6, and the portion of the third gate layer 12 in the first display area AA1 includes the second gate 12A of the second type transistor T5 and the second gate 12B of the second type transistor T6, wherein the gates 8A, 8C, 12A and 12B are all made of metal.

[0333] As shown in Figure 12B, the portion of the second gate layer 8 in the first display area AA1 includes the first gate 8A of the second type transistor T5 and the first gate 8C of the second type transistor T6 and the second electrode 8B of the storage capacitor, and the portion of the third gate layer 12 in the first display area AA1 includes the second gate 12A of the second type transistor T5 and the second gate 12B of the second type transistor T6, wherein the gates 8A, 8C, 12A and 12B and the second electrode 8B are all made of metal.

[0334] 11E , 12B and 20B , FIG20B shows an enlarged schematic diagram of the channel region H2 in FIG12a . Taking the second-type transistor T6 as an example, the third overlapping region C3 refers to the overlapping region of the orthographic projection of the second gate 12B on the substrate 1 and the orthographic projection of the active portion 10B on the substrate 1 , or the third overlapping region C3 refers to the overlapping region of the orthographic projection of the first gate 8C on the substrate 1 and the orthographic projection of the active portion 10B on the substrate 1 , or the third overlapping region C3 refers to the overlapping portion of the overlapping region of the orthographic projection of the first gate 8C and the second gate 12B on the substrate 1 and the orthographic projection of the active portion 10B on the substrate 1 .

[0335] 19 , 20A and 20B , the size L1 of the third overlapping area C3 in the first display area AA1 in the first direction y may be the same as the size of the first overlapping area in the second display area AA2 in the first direction y. In this way, the channel areas of the second type transistors in the first display area AA1 and the second display area AA2 may have the same size (W / L), thereby ensuring the display stability of the entire display panel.

[0336] In the display panel provided in some embodiments, as shown in FIG7A , FIG9 and FIG10 , the display panel may further include:

[0337] a third source-drain conductive layer 14-2, located between the first source-drain conductive layer 14-1 and the second source-drain conductive layer 17 in the thickness direction of the substrate 1, wherein the third source-drain conductive layer 14-2 includes at least part of the source and part of the drain of the second-type transistor;

[0338] The orthographic projection of the third source-drain conductive layer 14 - 2 on the substrate 1 is located in the second sub-region, and the third source-drain conductive layer 14 - 2 includes a light-transmitting conductive material.

[0339] As shown in FIG11D , the display panel includes a passivation layer 15 located on the side of the first source-drain conductive layer 14-1 facing away from the substrate 1, and a third source-drain conductive layer 14-2 located on the side of the passivation layer 15 facing away from the substrate 1. A first planar layer 16-1 is also included on the side of the third source-drain conductive layer 14-2 facing away from the substrate 1, and a second source-drain conductive layer 17 may be located on the side of the first planar layer 16-1 facing away from the substrate 1.

[0340] In which, the third source-drain conductive layer 14-2 may include part of the source and part of the drain of part of the second type transistor. For example, as shown in Figure 11D, the third source-drain conductive layer 14-2 may include the first electrode 14A of the second type transistor T5 and the second electrode 14D of the second type transistor T6. The positive projection of the third source-drain conductive layer 14-2 on the substrate 1 is located in the second sub-region AK22. The third source-drain conductive layer 14-2 is located in the second sub-region AK22.

[0341] The third source-drain conductive layer 14 - 2 may include a light-transmitting conductive material.

[0342] In this way, the portion of the source and drain of the second type transistor located in the second sub-region AK22 can be located in the third source and drain conductive layer 14-2. In this way, the source and drain formed by metal and the source and drain formed by light-transmitting conductive material in the second type transistor are arranged in different layers. For example, as shown in Figure 7A, the first electrode 14A and the second electrode 14B of the second type transistor T5 are in different layers. The first electrode 14A uses a light-transmitting conductive material, and the second electrode 14B needs to be electrically connected to the source / drain of the first type transistor, which includes metal.

[0343] In this way, for the source and drain of the second type transistor, the part electrically connected to the first type transistor is made of metal and is located in the first source and drain conductive layer 14-1, and the source and drain of the transparent conductive material overlapping with the active part of the second type transistor can be located in the third source and drain conductive layer 14-2, so that the via overlapping with the metal and the via overlapping with the transparent conductive material are not located in the same layer.

[0344] In this way, the via holes in the second semiconductor layer 10 that overlap with the light-transmitting conductive material of the third source-drain conductive layer 14 - 2 can be formed simultaneously with the via holes on the passivation layer, thereby reducing the number of masks.

[0345] In the display panel provided in some embodiments, in combination with Figure 22, Figure 22 shows an enlarged schematic diagram of the area where the second display area AA2 and the first display area AA1 in Figure 3 intersect. As shown in Figure 22, the second display area AA2 may include an intermediate display area 101, and a transition area 102 from the intermediate display area 101 to the first display area AA1; wherein, the portion where some or all of the signal lines in the multiple electrode layers are located in the transition area 102 includes metal and light-transmitting conductive material.

[0346] In this embodiment, the second sub-pixel P2 located in the middle display area 101 can have the structure of the embodiment associated with any of the figures in Figures 11A to 12B, and the wiring in the second pixel circuit Pc2 located in the transition area 102 (the above-mentioned multiple signal lines) can include metal and light-transmitting conductive material. Since the signal lines in this area include metal, the electrical connection performance between the second pixel circuit Pc2 in the transition area and the first pixel circuit Pc1 in the first display area AA1 can be guaranteed.

[0347] The signal lines mentioned above include gate lines, light emitting control signal lines, reset signal lines, initialization signal lines, data signal lines and first power signal lines.

[0348] Among them, the transition area 102 can enclose the middle display area 101, or partially enclose the middle display area 101. For example, when the second display area AA2 is surrounded by the first display area AA1 on all sides, the transition area 102 can enclose the middle display area 101; as shown in Figure 22, when the second display area AA2 is not fully surrounded by the first display area AA1 on all sides, the transition area 102 can partially enclose the middle display area 101.

[0349] As shown in FIG22 , the number of second sub-pixels P2 located in the middle display area 101 may be greater than the number of second sub-pixels P2 located in the transition area. For example, in a direction x from the middle display area to the transition area, the transition area may include one second sub-pixel P2. Of course, in some other embodiments, the transition area may include two second sub-pixels P2 or three second sub-pixels P2.

[0350] In one example, the portion of the transition region 102 serving as an element of the pixel circuit may also include metal and light-transmitting conductive materials. For example, the multiple electrode layers located in the transition region 102 serving as the source, drain, and gate of each transistor may all be made of metal and light-transmitting conductive materials.

[0351] In the display panel provided in some embodiments, a light-shielding layer 2 may also be included, which is located on the side of the first semiconductor layer 4 close to the substrate 1; the portion of the light-shielding layer 2 located in the first sub-area AK1 includes metal and light-transmitting conductive material, and the portion located in the second sub-area AK2 includes light-transmitting conductive material.

[0352] As shown in Figures 11A-11D, the first type transistor T3 includes a polysilicon transistor. In this case, the light-shielding layer 2 in the second display area AA2 is located between the substrate 1 and the buffer layer 3, and may include a first light-shielding layer 22A and a second light-shielding layer 22B located on the side of the first light-shielding layer 22A away from the substrate 1, wherein the second light-shielding layer 22B may include a light-transmitting conductive material, and the first light-shielding layer 22A may include a metal.

[0353] Specifically, the light shielding layer 22 includes metal and light-transmitting conductive material in a portion of the first sub-area AK1 , and includes light-transmitting conductive material in a portion of the second sub-area AK2 .

[0354] In one example, the light-transmitting conductive material in the light-shielding layer 2 of the second display area AA2, i.e., the second light-shielding layer 22B, can be stacked on the side of the first light-shielding layer 22A facing away from the substrate 1, and the orthographic projection of the second light-shielding layer 22B on the substrate 1 can cover the orthographic projection of the first light-shielding layer 22A on the substrate 1.

[0355] In some embodiments, the portion of the light shielding layer 2 in the second display area AA2 located in the first sub-area AK1 includes metal and light-transmitting conductive material, the portion located in the first sub-area AK21 includes metal and light-transmitting conductive material, and the portion located in the second sub-area AK22 includes light-transmitting conductive material.

[0356] 11C-11D , the light shielding layer 2 of the second display area AA2 includes metal and light-transmitting conductive material in the first sub-area AK1 and the first sub-area AK21 , and includes light-transmitting conductive material in the second sub-area AK22 .

[0357] As another example, as shown in FIG11B , the portion of the light-shielding layer 2 in the second display area AA2 located in the first sub-area AK1 includes metal and a light-transmitting conductive material, the portion located in the second sub-area AK22 includes a light-transmitting conductive material, and the portion located in the first sub-area AK21 includes metal and a light-transmitting conductive material. Specifically, in the portion of the light-shielding layer 2 located in the first sub-area AK21, the orthographic projection of the second light-shielding layer 22B on the substrate 1 can cover the orthographic projection of the first light-shielding layer 22A on the substrate 1. In other words, the area of ​​the light-transmitting conductive material in the first sub-area AK21 is larger, thereby improving light transmission efficiency.

[0358] In some embodiments, when the first-type transistor T3 is an oxide-type transistor, the light shielding layer 2 may not be included, as shown in FIG. 12A-12B .

[0359] In some other embodiments, when the first-type transistor T3 is an oxide-type transistor, a light-shielding layer 2 may also be included. In this case, the light-shielding layer 2 may include a light-transmitting conductive material.

[0360] In some embodiments, the transmittance of the first display area AA1 is less than the transmittance of the second display area AA2. Then, as shown in Figures 9F and 10B, the first source-drain conductive layer 14-1 and the second source-drain conductive layer 17 located in the first display area AA1 include metal, and the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the first display area AA1 include metal. When the display panel includes a light-shielding layer 22, the light-shielding layer 22 located in the first display area AA1 includes metal.

[0361] In addition to the above-mentioned electrode layer, the display panel may further include:

[0362] A buffer layer 3 is provided between the light-shielding layer 2 and the first semiconductor layer 4, and a support portion 20 is provided on the pixel definition layer 19. The support portion 20 is used to support the mask during the evaporation process (BP process) to prevent scratches between the mask and the film layer on the display panel. In some embodiments, the display panel further includes an encapsulation layer 29, a touch layer 23, an anti-reflection layer 24 (used to reduce reflectivity, which may include multiple sub-layers), an adhesive layer 25, and a cover plate 26.

[0363] The following describes two display panels as examples.

[0364] Display Panel #1

[0365] The first display area AA1 includes a plurality of first sub-pixels P1 arranged in an array, and the second display area AA2 includes a plurality of second sub-pixels P2 arranged in an array. The number of the second sub-pixels P2 is less than the number of the first sub-pixels P1.

[0366] Each sub-pixel of the display panel includes a pixel circuit with the same structure. The pixel circuit includes a first-type transistor T3 and a second-type transistor. The first-type transistor T3 serves as a driving transistor, and the second-type transistor serves as a switching transistor. The first-type transistor T3 is a polysilicon transistor, and the second-type transistor is an oxide transistor. The pixel circuit structure can be as shown in Figure 4A.

[0367] Among them, the cross-sectional structure of the display panel #1 can be shown as in Figure 7A, and specifically may include a substrate 1, in which a light-shielding layer 22, a buffer layer 3, a first semiconductor layer 4, a first gate insulating layer, a first gate layer 6, a second gate insulating layer 7, a second gate layer 8, a third gate insulating layer 9, a second semiconductor layer 10, a fourth gate insulating layer 11, a third gate layer 12, a fifth gate insulating layer 13, a first source-drain conductive layer 14-1, a passivation layer 15, a third source-drain conductive layer 14-2, a first planarization layer 16-1, a second source-drain conductive layer 17, a second planarization layer 16-2, an anode 18 (including 18a and 18b), a pixel definition layer 19 and a cathode 22 are sequentially arranged in the normal direction of the substrate 1; the pixel definition layer includes a plurality of openings, and a light-emitting functional layer 21 is included in the opening, and the positive projections of the anode 18 and the cathode 22 on the substrate 1 can cover the positive projections of the openings on the substrate 1.

[0368] Among them, the gate line, light-emitting control signal line, reset signal line, and initialization signal line included in the sub-pixel are located on at least one layer of the first gate layer 6, the second gate layer 8, and the third gate layer 12, and the first power signal line and the data line are located on at least one layer of the first source-drain conductive layer 14-1 and the second source-drain conductive layer 17.

[0369] Among them, the second sub-pixel P2 includes a first sub-area AK1 and a second sub-area AK2. The second sub-area AK2 further includes a first sub-area AK21 located in the light-emitting area KK2 part of the second sub-pixel P2 and a second sub-area AK22 located in the non-light-emitting area FKK2 of the second sub-area AK2. The first sub-area AK1 is the area where the first semiconductor layer 4 is located, and the second sub-area AK2 is the area in the second sub-pixel P2 except the first sub-area AK1.

[0370] The first gate layer 6 , the second gate layer 8 and the third gate layer 12 include metal in the first display area AA1 , and the first source-drain conductive layer 14 - 1 and the second source-drain conductive layer 17 include metal in the first display area AA1 .

[0371] As shown in FIG17 , portions of the first gate layer 6, the second gate layer 8, and the third gate layer 12 located in the first sub-area AK1 in the second display area AA2 include metal, portions of the first gate layer 6, the second gate layer 8, and the third gate layer 12 located in the region H1 where the channel region of the second semiconductor layer 10 is located in the second display area AA2 include a light-transmitting conductive material and metal (i.e., including the first sub-layer A1 and the second sub-layer A2), and portions of the first gate layer 6, the second gate layer 8, and the third gate layer 12 located in the region H2 where the non-channel region of the second semiconductor layer 10 is located in the second display area AA2 include a light-transmitting conductive material.

[0372] In which, in combination with what is shown in FIG17 , the first source-drain conductive layer 14-1 includes metal in a portion of the first display area AA1, and the first source-drain conductive layer 14-1 includes metal in a portion of the first sub-area AK1 in the second display area AA2. In combination with what is shown in FIG18 , FIG18 shows a schematic diagram of the distribution of the electrode layer in FIG11E , the first source-drain conductive layer 14-1 includes metal and light-transmitting conductive material in a portion of the first sub-area AK21 in the second display area AA2. As shown in FIG17 and FIG18 , the second source-drain conductive layer 17 and the third source-drain conductive layer 14-2 located in the second sub-area AK22 include light-transmitting conductive material; and, the second source-drain conductive layer 17 and the third source-drain conductive layer 14-2 located in the first sub-area AK21 include metal and light-transmitting conductive material.

[0373] 15 , the first electrode 6A and the second electrode 8B of the storage capacitor are respectively located on the first gate layer 6 and the second gate layer 8 , the orthographic projections of the first electrode 6A and the second electrode 8B on the substrate 1 are located in the first sub-area AK1 , and the first electrode 6A and the second electrode 8B include metal.

[0374] Among them, the portion of the light-shielding layer 2 located in the first sub-area AK1 includes metal and a light-transmitting conductive material, as shown in Figure 7A, including a first light-shielding layer 2A and a second light-shielding layer 2B located on the side of the first light-shielding layer 2A away from the substrate. The first light-shielding layer 2A is metal, and the second light-shielding layer 2B is a light-transmitting conductive material, wherein the orthographic projection of the second light-shielding layer 2B on the substrate covers the orthographic projection of the first light-shielding layer 2A on the substrate, and the portion of the second light-shielding layer 2 located in the second sub-area AK2 includes a light-transmitting conductive material.

[0375] Display Panel #2

[0376] Different from the display panel #1, the first type transistor T3 is an oxide type transistor, and the circuit structure of the pixel circuit of the sub-pixel can be any one of FIG. 5A to FIG. 5C .

[0377] As shown in FIG12A and FIG19 , the first gate layer 6 includes a light-transmitting conductive material and a metal in a portion of the first sub-area AK1, and includes a light-transmitting conductive material in a portion of the second sub-area AK2. The second gate layer 8 includes a light-transmitting conductive material in a portion of the second display area AA2 located in the channel region of the second semiconductor layer 10. The third gate layer 12 includes a light-transmitting conductive material and a metal in a portion of the second display area AA2 located in the channel region of the second semiconductor layer 10. The second gate layer 8 and the third gate layer 12 include a light-transmitting conductive material in a portion of the second display area AA2 located in the non-channel region H1 of the second semiconductor layer 10.

[0378] The light shielding layer 2 may not be included, or the light shielding layer 2 may be a light-transmitting conductive material.

[0379] Display Panel #3

[0380] Different from display panel #1, as shown in Figures 8B and 11D, it also includes a third source-drain conductive layer 14-2. The portion of the third source-drain conductive layer 14-2 located in the second display area AA2 is located between the first flat layer 16-1 and the passivation layer 15. The third source-drain conductive layer 14-2 is formed of a transparent conductive material.

[0381] Display Panel #4

[0382] As shown in Figure 11B, different from the display panel #1, the portion of the second gate layer 8 located in the area H1 where the channel region of the second semiconductor layer 10 is located includes a light-transmitting conductive material, and the portion of the third gate layer 12 located in the area H1 where the channel region of the second semiconductor layer 10 is located includes metal and a light-transmitting conductive material, and the light-transmitting conductive material is located on the side of the metal close to the substrate 1, and the metal covers the light-transmitting conductive material.

[0383] Display Panel #5

[0384] As shown in Figure 11D, unlike the display panel #1, the second gate layer 8 and the third gate layer 12 located in the channel region of the second semiconductor layer 10 both include metal and light-transmitting conductive material, and in the second gate layer 8, the light-transmitting conductive material is located on the side of the metal close to the substrate 1, and in the third gate layer 12, the metal is located on the side of the light-transmitting conductive material close to the substrate 1.

[0385] An embodiment of the application provides a display device, comprising the display panel as described above.

[0386] The specific structure of the display panel can be referred to in the previous description and will not be repeated here.

[0387] The display device provided in the embodiments of the present application may be an OLED display device, wherein the OLED display device may include a glass-based OLED display device and a silicon-based OLED display device.

[0388] In addition, the display device can be a display device such as an OLED display, as well as any product or component with a display function, such as a television, a digital camera, a mobile phone, a tablet computer, etc. that includes these display devices.

[0389] An embodiment of the present application provides a method for manufacturing a display panel as described above, wherein the method comprises:

[0390] S1, forming the first semiconductor layer 4 shown in FIG. 11A to FIG. 12B on the substrate 1;

[0391] S2, forming the first gate layer 6 shown in FIG11A to FIG12B on the side of the first semiconductor layer 4 facing away from the substrate 1;

[0392] S3, forming the second gate layer 8 shown in FIG. 11A to FIG. 12B on the side of the first gate layer 6 facing away from the substrate 1;

[0393] S4, forming the second semiconductor layer 10 shown in FIG. 11A to FIG. 12B on the side of the second gate layer 8 facing away from the substrate 1;

[0394] S5, forming the third gate layer 12 shown in FIG. 11A to FIG. 12B on the side of the second semiconductor layer 10 facing away from the substrate 1;

[0395] S6. Forming the first source-drain conductive layer 14 - 1 shown in FIG. 11A to FIG. 12B on the side of the third gate layer 12 facing away from the substrate 1 ;

[0396] S7, forming the second source-drain conductive layer 17 shown in FIG. 11A to FIG. 12B on the side of the first source-drain conductive layer 14 - 1 facing away from the substrate 1 ;

[0397] The transmittance of the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the first display area AA1 and the first sub-area AK1 is lower than the transmittance of the first gate layer 6, the second gate layer 8 and the third gate layer 12 located in the second sub-area AK2.

[0398] The transmittance of the portion of the first source-drain conductive layer 14 - 1 located in the first sub-area AK1 is lower than the transmittance of the portion located in the second sub-area AK2 .

[0399] In at least one method for manufacturing a display panel provided in an embodiment of the present application, when forming the first source-drain conductive layer 14-1, an insulating layer (the fifth gate insulating layer in FIG. 7A ) may be first formed on the side of the first gate layer 6 facing away from the substrate 1. Then, the first source-drain conductive layer 14-1 may be formed according to the following steps:

[0400] S61, forming a first via hole (the via hole connected to the first semiconductor layer 4 in FIG. 7A , not shown in the figure) on the insulating layer (fifth gate insulating layer);

[0401] S62, patterning a first metal layer in the first display area AA1 and the first sub-area AK1, wherein the first metal layer is overlapped with the active portion of the first type transistor T3 and part of the active portion of the second type transistor through a first via hole;

[0402] S63, forming a second via hole (the via hole connected to the second semiconductor layer 10 in FIG. 7A , not shown in the figure) on the insulating layer (fifth gate insulating layer);

[0403] S64 , patterning a transparent conductive layer in the second sub-area AK2 , wherein the transparent conductive layer is overlapped with a portion of the active portion of the second type transistor through a second via hole.

[0404] In this embodiment, the first source-drain conductive layer 14-1 includes the source and drain of the first-type transistor T3, as well as the source and drain of a portion of the second-type transistor. The first source-drain conductive layer 14-1 needs to overlap with the active portions of the first semiconductor layer 4 and the second semiconductor layer 10, so vias need to be provided in the insulation.

[0405] In further embodiments, a third source-drain conductive layer 14-2 may also be formed. Specifically, the portion of the first source-drain conductive layer 14-1 located in the first sub-area AK1 includes metal. A first via hole may be first formed in the insulating layer 15. The metal layer of the first source-drain conductive layer 14-1 is then patterned in the first display area AA1 and the first sub-area AK1 to form electrodes 14B and 14C. Subsequently, a first planar layer 16-1 is formed. A second via hole is then formed in the first planar layer 16-1. Finally, the third source-drain conductive layer 14-2 is patterned in the second sub-area AK2. The third source-drain conductive layer 14-2 is made of a light-transmitting conductive material to form electrodes 14A and 14D. This prevents damage to the second semiconductor layer 10 during etching of the first source-drain conductive layer 14-1.

[0406] This embodiment also provides a pixel circuit, as shown in Figures 4A-5C, wherein the pixel circuit includes transistors T1-T7, wherein transistor T3 is a first type transistor T3, and transistors T2-T7 are second type transistors. In Figures 4A-4B, the pixel circuit generally includes: a driving subcircuit, a first reset subcircuit, a second reset subcircuit, and a third reset subcircuit, as well as a light emitting control subcircuit and a storage subcircuit. The storage subcircuit is respectively connected to the power signal line ELVDD or VDD and is configured to store the voltage of the first node N1; the first reset subcircuit is respectively electrically connected to the first node N1, the first reset signal line Reset(n) or Reset1(n), and the first initialization signal line Vinit1, and is configured to write the first initialization signal transmitted by the first reset signal line Reset(n) or Reset1(n) into the first node N1 under the control of the first reset signal transmitted by the first reset signal line Reset(n) or Reset1(n);

[0407] The second reset sub-circuit is electrically connected to the second node N2 and the data signal line Data(m), and is configured to reset the voltage of the second node N2;

[0408] The third reset sub-circuit is electrically connected to the fourth node N4, the anode 18 of the light-emitting device Q, and the second initialization signal line Vinit2, and is configured to write the second initialization signal transmitted by the second initialization signal line Vinit2 into the anode 18; the fourth node N4 is electrically connected to the anode 18 of the light-emitting device Q;

[0409] The light-emitting control subcircuit is electrically connected to the light-emitting control signal line EM(n), the first power signal line ELVDD or VDD, the second node N2, the third node N3 and the fourth node N4, respectively, and is configured to transmit the current used to make the light-emitting device Q emit light to the anode 18 under the control of the light-emitting control signal transmitted by the light-emitting control signal line EM(n); wherein the anode 18 and the fourth node N4 are electrically connected, and the cathode 22 of the light-emitting device is electrically connected to the second power signal line ELVSS or VSS.

[0410] In FIG. 5A to FIG. 5C , the pixel circuit generally includes: a driving subcircuit, a reset subcircuit, a light emitting control subcircuit, a storage subcircuit, and a signal writing subcircuit.

[0411] In FIG5A , T1 , T2 , and T7 are reset sub-circuits, T5 and T6 are light-emitting control sub-circuits, T3 is a driving sub-circuit, C1 and C2 are storage sub-circuits, and T4 is a signal writing sub-circuit.

[0412] In FIG5B , T1 and T2 are reset sub-circuits, T5 and T6 are light-emitting control sub-circuits, T3 is a driving sub-circuit, C1 and C2 are storage sub-circuits, and T4 is a signal writing sub-circuit.

[0413] In FIG5C , T1 and T2 are reset sub-circuits, T5 and T6 are light-emitting control sub-circuits, T3 is a driving sub-circuit, Cst is a storage sub-circuit, and T4 and T7 are signal writing sub-circuits.

[0414] The working methods of the pixel circuits in FIG. 5A to FIG. 5C may refer to the working methods in FIG. 4 to FIG. 4B , and are not described in detail here.

[0415] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0416] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, commodity, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, commodity, or device that includes the element.

[0417] The above is a detailed introduction to a display panel and a display device provided by the present disclosure. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method and core idea of ​​the present disclosure. At the same time, for those skilled in the art, according to the idea of ​​the present disclosure, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

[0418] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0419] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

[0420] References herein to "one embodiment," "an embodiment," or "one or more embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Furthermore, please note that instances of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0421] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0422] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present disclosure may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0423] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A display panel, wherein: include: A substrate, comprising a first display area and at least one second display area, wherein the first display area at least partially surrounds the at least one second display area; A plurality of first sub-pixels, located in the first display area; A plurality of second sub-pixels, located in the second display area, the first sub-pixel and the second sub-pixel each comprising a pixel circuit, the pixel circuit comprising a first type transistor, and the pixel circuit of the second sub-pixel comprising a first sub-area and a second sub-area except the first sub-area; And, the display panel further includes: A first semiconductor layer, located on one side of the substrate, including an active portion of the first type transistor; The orthographic projection of the portion of the first semiconductor layer located in the second display area on the substrate falls on at least the first sub-area, the pixel circuit of the second sub-pixel is configured to allow light to pass through, and the transmittance of the first sub-area is less than the transmittance of the second sub-area.

2. The display panel according to claim 1, wherein: The second sub-pixel includes a light-emitting device, the light-emitting device includes a light-emitting area and a non-light-emitting area, the first sub-area falls within the light-emitting area, and the second sub-area includes a first sub-area falling within the light-emitting area and a second sub-area falling within the non-light-emitting area; The transmittance of the first sub-region is smaller than the transmittance of the first sub-region, and the transmittance of the first sub-region is smaller than the transmittance of the second sub-region.

3. The display panel according to claim 2, wherein: The display panel includes a plurality of signal lines, and the plurality of signal lines include at least one of a gate line, a light emitting control signal line, a reset signal line, an initialization signal line, a data signal line and a first power signal line; The display panel further includes: A plurality of electrode layers, including a source, a drain and a gate of the first type transistor, wherein the plurality of signal lines are located in the plurality of electrode layers; Among them, the transmittance of the portion of the multiple electrode layers located in the first sub-region is lower than the transmittance of the portion located in the first sub-region; and the transmittance of the portion of the electrode layers located in the first sub-region is lower than the transmittance of the portion located in the second sub-region.

4. The display panel according to claim 3, wherein: The portions of the plurality of electrode layers located in the first sub-region include metal, at least some of the portions of the electrode layers located in the first sub-region include light-transmitting conductive material and metal, and the portions of the plurality of electrode layers located in the second sub-region include light-transmitting conductive material.

5. The display panel according to claim 3, wherein: The pixel circuit further includes a second type transistor, and the display panel further includes: A second semiconductor layer, comprising an active portion of the second type transistor, wherein a portion of the second semiconductor layer located in the second display area has an orthographic projection on the substrate that falls on at least the second sub-area, and the second semiconductor layer comprises a channel area; The transmittance of the second sub-region in the area where the channel area is located is smaller than the transmittance of the second sub-region in the area where the non-channel area except the channel area is located.

6. The display panel according to claim 5, wherein: The plurality of electrode layers located in the second sub-region in the area where the channel region is located include metal and light-transmitting conductive material, and the plurality of electrode layers located in the second sub-region in the area where the non-channel region is located include light-transmitting conductive material.

7. The display panel according to claim 5 or 6, wherein: The plurality of electrode layers include: A first gate layer, located on a side of the first semiconductor layer away from the substrate, comprising a gate of the first type transistor and a first electrode of a storage capacitor; a second gate layer, located on a side of the first gate layer away from the substrate, comprising a first gate of the second type transistor and a second electrode of the storage capacitor, and the second semiconductor layer comprising an active portion of the second type transistor; a third gate layer, located on a side of the second semiconductor layer away from the substrate, comprising at least a portion of the second gate of the second type transistor, and the second semiconductor layer is also located on a side of the second gate layer away from the substrate; A first source-drain conductive layer, located on a side of the second gate layer away from the substrate, comprising at least the source and drain of the first type transistor and at least part of the second type transistor; A second source-drain conductive layer, located on a side of the first source-drain conductive layer away from the substrate, at least including at least a portion of the source and drain of the second type transistor; The gate line, the light emitting control signal line, the reset signal line, and the initialization signal line are located on at least one layer of the first gate layer, the second gate layer, and the third gate layer, and the first power signal line and the data line are located on at least one layer of the first source-drain conductive layer and the second source-drain conductive layer.

8. The display panel according to claim 7, wherein: The first gate layer, the second gate layer and the third gate layer in the first sub-region include metal, and the second sub-region in the non-channel region includes a light-transmitting conductive material, and the second gate layer and / or the third gate layer in the second sub-region in the channel region includes a light-transmitting conductive material and metal; The first source-drain conductive layer and the second source-drain conductive layer include metal in the first sub-region, include the light-transmitting conductive material and metal in the first sub-region, and include light-transmitting conductive material in the second sub-region.

9. The display panel according to claim 8, wherein: The third gate layer is located in the second sub-region and includes a first sub-layer and a second sub-layer in the area where the channel region is located, the material of the first sub-layer includes the metal, and the material of the second sub-layer includes the light-transmitting conductive material; The first sublayer is located on a side of the second sublayer facing away from the substrate, and an orthographic projection of the first sublayer on the substrate covers an orthographic projection of the second sublayer on the substrate.

10. The display panel according to claim 8, wherein: The thickness of the light-transmitting conductive material included in the first source-drain conductive layer and the second source-drain conductive layer located in the second sub-region is greater than the thickness of the light-transmitting conductive material in the first gate layer, the second gate layer and the third gate layer located in the second sub-region.

11. The display panel according to claim 8, wherein: The first source-drain conductive layer further includes a connection layer connected to the second semiconductor layer, and the connection layer includes metal.

12. The display panel according to claim 8, wherein: The first source-drain conductive layer and the second source-drain conductive layer located in the first sub-region both include a first sub-layer and a second sub-layer, the material of the first sub-layer includes the metal, and the material of the second sub-layer includes the light-transmitting conductive material; The second sub-layer is located on a side of the first sub-layer facing away from the substrate.

13. The display panel according to claim 8, wherein: The portion of the first gate layer located in the first sub-region further includes the light-transmitting conductive material.

14. The display panel according to claim 8, wherein: The display panel further includes: a third source-drain conductive layer, located between the first source-drain conductive layer and the second source-drain conductive layer in the thickness direction of the substrate, the third source-drain conductive layer including at least part of the source and part of the drain of the second type transistor; The orthographic projection of the third source-drain conductive layer on the substrate is located in the non-light-emitting sub-region, and the third source-drain conductive layer includes a light-transmitting conductive material.

15. The display panel according to claim 8, wherein: The gate portion of the second type transistor in the second display area in the second gate layer and / or the third gate layer includes a first sublayer and a second sublayer, the material of the first sublayer includes the metal, and the material of the second sublayer includes the light-transmitting conductive material; The orthographic projection of the first sublayer on the substrate and the orthographic projection of the channel region of the second semiconductor layer on the substrate have a first overlapping area, and the orthographic projection of the second sublayer on the substrate and the orthographic projection of the channel region of the second semiconductor layer on the substrate have a second overlapping area, A size of the first overlapping region in a first direction is greater than a size of the second overlapping region in the first direction, and the first direction is a direction from the channel region to the non-channel region.

16. The display panel according to claim 15, wherein: The portions of the second gate layer and the third gate layer used as the gates of the second type transistors in the first display area include a metal conductive layer; an orthographic projection of the metal conductive layer on the substrate and an orthographic projection of the channel region of the second semiconductor layer on the substrate have a third overlapping area; The size of the third overlapping area in the first direction is equal to the size of the first overlapping area in the first direction.

17. The display panel according to claim 3, wherein: The second display area includes a middle display area and a transition area from the middle display area to the first display area; Part or all of the signal lines located in the transition region include metal and light-transmitting conductive material.

18. The display panel according to claim 1, wherein: The display panel further includes: A light shielding layer, located on a side of the first semiconductor layer close to the substrate; The portion of the light shielding layer located in the first sub-region includes metal and light-transmitting conductive material, and the portion of the light shielding layer located in the second sub-region includes light-transmitting conductive material.

19. A display device, wherein: The invention comprises the display panel according to any one of claims 1 to 18.

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