Method for diagnosing current cables, test device for diagnosing same and computer program

Abstract

The invention relates to a method for diagnosing a current cable, the method comprising: receiving test data relating to a measurement on the current cable; providing an equivalent circuit (1) of the current cable with a plurality of equivalent switching units (2, 3, 6, 7), which have first and second conductor networks (4, 5) each connected in series, wherein the first conductor network (4) takes account of the skin effect of the current cable and the second conductor network (5) takes account of the proximity effect of the current cable; determining the parameters of the equivalent circuit (1) based on the received test data; and carrying out the diagnosis using the determined parameters (R, L, M, G, C).

Description

[0001] Description

[0002] Method for diagnosing power cables, test device for diagnosing the same and computer program

[0003] TECHNICAL FIELD

[0004] The invention relates to a method for diagnosing power cables, preferably high-current cables, having the features of the preamble of claim 1, in particular a fault diagnosis method, and a test device for diagnosing such a power cable, as well as a computer program and a data carrier in connection therewith.

[0005] The following background is intended only to provide information necessary to understand the context of the inventive ideas and concepts disclosed herein. Therefore, this background section may contain patentable subject matter and should not, per se, be considered prior art.

[0006] BACKGROUND

[0007] The use of high-current cables in power transmission systems presents various technical challenges that can be addressed through precise modeling of these cables. Modeling plays a crucial role in identifying, analyzing, and solving problems that may arise in connection with high-current transmission.

[0008] A key technical problem that can be solved through modeling is the overheating of high-current cables. Due to the intense current flow through these cables, heat is generated, which can lead to an increase in operating temperature. Modeling enables the simulation of thermal effects and the analysis of heat generation in various operating scenarios. By identifying overheating risks, appropriate measures can be taken to protect the cables from damage and ensure reliable power transmission.

[0009] Another problem concerns the electromagnetic fields generated by high-current cables. These fields can affect neighboring electronic systems and cause interference. Modeling enables the accurate prediction of these electromagnetic effects and allows the development of appropriate shielding measures to minimize interference and optimize the overall performance of the transmission system.

[0010] Power losses in high-current cables also pose a technical challenge. Modeling allows for the analysis of various factors that contribute to power losses, including the cable's ohmic resistance and capacitive effects. Based on this, optimizations can be made to increase power transmission efficiency and minimize power loss.

[0011] Modeling also plays a key role in predicting the transient behavior of high-current cables, especially during switching operations. Transient currents can lead to voltage spikes that compromise system stability. By creating models that account for the dynamic behavior of cables under various operating conditions, protection mechanisms can be designed to ensure system integrity and prevent unwanted effects.

[0012] Another area where modeling of high-current cables is crucial concerns the selection of suitable materials. The physical properties of the materials directly influence the performance and reliability of the cables. By integrating material models into the overall models, different scenarios can be analyzed and the optimal material composition for specific requirements can be identified. In summary, accurate modeling of high-current cables helps solve technical problems related to, for example, overheating, electromagnetic fields, power losses, transient behavior, or material selection. These models enable informed decisions to improve the efficiency and reliability of high-current transmission systems while addressing the challenges associated with transmitting large amounts of electrical power.

[0013] The invention is based on the object of eliminating disadvantages of the prior art, in particular to provide a better diagnosis of power cables.

[0014] SUMMARY

[0015] This summary is intended to introduce a selection of features and concepts of the invention that are explained further in the description. This summary is not intended to identify important or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0016] According to the invention, the above-mentioned object is achieved by the features of the independent claims.

[0017] Specifically, the problem is solved by a method for diagnosing, preferably remotely and / or fault diagnosing, (high-)power cables. The method comprises receiving test data relating to a measurement on the power cable. The method comprises providing an equivalent circuit of the power cable having a plurality of equivalent circuit blocks. Each equivalent circuit block of the plurality of equivalent circuit blocks has series-connected first and second conductor networks. The first conductor network takes into account the skin effect of the power cable. The second conductor network takes into account the proximity effect of the power cable. The method comprises determining the parameters of the equivalent circuit based on the received test data. The method comprises performing the diagnosis using the determined parameters.

[0018] The invention has the advantage that accuracy and prediction of the condition of the rated power cable can be improved.

[0019] To explain: The skin effect refers to the concentration of electric current on the outer surface of a power cable conductor at higher frequencies. This occurs due to the interaction of electric fields that force the current density to concentrate on the outer layers of the power cable conductor. As the frequency increases, the current in the power cable conductor may therefore tend to be confined to the outer layers, resulting in less utilization of the overall conductor cross-section. The proximity effect occurs when several parallel power cable conductors carry high-frequency currents. In this case, the electric fields of the adjacent power cable conductors influence each other. This can cause the current in the conductor to tend to concentrate on the side closer to the adjacent power cable conductor.This results in the usable cross-section of the conductor being distributed unevenly, which can lead to an increase in the effective resistance and additional losses.

[0020] The measurement mentioned may include impedance measurements that exhibit a frequency dependence. The impedance measurements resulting from the impedance measurements may be time- and / or frequency-resolved.

[0021] The test data can be provided by the impedance measuring device mentioned below. The test data can be converted by the impedance measuring device directly from the impedance measurement values ​​as raw data into a cleaned / pre-filtered format containing cleaned / pre-filtered time- and / or frequency-resolved impedance measurement values. The cleaning or pre-filtering can, in particular, filter out measurement values ​​that are below a first threshold and / or above a second threshold. The first threshold can correspond to a minimum of possible impedance values ​​of the power cable, and the second threshold can correspond to a maximum of possible impedance values ​​of the power cable.

[0022] The term "conductor network" can be understood here not as referring to the term "conductor" per se, but rather to a type of step-down or layered conductor. The steps, or layers here, can be similar to each other, for example, by containing the same number and / or type of elements, in this case, resistor and coil (inductance in the first conductor network and mutual inductance in the second conductor network).

[0023] The parameters can be the values ​​for resistances, self-inductances, mutual inductances, conductances and / or capacitances occurring in the equivalent circuit.

[0024] Advantageous embodiments of the invention are specified in the subclaims.

[0025] The first conductor network may comprise a resistance-inductance conductor network. The second conductor network may comprise a resistance-mutual inductance conductor network. Both the resistance-inductance conductor network and the resistance-mutual inductance conductor network may each comprise the same number of inductances and resistors. In the case of the first conductor network, the inductances may be self-inductances. In the case of the second conductor network, the inductances may be mutual inductances.

[0026] This can simplify modeling.

[0027] The number of elements of the first conductor network may be the same or different from the number of elements of the second conductor network. The number of elements of the respective first conductor networks of the plurality of equivalent circuit blocks may be the same. The number of elements of the respective second conductor networks of the plurality of equivalent circuit blocks may be the same. Thus, a simple model for improved power cable diagnostics can be provided.

[0028] The respective second conductor networks of series-connected equivalent circuit blocks of the plurality of equivalent circuit blocks can have mutually coupled mutual inductances. The mutual inductances can represent the inductances of the respective second conductor networks.

[0029] With the mutual inductances, the proximity effect can be better modeled and the energy system can be adapted accordingly.

[0030] Both the first conductor network and the second conductor network can be parameterized based on measurements on the power cable in the low-frequency and high-frequency ranges. The low-frequency range can cover a range from 1 ohms to 50 Hz or 500 kHz. The high-frequency range can cover a range above 1 kHz, for example, up to 10 kHz.

[0031] Negative influences can thus be divided into different areas and analyzed more easily.

[0032] The first conductor network can have two, three, or more levels / layers of a combination of resistance and inductance. The second conductor network can have two, three, or more levels / layers of a combination of resistance and mutual inductance. The number of levels / layers of the first and / or second conductor networks can be the same.

[0033] Each stage / layer of the first and / or second conductor networks can have exactly two elements: resistance and inductance. An input terminal of each first conductor network can be connected to each resistance of the corresponding first conductor network. An output terminal of each first conductor network can be connected to exactly one (self-)inductance of the corresponding first conductor network. An input terminal of each second conductor network can be connected to each resistance of the corresponding second conductor network. An output terminal of each second conductor network can be connected to exactly one (mutual)inductance of the corresponding second conductor network.

[0034] A resistor of the first stage / layer of the first / second conductor network can be connected to an inductance of the first and second stages / layers of the first / second conductor network. In general, it can be said that a resistor of the nth stage / layer of the first / second conductor network can be connected to an inductance of the nth and n+1st stages / layers of the first / second conductor network. Here, n can be a positive integer > 1. Furthermore, it can be said that an inductance of the nth stage / layer of the first / second conductor network can be connected to an inductance of the n+1st stage / layer of the first / second conductor network and an inductance of the n+1st stage / layer of the first / second conductor network.

[0035] For example, the power cable can be a multi-phase high-current cable. This allows the application area to be precisely defined.

[0036] The above-mentioned object is also achieved by a computer program. The computer program comprises instructions that, when the computer program is executed by a computer or by the test device mentioned below, cause the computer or the test device to execute or initiate the method described above or at least one of the steps thereof. The computer program can, for example, be a module for starting / operating the computer or the test device as described herein.

[0037] The above-mentioned task is also achieved by a data storage medium. The computer program can be stored on a machine-, processor-, or computer-readable storage medium, such as a permanent or rewritable storage medium. This also includes the possibility of making the computer program available for download on a server or a cloud server, e.g., via a data network such as the Internet or a communications connection such as a wireless connection.

[0038] The above-mentioned object is also achieved by a test device for diagnosing a power cable. The test device has an impedance measuring device. The impedance measuring device is designed to apply a test signal to the power cable. The impedance measuring device is designed to acquire or provide test data based on the test signal as a response from the power cable. The test device has a processor. The processor is designed to determine parameters of an equivalent circuit of the power cable based on the test data. The processor is designed to perform the diagnosis using the determined parameters. The equivalent circuit has a plurality of equivalent circuit blocks. The plurality of equivalent circuit blocks each have first and second conductor networks connected in series. The first conductor network takes the skin effect into account. The second conductor network takes the proximity effect of the power cable into account.

[0039] This can improve the reliability and accuracy of power cable diagnostics, particularly the impact on the high current source and electrical machine.

[0040] In other words, the invention relates to a modeling method for power cables in electric drives. In particular, a high-frequency model in the form of an electrical circuit is created for modeling power cables with an outer shield. The cable model takes both capacitive and inductive coupling into account. Compared to conventional techniques, the frequency-dependent mutual inductances between the various phases of the cable system are realized by a so-called resistance-mutual inductance conductor network. The method presented here can also model other components with frequency-dependent mutual inductance due to inductive coupling, including electrical machines. A high-frequency model in the form of an electrical circuit can be created for power cables with an outer shield. The high-frequency model takes both capacitive and inductive coupling into account.This allows frequency-dependent mutual inductances to be implemented between different phases. The cable model can be used to predict the overvoltage behavior at motor terminals during inverter-fed operation.

[0041] For explanation, a cable system with three-phase conductors and an outer shield is used as an example. The cable model can consist of differential mode and common mode circuits. The differential mode circuits for each phase and the shield of the cable system can extend from one cable end to another and each can have several series-connected push-pull units (also called push-pull circuit blocks herein). Each of the push-pull units described above has a circuit branch structure that takes the skin effect into account and another circuit branch structure that takes the proximity effect into account. The circuit branch structure that takes the skin effect into account is called a resistor-inductor ladder network and is intended to model an impedance that varies with frequency.In contrast, the circuit branch structure that takes the proximity effect into account is called a resistance-mutual inductance-ladder network and is intended to model a mutual inductance or mutual impedance that varies with frequency. The circuit branch structure that takes the proximity effect into account can consist of a network of resistors and mutual inductors. The network of resistors and mutual inductors can contain resistors and mutual inductors connected in series and in parallel. Here, a resistor and a mutual inductor can be connected in series to form a first branch circuit or a first layer of the network. The resistor of the first layer can be connected in parallel with a second branch circuit consisting of resistors and mutual inductors, forming a second layer of the network.The resistor of the second branch circuit can be connected in parallel with a third branch circuit, forming a third layer of the network. In general, the resistor of the nth branch circuit can be connected in parallel with the n+lth branch circuit, forming an n+lth layer.

[0042] The common-mode circuit can be created for the three phases of the cable conductors. For each phase, the common-mode units (also called common-mode circuit blocks) extend from the terminals of the cable system or the connection points between the differential-mode units to the shield. The common-mode unit includes resistors and capacitors.

[0043] In model implementation, each phase conductor in the cable and the outer shield can have two or three series-connected push-pull units, respectively. The resistance-mutual inductance ladder network in each push-pull unit can have two or three layers of resistance and mutual inductance in each push-pull unit. Similarly, the resistance-inductance ladder network corresponding to the skin effect can have two or three layers of resistance and inductance in each push-pull unit.

[0044] The parameters of each element of the equivalent circuit can first be pre-estimated based on the actually measured impedance spectrum. Then, the deviation of the impedance spectrum from the measured impedance spectrum calculated based on the pre-estimated circuit model can be used as a cost function. Finally, using a parameter optimization algorithm, the values ​​of all parameters can be iterated, and a minimum value of the cost function can be determined, whereby an optimal value of all parameters can be obtained. The parameter optimization method can consider the similarity among different phases and different push-pull units as follows. For the similarity among different push-pull units, the scaling factor between the parameters of the same phase at corresponding locations in the different push-pull units can be in a range of 0.8 to 1.2.To ensure similarity among the three phases, the initial parameter values ​​of a phase are first estimated for the components in that phase. Then, the parameters of the components at the same locations in the other phases are proportional to the parameters of the component in one phase. The proportionality coefficients range from 0.8 to 1.2. In particular, the method can be used to construct high-frequency models for power cables with an external shield.

[0045] In other words, the invention relates to a modeling methodology for power cables (herein referred to as power cables) in electrical machines. For example, a method is proposed for determining the maximum voltage at motor terminals to avoid defects due to overvoltage behavior. In shielded power cables with multiple phases, the following effects can influence the voltage behavior: self-inductance (skin effect), mutual inductance (proximity effect), and capacitive couplings between the phases of the power cable and the shield. In particular, the frequency-dependent mutual inductance of the various phases of a three-phase cable system can be considered here. Likewise, the frequency dependence of the capacitive couplings can be considered and integrated into the model. For a complete description of these effects, a network structure, including frequency dependencies, can be modeled and parameterized.To more accurately predict overvoltage behavior, for example, at motor connections, the power cables are measured and then used to parameterize the network structure model. The results can then be used to precisely design the parameters for the control technology.

[0046] Thus, a method can be envisaged for determining the voltage behavior on shielded power cables with multiple phases. This can involve, for example, in the following order: a) measuring cable parameters, b) parameterizing the model of the network structure, taking into account the frequency-dependent variables of self-inductances, mutual inductances, and capacitive couplings, e) defining an overvoltage behavior, and f) designing a control technology for application, for example, to motor connections (for electromobility, wind turbines, etc.). Even if some of the aspects described above relate to the method or the test device, these aspects can also apply to the other aspects accordingly.

[0047] In one example, the test device can be implemented using hardware circuits, software means, or a combination thereof. For example, multiple units of the test device can each be realized in a single physical unit, for example, when multiple functions are implemented in software. The units of the test device can also be implemented in hardware components. The units of the test device are each to be understood as functional units that are not necessarily physically separated from one another. For example, the test device can be realized at least partially as a computer, field-programmable logic array (FPLA), field-programmable gate array (FPGA), microcontroller, CPU (e.g., with multiple cores), graphics processing unit (GPU), application-specific integrated circuit (ASIC), and / or digital signal processor (DSP).

[0048] For example, methods can be used in the test device which are related to pipelining the test data. In this case, instead of an entire instruction being processed in one clock cycle of the processor used in the test device, only a sub-task of it, e.g. a portion of the test data. The various sub-tasks of several instructions are processed simultaneously. Furthermore, methods such as multithreading on the test data and further developments thereof can be applied, e.g. simultaneous multithreading of the test data. This enables better utilization of the processors due to the parallel use of several processor cores. The test device can be scalar or superscalar. The processor contained in the test device can be connected to a buffer memory of the test device which temporarily stores the test data before and / or after the test data has been processed.of the part of it. The buffer memory can be integrated into a volatile memory of the test device, e.g., a (D)RAM, or into a permanent memory of the test device, e.g., a non-volatile storage device such as an SSD. This can increase the performance of the test device.

[0049] All technical and scientific terms used herein have the meaning generally understood by those skilled in the art in the technical field of electrical power engineering; they are to be interpreted based on the definitions found in the dictionary or the technical jargon of that technical field. If technical terms are used incorrectly and thus do not express the technical spirit of the present invention, they shall be replaced by technical terms that provide a correct understanding to those skilled in the art.

[0050] The terms "first" and "second" are merely intended to distinguish components from one another. For example, a first component can be referred to as the second component, and a second component as the first component. It should be noted that these terms, as well as all numerical designations ("one," "two," etc.), are not intended to be exhaustive with regard to the scope of protection, but are also disclosed as exhaustive with regard to the disclosure content. For example, the expression "two ABC" can mean either "exactly two ABC" or "two or more ABC." For example, a sequence can be disclosed in this way.

[0051] If it is stated here that a component is "connected" or "communicates" with another component, this may mean, for the purposes of the present disclosure, that these components may also be directly connected or communicate with each other. The term "directly" indicates that no further component is present in between.

[0052] The process steps described herein should not be interpreted as requiring them to be performed in a particular order, unless expressly or implicitly stated otherwise, for example, if these process steps cannot be interchanged for technical reasons. The process steps may also be performed directly one after the other (without any further intervening steps) and / or continuously. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Further objects, features, advantages, and possible applications will become apparent from the following description of non-limiting embodiments with reference to the accompanying drawings, in which:

[0054] Fig. 1 is a view of an equivalent circuit of a power cable;

[0055] Fig. 2 is another view of an equivalent circuit of a power cable in a three-phase system;

[0056] Fig. 3 is a view of a method for diagnosing the power cable; and

[0057] Fig. 4 is a view of a test device for diagnosing the power cable.

[0058] The reference symbols used in the drawings and their meanings are summarized in the list of reference symbols at the end of this description. The same or similar components in the drawings are always provided with the same or similar reference symbols. Detailed explanations of known functions and structures are omitted if they detract from the invention.

[0059] DETAILED DESCRIPTION OF THE DRAWINGS

[0060] The method and test apparatus will now be described with reference to the embodiments. Without being limited thereto, specific details are explained to provide a deeper understanding of the invention.

[0061] Fig. 1 shows a view of an equivalent circuit 1 of a power cable. Fig. 2 shows, by way of example, another view of an equivalent circuit of a power cable in a three-phase system to clarify the application of the embodiments shown in Fig. 1. Fig. 3 shows a view of a method 50 for diagnosing the power cable. Fig. 3 will be explained below in conjunction with Fig. 1.

[0062] The method SO begins in S1 by receiving test data relating to a measurement on the power cable.

[0063] Before, during, or as a result, an equivalent circuit 1 of the power cable is created or provided in S2. The equivalent circuit 1 has a plurality of equivalent circuit blocks, represented here in the form of the first and second common-mode circuit blocks 2 and 6 (common-mode equivalent circuit blocks) and the first and second differential-mode circuit blocks 3 and 7 (differential-mode equivalent circuit blocks). The first and second common-mode circuit blocks 2 and 5 can be connected upstream and downstream of the first and second differential-mode circuit blocks 3 and 7, respectively. Each of the first and second differential-mode circuit blocks 3 and 7 has series-connected first and second conductor networks 4 and 5. The first conductor network 4 relates to the skin effect of the power cable, and the second conductor network 5 relates to the proximity effect of the power cable.

[0064] In S3, the parameters of equivalent circuit 1 are determined based on the received test data. The parameters include R1-R6, L1-L3, M1-M3, G1-G3, C1-C4, R1-R6, L1X-L3X, M1-M3, G1-G3, and C1-C4. Here, λ denotes a proportionality coefficient based on the parameters of equivalent circuit 1 assumed before the determination in S3 and the impedance measurement on the power cable.

[0065] In S4, a diagnosis is then performed using the determined parameters. This allows a prediction of voltage behavior, particularly overvoltage behavior, for example, at motor terminals in converter-fed operations. This allows for adaptation or improvement of the application, production, or use of the power cable. This allows future predictions to be more accurate and therefore more reliable due to the expanded equivalent circuit 1 of the power cable. Overall, this also allows for cost savings, such as manufacturing costs.

[0066] The method steps represented as blocks of the block diagram in Fig. 3 can, for example, be substantially mapped on a machine-, processor- or computer-readable data carrier and thus executed by a computer, in particular a test device 8 or a processor 9, as described below with reference to Fig. 4. Examples can further be or relate to a computer program which contains program code for executing at least some of the method steps from Fig. 3 when the computer program is executed on the computer, in particular the test device 8 or the processor 9. An example can also be a volatile memory 10 or persistent memory 11, as also described below with reference to Fig.4, which are machine-, processor- or computer-readable and encode machine-executable, processor-executable or computer-executable programs with instructions that cause the execution of some or all of the method steps.

[0067] Fig. 4 schematically shows a block diagram illustrating the test device 8 for diagnosing the power cable. The test device 8 implements one or more steps of the method SO, as illustrated in Fig. 3. In particular, the test device 8 provides functionality, such as computer software, that runs on the test device 8 and executes one or more steps of the method SO.

[0068] The term test data used herein may include, in particular, frequency-dependent impedance measurements or impedance measurement values.

[0069] In particular, the test device 8 may execute instructions associated with the test data contained in the computer program described herein and cause the test device 8 to execute or initiate the one or more steps of the method SO. It is contemplated herein that the test device 8 may take any suitable physical form. As an example, the test device 8 may be embodied at least partially as an embedded computer, system-on-chip (SOC), single-board computer (SBC), server, and / or user equipment (UE). The test device 8 may be unitary or distributed; span one or more locations; span one or more machines or data centers; or be located in a cloud, which may include cloud components in a network. The test device 8 may execute or initiate one or more steps of the method SO without substantial spatial or temporal limitations.For example, the test device 8 can execute or initiate one or more steps of the method SO in real time, in parallel, or in batch mode. The test device 8 can execute or initiate step(s) of the method SO at different times or at different locations.

[0070] The test device 8 has at least one or more of the following components: the processor 9, the volatile memory 10, the persistent memory 11, a bus 12, an arbiter 13, one or more interfaces 14, an impedance measuring device 15, a main power supply 16, and an auxiliary power supply 17. The components of the test device 8 can be implemented at least partially in hardware and / or software. The interconnection of the components of the test device 8 is structured as shown in Fig. 4 merely for the sake of simplicity. In particular, the interconnection and connection may differ in implementation due to signal processing and signaling.

[0071] The processor 9 has means for executing instructions associated with the test data, e.g., of the computer program described herein. For example, the processor 9 may load the instructions associated with the test data contained in the computer program described herein, e.g., from the volatile memory 10 and / or the persistent memory 11, and then execute the instructions, which in turn causes the processor 9 to execute or initiate the one or more steps of the method 50, as illustrated, e.g., in Fig. 3. The processor 9 may have an internal register / cache for the test data, for the instructions associated with the test data, and / or for associated addresses. The processor 9 may have an FPGA, ASIC, DSP, microcontroller, a CPU, and / or GPU for accessing the internal register / cache.As an example, to execute the instructions associated with the test data, the processor 9 may retrieve them from the internal register / cache of the processor 9, the volatile memory 10, or the persistent memory 11; decrypt and execute them; and then write a result to the internal register / cache of the processor 9, the volatile memory 10, or the persistent memory 11.

[0072] As an example, processor 9 may include an instruction cache, a data cache, and / or a translation buffer (TLB). The test data-related instructions in the instruction cache may be copies of instructions in volatile memory 10 and / or persistent storage 11, and the instruction cache may accelerate the retrieval of these test data-related instructions by processor 9. The test data in the data cache may be copies of data for the test data-related instructions currently executing on processor 9. The results of previous test data-related instructions executed on processor 9 may be provided for access by subsequent test data-related instructions to be executed on processor 9, or for writing to volatile memory 10 and / or persistent storage 11.The data cache can accelerate the read or write operations of processor 9. The addresses in the TLB associated with the test data can be address references to addresses in volatile memory 10 and / or persistent memory 11 to accelerate virtual address translation for processor 9.

[0073] The volatile memory 10 can be a dynamic RAM (DRAM) or a static RAM (SRAM). The volatile memory 10 can be embodied, in particular, as the data storage medium described herein, on which the computer program described herein can be stored, at least temporarily. Furthermore, the volatile memory 10 can be a single-channel or multi-channel RAM. The volatile memory 10 can have a main memory for storing instructions related to the test data for the processor 9, which then executes these instructions; or the test data for the processor 9, which the processor 9 uses to operate on them. For example, the test device 8 can load these instructions into the volatile memory 10 from the persistent memory 11 or another source (such as another computer, the network, or the cloud).Processor 9 can then load these instructions from volatile memory 10 into the internal register / cache of processor 9. To execute these instructions, processor 9 can retrieve and decrypt these instructions from the corresponding internal register / cache. During or after executing these instructions, processor 9 can write a result (which can be intermediate or final results) to the internal register / cache. Processor 9 can then write the result to volatile memory 10.

[0074] For example, processor 9 executes only the instructions related to the test data in the internal register / cache of processor 9 or in volatile memory 10 (as opposed to persistent memory 11), and operates only on the test data in the internal register / cache of processor 9 or in volatile memory 10 (as opposed to persistent memory 11).

[0075] The persistent memory 11 has a mass storage device, e.g., a non-volatile mass storage device (NVM), for the test data or the instructions associated with the test data. The persistent memory 11 can, in particular, be embodied as the data storage device described herein, on which the computer program described herein can be stored. As an example, the persistent memory 11 can be a flash memory, in particular an SSD or eMMC. The persistent memory 11 can store the test data in an erasable or non-erasable manner. The persistent memory 11 can be located in the test device 8, i.e., internally, or externally.

[0076] The processor 9 can be connected to the persistent memory 11 directly or indirectly, e.g., via the arbiter 13. The connection can be implemented via a clock bus, command bus, and data bus. This is shown only schematically using bus 12 in Fig. 4. The persistent memory 11 receives commands associated with the test data and the test data in conjunction with a clock signal provided by the processor 9 on the clock bus. The clock signal clocks the reception of the commands associated with the test data and the test data. The processor 9 sends a command associated with the test data to the persistent memory 11 via the command bus. Furthermore, the processor 9 sends the test data corresponding to the command via the data bus to the persistent memory 11 or receives the test data from the persistent memory 11 via the data bus.

[0077] In one example, persistent memory 11 may have a clock pin through which the clock signal is received at persistent memory 11. The clock signal may be a write enable signal and / or a read enable signal. Persistent memory 11 may further have first and second input / output (I / O) pins. Test data is received at persistent memory 11 via the first I / O pin in synchronization with the clock signal. Persistent memory 11 may further have a command / address buffer, control logic, and an I / O buffer. The command / address buffer operates at a first operating speed and, synchronously with the clock signal, buffers the command and corresponding address received via the second I / O pin and associated with the test data. One I / O buffer operates at the first operating speed and buffers the test data as read data from the NVM or writes the test data as write data to the NVM. The first and second I / O pins may coincide.Here, the clock signal can be formed by a first and second clock signal, in which the first clock signal only switches during a period in which the command and the address (both related to the test data) are received from persistent memory 11, and the second clock signal only switches during a period in which the test data is received from persistent memory 11. The first operating speed corresponds to a data input speed or data output speed between persistent memory 11 and processor 9. The control logic controls an operation with respect to the NVM based on the buffered command and the buffered address (both related to the test data). Here, the control logic operates at a second operating speed, which is lower than the first operating speed and corresponds to an internal operating speed of persistent memory 11.

[0078] The bus 12 can be understood herein as a subsystem of the test device 8 that transmits the test data and / or electrical power between the components of the test device 8. The (one) bus 12 can connect the components of the test device 8 to one another via the same set of lines. The bus 12 can be designed for dedicated communication of the test data between two or more of the components of the test device 8. The bus 12 can be a system bus via which the processor 9 is connected to the other components of the test device 8. In this case, the bus 12 can be synchronous - the test data is transferred bidirectionally with a clock edge of a clocking of the bus 12 - and / or asynchronous - no clocking, but a handshake takes place to transfer the test data.In such a semi-synchronous system bus, the bus 12 is clocked, but control lines allow wait cycles to also use slow components, such as the persistent memory 11, via the bus 12.

[0079] Arbiter 13 can be provided for at least partial control over bus 12. Arbiter 13 can be considered a coprocessor subordinate to processor 9. Arbiter 13 regulates access to bus 12 related to the test data based on a two-way handshake or three-way handshake. For this purpose, the three signals Bus Request (BREQ) are used to forward the test data, Bus Grant (BGRT) to confirm and approve the forwarding, and Bus Grant Acknowledge (BGA) for optional forwarding confirmation. Arbiter 13 simultaneously receives several BREQs from different components of test device 8 via bus 12. Arbiter 13 sorts the BREQs by priority and forwards them sequentially—in a pipeline—to processor 9. Once the processor 9 has received the BREQ, the processor 9 sends the BGRT to the arbiter 13 or directly to the component of the test device 8 that sends the BREQ.A subordinate BREQ of the BREQs in the pipeline—e.g., from another component of the test device 8—is forwarded to the processor 9 in response to a BGRT sent by the processor 9 relating to the BREQ with priority in the pipeline and related to at least a portion of the test data. The BGRT relating to the subordinate BREQ is sent by the processor 9 to the arbiter 13 after at least a portion of the test data has been processed. The arbiter 13 can, for example, in turn, in response to the BGRT relating to the subordinate BREQ, send a BREQ of the BREQs further down the pipeline—which, for example, relates to another portion of the test data—to the processor 9. Likewise, in response to each BGRT from the processor 9, the arbiter 13 can send a respective BGA relating to it to the processor 9. With the procedure described herein, a BGA can also be omitted entirely.This saves overhead in the communication between the components of the test device 8. That is, a two-way handshake is provided instead of a three-way handshake.

[0080] Bus 12 can also include a data bus, address bus, and control bus. The test data is transmitted bidirectionally between the components of test device 8 via the data bus. The address bus is operated solely by processor 9 and unidirectionally transmits memory addresses associated with the test data. The control bus is controlled solely by arbiter 13, e.g., in the sense of a watchdog, and transfers control of it to the processor in the pipelined manner described above to control the transmission of the test data.

[0081] The interface(s) 14 can enable frequency-dependent impedance measurements on the power cable, for example, in the immediate vicinity of the test device 8. The interface(s) 14 can be connected to a (e.g., external) impedance measuring device that couples to the processor 9 of the test device 8. The interface(s) 14 can have device and / or software drivers that enable the processor 9 to control the interface(s) 14 to obtain measured values ​​(the frequency-dependent impedance measured values) from the impedance measuring device, on which the test data are based or which are represented by the test data. The interface(s) 14 enable the test device 8 to communicate with a network, e.g., Bluetooth, WLAN, a mobile radio system, and / or at least part of the Internet.The interface(s) 14 provide means for communicating (such as packet-based communication) the test data between the test device 8 and other communication participants, e.g., to the network connected to the test device 8 (wired - via cable, e.g., optical connection - and / or wireless - via antenna).

[0082] The test device 8 as a New Radio (NR) UE can be used in Narrow Band (NB) Internet of Things (IoT) applications where only occasional and small amounts of data are transmitted in the uplink (UL), such as the test data. For example, the test data can be transmitted when the test device 8 is in a Radio Resource Control (RRC) CONNECTED state, which requires a significant amount of electrical power from the main power supply 16 or the auxiliary power supply 17. However, since the amount of NB-IoT data is small, the test data can be transmitted less frequently and more efficiently. In particular, the different RRC states of the test device 8 consume different amounts of resources, and therefore, the transition between the RRC states can efficiently reduce network resources.The test device 8 can be in one of the following states: (NR) RRC CONNECTED state, (NR) RRC INACTIVE state and (NR) RRC IDLE state.

[0083] When the test device 8 is turned off (e.g., when no electrical power is supplied from the main power supply 16 and / or the auxiliary power supply 17), the test device 8 is in a disconnected state and is not in any of the three RRC states. After the test device 8 is turned on, the test device 8 may initially transition to the RRC IDLE state. In the RRC IDLE state, the test device 8 may attempt to establish a wireless connection with a serving base station (e.g., gNB - not shown) and transition to the RRC CONNECTED state. After the test device 8 transitions, the test device 8 may also be released from the RRC CONNECTED state to return to the RRC IDLE state. However, after the initial transition to the RRC CONNECTED state, the test device 8 may transition to the RRC INACTIVE state to more efficiently utilize network resources.The RRC INACTIVE state of the test device 8 can be released, resumed, or suspended to transition back to the RRC CONNECTED state. Furthermore, the test device 8 can be released from the RRC INACTIVE state and transition back to the RRC IDLE state. The RRC INACTIVE state minimizes latency and reduces signaling load, thereby utilizing network resources more efficiently and reducing the power consumption of the test device 8 during test data transmission.

[0084] For example, the test device 8 may be part of a 4-stage Random Access Channel (RACH) transmission procedure, which includes the transmission of four messages (Msgl, Msg2, Msg3, and Msg4) before transmitting the test data to the serving base station. Here, the test device 8 may perform a random access by sending a RACH preamble—e.g., Msgl—on a RACH resource. The serving base station may respond with a Random Access Response (RAR)—e.g., Msg2. The test device 8 may then send a Radio Resource Control (RRC) connection request—e.g., Msg3—on the Physical Uplink Shared Channel (PUSCH) (e.g., NR-PUSCH). The serving base station may then respond with an RRC Connection Setup—e.g., Msg4—that completes the initial access process of the test device 8.This RACH mode is an inefficient way of transmitting the test data, since only after the four messages is a transmission of the test data between the test device 8 and the serving base station.

[0085] Another example: The test device 8 can be part of an Early Data Transmission (EDT) procedure that includes the transmission of two messages (Msg1 and Msg2) before transmitting the test data to the serving base station. This means that in this EDT mode, the test device 8 can send the test data in message 3 (Msg3), and the serving base station can send the downlink (DL) data in message 4 (Msg4) of the (legacy) 4-step RACH mode. This type of test data transmission is more efficient than the 4-step RACH mode. The test device 8 can continue to send / receive UL / DL data packets in EDT mode after Msg4 in the RRC IDLE state or RRC INACTIVE state.

[0086] The test device 8 can also transmit the test data via the interface(s) 14 upon a predefined event. This predefined event can be the successful completion of a communication connection with a network. In this case, the test device 8 can retrieve the test data stored in the volatile memory 10 and forward it in packets via the interface(s) 14 over the mobile radio system.

[0087] The main power supply 16 supplies at least one or more of the components of the test device 8 with electrical power, e.g., via the bus 12. In particular, the main power supply 16 charges the auxiliary power supply 17 with electrical power, e.g., from outside the test device 8, e.g., in the case where the main power supply 16 is connected to the power source outside the test device 8. Here, the main power supply 16 may represent a preferred component used to power the components of the test device 8 and may, for example, comprise an accumulator or a battery. The main power supply 16 may comprise further components such as voltage regulators, DC voltage stabilizers, series regulators, buck converters, and / or boost converters to meet the corresponding requirements of the components of the test device 8.The main power supply 16 can either have a dedicated fixed power supply connection to the external power source, such as a power grid, or a detachable power supply connection for charging the accumulator or battery of the main power supply 16. For this purpose, the main power supply 16 can have an inverter to provide a predetermined DC power supply from a connected AC power source as the external power source. The predetermined DC power supply can also already be provided by a connected DC power source as the external power source. The DC power supply can be regulated via the above-mentioned voltage regulators and supplied to the components of the test device 8 as set DC power supplies. The auxiliary power supply 17 is connected to the volatile memory 10 and / or the persistent memory 11 via the bus 12.The auxiliary power supply 17 is charged by the electrical power of the main power supply 16. The auxiliary power supply 17 can be arranged inside or outside the test device 8, or inside or outside the volatile memory 10 and / or the permanent memory 11. For example, the auxiliary power supply 17 can be housed on a main board of the test device 8 in order to supply the volatile memory 10 and / or the permanent memory 11 with auxiliary power. The auxiliary power supply 17 can, in particular, be embodied in the form of a supercapacitor, an accumulator, and / or a battery. The power capacity / energy capacity of the main power supply 16 can be many times, for example, at least 10 times or 50 times greater than the power capacity / energy capacity of the auxiliary power supply 17.

[0088] The processor 9 monitors changes in the electrical power supplied by the main power supply 16. In the event of a sudden power failure, e.g., if the power source external to the test device 8 is disconnected from the main power supply 16 or the main power supply 16 degrades or fails for another reason, and the processor 9 determines that the electrical power supplied by the main power supply 16 to one or more of the components of the test device 8 has fallen below a threshold value, e.g., 0.8 or 0.75 of an operating power of the main power supply 16, the processor 9 causes the auxiliary power supply 17 to assume a remaining supply power for a shutdown of the test device 8. The shutdown process includes supplying at least the processor 9, the volatile memory 10, and / or the persistent memory 11 with electrical power for the duration of the shutdown process.During the shutdown process, the test data currently located in the volatile memory 10 and / or the test data currently being processed in the processor 9, for example, in the register / cache of the processor 9, are transferred from the volatile memory 10 and / or the processor 9 to a meta-area of ​​the persistent memory 11. For this purpose, the meta-area of ​​the persistent memory 11 can be reserved specifically for the shutdown process.

[0089] In the event of a startup of the test device 8, during which the main power supply 16 again provides operating power, the processor 9 loads the test data from the meta-area of ​​the persistent memory 11 to enable faster data processing. After the startup process, the meta-area of ​​the persistent memory can be released or successively during the startup process. It should be noted at this point that all of the parts described above, viewed individually and in any combination, particularly the details shown in the drawings, are claimed as essential to the invention. Modifications thereof will be apparent to those skilled in the art.

[0090] LIST OF REFERENCE SYMBOLS

[0091] 1 equivalent circuit

[0092] 2 first push-pull circuit block

[0093] 3 first common-mode circuit blocks

[0094] 4 first control network

[0095] 5 second conductor network

[0096] 6 second push-pull circuit block

[0097] 7 second common-mode circuit blocks

[0098] 8 Test device

[0099] 9 processor

[0100] 10 Volatile memory

[0101] 11 Permanent storage

[0102] 12 buses

[0103] 13 Arbiters

[0104] 14 interface(s)

[0105] 15 Impedance measuring device

[0106] 16 Main power supply

[0107] 17 Auxiliary power supply

[0108] R resistance

[0109] L Self-inductance

[0110] M mutual inductance

[0111] G Conductance

[0112] C capacity

[0113] X scaling factor

[0114] U first phase

[0115] V second phase

[0116] W third phase

[0117] GND ground p parallel s serial

[0118] X proportionality coefficient

Claims

Claims 1. A method (SO) for diagnosing a power cable, the method (SO) comprising: receiving (S1) test data relating to a measurement on the power cable; Providing (S2) an equivalent circuit (1) of the power cable with a plurality of equivalent circuit blocks (2, 3, 6, 7), each having series-connected first and second conductor networks (4, 5), wherein the first conductor network (4) takes into account the skin effect of the power cable and the second conductor network (5) takes into account the proximity effect of the power cable; Determining (S3) the parameters (R, L, M, G, C) of the equivalent circuit (1) based on the received test data; and Performing (S4) the diagnosis using the determined parameters (R, L, M, G, C).

2. Method (SO) according to claim 1, characterized in that the first conductor network (4) comprises a resistance-inductance conductor network and the second conductor network (5) comprises a resistance-mutual inductance conductor network, and that the resistance-inductance conductor network and the resistance-mutual inductance conductor network each comprise the same number of inductances and resistors.

3. Method (SO) according to claim 1 or 2, characterized in that a number of elements of the first conductor network (4) corresponds to or is unequal to a number of elements of the second conductor network (5), and that the number of elements of the respective first conductor networks (4) of the plurality of equivalent circuit blocks (2, 3, 6, 7) is equal and / or the number of elements of the respective second conductor networks (5) of the plurality of equivalent circuit blocks (2, 3, 6, 7) is the same.

4. Method (SO) according to one of the preceding claims, characterized in that the respective second conductor networks (5) of series-connected equivalent circuit blocks of the plurality of equivalent circuit blocks (2, 3, 6, 7) have mutual inductances (M) coupled to one another.

5. Method (SO) according to one of the preceding claims, characterized in that both the first conductor network (4) and the second conductor network (5) are parameterized on the basis of a measurement on the power cable in the low-frequency range and the high-frequency range.

6. Method (SO) according to one of the preceding claims, characterized in that the first conductor network (4) has two, three or more layers of a combination of resistance and inductance, and that the second conductor network (5) has two, three or more layers of a combination of resistance and mutual inductance.

7. Method (SO) according to one of the preceding claims, characterized in that the power cable is a multi-phase high-current cable.

8. Computer program, characterized in that the computer program comprises instructions which, when the computer program is executed by a computer, cause the computer to execute or initiate the method (SO) according to one of the preceding claims or at least one of the steps thereof.

9. Data carrier (10, 11), characterized in that the computer program according to claim 8 is stored on the data carrier (10, 11).

10. A test device (8) for diagnosing a power cable, the test device (8) comprising: an impedance measuring device (15) configured to apply a test signal to the power cable and to acquire or provide test data based on the test signal as a response from the power cable; and a processor (9) configured to determine parameters (R, L, M, G, C) of an equivalent circuit (1) of the power cable based on the test data and to perform the diagnosis using the determined parameters (R, L, M, G, C), wherein the equivalent circuit (1) comprises a plurality of equivalent circuit blocks (2, 3, 6, 7), each comprising series-connected first and second conductor networks (4, 5), and wherein the first conductor network (4) takes into account the skin effect of the power cable and the second conductor network (5) takes into account the proximity effect of the power cable.

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