Semiconductor integrated circuit device

Abstract

This semiconductor integrated circuit device provided with clock buffer cells (C1, C2, C3) is provided with a back wiring. The clock buffer cells (C1, C2, C3) are provided with: a first signal wiring (31) that is formed in a wiring layer (M1) positioned on the surface side of a transistor, and serves as an input terminal; and a second signal wiring (41) that is formed in a wiring layer (BM1) positioned on the back surface side of the transistor and serves as an input terminal. The wiring width of the second signal wiring (41) is larger than the wiring width of the first signal wiring (31).

Description

semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor integrated circuit device including a clock buffer cell.

[0002] In recent years, the miniaturization of semiconductor devices has led to increased circuit speeds and increased power consumption. To accommodate these increased circuit speeds, it is important to transmit clock signals supplied to flip-flops and other devices while suppressing clock skew. To suppress clock skew, the driving capability of the clock buffer that transmits the clock signal is increased. However, when the driving capability of the clock buffer increases, a large current flows in the clock buffer's power supply, and also in the input / output terminals of the clock buffer. This leads to problems such as power supply voltage drop (IR-Drop) and electromigration (EM).

[0003] The standard cell method is also known as a method for forming a semiconductor integrated circuit on a semiconductor substrate. The standard cell method is a method for designing an LSI chip by preparing basic units (e.g., inverters, latches, flip-flops, full adders, etc.) having specific logic functions as standard cells in advance, arranging multiple standard cells on a semiconductor substrate, and connecting these standard cells with wiring.

[0004] Patent Document 1 discloses a clock buffer cell that has an input terminal and an output terminal, the output terminal being formed in an upper layer and having a larger wiring width.

[0005] Furthermore, Patent Document 2 discloses a technique for achieving even higher integration by providing wiring on the back surface of the substrate directly below the transistor and connecting the source / drain of the transistor to this wiring.

[0006] International Publication No. 2021 / 192265 U.S. Application Publication No. 2021 / 0375853

[0007] However, the technology of Patent Document 1 does not disclose a clock buffer structure that suppresses power supply voltage drops and solves the problem of electromigration in a configuration with backside wiring as shown in Patent Document 2.

[0008] The present disclosure aims to suppress problems such as power supply voltage drop and electromigration in a semiconductor integrated circuit device including clock buffer cells in a configuration in which backside wiring is provided.

[0009] A semiconductor integrated circuit device according to a first aspect of the present disclosure includes a clock buffer cell that is a standard cell for propagating a clock signal and has an input terminal and an output terminal, the clock buffer cell including a transistor, a first signal wiring that is formed in a first wiring layer located on the front side of the transistor and serves as the input terminal, and a second signal wiring that is formed in a second wiring layer located on the back side of the transistor and serves as the input terminal, and the wiring width of the second signal wiring is larger than the wiring width of the first signal wiring.

[0010] According to this aspect, the clock buffer cell includes, as input terminals, a first signal wiring formed in a first wiring layer located on the front side of the transistor and a second signal wiring formed in a second wiring layer located on the back side of the transistor. The wiring width of the second signal wiring is larger than the wiring width of the first signal wiring. In a clock tree, when this clock buffer cell inputs a clock signal output from a previous-stage clock buffer cell, a large current flows through the input terminal. By using the second signal wiring with a larger wiring width as the input terminal, the problem of electromigration can be suppressed.

[0011] A semiconductor integrated circuit device according to a second aspect of the present disclosure provides a standard cell for propagating a clock signal, the clock buffer cell comprising: a transistor; a first signal wiring formed in a first wiring layer located on the front surface side of the transistor and serving as the output terminal; and a second signal wiring formed in a second wiring layer located on the back surface side of the transistor and serving as the output terminal, the wiring width of the second signal wiring being greater than the wiring width of the first signal wiring.

[0012] According to this aspect, the clock buffer cell includes, as output terminals, a first signal wiring formed in a first wiring layer located on the front side of the transistor and a second signal wiring formed in a second wiring layer located on the back side of the transistor. The wiring width of the second signal wiring is larger than the wiring width of the first signal wiring. In a clock tree, when this clock buffer cell outputs a clock signal to a subsequent clock buffer cell, a large current flows through the output terminal. By using the second signal wiring with a larger wiring width as the output terminal, the problem of electromigration can be suppressed.

[0013] According to the present disclosure, in a semiconductor integrated circuit device including clock buffer cells, problems such as power supply voltage drop and electromigration can be suppressed in a configuration in which backside wiring is provided.

[0014] 4 is a plan view showing an example of the layout of the transistors and surface-side wiring of the clock buffer cell; FIG. 5 is a plan view showing an example of the layout of the back-side wiring of the clock buffer cell; FIG. 6 is an enlarged plan view of the buffer section in the clock buffer cell of FIGS. 2 and 3, where (a) is the transistors and surface-side wiring, and (b) is the back-side wiring; FIG. 7 is a cross-sectional view showing the cross-sectional structure of the buffer section of FIG. 4; FIG. 8 is a plan view showing an example of the layout of a normal standard cell, where (a) is the transistors and surface-side wiring, and (b) is the back-side wiring;

[0015] Hereinafter, embodiments will be described with reference to the drawings. In the following description, "VDD" and "VSS" are used to represent both the power supply itself and the power supply voltage provided by the power supply. Furthermore, standard cells will be abbreviated as simply "cells" where appropriate.

[0016] Furthermore, in the following description, the semiconductor integrated circuit device is assumed to include a nanosheet transistor, but the transistor included in the semiconductor integrated circuit device according to the present disclosure is not limited to a nanosheet transistor.

[0017] Fig. 1 is a circuit diagram showing an example of a clock tree including clock buffer cells. The clock tree receives an input clock generated by a clock generation circuit configured with a PLL (Phase Locked Loop) or the like, and outputs multiple output clocks to subsequent circuits via clock buffer cells connected in a tree configuration. The clock tree in Fig. 1 is configured with three stages of clock buffer cells.

[0018] The first-stage clock buffer cell (A) and the second-stage clock buffer cells (B, C) drive long wiring and drive many buffers connected to the output, so they have large drive capabilities. Therefore, large currents flow through the first-stage and second-stage clock buffer cells (A, B, C) to charge and discharge the output load. In contrast, the third-stage clock buffer cells (D, E, F, G) drive short wiring and have a relatively small input capacitance of the circuit connected to the output, so they have small drive capabilities. Therefore, large currents do not flow through the third-stage clock buffer cells (D, E, F, G) to charge and discharge.

[0019] 2 and 3 are plan views showing the layout of a clock buffer cell, with FIG. 2 showing the layout of the transistors and front-side wiring, and FIG. 3 showing the layout of the back-side wiring. CF is a cell frame. Here, the front side of a transistor refers to the side on which local wiring, metal wiring, etc. connected to the transistor are stacked. The back side of a transistor refers to the side opposite to the side on which local wiring, metal wiring, etc. connected to the transistor are stacked.

[0020] In this embodiment, as will be described later, the power supply wiring is formed in the BM0 wiring layer, which is the wiring layer on the back side. In this disclosure, the region between adjacent power supply wiring in the Y direction (corresponding to the second direction) is referred to as a height region. In each height region, a P-type field effect transistor (FET) and an N-type FET are arranged adjacent to each other in the Y direction. H is the height of the height region. The clock buffer cell shown in FIGS. 2 and 3 is a multi-height cell whose cell height is multiple times H (here, 22 times).

[0021] The clock buffer cell shown in FIGS. 2 and 3 includes four buffer sections 21, 22, 23, and 24.

[0022] 4A and 4B are enlarged plan views of the buffer section, where (a) shows the layout of the transistors and front-side wiring, and (b) shows the layout of the back-side wiring. Also, Fig. 5 is a cross-sectional view showing the cross-sectional structure taken along line X1-X1' in Figs. 4A and 4B. As shown in Fig. 4A, the buffer section has a circuit configuration in which inverters 1a and 1b are connected in series.

[0023] 3, in the BM0 wiring layer, power supply wiring 11 extending in the X direction (corresponding to the first direction) and supplying VDD and power supply wiring 12 extending in the X direction and supplying VSS are alternately arranged in the Y direction. Four buffer units 21, 22, 23, and 24 are arranged side by side in the Y direction. Each buffer unit 21, 22, 23, and 24 has a height of 3H, and the buffer units 21, 22, 23, and 24 are spaced apart by 2H. Decoupling capacitance units are arranged around each of the buffer units 21, 22, 23, and 24. The decoupling capacitance units form capacitance between VDD and VSS and suppress power supply voltage drops.

[0024] In the BM1 wiring layer on the back side of the BM0 wiring layer, signal wirings 41 and 42 extending in the Y direction are arranged. The signal wiring 41 corresponds to the input terminal of the clock buffer cell, and the signal wiring 42 corresponds to the output terminal of the clock buffer cell. The signal wirings 41 and 42 are formed across the four buffer units 21, 22, 23, and 24.

[0025] In addition, in the BM1 wiring layer, power supply wirings 13a, 13b, 13c, and 13d that extend in the Y direction and supply VDD, and power supply wirings 14a and 14b that extend in the Y direction and supply VSS are arranged. The power supply wirings 13a, 13b, 13c, and 13d are connected to the power supply wiring 11 through vias. The power supply wirings 14a and 14b are connected to the power supply wiring 12 through vias.

[0026] 2, signal wirings 31, 32a, 32b, and 32c extending in the Y direction are arranged in the M1 wiring layer, which is the wiring layer on the front surface side. The signal wiring 31 corresponds to the input terminal of the clock buffer cell, and the signal wirings 32a, 32b, and 32c correspond to the output terminal of the clock buffer cell. The signal wirings 31, 32a, 32b, and 32c are formed across the four buffer units 21, 22, 23, and 24. The M0 wiring layer is a wiring layer located between the transistors and the M1 wiring layer.

[0027] In the M1 wiring layer, signal wirings 33a, 33b, 33c, and 33d extending in the Y direction are arranged in each of the buffer units 21, 22, 23, and 24. The signal wirings 33a, 33b, 33c, and 33d correspond to intermediate nodes between the inverter 1a and the inverter 1b in each of the buffer units.

[0028] Here, with regard to the signal wiring corresponding to the input terminal, the signal wiring 41 in the BM1 wiring layer has a larger wiring width than the signal wiring 31 in the M1 wiring layer. This is due to the difference in the magnitude of the current flowing, with a larger current flowing through the signal wiring 41. Therefore, by increasing the wiring width of the signal wiring 41, the problem of electromigration can be suppressed.

[0029] Furthermore, with regard to the signal wiring corresponding to the output terminal, the signal wiring 42 in the BM1 wiring layer has a larger wiring width than the signal wirings 32a, 32b, and 32c in the M1 wiring layer. This is also due to the difference in the magnitude of the current flowing, with a larger current flowing through the signal wiring 42. Therefore, by increasing the wiring width of the signal wiring 42, the problem of electromigration can be suppressed.

[0030] Furthermore, in the BM1 wiring layer, power supply wirings 13a and 13b are arranged on both sides of signal wiring 41, which corresponds to an input terminal. Power supply wirings 13b and 13c are arranged on both sides of signal wiring 42, which corresponds to an output terminal. This makes it possible to suppress crosstalk caused by signal wirings 41 and 42, through which a large current of a clock signal flows. Note that, although the power supply wirings arranged on both sides of the signal wiring are power supply wirings that supply VDD in this example, this is not limiting. That is, power supply wirings that supply VSS may be arranged on both sides of the signal wiring, or a power supply wiring that supplies VDD may be arranged on one side and a power supply wiring that supplies VSS may be arranged on the other side.

[0031] The layout of the buffer section will be described with reference to Fig. 4. Although Fig. 4 shows the layout of the buffer section 22, the layout of the other buffer sections is similar.

[0032] In the buffer section, in the BM0 wiring layer, power supply wiring 11 that supplies VDD and power supply wiring 12 that supplies VSS each extend in the X direction and are arranged alternately in the Y direction. Active regions 2P1, 2P2, and 2P3 that form the channel, source, and drain of the P-type nanosheet FET are formed to extend in the X direction above the power supply wiring 11. Active regions 2N1, 2N2, and 2N3 that form the channel, source, and drain of the N-type nanosheet FET are formed to extend in the X direction above the power supply wiring 12.

[0033] The active regions 2P1 and 2N1 are provided with a common gate wiring 51. The gate wiring 51 extends in the Y direction and surrounds the outer peripheries of the nanosheet in the Y and Z directions via a gate insulating film (not shown). Similarly, the active regions 2N2 and 2P2 are provided with a common gate wiring 52. The gate wiring 52 extends in the Y direction and surrounds the outer peripheries of the nanosheet in the Y and Z directions via a gate insulating film (not shown). The active regions 2P3 and 2N3 are provided with a common gate wiring 53. The gate wiring 53 extends in the Y direction and surrounds the outer peripheries of the nanosheet in the Y and Z directions via a gate insulating film (not shown).

[0034] The active regions 2P1, 2P2, 2P3, 2N1, 2N2, and 2N3 form 11 nanosheet FETs arranged in the X direction. The three rows of nanosheet FETs from the left side of the drawing constitute the front-stage inverter 1a. The remaining rows, i.e., the eight rows of nanosheet FETs from the right side of the drawing, constitute the rear-stage inverter 1b.

[0035] In the active regions 2P1, 2P2, and 2P3, the portions that become the sources of the P-type nanosheet FETs are connected via vias to a power supply wiring 11 formed in the BM0 wiring layer. In the active regions 2N1, 2N2, and 2N3, the portions that become the sources of the N-type nanosheet FETs are connected via vias to a power supply wiring 12 formed in the BM0 wiring layer.

[0036] In each of the active regions 2P1, 2P2, 2P3, 2N1, 2N2, and 2N3, the portion that will become the source or drain is connected to a local wiring 91 extending in the Y direction. Active regions 2N1 and 2N2 adjacent to each other in the Y direction are connected to a common local wiring 92. Active regions 2P1 and 2P2 adjacent to each other in the Y direction are connected to a common local wiring 93. In addition, in the eight columns of nanosheet FETs from the right side of the drawing, the portion that will become the drain is connected to a common local wiring 94 extending in the Y direction.

[0037] In the M1 wiring layer, the signal wiring 31 extends in the Y direction. As described above, the signal wiring 31 corresponds to the input terminal of the clock buffer cell. The signal wiring 31 is connected to the gate wiring of the three rows of nanosheet FETs from the left side of the drawing via a via, an M0 wiring extending in the X direction, and a via. The local wiring connected to the portion that becomes the drain of the three rows of nanosheet FETs from the left side of the drawing is connected to the signal wiring 33b extending in the Y direction via a via, an M0 wiring extending in the X direction, and a via. As described above, the signal wiring 33b corresponds to the intermediate node of the clock buffer cell.

[0038] The signal wiring 33c is connected to the gate wiring of the eight rows of nanosheet FETs from the right side of the drawing via a via, an M0 wiring extending in the X direction, and a via. The local wiring connected to the drains of the eight rows of nanosheet FETs from the right side of the drawing is connected to the signal wirings 32a, 32b, and 32c extending in the Y direction via a via, an M0 wiring extending in the X direction, and a via. As described above, the signal wirings 32a, 32b, and 32c correspond to the output terminals of the clock buffer cells.

[0039] In the BM1 layer, the signal wiring 41 extends in the Y direction. As described above, the signal wiring 41 corresponds to the input terminal of the clock buffer cell. The signal wiring 41 is connected to the gate wiring of one row of nanosheets among the three rows of nanosheet FETs from the left side of the drawing via a via, a BM0 wiring, and a via. Also, in the BM1 layer, the signal wiring 42 extends in the Y direction. As described above, the signal wiring 42 corresponds to the output terminal of the clock buffer cell. The signal wiring 42 is connected to the local wiring connected to the drains of the eight rows of nanosheet FETs from the right side of the drawing via a via, a BM0 wiring extending in the X direction, and a via.

[0040] 6 shows an example of a typical standard cell layout, where (a) is the layout of the transistors and the front-side wiring, and (b) is the layout of the back-side wiring. Fig. 6 shows the layout of a two-input NAND cell having input terminals A and B and an output terminal Y.

[0041] As shown in FIG. 6, power supply wiring 111 and 112 extending in the X direction are formed in the BM0 wiring layer. The power supply wiring 111 supplies VDD, and the power supply wiring 112 supplies VSS. Above the power supply wiring 111, an active region 3P constituting the channel, source, and drain of the P-type nanosheet FET is formed so as to extend in the X direction. Above the power supply wiring 112, an active region 3N constituting the channel, source, and drain of the N-type nanosheet FET is formed so as to extend in the X direction. In the M1 wiring layer, signal wiring 131, 132, and 133 extending in the Y direction are formed. The signal wiring 131 corresponds to input A, the signal wiring 132 corresponds to input B, and the signal wiring 133 corresponds to output Y.

[0042] FIG. 7 is an example of a block layout in a semiconductor integrated circuit device according to an embodiment. In FIG. 7, thin dashed lines extending in parallel in the X direction conceptually represent power supply wiring PL. The power supply wiring PL is formed in the BM0 wiring layer, and power supply wiring for supplying VDD and power supply wiring for supplying VSS are arranged alternately in the Y direction. Although not shown in FIG. 7, standard cells are arranged in the height region between the power supply wirings. Most standard cells are single-height cells whose cell height is equal to the height H of the height region. For example, cell C10 is the two-input NAND cell shown in FIG. 6.

[0043] In the block layout of Figure 7, in addition to normal standard cells, three clock buffer cells C1, C2, and C3 are arranged, which are multi-height cells whose cell height is multiple times H (22 times in this case). Clock buffer cells C1, C2, and C3 correspond to buffer cells A, B, and C, respectively, in the circuit diagram of Figure 1. Cells C4, C5, C6, and C7 are arranged, which correspond to buffer cells D, E, F, and G, respectively, in the circuit diagram of Figure 1. Cells C4, C5, C6, and C7 are single-height cells and have smaller drive capabilities than clock buffer cells C1, C2, and C3.

[0044] The layout of the clock buffer cells C1, C2, and C3 is as shown in Figures 2 to 5. However, in Figure 7, the signal wiring corresponding to the output terminal in the M1 wiring layer is shown as one line for the sake of simplicity.

[0045] The first-stage clock buffer cell C1 receives an input clock output from a clock generation circuit (not shown) through M1 wiring 51, which serves as an input terminal on the front side. The clock buffer cell C1 outputs the clock through BM1 wiring 61, which serves as an output terminal on the back side. The clock output from BM1 wiring 61 is transmitted to the second-stage clock buffer cells C2 and C3 via BM2 wiring 71 extending in the X direction, BM3 wiring 72 extending in the Y direction, and BM2 wiring 73 and 74 extending in the X direction. The transmitted clock is input to BM1 wiring 62, which serves as an input terminal on the back side of clock buffer cell C2, and BM1 wiring 63, which serves as an input terminal on the back side of clock buffer cell C3.

[0046] The clock buffer cell C2 outputs a clock from the M1 wiring 52, which serves as an output terminal on the front side. The clock output from the M1 wiring 52 is transmitted to cells C4 and C5. The clock buffer cell C3 outputs a clock from the M1 wiring 53, which serves as an output terminal on the front side. The clock output from the M1 wiring 53 is transmitted to cells C6 and C7.

[0047] Although not shown, signal wiring other than the wiring between clock buffer cells is formed in the wiring layer on the front side. No signal wiring other than the wiring between clock buffer cells is formed in the wiring layer on the back side. This prevents crosstalk from occurring between the clock wiring and other signal wiring, thereby reducing clock skew.

[0048] FIG. 8 shows an example of the wiring arrangement of the BM1 wiring layer in the block layout of FIG. 7, and FIG. 9 shows an example of the wiring arrangement of the BM2 and BM3 wiring layers in the block layout of FIG.

[0049] 8, in the BM1 wiring layer, power supply wiring 81 extending in the Y direction is arranged throughout the entire block in an area other than the BM1 wiring that serves as the input and output terminals of the clock buffer cells C1, C2, and C3. As the power supply wiring 81, for example, power supply wiring that supplies VDD and power supply wiring that supplies VSS are arranged alternately. Note that the power supply wiring 81 may be provided in each cell to be placed, or may be laid when constructing the block layout.

[0050] 9, in the BM2 wiring layer and the BM3 wiring layer, power supply wirings 82 and 83 are provided in a mesh pattern over the entire block in the region other than the wirings 71, 72, 73, and 74 between the clock buffer cells. In FIG. 9, in the BM2 wiring layer, the power supply wiring 82 extends in the X direction, and in the BM3 wiring layer, the power supply wiring 83 extends in the Y direction.

[0051] 7, the first-stage clock buffer cell C1 receives the input clock from the M1 wiring 51, which serves as an input terminal on the front side. However, instead of this, the clock buffer cell C1 may receive the input clock from the BM1 wiring, which serves as an input terminal on the back side. This configuration is effective when the wiring length from the clock generation circuit to the first-stage clock buffer cell C1 is long.

[0052] <Effects of the Present Embodiment> In the present embodiment, the clock buffer cell, like a normal cell such as a two-input NAND cell, includes power supply wirings 11 and 12 in the BM0 wiring layer. Therefore, when designing a semiconductor integrated circuit device, by arranging the clock buffer cell in the same way as a normal cell, the power supply wirings in the BM0 wiring layer are connected to each other, making the design easier.

[0053] Furthermore, the clock buffer cell is a multi-height cell, and includes multiple VDD power supply wirings 11 and multiple VSS power supply wirings 12. This allows current to be distributed among multiple power supply wirings, thereby suppressing power supply voltage drops.

[0054] Furthermore, the clock buffer cell is provided with power supply wiring 13a, 13b, 13c, 13d, 14a, and 14b formed in the BM1 wiring layer and extending in the Y direction. The power supply wiring 13a, 13b, 13c, and 13d are connected to the power supply wiring 11 in the BM0 wiring layer. The power supply wiring 14a and 14b are connected to the power supply wiring 12 in the BM0 wiring layer. In other words, a mesh-like power supply wiring is formed. This allows the resistance of the power supply wiring to be reduced, and power supply voltage drops can be suppressed.

[0055] Furthermore, in clock buffer cells, the signal wiring corresponding to the input terminal in the BM1 wiring layer has a larger wiring width than the signal wiring in the M1 wiring layer. For example, in the block layout of FIG. 7 , clock buffer cells C2 and C3 receive the clock output from signal wiring 61 in the BM1 wiring layer of clock buffer cell C1 via signal wiring 62 and 63 in the BM1 wiring layer. Therefore, a large current flows through signal wiring 62 and 63 of clock buffer cells C2 and C3. Therefore, by increasing the wiring width of the signal wiring corresponding to the input terminal in the BM1 wiring layer, the problem of electromigration at the input terminal can be suppressed.

[0056] Furthermore, in clock buffer cells, the signal wiring corresponding to the output terminal has a larger wiring width in the BM1 wiring layer than in the M1 wiring layer. For example, in the block layout of FIG. 7 , clock buffer cell C1 outputs a clock to clock buffer cells C2 and C3 via signal wiring 61 in the BM1 wiring layer. Therefore, a large current flows through signal wiring 61 of clock buffer cell C1. Meanwhile, clock buffer cells C2 and C3 output clocks to buffer cells C4, C5, C6, and C7 at the final stage of the clock tree via signal wiring 52 and 53 in the M1 wiring layer. Because buffer cells C4, C5, C6, and C7 are single-height cells, no large current flows through signal wiring 52 and 53. Therefore, by increasing the wiring width of the signal wiring corresponding to the output terminal in the BM1 wiring layer, electromigration problems at the output terminal can be suppressed.

[0057] In the above embodiment, the clock buffer cell is a multi-height cell having a height 22 times that of a normal cell, and includes four buffer sections 21 to 24 each having a height three times that of a normal cell. However, the configuration of the clock buffer cell according to the present disclosure is not limited to this.

[0058] According to the present disclosure, in a configuration in which backside wiring is provided in a semiconductor integrated circuit device having clock buffer cells, problems such as power supply voltage drop and electromigration are suppressed, which is useful for improving the performance of, for example, an SOC (System On Chip).

[0059] C1, C2, C3 Clock buffer cells 11, 12 Power supply wiring 31 Signal wiring (input terminal) 32a, 32b, 32c Signal wiring (output terminal) 41 Signal wiring (input terminal) 42 Signal wiring (output terminal) 51 M1 wiring (input terminal) 52, 53 M1 wiring (output terminal) 61 BM1 wiring (output terminal) 62, 63 BM1 wiring (input terminal)

Claims

1. A semiconductor integrated circuit device comprising: a clock buffer cell which is a standard cell for propagating a clock signal and has an input terminal and an output terminal; the clock buffer cell comprising: a transistor; a first signal wiring which is formed in a first wiring layer located on the front side of the transistor and serves as the input terminal; and a second signal wiring which is formed in a second wiring layer located on the back side of the transistor and serves as the input terminal; and the wiring width of the second signal wiring is greater than the wiring width of the first signal wiring.

2. A semiconductor integrated circuit device according to claim 1, comprising: a first power supply wiring formed in a third wiring layer between said transistor and said second wiring layer, for supplying a first power supply voltage; and a second power supply wiring formed in said third wiring layer, for supplying a second power supply voltage.

3. A semiconductor integrated circuit device according to claim 2, wherein the first and second power supply wirings extend in a first direction, and the first and second signal wirings extend in a second direction perpendicular to the first direction.

4. A semiconductor integrated circuit device according to claim 1, comprising: a second clock buffer cell which is a standard cell for propagating a clock signal and has an input terminal and an output terminal, said second clock buffer cell being formed in said second wiring layer and comprising a third signal wiring which serves as said output terminal, and said second signal wiring of said clock buffer cell being electrically connected to said third signal wiring of said second clock buffer cell.

5. A semiconductor integrated circuit device comprising: a clock buffer cell which is a standard cell for propagating a clock signal and has an input terminal and an output terminal, the clock buffer cell comprising: a transistor; a first signal wiring which is formed in a first wiring layer located on the front side of the transistor and serves as the output terminal; and a second signal wiring which is formed in a second wiring layer located on the back side of the transistor and serves as the output terminal, the wiring width of the second signal wiring being greater than the wiring width of the first signal wiring.

6. A semiconductor integrated circuit device according to claim 5, comprising: a first power supply wiring formed in a third wiring layer between said transistor and said second wiring layer, for supplying a first power supply voltage; and a second power supply wiring formed in said third wiring layer, for supplying a second power supply voltage.

7. A semiconductor integrated circuit device according to claim 6, wherein the first and second power supply wirings extend in a first direction, and the first and second signal wirings extend in a second direction perpendicular to the first direction.

8. A semiconductor integrated circuit device according to claim 5, comprising: a second clock buffer cell which is a standard cell for propagating a clock signal and has an input terminal and an output terminal; said second clock buffer cell is formed in said second wiring layer and comprises a third signal wiring which serves as said input terminal; and said second signal wiring of said clock buffer cell is electrically connected to said third signal wiring of said second clock buffer cell.

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