Display panel and display apparatus

Abstract

The present application relates to the technical field of display, and provides a display panel and a display apparatus. The display panel comprises a substrate and a plurality of light-emitting devices arranged in an array on the substrate, the light-emitting devices at least being located in a display area. The display panel further comprises a first conductive layer, the first conductive layer comprising, electrically connected to each other, a first cathode loop and anodes of the light-emitting devices. The first cathode loop is located in a peripheral area, surrounds the display area, and is electrically connected to a pixel circuit of the display panel; the first cathode loop comprises a plurality of conductive patterns, a gap being formed between every two adjacent conductive patterns, and a planar graph of the conductive patterns comprising a concave polygon. The display panel is suitable for manufacture of high-quality display apparatuses.

Description

Display panel, display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the rapid development of various display technologies, customers are increasingly demanding higher performance from display panels. Current silicon-based display products are equipped with a cathode for the light-emitting device located in the active area (AA) and a cathode ring located in the peripheral area; the cathode ring is arranged around the active area.

[0003] However, the current cathode ring design is very likely to cause ESD (Electrostatic Discharge) to occur in the peripheral area of ​​the display product. ESD may cause corrosion or burns in the peripheral area of ​​the display product, thereby damaging the display product.

[0004] Summary of the Invention

[0005] The embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a display panel, comprising a display area and a peripheral area, wherein the peripheral area surrounds the display area; the display panel further comprises:

[0007] A substrate and a plurality of light-emitting devices arranged in an array on the substrate, wherein the light-emitting devices are at least located in the display area;

[0008] a first conductive layer, comprising a first cathode ring electrically connected to an anode of the light-emitting device; the first cathode ring is located in the peripheral area and surrounds the display area, and the first cathode ring is electrically connected to a pixel circuit of the display panel;

[0009] The first cathode ring includes a plurality of conductive patterns, a gap exists between two adjacent conductive patterns, and the plane figures of the conductive patterns include concave polygons.

[0010] In at least one display panel provided by an embodiment of the present application, the shape of the orthographic projection of the conductive pattern on the substrate includes a pattern formed by splicing together a first extension portion and a second extension portion;

[0011] The first extending portion extends along a first direction, and the second extending portion extends along a second direction; the first direction is a direction from the display area to the peripheral area, and the second direction is perpendicular to the first direction.

[0012] In at least one display panel provided by an embodiment of the present application, the planar shape of the first extending portion is a first rectangle, and the planar shape of the second extending portion is a second rectangle;

[0013] The geometric center of the first rectangle overlaps with the geometric center of the second rectangle, and the first side of the first rectangle is perpendicular to the first side of the second rectangle, and the first side is the long side of the rectangle.

[0014] In at least one display panel provided by an embodiment of the present application, the plurality of conductive patterns include a first conductive pattern group and a second conductive pattern group alternately arranged along the first direction; the first conductive pattern group and the second conductive pattern group are both arranged around the display area;

[0015] The first conductive pattern group includes a plurality of first conductive patterns arranged along the second direction, and the second conductive pattern group includes a plurality of second conductive patterns arranged along the second direction;

[0016] The shape of a line connecting geometric centers of two adjacent first conductive patterns along the first direction and a second conductive pattern between the two adjacent first conductive patterns is a first triangle.

[0017] In at least one display panel provided by an embodiment of the present application, the first conductive pattern and the second conductive pattern have the same structure and size.

[0018] In at least one display panel provided by an embodiment of the present application, the length of at least one side of the first triangle is in the range of 3 to 5 times the maximum size of a sub-pixel in the display area.

[0019] In at least one display panel provided by an embodiment of the present application, the first triangle is an isosceles triangle.

[0020] In at least one display panel provided by an embodiment of the present application, a first side of the first rectangle extends along the first direction, a first side of the second rectangle extends along the second direction, and an area of ​​the first rectangle is greater than an area of ​​the second rectangle.

[0021] In at least one display panel provided in an embodiment of the present application, along the first direction, the minimum distance between the second conductive pattern and the first conductive pattern on the side close to the display area is a first distance, and the minimum distance between the second conductive pattern and the first conductive pattern on the side away from the display area is a second distance, and the first distance and the second distance are approximately equal.

[0022] In at least one display panel provided in an embodiment of the present application, along the second direction, the minimum distance between the second conductive pattern and the first conductive pattern on one side thereof is a third distance, and the minimum distance between the second conductive pattern and the first conductive pattern on the other side thereof is a fourth distance, and the third distance and the fourth distance are approximately equal.

[0023] In at least one display panel provided by an embodiment of the present application, the ranges of the first distance, the second distance, the third distance, and the fourth distance are all 0.5 to 2 times the maximum size of a sub-pixel in the display area.

[0024] In at least one display panel provided by an embodiment of the present application, the first distance, the second distance, the third distance, and the fourth distance are all substantially equal.

[0025] In at least one display panel provided in an embodiment of the present application, the length of the first side of the first rectangle is less than or equal to the length of the first side of the second rectangle, and the length of the first side of the second rectangle is greater than 0.5 times the length of the first side of the first rectangle.

[0026] In at least one display panel provided by an embodiment of the present application, a maximum width of the first extending portion along the second direction is greater than a maximum width of the second extending portion along the first direction.

[0027] In at least one display panel provided by an embodiment of the present application, in the first rectangle and the second rectangle, the length of the first side is greater than the length of the second side;

[0028] An absolute value of a difference between a length of a first side of the first rectangle and a length of a second side of the first rectangle is greater than or equal to 0.5 to 2 times a maximum size of a sub-pixel in the display area.

[0029] In at least one display panel provided in an embodiment of the present application, for the first conductive pattern and the second conductive pattern adjacent to each other along the first direction, the minimum distance between the first side of the second rectangle in the first conductive pattern and the first side of the second rectangle in the second conductive pattern is the fifth distance; the minimum distance between the first side of the second rectangle in the second conductive pattern and the first side of the second rectangle in the first conductive pattern is the fifth distance; in the same conductive pattern, the minimum distance between the first side of the first rectangle and the second side of the second rectangle is the sixth distance; and the fifth distance is greater than the sixth distance.

[0030] In at least one display panel provided by an embodiment of the present application, for two adjacent first conductive patterns along the first direction, a minimum distance between first sides of the second rectangles in the two first conductive patterns is a seventh distance; and for two adjacent second conductive patterns along the first direction, a minimum distance between first sides of the second rectangles in the two second conductive patterns is the seventh distance.

[0031] For two adjacent first conductive patterns along the second direction, the minimum distance between the first sides of the first rectangles in the two first conductive patterns is the eighth distance; for two adjacent second conductive patterns along the second direction, the minimum distance between the first sides of the first rectangles in the two second conductive patterns is the eighth distance;

[0032] Wherein, the seventh distance is greater than or equal to the eighth distance.

[0033] In at least one display panel provided in an embodiment of the present application, the ratio of the length of the seventh distance to the length of the first side of the first rectangle is greater than or equal to the ratio of the length of the eighth distance to the length of the second side of the first rectangle.

[0034] In at least one display panel provided by an embodiment of the present application, a first hollow area is provided between two adjacent conductive patterns along the second direction;

[0035] A line connecting geometric centers of two adjacent first hollow areas along the first direction and a line connecting geometric centers of the conductive pattern between two adjacent first hollow areas along the first direction is a first line segment;

[0036] A line connecting the geometric centers of two adjacent first conductive patterns along the first direction is a second line segment; and the first line segment is parallel to the second line segment.

[0037] In at least one display panel provided by an embodiment of the present application, the lengths of the first line segment and the second line segment are substantially the same.

[0038] In at least one display panel provided by an embodiment of the present application, two first hollow areas arranged along the first direction and located on both sides of the first rectangle, and two first hollow areas arranged along the second direction and located on both sides of the second rectangle are provided around the same conductive pattern;

[0039] The shape of the lines connecting the geometric centers of the four first hollow areas around the same conductive pattern is a quadrilateral, and the quadrilateral includes two second triangles, and the second triangles are the same as the first triangle.

[0040] In at least one display panel provided in an embodiment of the present application, the peripheral area of ​​the display panel further includes a plurality of auxiliary electrodes, the auxiliary electrodes are arranged in the peripheral area, two adjacent auxiliary electrodes arranged along the first direction do not contact each other, the orthographic projection of the conductive pattern on the substrate overlaps with the orthographic projection of the auxiliary electrode on the substrate, and the conductive pattern is electrically connected to the auxiliary electrodes.

[0041] In at least one display panel provided in an embodiment of the present application, the planar figure of the conductive pattern is an axially symmetrical figure, and the conductive pattern has a first symmetry axis extending along the second direction; the area where the first symmetry axis is located overlaps with the area where the positive projection of the auxiliary electrode on the substrate is located.

[0042] In at least one display panel provided in an embodiment of the present application,

[0043] The display panel further includes a pixel definition layer and a cathode layer located on a side of the pixel definition layer away from the substrate, wherein a portion of the pixel definition layer located in the peripheral area includes a plurality of first through holes; the first cathode ring is disposed at the bottom of the first through hole;

[0044] A partial area of ​​the cathode layer falls into the first through hole and is electrically connected to the conductive pattern through the first through hole.

[0045] In at least one display panel provided in an embodiment of the present application, the display panel further includes a driving substrate, the driving substrate including the substrate and a driving unit, and the driving unit is located between the substrate and the first conductive layer;

[0046] The portion of the driving unit located in the peripheral area includes a second cathode ring, and the portion of the driving unit located in the display area includes the pixel circuit. The second cathode ring is electrically connected to the first cathode ring and the pixel circuit, respectively; the orthographic projection of the second cathode ring on the substrate is within the orthographic projection of the first cathode ring on the substrate.

[0047] In at least one display panel provided by an embodiment of the present application, the width of the second cathode ring along the first direction is smaller than the width of the first cathode ring along the first direction, and the conductive patterns in the second cathode ring and the first cathode ring have the same structure.

[0048] In at least one display panel provided by an embodiment of the present application, the plurality of auxiliary electrodes include a plurality of first connection electrodes and a plurality of second connection electrodes, the drive substrate includes a second conductive layer, and the second conductive layer is located between the plurality of second connection electrodes and the substrate;

[0049] The multiple first connecting electrodes are located between the first cathode ring and the second cathode ring, and the first connecting electrodes are respectively in contact and electrically connected with the first cathode ring and the second cathode ring; the multiple second connecting electrodes are located between the second conductive layer and the second cathode ring, and the second connecting electrodes are respectively in contact and electrically connected with the second cathode ring and the second conductive layer; the second conductive layer is electrically connected to the pixel circuit.

[0050] In at least one display panel provided by an embodiment of the present application, a plurality of auxiliary electrodes overlap with the conductive pattern of the same first cathode ring;

[0051] The number of the auxiliary electrodes overlapping the first rectangle is greater than or equal to the number of the auxiliary electrodes overlapping the second rectangle.

[0052] In at least one display panel provided by an embodiment of the present application, for the conductive pattern in the second cathode ring, the orthographic projections of the first connecting electrode and the second connecting electrode overlapping the same conductive pattern on the conductive pattern do not completely overlap.

[0053] In a second aspect, an embodiment of the present application provides a display device comprising a display panel as described in any one of the first aspects.

[0054] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0056] 1A and 1B are schematic top views of two display panels provided in embodiments of the present application;

[0057] FIG2 is a schematic diagram of the cross-sectional structure along the A1A2 direction of FIG1A;

[0058] FIG3 is a schematic diagram of the cross-sectional structure of FIG1A along the direction A3A4;

[0059] FIG4 is a schematic diagram of a partial top view of a first cathode ring provided in an embodiment of the present application;

[0060] FIG5A is a schematic top view of a conductive pattern of a first cathode ring provided in an embodiment of the present application;

[0061] (1) to (12) in FIG5B are schematic top views of twelve types of conductive patterns of the first cathode ring provided in an embodiment of the present application;

[0062] 6 and 7 are partial top views of two types of first cathode rings provided in embodiments of the present application;

[0063] 8 , 9 , and 10 are schematic top views illustrating the arrangement relationship between the first cathode ring and the auxiliary electrode according to an embodiment of the present application;

[0064] 11 to 13 are schematic diagrams showing the arrangement of the conductive patterns and the first through holes in three types of first cathode rings according to embodiments of the present application;

[0065] 14 to 17 are schematic diagrams showing the arrangement of four types of first connecting electrodes and second connecting electrodes on the conductive pattern in the second cathode ring according to an embodiment of the present application;

[0066] 18 and 19 are simplified schematic diagrams of the structures of two display panels provided in embodiments of the present application;

[0067] FIG20 is a schematic structural diagram of a display device provided in an embodiment of the present application. Specific embodiments

[0068] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0069] In the embodiments of the present application, words such as "first", "second", "third", and "fourth" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0070] In the embodiments of the present application, the terms "upper" and "lower" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0071] Throughout the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present application. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0072] In the embodiments of the present application, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0073] The features "parallel," "perpendicular," and "identical" used in the embodiments of the present application include features such as "parallel," "perpendicular," and "identical" in the strict sense, as well as "approximately parallel," "approximately perpendicular," and "approximately identical" that include certain tolerances, taking into account the measurement and tolerances associated with the measurement of a particular quantity (e.g., limitations of the measurement system), and represent within an acceptable range of deviation for a particular value determined by a person of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the stated value.

[0074] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, that is, meaning "including, but not limited to."

[0075] In the embodiments of this application, "same layer" refers to the relationship between multiple film layers formed from the same material after the same step (e.g., a one-step patterning process). "Same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same. Polygons in this specification are not strictly defined and can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, etc., and some small deformations due to tolerances may exist.

[0076] Micro OLED (Micro Organic Light Emitting Diode) displays are a new type of OLED display device using a silicon substrate as a backplane. Silicon-based OLED displays are characterized by their compact size and high resolution. Their backplanes are manufactured using a mature CMOS (Complementary Metal Oxide Semiconductor) integrated circuit process, enabling active pixel addressing and including various circuits such as the TCON (Timer Control Register) and OCP (Over Current Protection), contributing to their lightweight design.

[0077] Silicon-based OLED display products are widely used in the fields of near-eye display, virtual reality (VR), and augmented reality (AR), especially in AR / VR head-mounted display devices. With the rapid development of various display technologies, customers have higher and higher requirements for display panel performance. Current silicon-based display products are provided with a cathode of the light-emitting device located in the display area (Active area, AA), and a cathode ring located in the peripheral area; wherein the cathode ring is arranged around the display area. However, the current cathode ring design is very likely to cause ESD (Electrostatic Discharge) in the peripheral area of ​​the display product. ESD can cause corrosion or burns in the peripheral area of ​​the display product, damaging the display product.

[0078] Based on this, embodiments of the present application provide a display panel and a display device, wherein the display panel includes a display area and a peripheral area, wherein the peripheral area surrounds the display area; the display panel further includes: a substrate, a plurality of light-emitting devices arranged in an array on the substrate, and a first conductive layer; the light-emitting devices are located at least in the display area; the first conductive layer includes a first cathode ring and an anode of the light-emitting device electrically connected; the first cathode ring is located in the peripheral area and surrounds the display area, and the first cathode ring is electrically connected to the pixel circuit of the display panel; wherein the first cathode ring includes a plurality of conductive patterns, and the plane shape of the conductive patterns includes a concave polygon. In the display panel provided in the embodiments of the present application, by configuring the first cathode ring to include a plurality of conductive patterns, a gap is provided between adjacent two conductive patterns, and the plane shape of the conductive patterns includes a concave polygon; thus, compared to a convex polygon, the concave polygon has more relatively small vertex angles (tip structures). By providing multiple tip structures, it is beneficial to guide the accumulated static electricity away from the conductive path, thereby releasing the static electricity, greatly reducing the risk of ESD in the display panel, thereby improving the yield rate of the display panel, and improving the quality and reliability of the display panel.

[0079] The display panel and the display device provided in the embodiments of the present application will be described and introduced in detail below with reference to the accompanying drawings.

[0080] Figures 1A and 1B show two schematic diagrams of the top view structure of the display panel, and Figures 2 and 3 show two schematic diagrams of the cross-sectional structure of the display panel. Figure 1A illustrates the positional relationship between the lens layer 2 and the first cathode ring 7, while Figure 1B does not depict the lens layer 2. Figure 2 shows a schematic diagram of the cross-sectional structure of Figure 1A along the A1A2 direction, and Figure 3 shows a schematic diagram of the cross-sectional structure of Figure 1B along the A3A4 direction. It should be noted that Figure 3 does not show the cross-sectional structure of the area between the display area AA and the first cathode ring 7. In some display panels in actual applications, a dummy area (dummy pixel area) may also be provided between the display area AA and the first cathode ring 7.

[0081] An embodiment of the present application provides a display panel including a display area AA and a peripheral area BB, wherein the peripheral area BB surrounds the display area AA. With reference to FIG. 1A , FIG. 1B , FIG. 2 , and FIG. 3 , the display panel further includes:

[0082] A substrate 1 and a plurality of light-emitting devices Q arranged in an array on the substrate 1, wherein the light-emitting devices Q are at least located in the display area AA;

[0083] A first conductive layer includes a first cathode ring 7 and an anode AN of the light-emitting device Q that are electrically connected. The first cathode ring 7 is located in the peripheral area BB and surrounds the display area AA. The first cathode ring 7 is electrically connected to the pixel circuit 106 of the display panel.

[0084] The first cathode ring 7 includes a plurality of conductive patterns (such as 7a and 7b shown in FIG. 4 ), a gap exists between two adjacent conductive patterns, and the plane figures of the conductive patterns include concave polygons.

[0085] The display panel includes a substrate 1 and a plurality of sub-pixels arranged in an array. The sub-pixels are located on the substrate 1 and include a light-emitting device Q and a color conversion layer. The color conversion layer is located on the light-emitting side of the light-emitting device Q. Each light-emitting device Q includes a light-emitting functional layer (EML) and a first electrode and a second electrode located on either side of the light-emitting functional layer (EML). For example, as shown in FIG3 , one of the first electrode and the second electrode is an anode AN and the other is a cathode 3. When the first electrode is the anode AN and the second electrode is the cathode 3, the first electrode is located between the light-emitting functional layer (EML) and the substrate 1, and at least a portion of the second electrode is located on a side of the light-emitting functional layer (EML) away from the first electrode. In other words, the first electrode and the second electrode are located on opposite sides of the light-emitting functional layer (EML) in a direction perpendicular to the light-emitting functional layer (EML). The light-emitting functional layer (EML) includes not only layers that directly emit light but also functional layers that assist in light emission, such as a hole transport layer and an electron transport layer.

[0086] It should be noted that in the drawings provided in the embodiments of the present application, such as Figures 2 and 3, for the sake of simplicity, the light-emitting functional layers EML of each light-emitting device Q are drawn together. In actual applications, when the light-emitting colors of each light-emitting device Q are the same, the light-emitting functional layers EML of each light-emitting device Q can be connected together; when the light-emitting colors of each light-emitting device Q are not exactly the same, the light-emitting functional layers EML of each light-emitting device Q are separated by a pixel definition layer PDL to avoid color crosstalk of sub-pixels.

[0087] When the first electrode is an anode and the second electrode is a cathode, multiple light-emitting devices Q can share the second electrode, such as cathode 3. For example, cathode 3 can be formed of a material with high conductivity and low work function, such as a metal material. For example, anode AN can be formed of a transparent conductive material with a high work function.

[0088] In an exemplary embodiment, the material of the first electrode may be indium tin oxide (ITO); alternatively, the material of the first electrode may be titanium / aluminum / titanium / molybdenum (Ti / Al / Ti / Mo); alternatively, the material of the first electrode may be titanium / silver / indium tin oxide (Ti / Ag / ITO). The specific material can be determined based on actual conditions and is not limited here.

[0089] In an exemplary embodiment, the material of the second electrode CA may be a combination of one or more materials selected from magnesium (Mg) and silver (Ag).

[0090] Exemplarily, the second electrode CA includes a stacked magnesium layer and a silver layer, or the second electrode CA includes a magnesium-silver alloy layer.

[0091] In some examples, the driving substrate 100 includes a substrate 1 and a driving unit located on the substrate, where the driving unit includes a pixel circuit 106 and other conductive structures (eg, signal lines and a driving circuit).

[0092] In some examples, the material of the substrate 1 can be made of one or more materials selected from the group consisting of glass, polyimide, polycarbonate, polyacrylate, polyetherimide, and polyethersulfone, and this embodiment includes but is not limited to these.

[0093] In some examples, substrate 1 may be a rigid substrate or a flexible substrate; when substrate 1 is a flexible substrate, substrate 1 may include a single layer of flexible material layer; or, substrate 1 may include a first flexible material layer, a first inorganic non-metallic material layer, a second flexible material layer, and a second inorganic non-metallic material layer stacked in sequence. The first flexible material layer and the second flexible material layer are made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first inorganic non-metallic material layer and the second inorganic non-metallic material layer are made of silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate. The first inorganic non-metallic material layer and the second inorganic non-metallic material layer are also referred to as barrier layers.

[0094] When the substrate 1 is a rigid substrate, the substrate 1 may include a glass substrate or a silicon material substrate. In the case where the substrate 1 is a silicon material substrate, multiple layers of conductive material layers and multiple layers of insulating material layers may be arranged between the substrate 1 and the light-emitting device Q to form a driving circuit and a pixel circuit.

[0095] The silicon substrate may be a P-type single crystal silicon substrate or an N-type single crystal silicon substrate, which may be determined based on the actual product. It should be noted that the embodiments of the present application are described using the display panel having a silicon substrate as an example.

[0096] In some examples, other film layers may be provided between the substrate 1 and the light-emitting device Q. These other film layers may include a gate insulating layer, an interlayer insulating layer, various film layers in a pixel circuit (for example, including thin-film transistors, storage capacitors, and other structures), data lines, gate lines, power signal lines, reset power signal lines, reset control signal lines, light-emitting control signal lines, and other film layers or structures.

[0097] It should be noted that, in conjunction with FIG. 1A and FIG. 1B , it can be seen that the area enclosed by the outer contour of the orthographic projection of the first cathode ring 7 on the substrate 1 is a closed area.

[0098] In an exemplary embodiment, the cathode 3 of the light emitting device Q in the display area AA is electrically connected to the first cathode ring 7 in the peripheral area BB.

[0099] There is no limitation on the arrangement of the plurality of conductive patterns included in the first cathode ring 7. In some embodiments, the plurality of conductive patterns may be arranged in an array.

[0100] FIG4 shows a partial plan view of a plurality of conductive patterns in the first cathode ring 7 . In FIG4 , the planar shapes of all the conductive patterns are the same.

[0101] The above-mentioned concave polygon means that if one of the sides of a polygon is infinitely extended to both sides to form a straight line, and the other sides are not all on the same side of this straight line, then this polygon is called a concave polygon.

[0102] Concave polygons have the following properties:

[0103] 1. Having an internal angle greater than 180°;

[0104] 2. The line segment between two vertices of a polygon is outside the polygon;

[0105] 3. There are two vertices in the polygon, and the line connecting them is not entirely inside the polygon. "Not entirely inside the polygon" means that the line is partially inside the polygon and partially outside the polygon.

[0106] 5A provides a plan view schematic diagram of a concave polygon, and FIG. 5B provides a plan view schematic diagram of twelve types of concave polygons.

[0107] For example, the concave polygon may include a figure formed by splicing two rectangles as shown in FIG5A ;

[0108] Exemplarily, the concave polygon may include twelve shapes as provided in (1) to (12) in FIG. 5AB , for example, a star shape (including a four-pointed star, a five-pointed star, etc.), a cross shape, etc.

[0109] Here, there is no limitation on whether the shapes of the orthographic projections of the above-mentioned multiple conductive patterns on the substrate 1 (i.e., the shapes of the plane figures) are all the same. In some embodiments, the shapes of the plane figures of some conductive patterns are the same, and the shapes of the plane figures of some conductive patterns are different; in other embodiments, the shapes of the plane figures of all conductive patterns are the same.

[0110] FIG. 4 provided in the embodiment of the present application takes the concave polygon shown in FIG. 5A as an example to exemplarily illustrate the arrangement of multiple conductive patterns in the first cathode ring 7 .

[0111] In the display panel provided in the embodiment of the present application, the first cathode ring 7 is provided to include multiple conductive patterns, and there is a gap between two adjacent conductive patterns (for example, 7a or 7b), and the plane figure of the conductive pattern (for example, 7a or 7b) includes a concave polygon; in this way, compared with the convex polygon, the concave polygon has more vertex angles (tip structures) with relatively small angles. By providing multiple tip structures, it is beneficial to conduct the accumulated static electricity away from the conductive path, thereby releasing the static electricity, which greatly reduces the risk of ESD occurring in the display panel, thereby improving the yield of the display panel, and improving the quality and reliability of the display panel.

[0112] In at least one display panel provided in an embodiment of the present application, as shown in (4), (5) and (6) in Figures 5A and 5B, the shape of the positive projection of the conductive pattern (for example, 7a or 7b) on the substrate 1 includes a figure formed by splicing together a first extension portion and a second extension portion; the first extension portion extends along a first direction (for example, an OF1 direction), and the second extension portion extends along a second direction (for example, an OF2 direction); the first direction is the direction from the display area AA to the peripheral area BB, and the second direction is perpendicular to the first direction.

[0113] The first direction (e.g., OF1 direction) is the direction from the display area AA to the peripheral area BB, and the second direction (e.g., OF2 direction) is perpendicular to the first direction (e.g., OF1 direction). It should be noted that OF1 direction is only one of the first directions. Since the peripheral area BB surrounds the display area AA, the first direction can include horizontal rightward (e.g., OF1 direction) as marked in Figure 4, as well as horizontal leftward (the portion of the peripheral area BB located to the left of the display area AA), horizontal upward (the portion of the peripheral area BB located above the display area AA), and horizontal downward (the portion of the peripheral area BB located below the display area AA). The second direction always remains perpendicular to the first direction.

[0114] In an exemplary embodiment, as shown in FIG. 5A and FIG. 5B (4), FIG. 5B (5) and FIG. 6), the first extension portion and the second extension portion are both substantially in the shape of a long strip.

[0115] In at least one display panel provided in an embodiment of the present application, as shown in conjunction with FIG. 4 and FIG. 5A , the planar shape of the first extension portion is a first rectangle J1, the planar shape of the second extension portion is a second rectangle J2, and the shape of the orthographic projection of the conductive pattern (for example, 7a or 7b) on the substrate 1 includes a shape formed by splicing the first rectangle J1 and the second rectangle J2 together;

[0116] The geometric center M1 of the first rectangle J1 overlaps with the geometric center M2 of the second rectangle J2, and the first side B1 of the first rectangle J1 and the first side B1 of the second rectangle J2 are perpendicular. The first side B1 is the long side of the rectangle (referring to the first rectangle J1 and the second rectangle J2).

[0117] In at least one display panel provided in an embodiment of the present application, as shown in FIG4 , the plurality of conductive patterns include a first conductive pattern group G1 and a second conductive pattern group G2 alternately arranged along a first direction (e.g., the OF1 direction); the first conductive pattern group G1 and the second conductive pattern group G2 are both arranged around the display area AA; FIG4 only illustrates a schematic top view of the first cathode ring 7 located in a local area to the right of the display area AA;

[0118] The first conductive pattern group G1 includes a plurality of first conductive patterns 7a arranged along the second direction (eg, the OF2 direction), and the second conductive pattern group G2 includes a plurality of second conductive patterns 7b arranged along the second direction (eg, the OF2 direction).

[0119] As shown in Figure 4, the shape of the line connecting the geometric center of two adjacent first conductive patterns 7a along the first direction (for example, the OF1 direction) (the geometric centers are O1 and O2 respectively) and the geometric center of a second conductive pattern 7b between the two adjacent first conductive patterns 7a (the geometric center is O3) is a first triangle O1O2O3.

[0120] Exemplarily, as shown in FIG4 , the geometric centers of the first conductive patterns 7 a in the same row are located on the same straight line, and the geometric centers of the second conductive patterns 7 b in the same row are located on the same straight line.

[0121] Specifically, as shown in Figure 4, along the first direction (for example, the OF1 direction), the line connecting the geometric centers of the first conductive patterns 7a in the same row is a first straight line, and the first straight line does not overlap with the second conductive pattern 7b; the line connecting the geometric centers of the second conductive patterns 7b in the same row is a second straight line, and the second straight line does not overlap with the first conductive pattern 7a.

[0122] As shown in Figure 4, along the second direction (for example, the OF2 direction), the line connecting the geometric centers of the first conductive patterns 7a in the same row is a third straight line, and the third straight line does not overlap with the second conductive patterns 7b; the line connecting the geometric centers of the second conductive patterns 7b in the same row is a fourth straight line, and the fourth straight line does not overlap with the first conductive pattern 7a.

[0123] In at least one display panel provided by an embodiment of the present application, the first conductive pattern 7a and the second conductive pattern 7b have the same structure and size.

[0124] In at least one display panel provided by an embodiment of the present application, at least one side length of the first triangle O1O2O3 is 3 to 5 times the maximum size of a sub-pixel in the display area AA.

[0125] Exemplarily, the maximum size of a sub-pixel in the display area AA ranges from 5 μm to 10 μm.

[0126] Exemplarily, the length of at least one side of the first triangle O1O2O3 ranges from 15 μm to 50 μm.

[0127] In at least one display panel provided by an embodiment of the present application, at least one side length of the first triangle O1O2O3 is in a range of 15 μm to 30 μm.

[0128] For example, in the first triangle O1O2O3, the lengths of the side O1O2 and the side O1O3 are both in the range of 15 μm to 30 μm.

[0129] Exemplarily, in the first triangle O1O2O3, the lengths of the side O1O2, the side O1O3, and the side O2O3 are all in the range of 15 μm to 30 μm.

[0130] Exemplarily, in the first triangle O1O2O3, the length of the side O1O2 ranges from 15μm to 30μm, for example, the length of the side O1O2 is 16μm, 17μm, 18μm, 19μm, 20μm, 21μm, 22μm, 23μm, 24μm, 25μm, 26μm, 27μm, 28μm, 29μm or 30μm.

[0131] Exemplarily, the lengths of the side O1O3 and the side O2O3 are both shorter than the length of the side O1O2.

[0132] In the embodiment of the present application, when the length of at least one side of the first triangle O1O2O3 is 3 to 5 times the maximum size of the sub-pixel in the display area AA, the size of the conductive pattern is not much different from the size of a sub-pixel in the display area AA, thereby improving the distribution uniformity of the sub-pixels in the display area AA and the conductive pattern in the first cathode ring 7 in the peripheral area BB within the display panel, improving the optical uniformity, and improving the display effect and image quality of the display panel.

[0133] Among them, when the conductive pattern in the peripheral area BB is too large relative to the size of the sub-pixel, the size uniformity of the structures in the display area AA and the peripheral area BB in the display panel is poor, which may cause large differences in optical properties (such as transmittance and reflectivity), thereby reducing the display effect of the display panel; when the conductive pattern in the peripheral area BB is too small relative to the size of the sub-pixel, the contact resistance in the electrical connection path between the conductive pattern and the pixel electrode is too large, which reduces the conductive properties of the display panel, causes the stability of the line transmission in the display panel to deteriorate, and reduces the display effect of the display panel.

[0134] In at least one display panel provided by an embodiment of the present application, the first triangle O1O2O3 is an isosceles triangle.

[0135] Exemplarily, the lengths of side O1O3 and side O2O3 are equal.

[0136] For example, when the lengths of the side O1O3 and the side O2O3 are equal, and when the structures and sizes of the first conductive pattern 7a and the second conductive pattern 7b are the same, as shown in Figure 4, the shape of the line connecting the geometric centers of two adjacent second conductive patterns 7b along the first direction (for example, the OF1 direction) and a first conductive pattern 7a between the two adjacent second conductive patterns 7b is also a first triangle (the triangle shown in the lower right corner of Figure 4).

[0137] For example, when the lengths of side O1O3 and side O2O3 are equal, the distance between the geometric center of any first conductive pattern 7a and the geometric center of an adjacent second conductive pattern 7b along the first direction (for example, the OF1 direction) is approximately equal to half the length of side O1O2; the distance between the geometric center of any second conductive pattern 7b and the geometric center of an adjacent first conductive pattern 7a along the first direction (for example, the OF1 direction) is approximately equal to half the length of side O1O2.

[0138] In at least one display panel provided in an embodiment of the present application, as shown in Figure 5A, the first side B1 of the first rectangle J1 extends along a first direction (for example, the OF1 direction), the first side B1 of the second rectangle J2 extends along a second direction (for example, the OF2 direction), and the area of ​​the first rectangle J1 is greater than the area of ​​the second rectangle J2.

[0139] In at least one display panel provided in an embodiment of the present application, as shown in FIG6 , along a first direction (e.g., the OF1 direction), the minimum distance between the second conductive pattern 7b and the first conductive pattern 7a on the side closer to the display area AA is a first distance d1, and the minimum distance between the second conductive pattern 7b and the first conductive pattern 7a on the side farther from the display area AA is a second distance d2, with the first distance d1 and the second distance d2 being substantially equal. It should be noted that FIG6 through FIG10 each illustrate a partial top view of the first cathode ring 7 in the portion of the peripheral area BB located to the right of the display area AA.

[0140] In an exemplary embodiment, when the structure and size of the first conductive pattern 7a and the second conductive pattern 7b are the same, it can be understood that the first conductive pattern 7a and the second conductive pattern 7b are only named differently to facilitate the explanation of the arrangement of the conductive patterns in the first cathode ring 7, and the first conductive pattern 7a and the second conductive pattern 7b are actually the same structure.

[0141] Then, at this time, in some embodiments, along the first direction (for example, the OF1 direction), the minimum distance between the first conductive pattern 7a and the second conductive pattern 7b on the side close to the display area AA is the first distance d1, and the minimum distance between the first conductive pattern 7a and the second conductive pattern 7b on the side away from the display area AA is the second distance d2, and the first distance d1 and the second distance d2 are approximately equal.

[0142] In at least one display panel provided in an embodiment of the present application, as shown in Figure 6, along the second direction (for example, the OF2 direction), the minimum distance between the second conductive pattern 7b and the first conductive pattern 7a on one side thereof is a third distance d3, and the minimum distance between the second conductive pattern 7b and the first conductive pattern 7a on the other side thereof is a fourth distance d4, and the third distance d3 and the fourth distance d4 are approximately equal.

[0143] In some embodiments, along the second direction (e.g., the OF2 direction), the minimum distance between the first conductive pattern 7a and the second conductive pattern 7b on one side thereof is a third distance d3, and the minimum distance between the first conductive pattern 7a and the second conductive pattern 7b on the other side thereof is a fourth distance d4, and the third distance d3 and the fourth distance d4 are approximately equal.

[0144] In the display panel provided in the embodiment of the present application, by setting the first distance d1 and the second distance d2 to be approximately equal, and the third distance d3 and the fourth distance d4 to be approximately equal, the distribution uniformity of the conductive pattern in the first cathode ring 7 can be greatly improved, thereby uniformly reducing the probability of ESD occurring in the conductive pattern at various positions in the first cathode ring 7, and greatly reducing the risk of ESD occurring in the display panel, thereby improving the yield of the display panel, and improving the quality and reliability of the display panel.

[0145] In at least one display panel provided by an embodiment of the present application, the first distance d1 , the second distance d2 , the third distance d3 and the fourth distance d4 are all in the range of 0.5 to 2 times the maximum size of a sub-pixel in the display area AA.

[0146] Exemplarily, the maximum size of a sub-pixel in the display area AA ranges from 5 μm to 10 μm.

[0147] In at least one display panel provided by an embodiment of the present application, the first distance d1 , the second distance d2 , the third distance d3 , and the fourth distance d4 are in the range of 2.5 μm to 20 μm.

[0148] In at least one display panel provided by an embodiment of the present application, the first distance d1 , the second distance d2 , the third distance d3 , and the fourth distance d4 are all in the range of 5 μm to 10 μm.

[0149] For example, the first distance d1 and the second distance d2 may both be 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm, 9 μm, or 9.5 μm.

[0150] For example, the third distance d3 and the fourth distance d4 may both be 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm, 9 μm, or 9.5 μm.

[0151] In at least one display panel provided by an embodiment of the present application, as shown in FIG6 , the first distance d1 , the second distance d2 , the third distance d3 , and the fourth distance d4 are all substantially equal.

[0152] In the display panel provided in the embodiment of the present application, by setting the first distance d1, the second distance d2, the third distance d3 and the fourth distance d4 to be approximately equal, the distribution uniformity of the conductive pattern in the first cathode ring 7 can be greatly improved, thereby uniformly reducing the probability of ESD occurring between the conductive patterns at various positions in the first cathode ring 7, greatly reducing the risk of ESD occurring in the display panel, and thereby improving the yield of the display panel, and improving the quality and reliability of the display panel.

[0153] In at least one display panel provided in an embodiment of the present application, the length of the first side B1 of the first rectangle J1 is less than or equal to the length of the first side B1 of the second rectangle J2, and the length of the first side B1 of the second rectangle J2 is greater than 0.5 times the length of the first side B1 of the first rectangle J1.

[0154] In an embodiment of the present application, by setting the length of the first side B1 of the second rectangle J2 to be greater than 0.5 times the length of the first side B1 of the first rectangle J1, the difference between the maximum dimension along the first direction and the maximum dimension along the second direction in the conductive pattern of the concave polygon is not large, so that in the conductive path electrically connecting the first cathode ring 7 and the pixel circuit 106, the resistivity along the first direction and the second direction can be better balanced, thereby improving the resistance uniformity in the display panel and improving the driving characteristics of the display panel.

[0155] In at least one display panel provided in an embodiment of the present application, as shown in FIG5A , a length h4 of the first side B1 of the first rectangle J1 is less than or equal to a length h5 of the first side B1 of the second rectangle J2 , and the length h4 of the first side B1 of the first rectangle J1 is in the range of 30 μm to 50 μm.

[0156] Exemplarily, the length h4 of the first side B1 of the first rectangle J1 is smaller than the length h5 of the first side B1 of the second rectangle J2.

[0157] Exemplarily, the length h4 of the first side B1 of the first rectangle J1 is equal to the length h5 of the first side B1 of the second rectangle J2.

[0158] Exemplarily, the length h4 of the first side B1 of the first rectangle J1 is 32 μm, 35 μm, 38 μm, 40 μm, 43 μm, 45 μm, 48 μm, or 49 μm.

[0159] In at least one display panel provided by an embodiment of the present application, a maximum width of the first extension portion along the second direction (eg, OF2 direction) is greater than a maximum width of the second extension portion along the first direction (eg, OF1 direction).

[0160] Exemplarily, when the first extension portion and the second extension portion are both rectangular, in at least one display panel provided in an embodiment of the present application, as shown in FIG5A , the length h6 of the second side of the first rectangle J1 is greater than the length h7 of the second side of the second rectangle J2, the second side is the short side of the rectangle, and the length h6 of the second side of the first rectangle J1 ranges from 20 μm to 30 μm.

[0161] For example, the length h6 of the second side of the first rectangle J1 may be 22 μm, 23 μm, 24 μm, 25 μm, 26 μm, 27 μm, 28 μm, or 29 μm.

[0162] In an embodiment of the present application, by setting the maximum width of the first extension portion along the second direction (for example, the OF2 direction) to be greater than the maximum width of the second extension portion along the first direction (for example, the OF1 direction), it is possible to advantageously reduce the resistance of the first cathode ring 7 along the first direction (for example, the OF1 direction) in the conduction path with the pixel circuit 106 (i.e., the direction of current transmission), thereby improving the conductivity, wherein the direction of current transmission is the direction from the pixel circuit 106 toward the first cathode ring 7.

[0163] In at least one display panel provided in an embodiment of the present application, as shown in FIG5A , in the first rectangle J1 and the second rectangle J2, the length of the first side is greater than the length of the second side, that is, h4 is greater than h6, and h5 is greater than h7; the absolute value of the difference between the length h4 of the first side B1 of the first rectangle J1 and the length h6 of the second side of the first rectangle J1 is greater than or equal to 0.5 to 2 times the maximum size of the sub-pixel in the display area AA.

[0164] Exemplarily, the maximum size of a sub-pixel in the display area AA ranges from 5 μm to 10 μm.

[0165] Exemplarily, the absolute value of the difference between the length h4 of the first side of the first rectangle J1 and the length h6 of the second side of the first rectangle J1 is greater than or equal to a first parameter, and the range of the first parameter is 0.25 μm to 20 μm.

[0166] Exemplarily, an absolute value of a difference between a length h4 of a first side of the first rectangle J1 and a length h6 of a second side of the first rectangle J1 is greater than or equal to a first parameter, and the first parameter ranges from 5 μm to 15 μm.

[0167] Exemplarily, the absolute value of the difference between the length h4 of the first side of the first rectangle J1 and the length h6 of the second side of the first rectangle J1 is greater than or equal to 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm or 14 μm.

[0168] Exemplarily, the absolute value of the difference between the length h5 of the first side of the second rectangle J2 and the length h7 of the second side of the second rectangle J2 is greater than or equal to the second parameter, and the range of the second parameter is the same as the range of the first parameter.

[0169] Exemplarily, the second parameter is greater than or equal to the first parameter.

[0170] In at least one display panel provided in an embodiment of the present application, as shown in Figure 6, for the first conductive pattern 7a and the second conductive pattern 7b adjacent to each other along a first direction (for example, the OF1 direction), the minimum distance between the first side (long side) of the second rectangle J2 in the first conductive pattern 7a and the first side (long side) of the second rectangle J2 in the second conductive pattern 21b is the fifth distance d5; the minimum distance between the first side (long side) of the second rectangle J2 in the second conductive pattern 7b and the first side (long side) of the second rectangle J2 in the first conductive pattern 7a is the fifth distance d5; in the same conductive pattern, the minimum distance between the first side (long side) of the first rectangle J1 and the second side (short side) of the second rectangle J2 is the sixth distance d6; the fifth distance d5 is greater than the sixth distance d6.

[0171] In at least one display panel provided by an embodiment of the present application, as shown in FIG6 , the fifth distance d5 is in a range of 8 μm to 15 μm, and the sixth distance d6 is in a range of 6 μm to 12 μm.

[0172] Exemplarily, the fifth distance d5 may be 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, or 14 μm.

[0173] Exemplarily, the sixth distance d6 may be 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, or 12 μm.

[0174] In at least one display panel provided in an embodiment of the present application, as shown in FIG6 , for two first conductive patterns 7 a adjacent to each other along a first direction (e.g., the OF1 direction), the minimum distance between the first sides (long sides) of the second rectangle J2 in the two first conductive patterns 7 a is a seventh distance d7; for two second conductive patterns 7 b adjacent to each other along the first direction (e.g., the OF1 direction), the minimum distance between the first sides (long sides) of the second rectangle J2 in the two second conductive patterns 7 b is the seventh distance d7;

[0175] For two first conductive patterns 7a adjacent to each other along the second direction (for example, the OF2 direction), the minimum distance between the first side edges (long sides) of the first rectangle J1 in the two first conductive patterns 7a is the eighth distance d8; for two second conductive patterns 7b adjacent to each other along the second direction, the minimum distance between the first side edges (long sides) of the first rectangle J1 in the two second conductive patterns 7b is the eighth distance d8; wherein, the seventh distance d7 is greater than or equal to the eighth distance d8.

[0176] Exemplarily, the seventh distance d7 is greater than the eighth distance d8;

[0177] Exemplarily, the seventh distance d7 is equal to the eighth distance d8.

[0178] In at least one display panel provided in an embodiment of the present application, as shown in Figure 6, the ratio (d7 / h4) between the length of the seventh distance d7 and the length h4 of the first side (long side) of the first rectangle J1 is greater than or equal to the ratio (d8 / h6) between the length of the eighth distance d8 and the length h6 of the second side (short side) of the first rectangle J1, that is, d7 / h4≥d8 / h6.

[0179] In the embodiment of the present application, by setting the above-mentioned d7 / h4≥d8 / h6, it can be understood that when h4 and h6 are equal, d7 is greater than or equal to d8, that is, the size of the gap between two adjacent conductive patterns along the first direction (for example, OF1 direction) is greater than the size of the gap between two adjacent conductive patterns along the second direction (for example, OF2 direction), thereby avoiding direct contact and conduction between two adjacent conductive patterns along the first direction (for example, OF1 direction) as much as possible, and can further reduce the probability of ESD occurring in the conductive patterns at various positions in the first cathode ring 7, thereby greatly reducing the risk of ESD occurring in the display panel, thereby improving the yield of the display panel, and improving the quality and reliability of the display panel.

[0180] In at least one display panel provided by an embodiment of the present application, as shown in FIG7 , a first hollow region LK1 is provided between two adjacent conductive patterns along the second direction (eg, the OF2 direction);

[0181] Exemplarily, a first hollow area LK1 is provided between two adjacent first conductive patterns 7a along the second direction (eg, OF2 direction);

[0182] Exemplarily, a first hollow region LK1 is provided between two adjacent second conductive patterns 7b along the second direction (eg, the OF2 direction).

[0183] Among them, the line connecting the geometric centers of two adjacent first hollow areas LK1 along the first direction (for example, the OF1 direction) and the geometric centers of the conductive pattern between two adjacent first hollow areas LK1 along the first direction (for example, the OF1 direction) is a first line segment (for example, the line segment A1A2 marked in Figure 7); the line connecting the geometric centers of two adjacent first conductive patterns 7a along the first direction (for example, the OF1 direction) is a second line segment (for example, the line segment O1O2 marked in Figure 7); the first line segment A1A2 is parallel to the second line segment O1O2.

[0184] In an exemplary embodiment, the line connecting the geometric centers of two adjacent first hollow areas LK1 along the first direction (for example, the OF1 direction) is a first line segment; the line connecting the geometric centers of two adjacent first conductive patterns 7a along the first direction (for example, the OF1 direction) is a second line segment, and the line connecting the geometric centers of two adjacent second conductive patterns 7b along the first direction (for example, the OF1 direction) is also a second line segment. Any first line segment and the second line segment are arranged in parallel, and the extension directions of the first line segment and the second line segment are consistent with the first direction (for example, the OF1 direction).

[0185] In at least one display panel provided by an embodiment of the present application, as shown in FIG7 , the lengths of the first line segment and the second line segment are substantially the same.

[0186] In an exemplary embodiment, the geometric center of any two adjacent first hollow areas LK1 along the second direction (eg, OF2 direction) and the geometric center of the conductive pattern (including the first conductive pattern 7a or the second conductive pattern 7b) between the two first hollow areas LK1 are located on the same straight line.

[0187] In at least one display panel provided in an embodiment of the present application, as shown in FIG7 , a same conductive pattern (e.g., a same second conductive pattern 7b or a same first conductive pattern 7a) is provided with two first hollow regions LK1 arranged along a first direction (e.g., an OF1 direction) and located on both sides of a first rectangle J1, and two first hollow regions LK1 arranged along a second direction (e.g., an OF2 direction) and located on both sides of a second rectangle J2.

[0188] The shape of the geometric centers of the four first hollow areas LK1 around the same conductive pattern (for example, the same second conductive pattern 7b or the same first conductive pattern 7a) connected in sequence is a quadrilateral (for example, the quadrilateral A1A2A3A4 shown in Figure 7), and the quadrilateral A1A2A3A4 includes two second triangles (i.e., the second triangle A1A2A3 and the second triangle A1A2A4), and the second triangle is the same as the first triangle O1O2O3 marked in Figure 6.

[0189] The second triangle is identical to the first triangle, which means that the two triangles have the same shape and size, and is not limited to having the same arrangement direction or position.

[0190] Exemplarily, the second triangle A1A2A3 and the first triangle O1O2O3 are arranged in the same direction, and the second triangle A1A2A4 and the first triangle O1O2O3 are arranged symmetrically.

[0191] In the display panel provided in the embodiment of the present application, by setting the second triangle shown in Figure 7 (i.e., the second triangle A1A2A3 and the second triangle A1A2A4) to be the same as the first triangle O1O2O3 marked in Figure 6, the distribution uniformity of the conductive pattern in the first cathode ring 7 can be greatly improved, thereby uniformly reducing the probability of ESD occurring between the conductive patterns at various positions in the first cathode ring 7, greatly reducing the risk of ESD occurring in the display panel, and thereby improving the yield of the display panel, and improving the quality and reliability of the display panel.

[0192] In at least one display panel provided in an embodiment of the present application, the peripheral area BB of the display panel also includes multiple auxiliary electrodes (for example, W via1 and W via2), and two adjacent auxiliary electrodes (for example, two adjacent W via1 or two adjacent W via2) arranged along the first direction (the display area AA points to the peripheral area BB) do not contact each other, the orthographic projection of the conductive pattern (for example, 7a and 7b) on the substrate 1 overlaps with the orthographic projection of the auxiliary electrodes (for example, W via1 and W via2) on the substrate 1, and the conductive pattern (for example, 7a and 7b) is electrically connected to the auxiliary electrodes (for example, W via1 and W via2).

[0193] In an exemplary embodiment, the number of conductive patterns included in the conductive pattern group gradually increases along a direction from the display area AA toward the peripheral area BB.

[0194] In at least one display panel provided in an embodiment of the present application, as shown in Figures 8, 9 and 10, the same group of conductive patterns (including the first conductive pattern group G1 or the second conductive pattern group G2) is electrically connected to the pixel circuit 106 through one or more auxiliary electrodes (W via, including W via1 and / or W via2), and the orthographic projection of the same group of conductive patterns (including the first conductive pattern group G1 or the second conductive pattern group G2) on the substrate 1 overlaps with the orthographic projection of multiple auxiliary electrodes (W via, including W via1 or W via2) on the substrate 1.

[0195] Exemplarily, the orthographic projection of the same first conductive pattern group G1 on the substrate 1 overlaps with the orthographic projections of multiple auxiliary electrodes (eg, W via1 and / or W via2 ) on the substrate 1 ;

[0196] Exemplarily, the orthographic projection of the same second conductive pattern group G2 on the substrate 1 overlaps with the orthographic projections of multiple auxiliary electrodes (eg, W via1 and / or W via2 ) on the substrate 1 .

[0197] In an exemplary embodiment, when the orthographic projection of the same group of conductive patterns (including the first conductive pattern group G1 or the second conductive pattern group G2) on the substrate 1 overlaps with the orthographic projection of multiple auxiliary electrodes (for example, W via1 and / or W via2) on the substrate 1, the number of auxiliary electrodes (for example, W via1 or W via2) that overlap with the orthographic projection of the same group of conductive patterns on the substrate 1 gradually increases in the direction from the display area AA to the peripheral area BB.

[0198] Exemplarily, as shown in FIG10 , the length D of an auxiliary electrode (eg, W via1 or W via2 ) along the second direction (eg, OF2 direction) is substantially equal to the distance between two first sides (long sides) of the first rectangle of two adjacent conductive patterns.

[0199] In at least one display panel provided in an embodiment of the present application, as shown in Figures 8, 9 and 10, the planar figure of the conductive pattern is an axially symmetrical figure, and the conductive pattern has a first symmetry axis (dashed line drawn in Figures 8, 9 and 10) extending along a second direction (for example, the OF2 direction); the area where the first symmetry axis is located overlaps with the area where the positive projection of the auxiliary electrode (for example, W via1 and / or W via2) on the substrate 1 is located.

[0200] In an exemplary embodiment, by setting the area where the first symmetry axis is located to overlap with the area where the positive projection of the auxiliary electrode (for example, W via1 and / or W via2) on the substrate 1 is located, the auxiliary electrode (for example, W via1 or W via2) overlaps and is electrically connected to the area near the center axis of the conductive pattern, thereby avoiding electrical connection between two adjacent conductive patterns along the first direction through the auxiliary electrode (for example, W via1 or W via2) when the preparation process is unstable and the alignment accuracy deviates, which can further reduce the risk of ESD in the display panel, thereby improving the yield of the display panel, and improving the quality and reliability of the display panel.

[0201] In at least one display panel provided in an embodiment of the present application, as shown in Figure 3, the display panel also includes a pixel definition layer PDL and a cathode layer 3 located on the side of the pixel definition layer PDL away from the substrate 1, and the portion of the pixel definition layer PDL located in the peripheral area BB includes a plurality of first through holes PDL via; the first cathode ring 7 is arranged at the bottom of the first through hole PDL via; a partial area of ​​the cathode layer 3 falls into the first through hole PDL via and is electrically connected to the conductive pattern through the first through hole PDL via.

[0202] 11 , 12 and 13 illustrate top structural views of the positional relationship between three types of first through holes PDL via and the conductive pattern 7a or 7b; of course, the positional distribution of the plurality of first through holes PDL via is not limited to the above description and can also be adjusted according to actual conditions.

[0203] For example, the material of the pixel definition layer PDL may include organic materials such as polyimide, acrylic or polyethylene terephthalate, etc. The specific location and structure of the portion of the pixel definition layer PDL located in the display area AA may refer to related art and will not be described in detail here.

[0204] In an exemplary embodiment, the area enclosed by the orthographic projection of the outer contour of the first through-hole PDL via on the substrate 1 and the orthographic projection of the auxiliary electrode (eg, W via1 and / or W via2 ) on the substrate 1 do not completely overlap.

[0205] In this specification, terms such as "not completely overlapping" or "not completely identical" include at least two situations: first, partially overlapping and partially non-overlapping; second, completely non-overlapping. Alternatively, first, partially identical and partially different; second, completely different.

[0206] In at least one display panel provided in an embodiment of the present application, as shown in Figures 2 and 3, the display panel also includes a driving substrate 100, the driving substrate 100 includes a substrate 1 and a driving unit, the driving unit is located between the substrate 1 and the first conductive layer (including the first cathode ring 7 and the anode AN of the light-emitting device); the part of the driving unit located in the peripheral area BB includes a second cathode ring 102, and the part of the driving unit located in the display area AA includes a pixel circuit 106, the second cathode ring 102 is electrically connected to the first cathode ring 7 and the pixel circuit 106, respectively; the orthographic projection of the second cathode ring 102 on the substrate 1 is located within the orthographic projection of the first cathode ring 7 on the substrate 1.

[0207] In an exemplary embodiment, the orthographic projection of the second cathode ring 102 on the substrate 1 is located within the orthographic projection of the first cathode ring 7 on the substrate 1, including but not limited to the following situations:

[0208] The contours of the orthographic projections of the first and second cathode rings 102 on the substrate 1 are located within the contour of the orthographic projection of the first cathode ring 7 on the substrate 1;

[0209] Second, the outline of the orthographic projection of the second cathode ring 102 on the substrate 1 overlaps with the outline of the orthographic projection of the first cathode ring 7 on the substrate 1 .

[0210] In practical applications, the driving substrate 100 includes multiple metal layers and an insulating layer between any two adjacent metal layers. The second cathode ring 102 can be disposed in any one or more metal layers of the driving substrate 100 .

[0211] Exemplarily, the drive substrate 100 includes six metal layers, or the drive substrate 100 includes eight metal layers. For example, the six metal layers are the first metal layer, the second metal layer, the third metal layer, the fourth metal layer, the fifth metal layer, and the sixth metal layer, which are sequentially arranged on the substrate 1. The distance between the sixth metal layer and the first cathode ring 7 is the smallest, and the distance between the first metal layer and the first cathode ring 7 is the largest. The second cathode ring 102 can be arranged in a metal layer that is closer to the first cathode ring 7. For example, the second cathode ring 102 can be arranged on the fifth and sixth metal layers; in another example, the second cathode ring 102 can be arranged on the sixth metal layer.

[0212] For example, taking the example of the driving substrate 100 including six metal layers, the metal layer marked 101 in FIG3 can be one of the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer, which is used to electrically connect the second cathode ring 102 with the pixel circuit 106 in the display area AA.

[0213] In at least one display panel provided in an embodiment of the present application, the width of the second cathode ring 102 along the first direction (for example, the OF1 direction) is smaller than the width of the first cathode ring 7 along the first direction (for example, the OF1 direction), and the structures of the conductive patterns in the second cathode ring 102 and the first cathode ring 7 are the same.

[0214] In an exemplary embodiment, the width of the second cathode ring 102 along the first direction (eg, OF1 direction) is smaller than the width of the first cathode ring 7 along the first direction (eg, OF1 direction), including but not limited to the following:

[0215] The number of groups of conductive patterns in the first and second cathode rings 102 is the same as the number of groups of conductive patterns in the first cathode ring 7. The structures of the conductive patterns in the second cathode ring 102 and the first cathode ring 7 are the same. The size of the conductive pattern in the second cathode ring 102 along the first direction (for example, the OF1 direction) is smaller than the size of the conductive pattern in the first cathode ring 7 along the first direction (for example, the OF1 direction).

[0216] Second, the number of groups of conductive patterns in the second cathode ring 102 is smaller than the number of groups of conductive patterns in the first cathode ring 7 , and the structures and sizes of the conductive patterns in the second cathode ring 102 and the first cathode ring 7 are the same.

[0217] In an exemplary embodiment, the pixel circuit 106 may include two transistors and one capacitor (2T1C); alternatively, the pixel circuit 106 may include four transistors and one capacitor (4T1C); alternatively, the pixel circuit 106 may include five transistors and one capacitor (5T1C). The embodiments of the pixel circuit 106 in this application are not limited thereto. In other embodiments, the pixel circuit 106 may include more transistors, more capacitors, or other devices.

[0218] In addition, there is no limitation on the type of transistors in the pixel circuit 106. For example, the transistors may include N-type transistors, or the transistors may include P-type transistors, or the transistors may include both N-type transistors and P-type transistors.

[0219] When the substrate 1 is a silicon material substrate, multiple layers of conductive material layers and multiple layers of insulating material layers can be arranged between the substrate 1 and the light-emitting device Q to form a driving circuit and a pixel circuit, wherein the substrate 1 and the driving circuit and pixel circuit located on the substrate 1 can be collectively referred to as a driving substrate 100 (or driving backplane), and the driving backplane can be a field effect transistor driving backplane (MOS driving backplane), wherein the metal layers in the MOS driving backplane are separated by an insulating layer (for example, the first insulating layer 8 and the second insulating layer 9 shown in Figure 2) and are electrically connected through tungsten vias (W Via).

[0220] In at least one display panel provided in an embodiment of the present application, as shown in Figure 3, the portion of the driving unit located in the peripheral area BB also includes a plurality of auxiliary electrodes, the plurality of auxiliary electrodes include a plurality of first connection electrodes W Via1 and a plurality of second connection electrodes W Via2, the driving substrate includes a second conductive layer (the film layer where the conductive structure 101 is located), and the second conductive layer is located between the plurality of second connection electrodes W Via2 and the substrate 1; multiple refers to at least two.

[0221] In an exemplary embodiment, the plurality of first connection electrodes W Via1 and the plurality of second connection electrodes W Via2 may all be columnar connection circuits, and the columnar shape may include a cylinder and a prism.

[0222] Among them, multiple first connecting electrodes W Via1 are located between the first cathode ring 7 and the second cathode ring 102, and the first connecting electrodes W Via1 are respectively in contact and electrically connected with the first cathode ring 7 and the second cathode ring 102; multiple second connecting electrodes W Via2 are located between the second conductive layer (the film layer where the conductive structure 101 is located) and the second cathode ring 102, and the second connecting electrodes W Via2 are respectively in contact and electrically connected with the second cathode ring 102 and the second conductive layer (the film layer where the conductive structure 101 is located); the second conductive layer is electrically connected to the pixel circuit 106.

[0223] In an exemplary embodiment, the plurality of first connection electrodes W Via1 and the plurality of second connection electrodes W Via2 may also be referred to as tungsten vias.

[0224] For example, the driver substrate 100 includes six metal layers. These six metal layers are, respectively, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer, and a sixth metal layer, sequentially disposed on the substrate 1. The distance between the sixth metal layer and the auxiliary electrode (e.g., W via 1 or W via 2) is the smallest, while the distance between the first metal layer and the auxiliary electrode (e.g., W via 1 or W via 2) is the largest. The metal layer labeled 101 in FIG. 3 can be one of the first, second, third, or fourth metal layers, and is used to electrically connect the second cathode ring 102 to the pixel circuit 106 in the display area AA.

[0225] In at least one display panel provided in an embodiment of the present application, for multiple auxiliary electrodes (for example, W via1 and / or W via2) overlapping with the same conductive pattern; the number of multiple auxiliary electrodes overlapping with the first rectangle J1 is greater than or equal to the number of multiple auxiliary electrodes overlapping with the second rectangle J2.

[0226] Exemplarily, for a plurality of auxiliary electrodes (e.g., W via1 and / or W via2) overlapping with the same conductive pattern in the first cathode ring 7, the number of the plurality of auxiliary electrodes overlapping with the first rectangle J1 is greater than or equal to the number of the plurality of auxiliary electrodes overlapping with the second rectangle J2.

[0227] Exemplarily, as shown in Figures 14, 15, 16 and 17, for multiple auxiliary electrodes (for example, W via1 and / or W via2) that overlap with the same conductive pattern in the second cathode ring 102; the number of multiple auxiliary electrodes that overlap with the first rectangle J1 is greater than or equal to the number of multiple auxiliary electrodes that overlap with the second rectangle J2.

[0228] In an embodiment of the present application, for multiple auxiliary electrodes (for example, W via1 and / or W via2) overlapping with the same conductive pattern; by setting the number of multiple auxiliary electrodes overlapping with the first rectangle J1 (extending along the first direction) to be greater than or equal to the number of multiple auxiliary electrodes overlapping with the second rectangle J2; it can be beneficial to reduce the resistance of the first cathode ring 7 (or the second cathode ring 102) in the conduction path with the pixel circuit 106 along the first direction (for example, the OF1 direction) (i.e., the current transmission direction), and improve the conductivity, wherein the current transmission direction is the direction of the pixel circuit 106 toward the first cathode ring 7 (or the second cathode ring 102).

[0229] In at least one display panel provided in an embodiment of the present application, as shown in Figures 3, 14, 15, 16 and 17, for the conductive pattern in the second cathode ring 102, the orthographic projections of the overlapping first connection electrode W Via1 and the second connection electrode W Via2 on the same conductive pattern do not completely overlap.

[0230] The cases where the orthographic projections of the overlapping first connection electrode W Via1 and the second connection electrode W Via2 on the same conductive pattern do not completely overlap include the following situations:

[0231] First, the orthographic projections of the overlapping first connection electrode W Via1 and the second connection electrode W Via2 on the same conductive pattern overlap;

[0232] Second, the orthographic projections of the overlapping first connection electrode W Via1 and the second connection electrode W Via2 on the same conductive pattern do not overlap at all.

[0233] Figures 14, 15, 16, and 17 provide schematic diagrams of the arrangement of four types of first connection electrodes W Via1 and second connection electrodes W Via2 on the conductive pattern in the second cathode ring 102. In Figures 14 to 17, corresponding to the same conductive pattern in the second cathode ring 102, the multiple first connection electrodes W Via1 are symmetrically distributed, and the multiple second connection electrodes W Via2 are also symmetrically distributed. Symmetrical distribution includes central symmetry and axisymmetry.

[0234] In the embodiment of the present application, by arranging that the orthographic projections of the first connection electrode W Via1 and the second connection electrode W Via2, which overlap on the same conductive pattern, do not completely overlap, the first connection electrode W Via1 and the second connection electrode W Via2 are distributed as dispersedly as possible on the same conductive pattern in the second cathode ring 102, which is beneficial to the conductive stability of the first connection electrode W Via1 and the second connection electrode W Via2 and the same conductive pattern in the second cathode ring 102, thereby improving the quality and reliability of the display panel.

[0235] In addition, it should be noted that, as shown in Figure 2, the light-emitting device Q located in the display area AA can emit light and display, and the light-emitting device Q located in the local area (Dummy area) in the peripheral area BB cannot emit light and display; wherein, the light-emitting device Q located in the local area (Dummy area) in the peripheral area BB is used to improve the structural consistency of the display area AA and the peripheral area BB of the display panel, avoiding the display panel in the dark state due to the large structural difference in the junction area of ​​the display area AA and the peripheral area BB. The color difference is visible to the naked eye, so that the display area AA and the peripheral area BB have a natural transition, thereby improving the aesthetics of the display panel.

[0236] This specification does not limit the plane figure of the display area AA in the above-mentioned display panel. For example, the plane figure of the display area AA can be a rectangle as shown in the drawings of the embodiments of the present application; or, the plane figure of the display area AA can also be other polygons, such as a pentagon, hexagon, etc., which are determined according to the specific usage scenario and usage requirements. For example, the plane figure of the peripheral area BB can be a ring. As the plane figure of the display area AA is different, the plane figure of the peripheral area BB is also different. The plane figure of the peripheral area BB can be determined based on the plane figure of the display area AA. The above-mentioned plane figure refers to the figure of the positive projection on the substrate of the display panel.

[0237] In some embodiments, the light-emitting devices Q in the display area AA of the display panel emit the same color, for example, blue, or white. When the light-emitting devices Q emit blue, the color conversion layer may include a first color conversion pattern, a second color conversion pattern, and a third color pattern. The blue light emitted by the light-emitting device Q may emit red light after passing through the first color conversion pattern, may emit green light after passing through the second color conversion pattern, and may emit blue light after passing through the third color pattern. The first color conversion pattern may be a red quantum dot pattern, the second color conversion pattern may be a green quantum dot pattern, and the third color pattern may be a light-transmitting pattern.

[0238] In some embodiments, each light-emitting device Q in the display area AA of the display panel includes a first color light-emitting device, a second color light-emitting device, and a third color light-emitting device, and the first color light-emitting device, the second color light-emitting device, and the third color light-emitting device are arranged in an array according to a certain pattern, wherein the light emitted by the first color light-emitting device is red light, the light emitted by the second color light-emitting device is green light, and the light emitted by the third color light-emitting device is blue light; at this time, the color conversion layer may include a first filter pattern, a second filter pattern, and a third filter pattern, the first filter pattern may be a red color resist pattern, the second filter pattern may be a green color resist pattern, and the third filter pattern may be a blue color resist pattern; such a color conversion layer may also be referred to as a color filter layer or a color filter layer (as marked CF in Figures 2 and 3), wherein the orthographic projection of the first filter pattern on the substrate 1 overlaps with the orthographic projection of the first color light-emitting device on the substrate 1, the orthographic projection of the second filter pattern on the substrate 1 overlaps with the orthographic projection of the second color light-emitting device on the substrate 1, and the orthographic projection of the third filter pattern on the substrate 1 overlaps with the orthographic projection of the third color light-emitting device on the substrate 1.

[0239] As shown in Figure 2 or Figure 3, the above-mentioned lens layer 2 includes multiple lens structures 21 or 22, wherein the lens layer 2 is located at least on the side of each light-emitting device Q away from the substrate 1, that is, the lens layer 2 is located at least on the light-emitting side of each light-emitting device Q to adjust the optical path of the display light emitted by the light-emitting device Q and improve the light extraction efficiency.

[0240] The material of the lens layer 2 may include silicon nitride, silicon oxide, and silicon oxynitride. In addition, the refractive index of the material of the lens layer 2 is greater than the refractive index of the material of the film layer located on the light-emitting side of the lens layer 2 and in direct contact with the lens layer 2.

[0241] In some embodiments, as shown in FIG. 2 , the outer contour of the orthographic projection of the lens layer 2 on the substrate 1 overlaps with the inner contour of the orthographic projection of the first cathode ring 7 on the substrate 1 .

[0242] Exemplarily, as shown in FIG2 , the lens layer 2 includes a plurality of first lenses 22 and a plurality of second lenses 21 , wherein each first lens 22 is located in the display area AA, and each second lens 21 is located in the peripheral area BB; the height of each second lens 21 along the plane perpendicular to the substrate 1 is less than or equal to the height of each first lens 22 along the plane perpendicular to the substrate 1.

[0243] Exemplarily, as shown in FIG. 2 , along the direction from the display area AA to the peripheral area BB, the height of each second lens 21 is gradually reduced along the plane perpendicular to the substrate 1 .

[0244] In the display panel provided in the embodiment of the present application, by setting the height of the first lens 22 located in the display area AA to be greater than or equal to the height of the second lens 21 located in the peripheral area BB, the first lens 22 can converge the display light emitted from the display area AA and improve the light extraction efficiency; while the second lens 21 can also serve as a transition structure. On the one hand, the second lens 21 near the junction of the display area AA and the peripheral area BB can converge the light to a certain extent, thereby avoiding uneven brightness in the local area of ​​the display area AA near the peripheral area BB; on the other hand, it can further improve the structural consistency of the display area AA and the peripheral area BB of the display panel, avoiding visible color difference at the junction area of ​​the display area AA and the peripheral area BB due to the large structural difference in the display panel in the dark state, so that the area between the display area AA and the peripheral area BB can have a natural transition, thereby further improving the aesthetics of the display panel.

[0245] In some embodiments, as shown in FIG3 , an outer contour of an orthographic projection of the lens layer 2 on the substrate 1 and an inner contour of an orthographic projection of the first cathode ring 7 on the substrate 1 have a gap or are connected.

[0246] In some embodiments, as shown in FIG. 2 or FIG. 3 , the display panel further includes a light shielding layer ZG. The light shielding layer ZG is located in the peripheral area BB and surrounds the display area AA. The light shielding layer ZG and the color filter layer CF are disposed in the same layer.

[0247] It should be noted that the light shielding layer ZG and the color filter layer CF being disposed on the same layer means that the light shielding layer ZG and the color filter layer CF are formed in the same patterning process, and does not mean that the light shielding layer ZG and the color filter layer CF have the same thickness.

[0248] The color filter layer CF includes a black matrix BM, a red filter pattern R, a green filter pattern G, and a blue filter pattern B.

[0249] In some embodiments, the light shielding layer ZG may include a single-layer structure. For example, the light shielding layer ZG is made of the same material as the black matrix BM.

[0250] In other embodiments, the light shielding layer ZG may include a multi-layer structure. For example, the light shielding layer ZG may include multiple sub-layers. For example, the light shielding layer ZG may include: a first sub-layer made of the same material as the red filter pattern, a second sub-layer made of the same material as the green filter pattern, and a third sub-layer made of the same material as the blue filter pattern. The order in which the first, second, and third sub-layers are arranged is not limited. For example, the first sub-layer, the second sub-layer, and the third sub-layer may be arranged in sequence in a direction away from the substrate. For another example, the first sub-layer, the third sub-layer, and the second sub-layer may be arranged in sequence in a direction away from the substrate. For another example, the second sub-layer, the first sub-layer, and the third sub-layer may be arranged in sequence in a direction away from the substrate. Of course, other situations may also be included, which may be determined based on the order in which the red, green, and blue filter patterns are prepared.

[0251] In some embodiments, as shown in FIG. 2 or FIG. 3 , the orthographic projection of the first cathode ring 7 on the substrate 1 is located within the orthographic projection of the light shielding layer ZG on the substrate 1 .

[0252] In an exemplary embodiment, the light shielding layer ZG in the peripheral area BB surrounds the display area AA. It is understood that the projection of the light shielding layer ZG may be in the shape of a ring. The specific shape of the ring is not limited herein, and illustratively, the ring may include a circular ring, an elliptical ring, a polygonal ring, and the like.

[0253] In the embodiment of the present application, a light shielding layer ZG is provided so that the light shielding layer ZG can shield at least part of the circuits and wirings in the peripheral area BB to prevent them from generating reflections that reduce the display effect.

[0254] The orthographic projection of the first cathode ring 7 on the substrate 1 is located within the orthographic projection of the light shielding layer ZG on the substrate 1, including but not limited to the following situations:

[0255] First, the outer contour of the orthographic projection of the first cathode ring 7 on the substrate 1 is located within the outer contour of the orthographic projection of the light shielding layer ZG on the substrate 1;

[0256] Second, the outer contour of the orthographic projection of the first cathode ring 7 on the substrate 1 overlaps with the outer contour of the orthographic projection of the light shielding layer ZG on the substrate 1 .

[0257] In an embodiment of the present application, by setting the orthographic projection of the first cathode ring 7 on the substrate 1 to be within the orthographic projection of the light-shielding layer ZG on the substrate 1, the light-shielding layer ZG can block the first cathode ring 7, thereby preventing the first cathode ring 7 from generating reflections that reduce the display effect.

[0258] In an exemplary embodiment, as shown in FIG2 , the display panel further includes a first encapsulation layer TFE1 and a second encapsulation layer TFE2. The first encapsulation layer TFE1 and the second encapsulation layer TFE2 may both include an organic layer and an inorganic layer. The material of the inorganic layer may be a combination of one or more of silicon nitride, silicon oxide, silicon oxynitride or aluminum oxide, and the material of the organic layer may be polyimide or polyparaxylene.

[0259] In an exemplary embodiment, as shown in Figure 3, the display panel also includes an encapsulation layer TFE, which includes a plurality of sub-layers stacked together. For example, the encapsulation layer TFE includes a silicon oxynitride sub-layer, a silicon nitride sub-layer, a silicon oxynitride sub-layer, and a silicon nitride sub-layer stacked in sequence in a direction away from the substrate 1.

[0260] In an exemplary embodiment, as shown in FIG3 , the display panel further includes at least one barrier dam (Dam) located in the peripheral area (BB). The barrier dam (Dam) is a closed annular structure that prevents moisture from the edge of the display panel from penetrating into the display panel along a path extending from the pixel definition layer (PDL). It should be understood that the barrier dam (Dam) is a groove dug into the pixel definition layer (PDL).

[0261] In an exemplary embodiment, in combination with Figure 1B and Figure 3, the display panel also includes a binding terminal 5 located in the peripheral area BB, and the binding terminal is provided with an opening 105, which is used to expose a partial area of ​​the conductive material of the binding terminal 5 so that the binding terminal 5 can be more electrically connected to the circuit board FPC (the circuit board FPC is not drawn in Figure 3); wherein, the electrical connection method between the binding terminal 5 and the driving unit is not drawn in the drawings of this specification, and for details, please refer to the introduction in the relevant technology.

[0262] In addition, as shown in Figures 2, 3, 18, and 19, the display panel further includes an adhesive layer 11 and a cover plate 12 (CG). As shown in Figure 13, the display panel may further include an aluminum oxide layer 21 and a silicon nitride layer 22, which are used to improve the light extraction efficiency of the light-emitting device; the display panel may further include a first flat layer 23, a second flat layer 24, a third flat layer 25, and a protective portion 103;

[0263] The protective portion 103 surrounds the second cathode ring 102, forming a closed ring. Furthermore, the protective portion 103 extends from the bottom metal layer of the driver substrate 100 (the metal layer closest to the substrate 1) to the top metal layer of the driver substrate 100 (the metal layer farthest from the substrate 1). The metal layers within the protective portion 103 are electrically connected via tungsten vias. The protective portion 103 is also covered with an insulating material. The protective portion 103 protects the edges of the driver substrate, preventing cracks from extending into the interior of the display panel during its manufacture or use, thereby improving the quality and reliability of the display panel.

[0264] Of course, the above-mentioned display panel may also include other structures and components. This specification only introduces structures and components related to the invention. For other structures and components included in the display panel, reference may be made to the introduction in the relevant technology.

[0265] An embodiment of the present application provides a display device, comprising a display panel as described above.

[0266] The structure of the display panel can be referred to in the above description and will not be repeated here.

[0267] As shown in FIG20 , the display device further includes a flexible circuit board FPC and a driver chip IC;

[0268] Alternatively, the display panel includes a display control unit, and the display device further includes a flexible circuit board (FPC).

[0269] The display device provided in the embodiments of the present application may be an OLED display device, wherein the OLED display device may include a glass-based OLED display device and a silicon-based OLED display device.

[0270] In addition, the display device can be a display device such as an OLED display, as well as any product or component with a display function, such as a television, a digital camera, a mobile phone, a tablet computer, etc. that includes these display devices.

[0271] In an exemplary embodiment, when the substrate 1 of the display panel is a silicon substrate, the array substrate of the silicon substrate in the display device can integrate the pixel driving circuit array, source driver, gate driver, emission control driver, OSC (oscillator), gamma register, and display control unit integrated circuit on the same chip. In this case, there is no need to set up an additional driver chip, and the display panel is directly electrically connected to the flexible circuit board (FPC). This is called One Chip technology. The display device prepared by One Chip technology has a higher degree of integration, but is smaller in size, and can be applied to high-resolution display products, such as virtual reality or augmented reality near-eye display fields.

[0272] In an exemplary embodiment, when the substrate of the display panel is a silicon substrate, the array substrate of the silicon substrate can also separate analog circuit parts such as the pixel driving circuit array, source driver, gate driver, emission driver (EOA unit) from the OSC, gamma register, interface and display control unit, changing from One Chip technology to Two Chip technology. At this time, the display panel needs to be electrically connected to the flexible circuit board FPC and the driver chip IC respectively. Compared with products with One Chip technology, this type of product has low manufacturing process requirements and can use low process technology to reduce production costs.

[0273] The display device can be a flexible display device (also known as a flexible screen) or a rigid display device (i.e., a non-bendable display device), without limitation. The display device can be an OLED display device, or any product or component with a display function, such as a television, digital camera, mobile phone, tablet computer, etc. that includes an OLED. The display device has advantages such as good display quality, long life, and high stability.

[0274] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be readily conceived by a person skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A display panel, wherein, It includes a display area and a peripheral area, and the peripheral area surrounds the display area; The display panel further includes: a substrate and a plurality of light-emitting devices arranged in an array on the substrate, and the light-emitting devices are at least located in the display area; a first conductive layer, including a first cathode ring and anodes of the light-emitting devices; the first cathode ring is located in the peripheral area and the first cathode ring surrounds the display area, and the first cathode ring is electrically connected to a pixel circuit of the display panel; Wherein, the first cathode ring includes a plurality of conductive patterns, there is a gap between two adjacent conductive patterns, and a planar pattern of the conductive pattern includes a concave polygon.

2. The display panel according to claim 1, wherein, A shape of a positive projection of the conductive pattern on the substrate includes a pattern formed by splicing a first extension portion and a second extension portion together; The first extension portion extends along a first direction, and the second extension portion extends along a second direction; the first direction is a direction from the display area to the peripheral area, and the second direction is perpendicular to the first direction.

3. The display panel according to claim 2, wherein, A planar pattern of the first extension portion is a first rectangle, and a planar pattern of the second extension portion is a second rectangle; A geometric center of the first rectangle and a geometric center of the second rectangle overlap, and a first side of the first rectangle and a first side of the second rectangle are perpendicular, and the first side is a long side of the rectangle.

4. The display panel according to claim 3, wherein, The plurality of conductive patterns include a first conductive pattern group and a second conductive pattern group alternately arranged along the first direction; both the first conductive pattern group and the second conductive pattern group are arranged around the display area; The first conductive pattern group includes a plurality of first conductive patterns arranged along the second direction, and the second conductive pattern group includes a plurality of second conductive patterns arranged along the second direction; A shape of a connection line of geometric centers of two adjacent first conductive patterns and a second conductive pattern between the two adjacent first conductive patterns along the first direction is a first triangle.

5. The display panel according to claim 4, wherein, Structures and sizes of the first conductive pattern and the second conductive pattern are the same.

6. The display panel according to claim 5, wherein, At least one side length of the first triangle is 3 to 5 times a maximum size of sub-pixels in the display area.

7. The display panel according to claim 5, wherein, The first triangle is an isosceles triangle.

8. The display panel according to claim 7, wherein, The first side of the first rectangle extends along the first direction, the first side of the second rectangle extends along the second direction, and an area of the first rectangle is larger than an area of the second rectangle.

9. The display panel according to claim 8, wherein, Along the first direction, a minimum distance between the second conductive pattern and the first conductive pattern on a side close to the display area is a first distance, a minimum distance between the second conductive pattern and the first conductive pattern on a side far from the display area is a second distance, and the first distance and the second distance are substantially equal.

10. The display panel according to claim 9, wherein, Along the second direction, a minimum distance between the second conductive pattern and the first conductive pattern on one side of it is a third distance, a minimum distance between the second conductive pattern and the first conductive pattern on the other side of it is a fourth distance, and the third distance and the fourth distance are substantially equal.

11. The display panel according to claim 10, wherein, The ranges of the first distance, the second distance, the third distance, and the fourth distance are all 0.5 to 2 times the maximum size of the sub-pixels in the display area.

12. The display panel according to claim 11, wherein, The first distance, the second distance, the third distance, and the fourth distance are all substantially equal.

13. The display panel according to claim 9, wherein, The length of the first side of the first rectangle is less than or equal to the length of the first side of the second rectangle, and the length of the first side of the second rectangle is greater than 0.5 times the length of the first side of the first rectangle.

14. The display panel according to claim 2, wherein, The maximum width of the first extension portion in the second direction is greater than the maximum width of the second extension portion in the first direction.

15. The display panel according to claim 13, wherein, In the first rectangle and the second rectangle, the length of the first side is greater than the length of the second side; The absolute value of the difference between the length of the first side and the length of the second side of the first rectangle is greater than or equal to 0.5 to 2 times the maximum size of the sub-pixels in the display area.

16. The display panel according to claim 8, wherein, For the first conductive pattern and the second conductive pattern adjacent in the first direction, the minimum distance between the first side of the second rectangle in the first conductive pattern and the first side of the second rectangle in the second conductive pattern is the fifth distance; the minimum distance between the first side of the second rectangle in the second conductive pattern and the first side of the second rectangle in the first conductive pattern is the fifth distance; in the same conductive pattern, the minimum distance between the first side of the first rectangle and the second side of the second rectangle is the sixth distance; the fifth distance is greater than the sixth distance.

17. The display panel according to claim 8, wherein, For two adjacent first conductive patterns in the first direction, the minimum distance between the first sides of the second rectangles in the two first conductive patterns is the seventh distance; for two adjacent second conductive patterns in the first direction, the minimum distance between the first sides of the second rectangles in the two second conductive patterns is the seventh distance; For two adjacent first conductive patterns in the second direction, the minimum distance between the first sides of the first rectangles in the two first conductive patterns is the eighth distance; for two adjacent second conductive patterns in the second direction, the minimum distance between the first sides of the first rectangles in the two second conductive patterns is the eighth distance; Wherein, the seventh distance is greater than or equal to the eighth distance.

18. The display panel according to claim 17, wherein, The ratio of the length of the seventh distance to the length of the first side of the first rectangle is greater than or equal to the ratio of the length of the eighth distance to the length of the second side of the first rectangle.

19. The display panel according to claim 8, wherein, There is a first hollow area between two adjacent conductive patterns in the second direction; The line connecting the geometric centers of two adjacent first hollow areas in the first direction, and the geometric center of the conductive pattern between two adjacent first hollow areas in the first direction is the first line segment; The line connecting the geometric centers of two adjacent first conductive patterns in the first direction is the second line segment; The first line segment is parallel to the second line segment.

20. The display panel according to claim 19, wherein, The lengths of the first line segment and the second line segment are substantially the same.

21. The display panel according to claim 19, wherein, Two first hollow areas arranged along the first direction and located on both sides of the first rectangle, and two first hollow areas arranged along the second direction and located on both sides of the second rectangle are provided around the same conductive pattern; The shape formed by sequentially connecting the geometric centers of the four first hollow areas around the same conductive pattern is a quadrilateral, and the quadrilateral includes two second triangles, which are the same as the first triangles.

22. The display panel according to any one of claims 4 to 21, wherein, The display panel further includes a plurality of auxiliary electrodes, which are arranged in the peripheral area. Adjacent two of the auxiliary electrodes arranged along the first direction do not contact each other. The orthographic projection of the conductive pattern on the substrate overlaps with the orthographic projection of the auxiliary electrodes on the substrate, and the conductive pattern is electrically connected to the auxiliary electrodes.

23. The display panel according to claim 22, wherein, The planar graph of the conductive pattern is an axisymmetric graph, and the conductive pattern has a first axis of symmetry extending along the second direction; the area where the first axis of symmetry is located overlaps with the area where the orthographic projection of the auxiliary electrodes on the substrate is located.

24. The display panel according to claim 22, wherein, The display panel further includes a pixel defining layer and a cathode layer located on the side of the pixel defining layer away from the substrate. The part of the pixel defining layer located in the peripheral area includes a plurality of first through holes; the first cathode ring is provided at the bottom of the first through holes; Part of the cathode layer falls into the first through holes and is electrically connected to the conductive pattern through the first through holes.

25. The display panel according to claim 24, wherein, The display panel further includes a driving substrate, and the driving substrate includes the substrate and a driving unit, and the driving unit is located between the substrate and the first conductive layer; The part of the driving unit located in the peripheral area includes a second cathode ring, and the part of the driving unit located in the display area includes the pixel circuit. The second cathode ring is electrically connected to the first cathode ring and the pixel circuit respectively; the orthographic projection of the second cathode ring on the substrate is located within the orthographic projection of the first cathode ring on the substrate.

26. The display panel according to claim 25, wherein, The width of the second cathode ring along the first direction is less than the width of the first cathode ring along the first direction, and the conductive pattern structures of the second cathode ring and the first cathode ring are the same.

27. The display panel according to claim 25, wherein, The plurality of auxiliary electrodes include a plurality of first connection electrodes and a plurality of second connection electrodes. The driving substrate includes a second conductive layer, and the second conductive layer is located between the plurality of second connection electrodes and the substrate; The plurality of first connection electrodes are located between the first cathode ring and the second cathode ring, and the first connection electrodes are in contact electrical connection with the first cathode ring and the second cathode ring respectively. The plurality of second connection electrodes are located between the second conductive layer and the second cathode ring, and the second connection electrodes are in contact electrical connection with the second cathode ring and the second conductive layer respectively. The second conductive layer is electrically connected to the pixel circuit.

28. The display panel according to claim 27, wherein, For the plurality of auxiliary electrodes that overlap with the conductive pattern of the same first cathode ring; The number of the plurality of auxiliary electrodes that overlap with the first rectangle is greater than or equal to the number of the plurality of auxiliary electrodes that overlap with the second rectangle.

29. The display panel according to claim 27, wherein, For the conductive pattern in the second cathode ring, the orthographic projections of the overlapping first connection electrode and the second connection electrode on the conductive pattern do not completely overlap for the same conductive pattern.

30. A display device, wherein, A display panel includes any one of claims 1 to 29.

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