Mosfet chip, transistor, power supply, and electronic device

Abstract

A MOSFET chip, a transistor, a power supply, and an electronic device. The MOSFET chip comprises a gate pad, at least two gate buses, and at least two unit cell regions. Each unit cell region among the at least two unit cell regions comprises at least one unit cell element. Each gate bus among the at least two gate buses is connected to a different unit cell region among the at least two unit cell regions, and the gate pad is connected to the at least two gate buses. The gate pad is used for driving, by means of the at least two gate buses, the at least one unit cell element to start, and the start time point of at least one unit cell region among the at least two unit cell regions is different. in this way, unit cells in the MOSFET chip are divided into different regions, and the start time points of different regions are different. By means of time-division start, the thermal aggregation of unit cells with a small pitch in a slow start stage is avoided, thereby improving the reliability of MOSFET transistors.

Description

MOSFET chip, transistor, power supply and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on December 12, 2023, with application number 202311704685.3 and application name “A MOSFET chip, transistor, power supply and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of electronic technology, and specifically to a MOSFET chip, a transistor, a power supply, and an electronic device. Background Art

[0003] With the continuous development and widespread application of communication technology, the reliability of power supply systems has become particularly important. Metal-oxide-semiconductor field-effect transistors (MOSFETs) are a commonly used electronic device in power supply systems.

[0004] Nowadays, power system downtime can have serious consequences. Therefore, maintaining the system and replacing faulty components without disrupting its operation are highly effective methods for improving system reliability. This ability to plug and unplug components without interrupting power and affecting the normal operation of other components requires a soft-start feature for the core MOSFET components in the circuit. During soft-start, the MOSFET device is not fully turned on, typically lasting hundreds of microseconds or even tens of milliseconds, generating significant inrush current.

[0005] However, in order to reduce the loss of MOSFET devices and improve the efficiency of the devices, the unit cells in MOSFET have evolved from a planar structure to a trench structure, making the spacing between the unit cells smaller and smaller. As the spacing between the unit cells becomes smaller and smaller, the MOSFET is more prone to heat accumulation during the slow start phase. When the slow start phase exceeds the single pulse current that the MOSFET can withstand, the device will burn out due to heat.

[0006] Summary of the Invention

[0007] The present invention provides a MOSFET chip that prevents heat accumulation in cells with small spacing between them during a slow startup phase, thereby improving the reliability of the MOSFET transistor. The present invention also provides a corresponding transistor, power supply, and electronic device.

[0008] In a first aspect, the present application provides a MOSFET chip, which includes a gate pad, at least two gate buses and at least two primitive cell regions; each of the at least two primitive cell regions includes at least one primitive cell unit; each of the at least two gate buses is connected to a different primitive cell region in the at least two primitive cell regions, and the gate pad is connected to the at least two gate buses; the gate pad is used to drive at least one primitive cell unit to start through the at least two gate buses, and the start-up time point of at least one primitive cell region in the at least two primitive cell regions is different.

[0009] In this application, the MOSFET chip also includes a source pad and a drain pad, and at least two primitive cell regions are also connected to the source pad. Gate buses correspond to primitive cell regions one-to-one, that is, each gate bus is responsible for connecting one primitive cell region to the gate pad.

[0010] In the present application, at least one of the at least two primitive cell regions has a different activation time point, that is, at least one primitive cell region has a different activation time point from the other primitive cell regions. By adjusting the activation time points of the primitive cell regions, setting the activation time points of at least one primitive cell region to be different from the activation time points of the other primitive cell regions, heat accumulation caused by simultaneous activation of all primitive cell regions can be avoided.

[0011] In the first aspect, the MOSFET chip includes a gate pad, at least two gate buses, and at least two primitive cell regions, each of the at least two primitive cell regions including at least one primitive cell unit. Each of the at least two gate buses is connected to a different primitive cell region in the at least two primitive cell regions, and the gate pad is connected to the at least two gate buses. The gate pad is used to drive at least one primitive cell unit to start up via the at least two gate buses, and at least one primitive cell region in the at least two primitive cell regions has a different start-up time point, thereby dividing the primitive cells in the MOSFET chip into different regions, and the different regions have different start-up time points. By time-sharing startup, heat accumulation in primitive cells with small spacing is avoided during the slow startup phase, thereby improving the reliability of the MOSFET transistor.

[0012] In a possible implementation of the first aspect, the chip further includes at least two delay units, each of the at least two gate buses is connected to a different delay unit in the at least two delay units, and the gate pad is connected to the at least two gate buses through the at least two delay units; the at least two delay units are used to extend the start-up time point of at least two primitive cell regions, and the extension time set for each delay unit in the at least two delay units is different.

[0013] In this possible implementation, the delay unit does not require changes to the peripheral circuits of the MOSFET chip. It can be implemented by integrating units with delay functions such as capacitors on the die of the chip. The overall structure has low complexity and high adaptability.

[0014] In a possible implementation manner of the first aspect, the at least two delay units are delay circuits composed of capacitors and resistors, and the capacitance values ​​and / or resistance values ​​of the at least two delay units are different.

[0015] In this possible implementation, the delay unit is specifically a delay circuit, which is composed of a capacitor and a resistor. By adjusting the capacitance of the capacitor and / or the resistance of the resistor, the extension time set by the delay unit can be changed, thereby changing the start-up time point of each primitive cell area, thereby improving the feasibility of the solution.

[0016] In a possible implementation of the first aspect, the number of gate pads is at least two, each of the at least two gate pads is connected to a different gate bus among the at least two gate buses, and the driving time point of each of the at least two gate pads is different.

[0017] In this possible implementation, the driving time point of the external driver can be controlled to change the start time point of each gate PIN pin driving each cell area, thereby achieving more flexible adjustment of the driving time point to meet different user needs.

[0018] In a possible implementation manner of the first aspect, the chip further includes a driving unit, which is configured to control a driving time point at which the at least two gate pads drive the at least one primitive cell unit to start.

[0019] In this possible implementation, the driving unit can be built into the chip, which improves the feasibility of the solution.

[0020] In a possible implementation manner of the first aspect, the activation time point of each primitive cell region in the at least two primitive cell regions is different.

[0021] In this possible implementation, the start-up time point of each primitive cell region is different from each other, ensuring that the start-up time points of adjacent primitive cell regions are different, further avoiding the thermal aggregation phenomenon of primitive cell units with small spacing.

[0022] In a possible implementation manner of the first aspect, at least one primitive cell unit is a groove structure primitive cell.

[0023] In this possible implementation, the unit cells in each unit cell area have a groove structure, thereby reducing the loss of the MOSFET device and improving the efficiency of the device. Although the groove structure will reduce the spacing between the unit cells, by combining the method of setting a delay unit or controlling the driving time point in the embodiment of the present application, the heat accumulation phenomenon caused by the small spacing between the unit cells can be avoided.

[0024] A second aspect of the present application provides a MOSFET transistor, which includes a MOSFET chip as described in the first aspect or any possible implementation of the first aspect.

[0025] A third aspect of the present application provides a power supply, which includes a MOSFET chip and a drive circuit as described in the first aspect or any possible implementation of the first aspect, wherein the drive circuit is coupled to the MOSFET chip.

[0026] A fourth aspect of the present application provides an electronic device, which includes a MOSFET chip as described in the first aspect or any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG1 is an equivalent circuit diagram of an existing MOSFET chip layout design;

[0028] FIG2 is a schematic diagram of an embodiment of a MOSFET chip provided in an embodiment of the present application;

[0029] FIG3 is a schematic diagram of another embodiment of a MOSFET chip provided in an embodiment of the present application;

[0030] FIG4 is a schematic diagram of another embodiment of a MOSFET chip provided in an embodiment of the present application;

[0031] FIG5 is a schematic diagram of an embodiment of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following describes the embodiments of the present application in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present application, rather than all the embodiments. Those skilled in the art will appreciate that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0033] The terms "first," "second," and the like in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0034] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0035] In addition, numerous specific details are provided in the detailed description below to better illustrate the present application. Those skilled in the art will appreciate that the present application can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main purpose of the present application.

[0036] The key terms involved in the embodiments of this application are explained below.

[0037] (1) Metal-oxide-semiconductor field-effect transistor (MOSFET)

[0038] The MOSFET transistor (the main component is the MOSFET chip or die, hereinafter referred to as MOSFET) is a common electronic device widely used in various circuits. It features high current drive capability, low power consumption, and fast response, making it widely used in power amplification, switch control, and analog signal processing. A MOSFET consists of a metal oxide semiconductor (MOS) structure, which includes an insulating layer, a control electrode (gate), and a semiconductor material between the two control electrodes.

[0039] The working principle of MOSFET is to control the current in the channel by controlling the gate voltage. MOSFET has three operating modes: cutoff region, saturation region, and amplification region. In the cutoff region, the MOSFET is off and no current flows. In the saturation region, the MOSFET can carry a large current, and the voltage can control the magnitude of the current. In the amplification region, the MOSFET can amplify voltage or current signals. The working principle of MOSFET is based on the field effect. When the gate voltage is zero, no conductive channel is formed in the semiconductor material under the insulating layer, so current cannot flow. When a forward voltage is applied to the gate, an electric field is generated under the insulating layer, forming a conductive channel in the semiconductor material, allowing current to flow. By changing the gate voltage, the resistance of the conductive channel can be controlled, and thus the magnitude of the current.

[0040] One of the advantages of MOSFETs is their low power consumption. Due to the presence of the insulating layer, MOSFETs have almost no leakage current in the cut-off region, so they consume almost no energy when not operating. This makes MOSFETs suitable for applications that require low power consumption, such as mobile devices and battery-powered circuits. Another advantage is the fast response characteristic of MOSFETs. Due to the presence of the insulating layer, the response time of MOSFETs is very short, and current can be switched on and off quickly. This makes MOSFETs suitable for applications that require high-frequency operation, such as radio frequency (RF) circuits and communications equipment. MOSFETs also have high current drive capability. Due to the presence of the conductive channel, MOSFETs can withstand large currents. This makes MOSFETs suitable for applications that need to drive high-power loads, such as motor drives and power supply controls.

[0041] In summary, the MOSFET is an important electronic device, characterized by high current drive capability, low power consumption, and fast response. It is widely used in various circuits, such as power amplification, switch control, and analog signal processing. By controlling the gate voltage, the MOSFET's conductive channel can be controlled, thereby controlling the current and achieving precise control of the circuit.

[0042] (2) MOSFET primitive cell:

[0043] The most basic working unit of MOSFET is called a cell. A cell is mainly composed of four parts: source, drain, gate and substrate. The functions of each part are as follows:

[0044] Source and drain: In the MOSFET cell structure, the source and drain are the two endpoints used to turn the channel on and off. When the MOSFET is in the on state, current flows from the source to the drain.

[0045] Gate: The gate is the key part of the MOSFET, which controls the switching of the channel. The electric field of the gate can attract or repel electrons in the channel, thereby controlling the flow of current.

[0046] Substrate: The substrate is the foundation of the entire MOSFET and is generally made of semiconductor material. The main function of the substrate is to provide a path for electron conduction and support the structure of the entire device.

[0047] In addition, the MOSFET's primitive cell structure also involves several important physical parameters, such as channel length and channel width. These parameters affect the MOSFET's performance and characteristics, such as switching speed, on-state resistance, and avalanche energy. In general, the MOSFET's primitive cell structure is highly symmetrical, and its various components work together to enable the MOSFET to play a vital role in semiconductor devices. Typical MOSFET primitive cells are divided into planar and trench structures. MOSFET primitive cells are connected together through a gate bus to form a MOSFET device (transistor).

[0048] (3) Gate:

[0049] The gate of a MOSFET is a crucial component. It controls the on / off state of the field-effect transistor (FET) within the MOSFET. A crucial feature of the MOSFET gate is its ability to control the flow of current through the MOSFET by means of an electric field. This means that the gate can control the flow of current by varying the strength of the electric field. Depending on the MOSFET's construction, the gate is typically a very thin layer of metal or semiconductor material sandwiched between the MOSFET's source and drain. When a voltage is applied to the gate, it creates an electric field that controls the width of the conductive layer within the MOSFET, thereby controlling the flow of current. During MOSFET operation, the gate voltage determines the MOSFET's on / off state. When a positive voltage is applied to the gate, it attracts electrons, causing the MOSFET's electron layer to move toward the drain, forming a path and allowing current to flow. When a negative voltage is applied to the gate, it repels electrons, causing the MOSFET's electron layer to move toward the source, thereby blocking the flow of current and turning the MOSFET off. By controlling the gate voltage, the flow of current in the MOSFET can be effectively controlled, thereby achieving circuit control.

[0050] (4) Gate bus:

[0051] MOSFET is composed of many independent unit cells connected in parallel and connected together by a gate bus. The bus used to connect the gates of each independent unit cell inside the MOSFET device is called the gate bus.

[0052] (5) Gate pad:

[0053] The surface of a MOSFET chip is generally composed of a source pad, a gate pad, and a drain pad. The gate pad is the pad that connects to the gate pin of the device frame. Its main function is to transmit the gate signal to each switching unit.

[0054] (6) Safety operation area (SOA):

[0055] SOA refers to the range of conditions under which a power semiconductor device can operate reliably. It is determined by five factors: on-resistance, maximum current, maximum power dissipation, secondary breakdown power, and maximum withstand voltage. As technology advances, MOSFET cells are becoming increasingly dense, and the thermal effects of devices are becoming increasingly pronounced. A typical failure scenario within the safe operating area (SOA) is secondary breakdown caused by heat accumulation during high current applications in the linear operating region.

[0056] (7) Gate charge (Qg):

[0057] Qg refers to the gate charge of a transistor, also known as gate charge or gate charge. In MOSFET devices, Qg is the charge required to charge and discharge the gate capacitance. The magnitude of Qg is dependent on factors such as gate length, gate area, and insulation thickness. Qg affects device performance indicators such as switching speed, power consumption, and thermal stability.

[0058] The following uses the above definitions of key terms to illustrate the application scenarios involved in the embodiments of the present application.

[0059] With the continuous development and widespread application of communications technology, the reliability of power supply systems has become increasingly important. MOSFETs are a commonly used electronic component in power supply systems. Currently, even a single second of power system downtime can have serious consequences. Therefore, being able to maintain the system and replace faulty components without disrupting the operation of the power system is a very effective way to improve system reliability. This ability to plug and unplug components without interrupting power and affecting the normal operation of other components requires the MOSFET, a core component in the circuit, to have a soft-start feature. The soft-start period for a single board typically lasts for hundreds of microseconds or even tens of milliseconds, generating a large inrush current. However, power MOSFETs typically only operate normally under these conditions for a few microseconds or less. Therefore, the inrush current and duration generated during the soft-start period exceed the device's safe operating area (SOA), ultimately leading to device failure. As next-generation telecommunications network products evolve towards higher capacity and lower loss, they require low-loss, highly reliable, and wide SOA power MOSFETs.

[0060] At present, in order to pursue lower characteristic on-resistance, reduce the loss of MOSFET devices and improve the efficiency of devices, the primitive cell of power MOSFET devices has evolved from a planar structure to a trench structure, and the size of the primitive cell of MOSFET devices has been continuously reduced, so that the power density of MOSFET devices is further increased, while the spacing between primitive cells is getting smaller and smaller.

[0061] However, as shown in Figure 1, the design of traditional MOSFET chips interconnects all primitive cells to a gate bus (usually using metal materials such as aluminum). When voltage is applied to the MOSFET startup gate, all primitive cells within the MOSFET device start simultaneously. In slow-start applications, the MOSFET device is not fully turned on, and the drain and source are subjected to high voltage and high current for a long time. As the spacing between primitive cells decreases, heat accumulation is more likely to occur during the slow-start phase, inevitably leading to a significant reduction in the device's SOA. If the slow-start phase exceeds the single pulse current that the MOSFET can withstand, the device will burn out due to heat.

[0062] The current approach to improving MOSFET device soft-start performance is to increase the spacing between the cells without reducing the number of MOSFET cells. This increases heat dissipation and reduces heat accumulation during the soft-start phase, thereby improving the MOSFET's soft-start capability. This results in an increase in chip area. In short, the SOA capability of the MOSFET is improved by increasing the chip area.

[0063] The most typical problem of increasing chip area is the increase in the total gate charge Qg. The increase in the total gate charge Qg will lead to the following problems:

[0064] 1. Increased input capacitance: The larger the Qg, the larger the input capacitance. The size of the input capacitance affects the input impedance and frequency response of the MOSFET, thereby changing the input characteristics of the device.

[0065] 2. Reduced switching speed: When the gate voltage changes, the larger the gate charge Qg, the slower the switching speed. This is mainly because the larger the Qg, the longer it takes for the MOS tube's drive circuit to charge or discharge, resulting in a reduced switching speed.

[0066] 3. Increased power consumption: As Qg increases, the gate drive circuit needs to provide a larger current to meet the charge demand, resulting in increased power consumption. This may cause problems such as device heating and reduced efficiency.

[0067] 4. Reduced equipment life: An increase in Qg may reduce the number of MOS tube switching times, thereby reducing the service life of the equipment. This is mainly because an increase in Qg slows down the switching speed of the MOS tube, increasing switching loss and heat loss, leading to accelerated equipment aging.

[0068] Therefore, when designing the MOSFET layout, it is necessary to reduce the gate charge Qg as much as possible, improve the switching performance of the MOSFET, reduce the switching loss of the MOSFET device, and improve the slow start performance of the MOSFET device. Based on this, the embodiment of the present application provides a MOSFET chip for avoiding the thermal aggregation phenomenon of the primitive cells with small spacing in the MOSFET chip during the slow start phase, thereby improving the reliability of the MOSFET transistor. The embodiment of the present application also provides corresponding transistors, power supplies, and electronic devices. They are described in detail below.

[0069] The MOSFET chip provided in the embodiment of the present application is described below in combination with the above key term definitions and application scenarios.

[0070] As shown in FIG. 2 , an embodiment of the present application provides a MOSFET chip. An embodiment of the MOSFET chip includes a gate pad 100 , at least two gate bus lines 200 , and at least two unit cell regions 300 .

[0071] Each of the at least two unit cell regions 300 includes at least one unit cell unit 310. Each of the at least two gate bus lines 200 is connected to a different unit cell region 300 in the at least two unit cell regions 300, and the gate pad 100 is connected to the at least two gate bus lines 200. The gate pad 100 is used to drive at least one unit cell unit 310 to start up through the at least two gate bus lines 200. At least one unit cell region 300 in the at least two unit cell regions 300 has a different start-up time point.

[0072] Specifically, the MOSFET chip (hereinafter referred to as the chip) also includes a source pad 400 and a drain pad (the drain and drain pad are located on the back of the chip, not shown in the figure), and at least two unit cell regions 300 are also connected to the source pad 400. The gate bus lines 200 correspond one to each unit cell region 300, that is, each gate bus line 200 is responsible for connecting one unit cell region 300 to the gate pad 100.

[0073] It should be understood that the MOSFET chip described in the embodiments of the present application is a key component of the MOSFET transistor. In some implementations or descriptions, the relationship between the MOSFET chip and the MOSFET transistor may be equivalent.

[0074] Exemplarily, the chip includes two gate buses 200, a primitive cell region A and a primitive cell region B. Both the primitive cell region A and the primitive cell region B include three primitive cell units 310. The gate pad 100 is used to drive the primitive cell region A and the primitive cell region B to start. The start time point of the primitive cell region A is a, and the start time point of the primitive cell region B is b. a and b are not equal, that is, the start time points of the primitive cell region A and the primitive cell region B are different, thereby avoiding the heat accumulation phenomenon caused by the simultaneous start of the primitive cell region A and the primitive cell region B.

[0075] It should be understood that when there are more primitive cell regions 300, it is necessary to set the startup time point of at least one primitive cell region 300 to be different from the startup time points of other primitive cell regions 300, while the startup time points between other primitive cell regions 300 may be the same. The embodiments of the present application do not limit this.

[0076] In the embodiment of the present application, at least one of the at least two primitive cell regions 300 has a different activation time point, that is, the activation time point of at least one primitive cell region 300 is different from the activation time points of the other primitive cell regions 300. By adjusting the activation time points of the primitive cell regions 300 and setting the activation time points of at least one primitive cell region 300 to be different from the activation time points of the other primitive cell regions 300, heat accumulation caused by the simultaneous activation of all primitive cell regions 300 can be avoided.

[0077] Optionally, to further prevent heat accumulation in the closely spaced unit cells 310, the activation time points of each unit cell region 300 in at least two unit cell regions 300 are different, that is, the activation time points of each unit cell region 300 are different from each other. There are various ways to control the activation time points of the unit cell regions 300, each of which is described in detail below.

[0078] 1. Set the delay unit

[0079] In this case, the chip further includes at least two delay units. Each of the at least two gate buses is connected to a different one of the at least two delay units, and the gate pad is connected to the at least two gate buses via the at least two delay units. The at least two delay units are used to extend the start-up time of at least two primitive cell regions. Each of the at least two delay units is set to a different extended time point, so that the start-up time of each primitive cell region is different.

[0080] Specifically, the delay units correspond to the gate buses one-to-one, and the delay units also correspond to the primitive cell regions one-to-one, that is, each delay unit is only responsible for extending the start-up time point of one primitive cell region.

[0081] For example, as shown in FIG3 (the actual gate bus is connected to each primitive cell unit), at least two delay units are RC delay circuits composed of capacitors and resistors. The at least two primitive cell regions are region A, region B, and region C, each primitive cell region includes multiple primitive cell units, and at least two delay units are delay circuits composed of capacitor A and resistor A, delay circuits composed of capacitor B and resistor B, and delay circuits composed of capacitor C and resistor C. The corresponding gate buses are also three. The gate bus of region A is connected to the gate pad through capacitor A, the gate bus of region B is connected to the gate pad through capacitor B, and the gate bus of region C is connected to the gate pad through capacitor C.

[0082] When the gate pad drives the primitive cell to start up and voltage is applied, the three capacitors A, B, and C must first be charged. Capacitors A, B, and C have different capacitances, so their charging times are different. Consequently, the primitive cells on the gate buses in regions A, B, and C are powered up at different times, resulting in different startup times for the primitive cells in regions A, B, and C.

[0083] Optionally, the interval between the start-up time points of each of the at least two primitive cell regions is greater than the time point required for each of the at least two primitive cell regions to start. That is, when the capacitance value of the capacitor interconnected with the gate bus is set reasonably, it can be achieved that when all the primitive cell units in region A are started, the primitive cell units in regions B and C have not yet started to start. When the primitive cell units in region A are completed to start, the primitive cell units in region B start to start, and the primitive cell units in region C have not yet started to start. When the primitive cell units in regions A and B are completed to start, the primitive cell units in region C start to start. After the primitive cell units in region C are started, the entire MOSFET chip is completed to start.

[0084] Thus, by providing a delay unit, the goal of regional and time-sharing slow startup can be achieved. Furthermore, during regional slow startup, heat accumulation during the slow startup phase is avoided in areas that are not starting or have already completed startup. Furthermore, this delay unit does not require changes to the peripheral circuitry of the MOSFET chip; it can be implemented by integrating a delay unit, such as a capacitor, on the chip's die. This reduces overall structural complexity and offers high adaptability.

[0085] It should be understood that the delay unit, in addition to being a delay circuit composed of capacitors and resistors, can also be replaced by other units or elements with a delay function, such as a delay circuit composed of capacitors, resistors and inductors, etc., as long as the delay effect is inconsistent. The embodiments of the present application do not limit this.

[0086] 2. Control driving time point

[0087] At this time, the number of gate pads is at least two, each of the at least two gate pads is connected to a different gate bus of the at least two gate buses, and the driving time point of each of the at least two gate pads is different.

[0088] Specifically, the gate pads correspond to the gate buses one-to-one, and the gate pads also correspond to the primitive cell regions one-to-one, that is, each gate pad is responsible for driving only one primitive cell region.

[0089] For example, as shown in FIG4 (the actual gate bus is connected to each primitive cell unit), each primitive cell region has an independent gate pad (gate pad in region A, gate pad in region B, and gate pad in region C). The startup time points of the primitive cell units in regions A, B, and C are different when driven by an external driver (such as a driver circuit IC outside the transistor) through different gate PIN pins. When the driver driving time point is set reasonably, it can be achieved that when all primitive cell units in region A are started, the primitive cell units in regions B and C have not yet started to start. When the primitive cell units in region A are completed to start, the primitive cell units in region B start to start, and the primitive cell units in region C have not yet started to start. When the primitive cell units in regions A and B are completed to start, the primitive cell units in region C start to start. After the primitive cell units in region C are started, the entire MOSFET chip is completed to start.

[0090] Optionally, the chip further includes a driver unit configured to control the timing at which at least two gate pads drive at least one unit cell to start. This means that rather than using an external driver to control each gate PIN pin, the driver unit can be built into the chip, controlling the timing at which each gate pad drives each unit cell to start.

[0091] Therefore, by providing multiple gate pads, it is possible to achieve regional and time-sharing slow startup. Furthermore, during regional slow startup, the heat accumulation effect during the slow startup phase is avoided in areas that are not started or have already started. Furthermore, by controlling the driving timing of an external driver, the starting time of each gate pad driving each unit cell region can be changed, allowing for more flexible adjustment of the driving timing to meet the diverse needs of users.

[0092] Optionally, at least one unit cell has a trench structure, such as a shielded gate galvanometer (SGT) structure or a super junction (SJ) structure. That is, the units in each unit cell region have a trench structure, thereby reducing the loss of the MOSFET device and improving the efficiency of the device. Although the trench structure reduces the spacing between unit cells, by combining the method of setting a delay unit or controlling the driving time point in the embodiments of the present application, the heat accumulation phenomenon caused by the small spacing between unit cells can be avoided.

[0093] It should be understood that in the embodiment of the present application, all the primitive cell units in the MOSFET chip can be divided into at least two primitive cell areas, and the maximum value of the primitive cell area is the number of primitive cell units, that is, each primitive cell unit can be divided into a separate primitive cell area. The specific division rules can be determined based on the user's needs. It only needs to ensure that there are at least two primitive cell areas that can be started in time and area.

[0094] In an embodiment of the present application, a MOSFET chip includes a gate pad, at least two gate buses, and at least two primitive cell regions, each of the at least two primitive cell regions including at least one primitive cell unit. Each gate bus of the at least two gate buses is connected to a different primitive cell region in the at least two primitive cell regions, and the gate pad is connected to the at least two gate buses. The gate pad is used to drive at least one primitive cell unit to start up through the at least two gate buses, and at least one primitive cell region in the at least two primitive cell regions has a different start-up time point, thereby dividing the primitive cells in the MOSFET chip into different regions, and the different regions have different start-up time points. By time-sharing startup, heat accumulation in primitive cells with small spacing is avoided during the slow startup phase, thereby improving the reliability of the MOSFET transistor.

[0095] The MOSFET chip provided in the embodiment of the present application is introduced above. The transistor, power supply and electronic device provided in the embodiment of the present application are introduced below with reference to the accompanying drawings.

[0096] As shown in Figure 5, an embodiment of the present application provides an electronic device 500, which includes a power supply 510 and a power consumption unit 520. The power supply 510 includes a MOSFET transistor 511 and a driving circuit 512 coupled to the MOSFET transistor 511. The MOSFET transistor 511 includes the MOSFET chip provided in the embodiment of the present application.

[0097] Specifically, the electronic device 500 can be any device that requires a power supply 510 or a MOSFET transistor 511 , and this embodiment of the present application does not limit this.

[0098] For example, when the electronic device 500 needs to be used, the driving circuit 512 starts the power supply 510 by driving the MOSFET transistor 511 , and the power supply 510 provides an operating voltage to the power consumption unit 520 , so that the electronic device 500 can operate normally.

[0099] When the power-consuming unit needs to be maintained or replaced, it is necessary to ensure that the power supply does not stop working. At this time, the MOSFET transistor enters the slow start mode. The MOSFET transistor provided in the embodiment of the present application can be slow started in different areas and time periods, so there will be no heat accumulation effect, thereby ensuring the reliability of the entire electronic device.

[0100] Optionally, the MOSFET transistor provided in the embodiment of the present application can also be applied to other power devices such as DrMOS, and the embodiment of the present application does not limit this.

[0101] Those skilled in the art will appreciate that the structural units of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of this application.

[0102] In the several embodiments provided in this application, it should be understood that the disclosed structure can be implemented in other ways. For example, the embodiments described above are merely schematic. For example, the division of the structure can be divided in other ways in actual implementation, such as multiple units or components can be combined or integrated into another structure, or some features can be ignored. Some or all of the structures can be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, structures or units, which can be electrical, mechanical or other forms.

[0103] In addition, the various structures in the embodiments of the present application may be integrated into one structure, or each structure may exist physically separately, or two or more structures may be integrated into one structure.

[0104] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A MOSFET chip, characterized in that: including a gate pad, at least two gate buses and at least two primitive cell regions; Each of the at least two primitive cell regions includes at least one primitive cell unit; Each of the at least two gate bus lines is connected to a different primitive cell region among the at least two primitive cell regions, and the gate pad is connected to the at least two gate bus lines; The gate pad is used to drive the at least one primitive cell unit to start up through the at least two gate buses, and at least one primitive cell region among the at least two primitive cell regions has a different start-up time point.

2. The chip according to claim 1, characterized in that: The chip further comprises at least two delay units, each of the at least two gate buses is connected to a different delay unit of the at least two delay units, and the gate pad is connected to the at least two gate buses through the at least two delay units; The at least two delay units are used to extend the start time point of the at least two primitive cell regions, and the extension time set for each of the at least two delay units is different.

3. The chip according to claim 2, characterized in that: The at least two delay units are delay circuits composed of capacitors and resistors, and the capacitance values ​​and / or resistance values ​​of the at least two delay units are different.

4. The chip according to claim 1, characterized in that: The number of the gate pads is at least two, each of the at least two gate pads is connected to a different gate bus of the at least two gate buses, and each of the at least two gate pads has a different driving time point.

5. The chip according to claim 4, characterized in that: The chip further includes a driving unit, and the driving unit is used to control a driving time point at which the at least two gate pads drive the at least one primitive cell unit to start.

6. The chip according to any one of claims 1 to 5, characterized in that: The start time point of each of the at least two protocellular regions is different.

7. The chip according to any one of claims 1 to 6, characterized in that: The at least one primitive cell unit is a groove structure primitive cell.

8. A MOSFET transistor, characterized in that: The transistor comprises a MOSFET chip as claimed in any one of claims 1 to 7.

9. A power supply, characterized in that: The power supply comprises a MOSFET chip and a drive circuit as claimed in any one of claims 1 to 7, wherein the drive circuit is coupled to the MOSFET chip.

10. An electronic device, characterized in that: The electronic device comprises the MOSFET chip according to any one of claims 1 to 7.

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