Gate drive circuit

Abstract

This gate drive circuit is connected to an inverter circuit having a plurality of power semiconductor elements, the gate drive circuit applying a gate signal generated using a first voltage supplied from a gate electric power supply to a gate terminal of the power semiconductor elements to drive the power semiconductor elements, the gate drive circuit comprising: a gate resistor that is connected between the gate electric power supply and the gate terminal; a switching circuit that is connected in series with the gate resistor between the gate electric power supply and the gate terminal, the switching circuit switching a connection state of the gate electric power supply and the gate terminal with the gate resistor interposed therebetween; a monitoring resistor, of which one end side is connected between the switching circuit and the gate resistor and the other end side is connected to a monitor electric power supply for supplying a second voltage; a diode that is connected between the switching circuit and the gate terminal; and a diagnosis unit that acquires the potential between the switching circuit and the monitoring resistor and diagnoses the switching circuit on the basis of the potential.

Description

Gate drive circuit

[0001] The present invention relates to a gate drive circuit that applies a gate signal to a gate terminal of a power semiconductor element to drive the power semiconductor element.

[0002] In recent years, a technology called active gate control has become known as a technique for improving the efficiency of power conversion devices. This technology switches gate resistors connected to the gate terminals of multiple power semiconductor elements that make up the power conversion device according to the current and voltage, thereby selecting the switching speed of the power semiconductor elements.

[0003] In a gate drive circuit equipped with an active gate control function, if the gate resistor switching operation does not function properly, the temperature of the power semiconductor element may rise excessively or an excessively high voltage may be applied to the power semiconductor element. Patent Document 1, for example, is known as a technology for solving these problems. Patent Document 1 describes a power semiconductor element drive device that uses a comparator to compare the potentials of two types of discharge resistors connected to the gate terminal of the power semiconductor element with predetermined threshold voltages, and diagnoses the presence or absence of an abnormality in the active gate control switching elements connected to each resistor based on the comparison results.

[0004] Japanese Patent Application Publication No. 2013-158169

[0005] The drive device of Patent Document 1 drives a power semiconductor element by applying a gate signal to the gate terminal of the power semiconductor element through the switching operation of a switching element for active gate control. While the power semiconductor element is being driven, the potential of the resistor is detected and a diagnosis of an abnormality in the switching element is performed only when the power semiconductor element is switched from an on state to an off state or from an off state to an on state. Therefore, there is a problem in that a diagnosis cannot be performed at other times.

[0006] Furthermore, a conventional gate drive circuit without an active gate control function is known in which a switching circuit such as a switching element is connected to the gate terminal of a power semiconductor element, and the power semiconductor element is driven by the switching operation of this switching circuit. As with the drive device of Patent Document 1, even in such a gate drive circuit, it is required to be able to diagnose the presence or absence of an abnormality in the switching circuit used to drive the power semiconductor element at any timing.

[0007] The present invention has been made in view of the above-mentioned problems, and a main object of the present invention is to diagnose a switching circuit connected to a gate terminal of a circuit that drives a power semiconductor element by applying a gate signal to the gate terminal of the power semiconductor element, at any timing regardless of the switching state of the power semiconductor element.

[0008] A gate drive circuit according to the present invention is connected to an inverter circuit having a plurality of power semiconductor elements, and drives the power semiconductor elements by applying a gate signal generated using a first voltage supplied from a gate power supply to the gate terminal of the power semiconductor element, and includes: a gate resistor connected between the gate power supply and the gate terminal; a switching circuit connected in series with the gate resistor between the gate power supply and the gate terminal, and switching a connection state between the gate power supply and the gate terminal via the gate resistor; a monitor resistor having one end connected between the switching circuit and the gate resistor and the other end connected to a monitor power supply that supplies a second voltage; a diode connected between the switching circuit and the gate terminal; and a diagnostic unit that obtains a potential between the switching circuit and the monitor resistor and diagnoses the switching circuit based on the potential.

[0009] According to the present invention, in a circuit that drives a power semiconductor element by applying a gate signal to the gate terminal of the power semiconductor element, diagnosis of a switching circuit connected to the gate terminal can be performed at any timing regardless of the switching state of the power semiconductor element.

[0010] 1 is a block diagram showing a schematic configuration of a motor drive system including a power conversion device according to an embodiment of the present invention. FIG. 2 is a circuit block diagram showing the configuration of a gate drive circuit according to a first embodiment of the present invention. FIG. 3 is a diagram showing an example of selection conditions for a target switching speed. FIG. 4 is a diagram showing an example of a timing chart when a switching speed switching unit is normal in a gate drive circuit according to the first embodiment of the present invention. FIG. 5 is a table summarizing the contents of diagnostic processing according to the first embodiment of the present invention. FIG. 6 is a circuit block diagram showing the configuration of a gate drive circuit according to a second embodiment of the present invention. FIG. 7 is a table summarizing the contents of diagnostic processing according to the second embodiment of the present invention. FIG. 8 is a circuit block diagram showing the configuration of a gate drive circuit according to a third embodiment of the present invention. FIG. 9 is a diagram showing an example of a timing chart when a switching speed switching unit is normal in a gate drive circuit according to the third embodiment of the present invention. FIG. 10 is a table summarizing the contents of diagnostic processing according to the third embodiment of the present invention.

[0011] Fig. 1 is a block diagram showing a schematic configuration of a motor drive system including a power conversion device according to one embodiment of the present invention. In the motor drive system shown in Fig. 1, a power conversion device 200 is connected between a motor 900 and a high-voltage battery 901, and drives the motor 900 by converting DC power supplied from the high-voltage battery 901 into AC power and outputting the AC power to the motor 900. A contactor 902 is provided between the power conversion device 200 and the high-voltage battery 901 to control the connection state between them.

[0012] The power conversion device 200 includes a gate drive circuit 100, an inverter circuit 300, and a voltage smoothing capacitor 500. A command (e.g., a torque command or a rotation command) for driving the motor 900 is input to the power conversion device 200 from a host controller (not shown). The inverter circuit 300 is provided with a plurality of legs, each of which has a plurality of power semiconductor elements arranged in an upper arm and a lower arm, corresponding to the number of phases of the AC power to be output. These legs are connected in parallel to each other to form a bridge circuit. In the example of FIG. 1 , the motor 900 is a three-phase AC motor, and therefore the power conversion device 200 outputs three-phase AC power to the motor 900. Therefore, the inverter circuit 300 is provided with legs for three phases.

[0013] The power conversion device 200 also includes a voltage sensor 10 that measures the voltage of the DC power supplied from the high-voltage battery 901 , and a current sensor 20 that measures the current of the AC power output to the motor 900 .

[0014] The gate drive circuit 100 includes a controller 100a and a driver 100b. The controller 100a generates a drive signal (PWM signal) in response to a command from a higher-level controller based on the voltage value of DC power and the current value of AC power measured by the voltage sensor 10 and the current sensor 20, respectively, and outputs the generated signal to the driver 100b. The driver 100b has a plurality of drive circuits 50 provided for each power semiconductor element of the inverter circuit 300, and drives each power semiconductor element by controlling the switching of the corresponding upper arm or lower arm power semiconductor element using each drive circuit 50. This activates the inverter circuit 300, converting DC power supplied from the high-voltage battery 901 into AC power.

[0015] The voltage smoothing capacitor 500 is connected between the high-voltage battery 901 and the inverter circuit 300, and smoothes the voltage applied to the inverter circuit 300 that fluctuates during power conversion. The voltage across the voltage smoothing capacitor 500 is measured by the voltage sensor 10 as the voltage applied from the high-voltage battery 901 to the inverter circuit 300.

[0016] Next, the gate drive circuit 100 will be described in detail below with reference to the drawings.

[0017] First Embodiment FIG. 2 is a circuit block diagram showing the configuration of a gate drive circuit 100 according to a first embodiment of the present invention. The circuit block diagram of FIG. 2 shows the circuit configuration of the gate drive circuit 100, including a controller 100a and a drive circuit 50, for one of the multiple power semiconductor elements (e.g., the U-phase upper arm) that constitutes an inverter circuit 300. In practice, in a power conversion device 200, a drive circuit 50 is provided for each power semiconductor element of the inverter circuit 300, and the gate drive circuit 100 shown in FIG. 2 is configured by combining each drive circuit 50 with the controller 100a. Note that this circuit block diagram shows an example in which the power semiconductor element is configured by a parallel connection of a power transistor TP1, such as an IGBT, and a freewheel diode DP1, but other types of semiconductor elements, such as a MOSFET, may also be used.

[0018] The controller 100a has the following functional blocks: a drive signal generation unit 31, a switching speed selection unit 32, and a switching speed switch diagnosis unit 33. In the controller 100a, these functional blocks are realized by, for example, a microcomputer executing a predetermined program.

[0019] 1, the voltage sensor 10 measures the voltage HVDC of the DC power supplied from the high-voltage battery 901 and outputs a voltage signal V-hvdc corresponding to the measurement result to the controller 100a. In addition, the current sensor 20 measures the current Io of the phase corresponding to the power transistor TP1 out of the AC power output to the motor 900 and outputs a voltage signal V-io corresponding to the measurement result to the controller 100a.

[0020] Based on the voltage signal V-hvdc and voltage signal V-io input from the voltage sensor 10 and current sensor 20, respectively, the drive signal generation unit 31 acquires the values ​​of the voltage HVDC and current Io represented by these signals. Then, based on the acquired values ​​of the voltage HVDC and current Io and a command from a higher-level controller (not shown), the drive signal generation unit 31 generates a drive signal PWM for controlling the drive of the power transistor TP1 and outputs it to the drive circuit 50. The drive signal generation unit 31 can generate the drive signal PWM by, for example, performing pulse width modulation using well-known feedback control.

[0021] Based on the voltage signal V-hvdc and voltage signal V-io input from the voltage sensor 10 and the current sensor 20, the switching speed selector 32 acquires the values ​​of the DC voltage HVDC and AC current Io represented by these signals. Then, based on the acquired values ​​of the DC voltage HVDC and AC current Io, the switching speed selector 32 selects the target switching speed of the power transistor TP1 from either "low speed" or "high speed," and outputs a switching command Vsel according to the selection result to the drive circuit 50.

[0022] The switching speed switching diagnostic unit 33 diagnoses the switching speed switching unit 53 of the drive circuit 50 based on the switching command Vsel output from the switching speed selector 32 to the drive circuit 50 and the ON-side monitor signal Vmon_ON and OFF-side monitor signal Vmon_OFF input from the switching state monitor unit 54 in the drive circuit 50. Details of the ON-side monitor signal Vmon_ON and OFF-side monitor signal Vmon_OFF input from the switching state monitor unit 54 will be described later.

[0023] Isolation elements 40, 41, 42, and 43 are provided between the controller 100a and the drive circuit 50. These isolation elements may be, for example, photocouplers or transformers.

[0024] The drive circuit 50 includes a gate signal control unit 51, a gate signal generation unit 52, a switching speed changeover unit 53, and a changeover state monitor unit 54.

[0025] The drive signal PWM output from the drive signal generation unit 31 is input to the gate signal control unit 51 via the insulating element 40. The gate signal control unit 51 controls the operations of the buffer transistors TR1 and TR3 included in the gate signal generation unit 52 based on the drive signal PWM, thereby causing the gate signal generation unit 52 to generate a gate signal.

[0026] The gate signal generating unit 52 is a circuit that generates a gate signal using a bias voltage VCC supplied from a gate power supply (not shown) under the control of the gate signal control unit 51, and outputs the generated gate signal to the gate terminal of the power transistor TP1. The gate signal generating unit 52 is connected between the high potential side (VCC side) and low potential side (GND2 side) of the gate power supply.

[0027] The gate signal generating unit 52 includes a turn-on gate resistor Ron1, a turn-off gate resistor Roff1, and buffer transistors TR1 and TR3. The turn-on gate resistor Ron1 is connected between the high-potential side of the gate power supply and the gate terminal of the power transistor TP1. One end of the turn-on gate resistor Ron1 is applied with a bias voltage VCC supplied from the gate power supply, and the other end is connected to the gate terminal of the power transistor TP1 via the buffer transistor TR3. The turn-off gate resistor Roff1 is connected between the low-potential side of the gate power supply and the gate terminal of the power transistor TP1. One end of the turn-off gate resistor Roff1 is applied with a ground voltage GND2 as well as the low-potential side (emitter side) of the power transistor TP1, and the other end is connected to the gate terminal of the power transistor TP1 via the buffer transistor TR1. The buffer transistors TR1 and TR3 are switched on or off in response to a control signal from the gate signal control unit 51, thereby switching the connection destination of the gate terminal of the power transistor TP1. The buffer transistors TR1 and TR3 are configured using, for example, MOSFETs.

[0028] When turning on the power transistor TP1, the gate signal control unit 51 controls the gate signal generation unit 52 to switch on the buffer transistor TR3 and switch off the buffer transistor TR1. As a result, a bias voltage VCC is applied to the gate terminal of the power transistor TP1 via the turn-on gate resistor Ron1, turning on the power transistor TP1. On the other hand, when turning off the power transistor TP1, the gate signal control unit 51 controls the gate signal generation unit 52 to switch off the buffer transistor TR3 and switch on the buffer transistor TR1. As a result, the gate terminal of the power transistor TP1 becomes the same potential as the emitter terminal via the turn-off gate resistor Roff1, turning off the power transistor TP1.

[0029] The switching speed switching unit 53 has a turn-on gate resistor Ron2 connected in parallel to the turn-on gate resistor Ron1, a turn-off gate resistor Roff2 connected in parallel to the turn-off gate resistor Roff1, and switch elements TR2 and TR4. A switch command Vsel output from the switching speed selection unit 32 is input to the switching speed switching unit 53 via an insulating element 41. The switch elements TR2 and TR4 are configured using, for example, MOSFETs.

[0030] The switching speed switching unit 53 switches the connection state of the turn-off gate resistor Roff2 between the gate terminal and emitter terminal of the power transistor TP1 and the connection state of the turn-on gate resistor Ron2 between the gate power supply and the gate terminal of the power transistor TP1 by switching on and off the switch elements TR2 and TR4 in response to the switching command Vsel, respectively. This switches the resistance value when the power transistor TP1 is turned on and off, thereby changing the switching speed of the power transistor TP1.

[0031] When the switching speed selection unit 32 selects the target switching speed of the power transistor TP1 to "low speed" and a corresponding switching command Vsel is input to the switching speed switching unit 53, the switch elements TR2 and TR4 are each switched off. As a result, the resistance value of the power transistor TP1 when turned off becomes the resistance value of the turn-off gate resistor Roff1, and the resistance value when turned on becomes the resistance value of the turn-on gate resistor Ron1. On the other hand, when the switching speed selection unit 32 selects the target switching speed of the power transistor TP1 to "high speed" and a corresponding switching command Vsel is input to the switching speed switching unit 53, the switch elements TR2 and TR4 are each switched on. As a result, the resistance value of the power transistor TP1 when turned off becomes the combined resistance value of the turn-off gate resistors Roff1 and Roff2, and the resistance value when turned on becomes the combined resistance value of the turn-on gate resistors Ron1 and Ron2. These resistance values ​​are smaller than the resistance value of the turn-off gate resistor Roff1 alone and the resistance value of the turn-on gate resistor Ron1 alone, respectively. Therefore, the switching speed of the power transistor TP1 is increased compared to when the target switching speed is "slow."

[0032] 3 is a diagram showing an example of the selection conditions for the target switching speed in the switching speed selection unit 32. In FIG. 3, the horizontal axis represents the instantaneous value (A) of the current Io based on the voltage signal V-io acquired from the current sensor 20, and the vertical axis represents the peak voltage value Vcep (V) between the collector and emitter applied to the power transistor TP1.

[0033] When the current Io is greater than a predetermined current threshold Igc, the switching speed selection unit 32 selects "low" as the target switching speed of the power transistor TP1. This causes the switching elements TR2 and TR4 to be switched off in the switching speed switching unit 53, and "large Rg" is selected, in which the resistance value connected to the gate terminal of the power transistor TP1 is relatively large. At this time, the power transistor TP1 is turned off at a switching speed corresponding to the resistance value of the turn-off gate resistor Roff1, and is turned on at a switching speed corresponding to the resistance value of the turn-on gate resistor Ron1. The resistance values ​​of the turn-off gate resistor Roff1 and the turn-on gate resistor Ron1 are adjusted so that the peak voltage Vcep does not exceed the breakdown voltage Vlimit of the power transistor TP1 even during high current, as shown by curve 321, for example.

[0034] When the current Io is equal to or less than the current threshold Igc, the switching speed selection unit 32 selects "high speed" as the target switching speed of the power transistor TP1. As a result, the switching elements TR2 and TR4 are each switched on in the switching speed changeover unit 53, and "low Rg" is selected, in which the resistance value connected to the gate terminal of the power transistor TP1 is relatively small. At this time, the power transistor TP1 is turned off at a switching speed corresponding to the combined resistance value Roff1·Roff2 / (Roff1+Roff2) of the turn-off gate resistors Roff1 and Roff2, and the power transistor TP1 is turned on at a switching speed corresponding to the combined resistance value Ron1·Ron2 / (Ron1+Ron2) of the turn-on gate resistors Ron1 and Ron2. Since this combined resistance value is smaller than the resistance value of the turn-off gate resistor Roff1 and the resistance value of the turn-on gate resistor Ron1, the switching speed is faster than when the switch elements TR2 and TR4 are off. However, the above combined resistance value ignores the resistance components of diodes D2 and D4, which will be described later, connected in the switching state monitor 54 between the buffer transistor TR1 and the turn-off gate resistor Roff2, and between the buffer transistor TR3 and the turn-on gate resistor Ron2, respectively.

[0035] 3, the target switching speed is switched in accordance with the comparison result between the current Io measured by the current sensor 20 and the current threshold Igc, but the target switching speed may be switched using other indicators as switching conditions, such as the measurement result of the DC power voltage HVDC by the voltage sensor 10. Also, in the example of FIG. 3, the target switching speed is switched between two levels, "low speed" and "high speed," but it may be switched between three or more levels by setting multiple switching conditions.

[0036] 2, the switching state monitor 54 is a circuit that generates an OFF-side monitor signal Vmon_OFF for diagnosing the state of the switch element TR2 and an ON-side monitor signal Vmon_ON for diagnosing the state of the switch element TR4. The switching state monitor 54 has monitor resistors 75 and 76 and diodes D2 and D4.

[0037] One end of the monitor resistor 75 is connected between the turn-off gate resistor Roff2 and the switch element TR2, and the other end is connected to the high potential side (VDD2 side) of a monitor power supply (not shown). As a result, a bias voltage VDD2 is applied to the drain terminal of the switch element TR2 via the monitor resistor 75, and the potential between the turn-off gate resistor Roff2 and the switch element TR2 changes depending on the switching state of the switch element TR2. The monitor resistor 75 is a current limiting resistor that prevents excessive current from flowing from the monitor power supply when the switch element TR2 is on.

[0038] A backflow prevention diode D2 is connected between the switch element TR2 and the gate terminal of the power transistor TP1 to prevent the bias voltage VDD2 from the monitor power supply from being applied to the gate terminal of the power transistor TP1. Note that, in Fig. 2, between the switch element TR2 and the gate terminal of the power transistor TP1, the turn-off gate resistor Roff2 is connected on the switch element TR2 side, and the diode D2 is connected on the gate terminal side of the power transistor TP1, but the positional relationship of these may be reversed.

[0039] One end of the monitor resistor 76 is connected between the turn-on gate resistor Ron2 and the switch element TR4, and the other end is connected to the low potential side (GND2 side) of a monitor power supply (not shown). As a result, a ground voltage GND2 is applied to the drain terminal of the switch element TR4 via the monitor resistor 76, and the potential between the turn-on gate resistor Ron2 and the switch element TR4 changes depending on the switching state of the switch element TR4. The monitor resistor 76 is a current limiting resistor that prevents excessive current from flowing from the monitor power supply when the switch element TR4 is on.

[0040] A backflow prevention diode D4 is connected between the switch element TR4 and the gate terminal of the power transistor TP1 to prevent the ground voltage GND2 from the monitor power supply from being applied to the gate terminal of the power transistor TP1. Note that, in Fig. 2, between the switch element TR4 and the gate terminal of the power transistor TP1, the turn-on gate resistor Ron2 is connected to the switch element TR4 side, and the diode D4 is connected to the gate terminal of the power transistor TP1 side, but the positional relationship of these may be reversed.

[0041] The switching state monitor 54 outputs the potential between the monitor resistor 75 and the switch element TR2 and the potential between the monitor resistor 76 and the switch element TR4 as an OFF-side monitor signal Vmon_OFF and an ON-side monitor signal Vmon_ON, respectively.

[0042] The OFF-side monitor signal Vmon_OFF and the ON-side monitor signal Vmon_ON each change depending on the switching states of the switch elements TR2 and TR4 in the switching speed switching unit 53. That is, when the switch element TR2 is switched OFF, a voltage corresponding to the bias voltage VDD2 is output as the OFF-side monitor signal Vmon_OFF, regardless of the switching state of the power transistor TP1. On the other hand, when the switch element TR2 is switched ON, a voltage corresponding to the ground voltage GND2 is output as the OFF-side monitor signal Vmon_OFF, regardless of the switching state of the power transistor TP1. Furthermore, when the switch element TR4 is switched OFF, a voltage corresponding to the ground voltage GND2 is output as the ON-side monitor signal Vmon_ON, regardless of the switching state of the power transistor TP1. On the other hand, when the switch element TR4 is switched ON, a voltage corresponding to the bias voltage VCC is output as the ON-side monitor signal Vmon_ON, regardless of the switching state of the power transistor TP1. Therefore, by observing the changes in the OFF-side monitor signal Vmon_OFF and the ON-side monitor signal Vmon_ON at any timing and checking whether the observation results match the switching states of the switch elements TR2, TR4 in response to the switching command Vsel, it is possible to diagnose whether the switching speed switching unit 53 is operating normally.

[0043] The OFF-side monitor signal Vmon_OFF and the ON-side monitor signal Vmon_ON output from the switching state monitor unit 70 are input to the controller 100a via the isolation elements 42, 43, respectively. In the controller 100a, the switching speed switching diagnostic unit 33 diagnoses the switching speed switching unit 53 using the OFF-side monitor signal Vmon_OFF and the ON-side monitor signal Vmon_ON. That is, by checking whether the OFF-side monitor signal Vmon_OFF and the ON-side monitor signal Vmon_ON each change as described above in response to the switching command Vsel, the diagnosis unit 33 determines whether the switching speed switching unit 53 is operating normally.

[0044] Next, a specific example of the diagnosis of the switching speed changeover unit 53 performed by the switching speed changeover diagnosis unit 33 of this embodiment will be described with reference to the timing chart of FIG.

[0045] 4 is a diagram showing an example of a timing chart when the switching speed switching unit 53 is normal in the gate drive circuit 100 according to the first embodiment of the present invention. From top to bottom, Fig. 4 shows the instantaneous value of the current Io of the relevant phase measured by the current sensor 20, the switching command Vsel, the gate-source voltage Vgs of the switch elements TR2 and TR4, the drain-source voltage Vds of the switch element TR2, the OFF-side monitor signal Vmon_OFF, the drain-source voltage Vds of the switch element TR4, and the changes over time of the ON-side monitor signal Vmon_ON.

[0046] First, at time t0, the absolute value of the current Io is smaller than the aforementioned current threshold Igc, so the switching speed selection unit 32 sets the target switching speed of the power transistor TP1 to "high speed" as described above, and outputs an H-level switching command Vsel. At this time, the gate-source voltages Vgs of the switch elements TR2 and TR4 are H-level, so the switch elements TR2 and TR4 are each switched on, and the state of the switching speed switching unit 53 is "Rg small." Therefore, the drain-source voltage Vds of the switch element TR2 and the OFF-side monitor signal Vmon_OFF are both L-level, while the drain-source voltage Vds of the switch element TR4 and the ON-side monitor signal Vmon_ON are both H-level.

[0047] Next, when the current Io exceeds the negative current threshold value −Igc at time t1, the switching speed selection unit 32 switches the target switching speed of the power transistor TP1 from “high speed” to “low speed” and changes the switching command Vsel from H level to L level. As a result, the gate-source voltages Vgs of the switch elements TR2 and TR4 each change from H level to L level, and the switch elements TR2 and TR4 are each switched from ON to OFF, causing the state of the switching speed switching unit 53 to change from “small Rg” to “large Rg.” As a result, the drain-source voltage Vds of the switch element TR2 and the OFF-side monitor signal Vmon_OFF each change from L level to H level, while the drain-source voltage Vds of the switch element TR4 and the ON-side monitor signal Vmon_ON each change from H level to L level.

[0048] Thereafter, at time t2, when the current Io falls within the negative current threshold value −Igc, the switching speed selection unit 32 switches the target switching speed of the power transistor TP1 from “low speed” to “high speed” and changes the switching command Vsel from L level to H level. As a result, the gate-source voltages Vgs of the switch elements TR2 and TR4 each change from L level to H level, and the switch elements TR2 and TR4 are each switched from OFF to ON, causing the state of the switching speed switching unit 53 to change from “large Rg” to “small Rg.” As a result, the drain-source voltage Vds of the switch element TR2 and the OFF-side monitor signal Vmon_OFF each change from H level to L level, while the drain-source voltage Vds of the switch element TR4 and the ON-side monitor signal Vmon_ON each change from L level to H level.

[0049] Next, when the current Io exceeds the positive-side current threshold +Igc at time t3, the switching speed selection unit 32 switches the target switching speed of the power transistor TP1 from "high" to "low," and changes the switching command Vsel from H level to L level. As a result, the gate-source voltages Vgs of the switch elements TR2 and TR4 each change from H level to L level, and the switch elements TR2 and TR4 are each switched from ON to OFF, and the state of the switching speed switching unit 53 changes from "small Rg" to "large Rg." As a result, the drain-source voltage Vds of the switch element TR2 and the OFF-side monitor signal Vmon_OFF each change from L level to H level, while the drain-source voltage Vds of the switch element TR4 and the ON-side monitor signal Vmon_ON each change from H level to L level.

[0050] Thereafter, at time t4, when the current Io falls within the positive current threshold value +Igc, the switching speed selection unit 32 switches the target switching speed of the power transistor TP1 from "low speed" to "high speed" and changes the switching command Vsel from L level to H level. As a result, the gate-source voltages Vgs of the switch elements TR2 and TR4 each change from L level to H level, and the switch elements TR2 and TR4 are each switched from OFF to ON, causing the state of the switching speed switching unit 53 to change from "large Rg" to "small Rg." As a result, the drain-source voltage Vds of the switch element TR2 and the OFF-side monitor signal Vmon_OFF each change from H level to L level, while the drain-source voltage Vds of the switch element TR4 and the ON-side monitor signal Vmon_ON each change from L level to H level.

[0051] Note that the same operation as above is performed from time t4 onwards. For example, when the current Io exceeds the negative current threshold -Igc at time t5, the switching command Vsel, the OFF-side monitor signal Vmon_OFF, and the ON-side monitor signal Vmon_ON, and the gate-source voltage Vgs and drain-source voltage Vds of the switch elements TR2 and TR4 all change in the same way as at time t1. Furthermore, when the current Io falls within the negative current threshold -Igc at time t6, the switching command Vsel, the OFF-side monitor signal Vmon_OFF, and the ON-side monitor signal Vmon_ON, and the gate-source voltage Vgs and drain-source voltage Vds of the switch elements TR2 and TR4 all change in the same way as at time t2.

[0052] In this embodiment, the switching speed switching diagnostic unit 33 determines whether the operation of the switching speed switching unit 53 is normal or abnormal by determining whether the relationship between the switching command Vsel and the OFF-side monitor signal Vmon_OFF and the ON-side monitor signal Vmon_ON matches the above relationship. Specifically, when the switching command Vsel is at an L level, the switching speed switching unit 53 is diagnosed as normal if the OFF-side monitor signal Vmon_OFF is at an H level and the ON-side monitor signal Vmon_ON is at an L level. Otherwise, the switching speed switching unit 53 is diagnosed as abnormal. On the other hand, when the switching command Vsel is at an H level, the switching speed switching unit 53 is diagnosed as normal if the OFF-side monitor signal Vmon_OFF is at an L level and the ON-side monitor signal Vmon_ON is at an H level. Otherwise, the switching speed switching unit 53 is diagnosed as abnormal. Therefore, the diagnosis of the switching speed switching unit 53 can be performed at any timing regardless of the switching state of the power transistor TP1.

[0053] 5 is a table summarizing the contents of the diagnostic processing according to the first embodiment of the present invention. As shown in table 330 in FIG. 5 , switching speed switching diagnostic unit 33 determines the state of switching speed switching unit 53 based on the combination of OFF-side monitor signal Vmon_OFF and ON-side monitor signal Vmon_ON when switching command Vsel is at L level (large Rg) and when it is at H level (small Rg).

[0054] In table 330, row 331 represents a case where the OFF-side monitor signal Vmon_OFF and the ON-side monitor signal Vmon_ON are both at the L level when the switching command Vsel is at the L level (large Rg). In this case, it can be determined that the switching speed switching unit 53 is in an abnormal state where the turn-off side is stuck at "small Rg," that is, the switch element TR2 on the side of the turn-off gate resistor Roff2 is stuck on.

[0055] In table 330, row 332 represents a case where, when switching command Vsel is at L level (large Rg), OFF-side monitor signal Vmon_OFF is at L level and ON-side monitor signal Vmon_ON is at H level. In this case, it can be determined that switching speed switching unit 53 is in an abnormal state where both the turn-on side and the turn-off side are stuck at "small Rg," that is, the switch element TR4 on the turn-on gate resistor Ron2 side and the switch element TR2 on the turn-off gate resistor Roff2 side are both stuck on.

[0056] In table 330, row 333 represents a case where, when the switching command Vsel is at L level (Rg large), the OFF-side monitor signal Vmon_OFF is at H level and the ON-side monitor signal Vmon_ON is at L level. In this case, it can be determined that the switching speed switching unit 53 is in a normal state.

[0057] In table 330, row 334 represents a case where the OFF-side monitor signal Vmon_OFF and the ON-side monitor signal Vmon_ON are both H-level when the switching command Vsel is L-level (large Rg). In this case, it can be determined that the switching speed switching unit 53 is in an abnormal state where the turn-on side is stuck at "small Rg," that is, the switch element TR4 on the turn-on gate resistor Ron2 side is stuck on.

[0058] If at least one of the switch elements TR2 and TR4 is in a stuck-on state, the state of the switching speed switching unit 53 is always "Rg low" regardless of the switching command Vsel when the power transistor TP1 is turned on or off. Therefore, when a large current flows, the gate resistance becomes lower than normal, increasing the surge voltage. If this surge voltage exceeds the withstand voltage of the power transistor TP1, there is a risk of the power transistor TP1 failing. To avoid this situation, when the switching speed switching diagnostic unit 33 diagnoses that the switch elements TR2 and TR4 are stuck-on as an abnormality in the switching speed switching unit 53, it is preferable that the power conversion device 200 perform a limp-home process, such as reducing the output current of the inverter circuit 300, depending on the state of the DC voltage HVDC obtained from the voltage sensor 10, as shown in rows 331, 332, and 334 of Table 330.

[0059] In table 330, row 335 represents a case where the OFF-side monitor signal Vmon_OFF and the ON-side monitor signal Vmon_ON are both at L level when the switching command Vsel is at H level (small Rg). In this case, it can be determined that the switching speed switching unit 53 is in an abnormal state where the turn-on side is stuck at "large Rg," that is, the switch element TR4 on the turn-on gate resistor Ron2 side is stuck off.

[0060] In table 330, row 336 represents a case where, when the switching command Vsel is at H level (Rg small), the OFF-side monitor signal Vmon_OFF is at L level and the ON-side monitor signal Vmon_ON is at H level. In this case, it can be determined that the switching speed switching unit 53 is in a normal state.

[0061] In table 330, row 337 represents a case where, when switching command Vsel is at H level (small Rg), OFF-side monitor signal Vmon_OFF is at H level and ON-side monitor signal Vmon_ON is at L level. In this case, it can be determined that switching speed switching unit 53 is in an abnormal state where both the turn-on side and the turn-off side are stuck at "large Rg," that is, the switch element TR4 on the turn-on gate resistor Ron2 side and the switch element TR2 on the turn-off gate resistor Roff2 side are both stuck off.

[0062] In table 330, row 338 represents a case where the OFF-side monitor signal Vmon_OFF and the ON-side monitor signal Vmon_ON are both at the H level when the switching command Vsel is at the H level (small Rg). In this case, it can be determined that the switching speed switching unit 53 is in an abnormal state where the turn-off side is stuck at "large Rg," that is, the switch element TR2 on the side of the turn-off gate resistor Roff2 is stuck off.

[0063] If at least one of the switch elements TR2 and TR4 is in a stuck-off state, the state of the switching speed switching unit 53 is always "Rg high" regardless of the switching command Vsel when the power transistor TP1 is turned on or off. Therefore, when the current is small, the gate resistance becomes higher than normal, which increases the loss of the power transistor TP1, but this does not cause a failure of the power transistor TP1. Therefore, when the switching speed switching diagnostic unit 33 diagnoses that the switch elements TR2 and TR4 are stuck-off as an abnormality in the switching speed switching unit 53, the power conversion device 200 outputs an alarm for the diagnosis result and does not perform limp home, as shown in rows 335, 337, and 338 of Table 330.

[0064] As described above, according to the first embodiment of the present invention, the switching speed switching unit 53 can be diagnosed at any timing regardless of the switching state of the power transistor TP1, and therefore the reliability of the power conversion device 200 can be improved.

[0065] According to the first embodiment of the present invention described above, the following advantageous effects are achieved.

[0066] (1) The gate drive circuit 100 is connected to an inverter circuit 300 having a plurality of power semiconductor elements (power transistors TP1), and drives the power transistor TP1 by applying a gate signal generated using a first voltage (bias voltage VCC) supplied from a gate power supply to the gate terminal of the power transistor TP1. The gate drive circuit 100 includes gate resistors (turn-off gate resistor Roff2, turn-on gate resistor Ron2) connected between a gate power supply and a gate terminal, a switching circuit (switch elements TR2, TR4) connected in series with the gate resistors Roff2, Ron2 between the gate power supply and the gate terminal and configured to switch the connection state between the gate power supply and the gate terminal via the gate resistors Roff2, Ron2, monitor resistors 75, 76 having one end connected between the switch elements TR2, TR4 and the gate resistors Roff2, Ron2 and the other end connected to a monitor power supply that supplies a second voltage (VDD2, GND2), diodes D2, D4 connected between the switch elements TR2, TR4 and the gate terminal, and a diagnostic unit (switching speed switching diagnostic unit 33) that acquires a potential between the switch elements TR2, TR4 and the monitor resistors 75, 76 and diagnoses the switch elements TR2, TR4 based on the potential. As a result, the diagnosis of the switch elements TR2 and TR4, which are switching circuits that switch the connection state between the gate power supply and the gate terminal in order to apply a gate signal to the gate terminal of the power transistor TP1, can be performed at any timing regardless of the state of the power transistor TP1.

[0067] (2) The gate drive circuit 100 includes a switching speed switching unit 53 that switches the switching speed of the power transistor TP1 in response to a gate signal. The switching speed switching unit 53 includes a first gate resistor (turn-off gate resistor Roff1, turn-on gate resistor Ron1) connected between the gate power supply and the gate terminal, a second gate resistor (turn-off gate resistor Roff2, turn-on gate resistor Ron2) connected in parallel with the first gate resistor, and switch elements TR2 and TR4 that establish or break electrical connection between the second gate resistor and the gate power supply. The switching speed switching diagnostic unit 33 diagnoses the switching circuit, focusing on the switch elements TR2 and TR4 as diagnostic targets. This configuration allows the gate drive circuit 100, which has an active gate control function, to diagnose the switch elements TR2 and TR4 used to switch the gate resistance at any timing, regardless of the state of the power transistor TP1.

[0068] (3) When the switching speed switching diagnostic unit 33 diagnoses that the switching elements TR2 and TR4 are abnormal, the power transistor TP1 is driven in parallel with the limp home or alarm output while the electrical connections between the gate power supplies and the turn-off gate resistor Roff2 and the turn-on gate resistor Ron2 by the switching elements TR2 and TR4 are fixed to either conductive or cut-off, as shown in rows 331, 332, 334, 335, 337, and 338 in table 330 of Fig. 5. In this way, even when the switching elements TR2 and TR4 are abnormal, the operation of the power conversion device 200 can be continued to the extent possible without impairing the availability of the system of the vehicle or the like in which the power conversion device 200 is mounted.

[0069] Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIGS.

[0070] FIG. 6 is a circuit block diagram showing the configuration of a gate drive circuit 100 according to a second embodiment of the present invention. The circuit block diagram of FIG. 6 differs from the circuit block diagram of FIG. 2 described in the first embodiment in that an XOR circuit 80 is provided between the controller 100a and the drive circuit 50. Note that although the voltage sensor 10 and the current sensor 20 are not shown in FIG. 6, in the circuit configuration of FIG. 6 as in the first embodiment, a signal V-hvdc representing the voltage measurement result of the high-voltage battery 901 and a signal V-io representing the measurement result of the current Io of each phase are input from the voltage sensor 10 and the current sensor 20 to the controller 100a, respectively.

[0071] The switching speed selection unit 32 outputs switching commands Vsel-U, Vsel-V, and Vsel-W to switching speed changeover units 53 of drive circuits 50 provided corresponding to the U-phase, V-phase, and W-phase arms of the inverter circuit 300. In the drive circuits 50 for the arms of each phase, the switching speed changeover units 53 perform the same operations as those described in the first embodiment in response to the switching commands Vsel-U, Vsel-V, and Vsel-W. That is, in the drive circuits 50 for the upper and lower arms of the U-phase, the switching speed changeover units 53 turn on or off the switch elements TR2 and TR4 in response to the switching command Vsel-U, thereby setting the state of the gate resistance in each arm to either "small Rg" or "large Rg." Similarly, in the drive circuits 50 for the V-phase upper and lower arms, the respective switching speed changeover units 53 turn on or off switch elements TR2, TR4 in accordance with the switching command Vsel-V, thereby setting the state of the gate resistance in each arm to either "small Rg" or "large Rg." Also, in the drive circuits 50 for the W-phase upper and lower arms, the respective switching speed changeover units 53 turn on or off switch elements TR2, TR4 in accordance with the switching command Vsel-W, thereby setting the state of the gate resistance in each arm to either "small Rg" or "large Rg." Note that while FIG. 6 only shows the drive circuit 50 for the U-phase upper arm, the same applies to the U-phase lower arm and the upper and lower arms of the V and W phases.

[0072] In the drive circuit 50 for each arm of each phase, the switching state monitor 54 outputs a monitor signal that changes depending on the switching state of the switch elements TR2, TR4, as described in the first embodiment. In this embodiment, the monitor signals output from the switching state monitor 54 for each arm of each phase are input to an XOR circuit 80. Specifically, the OFF-side monitor signal VmonUP_OFF ​​and the ON-side monitor signal VmonUP_ON output from the switching state monitor 54 for the U-phase upper arm, the OFF-side monitor signal VmonUN_OFF and the ON-side monitor signal VmonUN_ON output from the switching state monitor 54 for the U-phase lower arm, the OFF-side monitor signal VmonVP_OFF ​​and the ON-side monitor signal VmonVP_ON output from the switching state monitor 54 for the V-phase upper arm, and the ON-side monitor signal VmonVP_ON output from the switching state monitor 54 for the V-phase lower arm are input to an XOR circuit 80. The OFF-side monitor signal VmonVN_OFF and the ON-side monitor signal VmonVN_ON output from the switching state monitor section 54 of the W-phase upper arm, the OFF-side monitor signal VmonWP_OFF ​​and the ON-side monitor signal VmonWP_ON output from the switching state monitor section 54 of the W-phase upper arm, and the OFF-side monitor signal VmonWN_OFF and the ON-side monitor signal VmonWN_ON output from the switching state monitor section 54 of the W-phase lower arm are each input to an XOR circuit 80.

[0073] The XOR circuit 80 performs an exclusive OR operation on the OFF-side and ON-side NOT values ​​of the input monitor signals for each phase and each arm, and outputs the results to the controller 100a. Specifically, the XOR circuit 80 outputs the exclusive OR of the OFF-side monitor signals VmonUP_OFF, VmonUN_OFF of the U-phase upper and lower arms and the NOT value of the ON-side monitor signals VmonUP_ON, VmonUN_ON as the U-phase monitor signal Vmon-U. Also, the XOR circuit 80 outputs the exclusive OR of the OFF-side monitor signals VmonVP_OFF, VmonVN_OFF of the V-phase upper and lower arms and the NOT value of the ON-side monitor signals VmonVP_ON, VmonVN_ON as the V-phase monitor signal Vmon-V. Similarly, the exclusive OR of the OFF-side monitor signals VmonWP_OFF, VmonWN_OFF of the W-phase upper and lower arms and the NOT value of the ON-side monitor signals VmonWP_ON, VmonWN_ON is output as the W-phase monitor signal Vmon-W.

[0074] In the controller 100 a, the switching speed changeover diagnostic unit 33 diagnoses the switching speed changeover unit 53 using the monitor signals Vmon-U, Vmon-V, and Vmon-W of each phase input from the XOR circuit 80 .

[0075] FIG. 7 is a table summarizing the contents of the diagnostic processing according to the second embodiment of the present invention. As shown in Table 340 in FIG. 7 , the switching speed switching diagnostic unit 33 diagnoses the state of the switching speed switching unit 53 for each phase based on the monitor signals Vmon-U, Vmon-V, and Vmon-W for each phase when the switching commands Vsel-U, Vsel-V, and Vsel-W for each phase are at L level (large Rg) and H level (small Rg). Note that FIG. 7 summarizes the contents of these diagnostic processing for each of the U, V, and W phases in Table 340. That is, in Table 340, "Vsel-x" commonly represents the switching commands Vsel-U, Vsel-V, and Vsel-W for each phase, and "Vmon-x" commonly represents the monitor signals Vmon-U, Vmon-V, and Vmon-W for each phase. The diagnostic process of this embodiment will be described below using these common switching commands Vsel-x and monitor signals Vmon-x.

[0076] In table 340, row 341 represents a case where the monitor signal Vmon-x is at the L level when the switching command Vsel-x is at the L level (Rg is large). In this case, it can be determined that the switching speed switching units 53 of the upper and lower arms of the corresponding phase are in a normal state.

[0077] In table 340, row 342 represents a case where monitor signal Vmon-x is at the H level when switching command Vsel-x is at the L level (large Rg). In this case, it can be determined that the switching speed switching unit 53 for the upper arm or lower arm of the corresponding phase is in an abnormal state in which the turn-off side or turn-on side is stuck at "small Rg," i.e., the switch element TR2 on the turn-off gate resistor Roff2 side or the switch element TR4 on the turn-on gate resistor Ron2 side is stuck on. In this case, as in the first embodiment, it is preferable to perform a limp-home process, such as reducing the output current of the inverter circuit 300, to avoid failure of power transistor TP1.

[0078] In table 340, row 343 represents a case where the monitor signal Vmon-x is at level L when the switching command Vsel-x is at level H (small Rg). In this case, it can be determined that the switching speed switching units 53 for the upper and lower arms of the corresponding phase are in a normal state.

[0079] In table 340, row 344 represents a case where monitor signal Vmon-x is at the H level when switching command Vsel-x is at the H level (small Rg). In this case, it can be determined that the switching speed switching unit 53 for the upper arm or lower arm of the corresponding phase is in an abnormal state in which the turn-off side or turn-on side is stuck at "large Rg," that is, the switch element TR2 on the turn-off gate resistor Roff2 side or the switch element TR4 on the turn-on gate resistor Ron2 side is stuck off. In this case, as in the first embodiment, it is preferable to continue operation of the power conversion device 200 while outputting an alarm in response to the diagnosis result.

[0080] As described above, according to the second embodiment of the present invention, similarly to the first embodiment, the switching speed switching unit 53 can be diagnosed at any timing regardless of the switching state of the power transistor TP1, and therefore it is possible to improve the reliability of the power conversion device 200.

[0081] According to the second embodiment of the present invention described above, the gate drive circuit 100 includes a switching circuit (switch elements TR2, TR4) and monitor resistors 75, 76 for the power transistor TP1 provided corresponding to each arm of each phase (U phase, V phase, W phase) of the three-phase AC power generated by the inverter circuit 300. The switching speed switching diagnostic unit 33 acquires the potentials between the switch elements TR2, TR4 and the monitor resistors 75, 76 for the power transistor TP1 of each arm of each phase, and diagnoses the switch elements TR2, TR4 for each phase based on the acquired potentials. As a result, for each phase of the three-phase AC power, similar to the first embodiment, diagnosis of the switch elements TR2, TR4, which are switching circuits that switch the connection state between the gate power supply and the gate terminal to apply a gate signal to the gate terminal of the power transistor TP1, can be performed at any timing regardless of the state of the power transistor TP1.

[0082] Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIGS. 8, 9 and 10. FIG.

[0083] 8 is a circuit block diagram showing the configuration of a gate drive circuit 100 according to a third embodiment of the present invention. The circuit block diagram of Fig. 8 differs from the circuit block diagram of Fig. 6 described in the second embodiment in that the switching speed selector 32 outputs a common switching command Vsel-UVW to the drive circuits 50 of each phase and each arm, and that the XOR circuit 80 outputs a monitor signal Vmon(XOR) for all phases to the controller 100a.

[0084] In this embodiment, the switching speed selection unit 32 acquires the effective current value of the current Io, and based on this effective current value, sets the target switching speed of the power transistor TP1 corresponding to each arm of each phase to either "low speed" or "high speed." Then, a switching command Vsel-UVW common to all phases is output. In the drive circuit 50 for each arm of each phase, the switching speed switching unit 53 turns on or off the switch elements TR2, TR4 in accordance with the switching command Vsel-UVW, thereby setting the state of the gate resistance to either "small Rg" or "large Rg."

[0085] As described above, in this embodiment, the state of the gate resistance of each arm of each phase is switched to either "Rg small" or "Rg large" based on the effective current value of the current Io using the switching command Vsel-UVW common to all phases. Therefore, the switching speed switching diagnostic unit 33 can perform the same diagnostic processing as described in the second embodiment using the monitor signal Vmon(XOR) of all phases output from the XOR circuit 80.

[0086] A specific example of the diagnosis of the switching speed changeover unit 53 performed by the switching speed changeover diagnosis unit 33 of this embodiment will be described using the timing chart of FIG.

[0087] 9 is a diagram showing an example of a timing chart when the switching speed switching unit 53 is normal in the gate drive circuit 100 according to the third embodiment of the present invention. From top to bottom, Fig. 9 shows the instantaneous value and effective value of the current Io of any phase measured by the current sensor 20, the switching command Vsel-UVW, the gate-source voltage Vgs of the switch elements TR2 and TR4, the drain-source voltage Vds of the switch element TR2, the OFF-side monitor signal Vmon_OFF, the drain-source voltage Vds of the switch element TR4, and the changes over time of the ON-side monitor signal Vmon_ON.

[0088] First, at time t10, because the effective value of the current Io is smaller than the current threshold value Igc, the switching speed selection unit 32 sets the target switching speed of the power transistor TP1 of each phase and arm to "high speed," and outputs an H-level switching command Vsel-UVW. At this time, in the drive circuit 50 of each phase and arm, the gate-source voltages Vgs of the switch elements TR2 and TR4 are at an H level, so the switch elements TR2 and TR4 are each switched on, and the state of the switching speed switching unit 53 is set to "low Rg." Therefore, as described in the first embodiment, the drain-source voltage Vds of the switch element TR2 and the OFF-side monitor signal Vmon_OFF are both at an L level, while the drain-source voltage Vds of the switch element TR4 and the ON-side monitor signal Vmon_ON are both at an H level.

[0089] When the effective value of the current Io exceeds the current threshold Igc at time t11, the switching speed selection unit 32 switches the target switching speed of the power transistor TP1 of each phase and arm from "high speed" to "low speed" and changes the switching command Vsel-UVW from H level to L level. As a result, in the drive circuit 50 of each phase and arm, the gate-source voltages Vgs of the switch elements TR2 and TR4 change from H level to L level, and the switch elements TR2 and TR4 are switched from ON to OFF, and the state of the switching speed switching unit 53 changes from "small Rg" to "large Rg." As a result, the drain-source voltage Vds of the switch element TR2 and the OFF-side monitor signal Vmon_OFF change from L level to H level, while the drain-source voltage Vds of the switch element TR4 and the ON-side monitor signal Vmon_ON change from H level to L level.

[0090] The XOR circuit 80 performs an exclusive OR operation on the NOT value of the OFF-side monitor signal Vmon_OFF and the ON-side monitor signal Vmon_ON output from the switching state monitor units 54 of each phase and each arm, and outputs the result as the monitor signal Vmon(XOR) for all phases. Therefore, if all switching speed changeover units 53 are normal, an L-level monitor signal Vmon(XOR) is output at both times t10 and t11.

[0091] Similarly, at times other than times t10 and t11, if all switching speed switching units 53 are normal, the XOR circuit 80 outputs an L-level monitor signal Vmon(XOR). On the other hand, if the switching speed switching unit 53 of the upper arm or lower arm in any phase is abnormal, the XOR circuit 80 outputs an H-level monitor signal Vmon(XOR).

[0092] The switching speed switching diagnostic unit 33 of this embodiment can collectively diagnose whether the operation of the switching speed switching units 53 for each phase is normal or abnormal, based on the monitor signal Vmon(XOR) output from the XOR circuit 80 as described above. That is, if the monitor signal Vmon(XOR) is at L level, the switching speed switching units 53 of the upper and lower arms in all phases are diagnosed as normal, and if the monitor signal Vmon(XOR) is at H level, the switching speed switching unit 53 of the upper or lower arm in any phase is diagnosed as abnormal. Therefore, the switching speed switching unit 53 can be diagnosed at any timing, regardless of the switching state of the power transistor TP1.

[0093] Fig. 10 is a table summarizing the contents of the diagnostic processing according to the third embodiment of the present invention. As shown in table 350 in Fig. 10, switching speed switching diagnostic unit 33 collectively diagnoses the state of switching speed switching unit 53 for each phase using monitor signal Vmon (XOR) when switching command Vsel-UVW is at L level (large Rg) and when it is at H level (small Rg).

[0094] In table 350, row 351 represents a case where monitor signal Vmon (XOR) is at level L when switching command Vsel-UVW is at level L (Rg large). In this case, it can be determined that switching speed changeover units 53 of the upper and lower arms are all in a normal state for all phases.

[0095] In table 350, row 352 represents a case where the monitor signal Vmon(XOR) is at a high level when the switching command Vsel-UVW is at a low level (large Rg). In this case, it can be determined that the upper arm or lower arm switching speed switching unit 53 of either phase is in an abnormal state in which the turn-off side or the turn-on side is stuck at "small Rg," i.e., the switch element TR2 on the turn-off gate resistor Roff2 side or the switch element TR4 on the turn-on gate resistor Ron2 side is stuck on. In this case, as in the first and second embodiments, it is preferable to perform a limp-home process, such as reducing the output current of the inverter circuit 300, to avoid a failure of the power transistor TP1.

[0096] In table 350, row 353 represents a case where monitor signal Vmon (XOR) is at level L when switching command Vsel-UVW is at level H (small Rg). In this case, it can be determined that switching speed changeover units 53 of the upper and lower arms are all in a normal state for all phases.

[0097] In table 350, row 354 represents a case where monitor signal Vmon(XOR) is at the H level when switching command Vsel-UVW is at the H level (small Rg). In this case, it can be determined that the upper arm or lower arm switching speed switching unit 53 of either phase is in an abnormal state in which the turn-off side or the turn-on side is stuck at "large Rg," i.e., the switch element TR2 on the turn-off gate resistor Roff2 side or the switch element TR4 on the turn-on gate resistor Ron2 side is stuck off. In this case, as in the first and second embodiments, it is preferable to continue operation of power conversion device 200 while outputting an alarm in response to the diagnosis result.

[0098] According to the third embodiment of the present invention described above, the gate drive circuit 100 includes a switching circuit (switch elements TR2, TR4) and monitor resistors 75, 76 for the power transistor TP1 provided corresponding to each arm of each phase (U phase, V phase, W phase) of the three-phase AC power generated by the inverter circuit 300. The switching speed switching diagnostic unit 33 acquires the potentials between the switch elements TR2, TR4 and the monitor resistors 75, 76 for the power transistor TP1 of each arm of each phase, and diagnoses the switch elements TR2, TR4 of each phase collectively based on the acquired potentials. In this manner, it is possible to perform the same diagnosis as in the first and second embodiments collectively for all phases of the three-phase AC power.

[0099] Fourth Embodiment Next, a fourth embodiment of the present invention will be described with reference to FIG.

[0100] Fig. 11 is a circuit block diagram showing the configuration of a gate drive circuit 100 according to a fourth embodiment of the present invention. The circuit block diagram of Fig. 11 differs from the circuit block diagram of Fig. 2 described in the first embodiment in that low-pass filters 44 and 45 are provided between the isolation elements 42 and 43 and the controller 100a, respectively.

[0101] The low-pass filter 44 removes noise superimposed on the potential between the monitoring resistor 75 and the switching element TR2, which is output from the switching state monitor unit 54 via the insulating element 42, and outputs the noise-removed potential as the OFF-side monitor signal Vmon_OFF. The low-pass filter 45 removes noise superimposed on the potential between the monitoring resistor 76 and the switching element TR4, which is output from the switching state monitor unit 54 via the insulating element 43, and outputs the noise-removed potential as the ON-side monitor signal Vmon_ON. The OFF-side monitor signal Vmon_OFF and the ON-side monitor signal Vmon_ON output from the low-pass filters 44 and 45, respectively, are input to the controller 100a and used by the switching speed switching diagnostic unit 33 for diagnosing the switching speed switching unit 53.

[0102] According to the fourth embodiment of the present invention described above, the gate drive circuit 100 includes low-pass filters 44, 45 that remove noise superimposed on the potential between the switch elements TR2, TR4 and the monitor resistors 75, 76. The switching speed switching diagnosis unit 33 acquires the potential from which noise has been removed by the low-pass filters 44, 45 as the OFF-side monitor signal Vmon_OFF and the ON-side monitor signal Vmon_ON. This allows the switching speed switching diagnosis unit 33 to accurately diagnose the switching speed switching unit 53 even when noise is superimposed on the potential between the switch elements TR2, TR4 and the monitor resistors 75, 76, which is output from the switching state monitor unit 54.

[0103] In the above-described embodiments, examples have been described in which the switch elements TR2 and TR4 in the switching speed switching unit 53 are diagnosed. However, as a modification of the present invention, the buffer transistors TR1 and TR3 may be diagnosed by applying a similar circuit configuration to the buffer transistors TR1 and TR3 in the gate signal generating unit 52. That is, the gate drive circuit 100 includes a gate signal generating unit 52 connected between the high-potential side (VCC side) and the low-potential side (GND2 side) of a gate power supply to generate a gate signal. The gate signal generating unit 52 includes a turn-on gate resistor Ron1 connected to the high-potential side of the gate power supply, a turn-off gate resistor Roff1 connected to the low-potential side of the gate power supply, a turn-on buffer element (buffer transistor TR3) that establishes or breaks electrical connection between the turn-on gate resistor Ron1 and the gate terminal, and a turn-off buffer element (buffer transistor TR1) that establishes or breaks electrical connection between the turn-off gate resistor Roff1 and the gate terminal. In a modified example, the switching circuit can be diagnosed by targeting the turn-on buffer transistor TR3 and / or the turn-off buffer transistor TR1 as the diagnostic target. In this way, the diagnosis of the buffer transistors TR1 and TR3 used to generate the gate signal can be performed at any timing regardless of the state of the power transistor TP1.

[0104] It is also possible to generate gate signals by using the switch elements TR2 and TR4 instead of the buffer transistors TR1 and TR3. In this case, the switch elements TR2 and TR4 can be diagnosed in the same manner as described in each embodiment.

[0105] Furthermore, in the above-described modified example, when the turn-on buffer transistor TR3 and / or the turn-off buffer transistor TR1 are diagnosed as abnormal, the switch elements TR2 and TR4 may be used instead of the buffer transistors TR1 and TR3 to generate gate signals. That is, when the buffer transistor TR1 is diagnosed as being in a stuck-on state, the switch element TR2 is switched instead of the buffer transistor TR1 to make or break the electrical connection between the gate terminal of the power transistor TP1 and the low-potential side (GND2 side) of the gate power supply via the turn-off gate resistor Roff2, thereby driving the power transistor TP1. Also, when the buffer transistor TR3 is diagnosed as being in a stuck-on state, the switch element TR4 is switched instead of the buffer transistor TR3 to make or break the electrical connection between the gate terminal of the power transistor TP1 and the high-potential side (VCC side) of the gate power supply via the turn-on gate resistor Ron2, thereby driving the power transistor TP1. In this way, it is possible to continue driving the power transistor TP1 even when an abnormality occurs in the buffer transistors TR1 and TR3.

[0106] Furthermore, in each of the above-described embodiments and modifications, the case where the switching speed switching unit 53 and the switching state monitoring unit 54 are provided on both the turn-off side and the turn-on side of the power transistor TP1 has been described. However, the switching speed switching unit 53 and the switching state monitoring unit 54 may be provided on only one of the turn-off side and the turn-on side to diagnose the switch elements TR2, TR4 and the buffer transistors TR1, TR3.

[0107] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and are not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. Furthermore, the above-described configurations, functions, processing units, processing means, etc. may be implemented in hardware, in part or in whole, by, for example, designing them as integrated circuits. Furthermore, the above-described configurations, functions, etc. may be implemented in software, by a processor interpreting and executing a program that realizes each function. Information such as programs, tables, and files that realize each function may be stored in a memory, a recording device such as a hard disk or SSD (Solid State Drive), or a recording medium such as an IC card, SD card, or DVD.

[0108] The present invention is not limited to the above-described embodiment, and various modifications are possible without departing from the spirit of the present invention.

[0109] 10: voltage sensor, 20: current sensor, 31: drive signal generation unit, 32: switching speed selection unit, 33: switching speed switching diagnosis unit, 40, 41, 42, 43: insulation elements, 44, 45: low-pass filters, 50: drive circuit, 51: gate signal control unit, 52: gate signal generation unit, 53: switching speed switching unit, 54: switching state monitor unit, 75, 76: monitoring resistors, 80: XOR circuit, 100a: controller, 100b: driver, 200: power conversion device, 300: inverter circuit, 500: voltage smoothing capacitor, 900: motor, 901: high-voltage battery, TP1: power transistor, DP1: freewheel diode, Ron1, Ron2: turn-on gate resistors, Roff1, Roff2: turn-off gate resistors, TR1, TR3: buffer transistors, TR2, TR4: switch elements, D2, D4: diodes

Claims

1. A gate drive circuit connected to an inverter circuit having a plurality of power semiconductor devices, and driving the power semiconductor devices by applying a gate signal generated using a first voltage supplied from a gate power supply to a gate terminal of the power semiconductor devices, the gate drive circuit comprising: a gate resistor connected between the gate power supply and the gate terminal; a switching circuit connected in series with the gate resistor between the gate power supply and the gate terminal, the switching circuit switching a connection state between the gate power supply and the gate terminal via the gate resistor; a monitoring resistor having one end connected between the switching circuit and the gate resistor and the other end connected to a monitoring power supply supplying a second voltage; a diode connected between the switching circuit and the gate terminal; and a diagnosis unit that acquires a potential between the switching circuit and the monitoring resistor and diagnoses the switching circuit based on the potential.

2. The gate drive circuit according to claim 1, further comprising a switching speed switching unit that switches a switching speed of the power semiconductor device according to the gate signal, the switching speed switching unit including: a first gate resistor connected between the gate power supply and the gate terminal; a second gate resistor connected in parallel with the first gate resistor; and a switch element that conducts or cuts off an electrical connection between the second gate resistor and the gate power supply, and the diagnosis unit diagnoses the switching circuit with the switch element as a diagnosis target.

3. The gate drive circuit according to claim 2, wherein when the diagnosis unit diagnoses that the switch element is abnormal, the power semiconductor device is driven with the electrical connection between the second gate resistor and the gate power supply by the switch element fixed to either conduction or cutoff.

4. The gate drive circuit according to claim 1, comprising a gate signal generation unit connected between the high potential side and the low potential side of the gate power supply to generate the gate signal, wherein the gate signal generation unit includes a turn-on gate resistor connected to the high potential side of the gate power supply, a turn-off gate resistor connected to the low potential side of the gate power supply, a turn-on buffer element for conducting or interrupting the electrical connection between the turn-on gate resistor and the gate terminal, and a turn-off buffer element for conducting or interrupting the electrical connection between the turn-off gate resistor and the gate terminal, and the diagnosis unit diagnoses the switching circuit with the turn-on buffer element and / or the turn-off buffer element as the diagnosis target.

5. The gate drive circuit according to claim 4, comprising a switching speed switching unit for switching the switching speed of the power semiconductor element according to the gate signal, wherein the switching speed switching unit includes a first gate resistor connected between the gate power supply and the gate terminal, a second gate resistor connected in parallel with the first gate resistor, and a switch element for conducting or interrupting the electrical connection between the second gate resistor and the gate power supply, and when the turn-on buffer element and / or the turn-off buffer element is diagnosed as abnormal by the diagnosis unit, the switch element is used instead of the element to conduct or interrupt the electrical connection between the gate terminal and the gate power supply through the second gate resistor, thereby generating the gate signal.

6. The gate drive circuit according to claim 1, having a filter for removing noise superimposed on the potential, and the diagnosis unit acquires the potential from which the noise has been removed by the filter.

7. The gate drive circuit according to claim 1, wherein the gate drive circuit includes the switching circuit and the monitoring resistor for each arm of each phase of the three-phase AC power generated by the inverter circuit, respectively, for the power semiconductor element provided corresponding to each arm of each phase of the three-phase AC power generated by the inverter circuit, and the diagnosis unit acquires the potential between the switching circuit and the monitoring resistor for each power semiconductor element of each arm of each phase, and diagnoses the switching circuit for each phase based on the acquired potential.

8. The gate drive circuit according to claim 1, wherein the gate drive circuit includes the switching circuit and the monitoring resistor for each arm of each phase of the three-phase AC power generated by the inverter circuit, respectively, for the power semiconductor element provided corresponding to each arm of each phase of the three-phase AC power generated by the inverter circuit, and the diagnosis unit acquires the potential between the switching circuit and the monitoring resistor for each power semiconductor element of each arm of each phase, and collectively diagnoses the switching circuits of each phase based on the acquired potential.

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