Semiconductor device manufacturing method, semiconductor device manufacturing management system, semi-finished semiconductor substrate, and semiconductor substrate

Abstract

Provided is a method for manufacturing a semiconductor integrated circuit, the method enabling shortening of the product development period for high-mix, low-volume production. In this semiconductor device manufacturing method, a plurality of functional circuit formation fabs cooperate with a back-end wiring step fab. The plurality of functional circuit formation fabs are responsible for a front-end wiring step in which functional circuit blocks corresponding to individual functions are independently formed as part of a front-end step, and performs stocking in a wafer bank. The functional circuit blocks corresponding to the individual functions for achieving desired overall functionality are formed in accordance with instructions of a designer who designs a back-end wiring step, and a stocked wafer is selected. The back-end wiring step fab forms a wiring pattern on the selected wafer for connecting a plurality of circuit blocks to achieve the overall functionality.

Description

Semiconductor device manufacturing method, semiconductor device manufacturing management system, semi-finished semiconductor substrate, and semiconductor substrate

[0001] The present invention relates to a method for manufacturing a semiconductor device for forming a semiconductor integrated circuit on a semiconductor substrate, a semiconductor device manufacturing management system, a semi-finished semiconductor substrate, and a semiconductor substrate.

[0002] (Development trends of semiconductor integrated circuits)

[0003] In semiconductor integrated circuits formed on semiconductor substrates typified by silicon (Si) semiconductors, performance has been improved by increasing the number of active devices such as transistors formed on one chip, in other words, by increasing the degree of integration.

[0004] Since the development and practical application of large-scale semiconductor integrated circuits (LSIs), Moore's Law has been used as an empirical rule of thumb to predict the long-term trends in their manufacturing and production. Initially, Moore's Law stated that the number of transistors on an integrated circuit will double every two years. While Moore's Law has generally maintained its trend over the long term due to improvements in the transistor structure of semiconductor integrated circuits and advances in microfabrication technology, its limitations have been pointed out in recent years.

[0005] For example, taking a typical transistor structure, CMOS (Complementary Metal-Oxide-Semiconductor) transistor, one of the challenges in miniaturization is suppressing short channel effects when P-channel FET transistors and N-channel FET transistors are configured planarly on a silicon substrate. Therefore, developments have been made to change the FET (Field Effect Transistor) from a planar (flat) type FET to a FinFET, which improves performance by changing the shape of the silicon substrate from a flat type to a fin (fish fin) type, as well as a Gate-All-Around type nanosheet structure in which the gate surrounds the entire periphery of the channel.

[0006] As a result, the most advanced process currently being developed and put into practical use for logic ICs in semiconductor integrated circuits has become an ultra-fine technology, sometimes called the "2 nm process."

[0007] However, the applications of semiconductor integrated circuits are not limited to chips for processing artificial intelligence calculations, which require such cutting-edge processes, but are actually widespread, including those that require semiconductor integrated circuits manufactured using processes based on earlier miniaturization technology.

[0008] Furthermore, the wiring width / wiring spacing pitch formed using cutting-edge EUV (Extreme Ultraviolet Lithography) lithography is approximately 20-30 nm, and the term "2 nm process" is a symbolic name used due to so-called "area scaling" rather than referring to the planar wiring processing dimensions as transistor structures become three-dimensional. In reality, integrated circuits with looser processing accuracy depending on the transistor structure, such as those called "22-28 nm process," are currently widely used for automotive control applications and as "logic processing LSIs" mounted on the back of image sensors.

[0009] Meanwhile, in the past, semiconductor integrated circuit manufacturing was vertically integrated, with a single company handling everything from design to circuit formation on semiconductor substrates (semiconductor wafers), cutting chips from the semiconductor wafers, bonding, and packaging. However, nowadays, semiconductor integrated circuits are generally manufactured through horizontal division of labor, with fabless companies in charge of design, foundry companies (hereinafter simply referred to as "fabs") in charge of wafer processing, and assembly companies in charge of assembly.

[0010] FIG. 35 is a conceptual diagram showing a conventional manufacturing process for a semiconductor device.

[0011] Referring to Figure 35, the front-end process is also called the wafer process, and is a process for manufacturing LSI chips on a silicon wafer. In contrast, the back-end process is an assembly process in which the LSI chips (also called "dies" in the back-end process) completed on the wafer are cut out individually and packaged. In the front-end process, the workpiece to be worked on is in the form of a silicon wafer, whereas in the back-end process, it may be a silicon wafer, a chip, or a packaged chip.

[0012] As shown in Figure 35, nowadays, it is more common for front-end and back-end processes to be performed in separate fabs. In the front-end process, the front-end process mainly refers to the process up to transistor formation, while the back-end process refers to the wiring process thereafter. (ASIC and cell-based design)

[0013] In particular, as mentioned above, unlike general-purpose semiconductor integrated circuits, application-specific integrated circuits often do not necessarily need to be manufactured using cutting-edge processes. Here, application-specific integrated circuits are generally called ASICs (application specific integrated circuits), and refer to integrated circuits that combine multiple circuits with different functions for a specific application.

[0014] ASICs can be broadly divided into "full-custom ICs," in which logic circuits are built from scratch, and "semi-custom ICs," in which designs are made by combining basic circuits and functional blocks. Naturally, full-custom ICs require a longer development period and higher development costs.

[0015] On the other hand, semi-custom ICs that aim to mitigate these disadvantages include the "gate array" method, in which a semi-finished product filled with basic logic circuits is prepared and functions are implemented by specifying the wiring between the circuits, and the "standard cell" method, in which modularized circuits (cells) that implement a certain degree of functionality are combined.

[0016] A cell-based IC (Cell-based Integrated Circuit) designed using the "standard cell" method is configured as an integrated circuit that mixes large-scale circuit blocks (megacells or macrocells) based on standard cells (basic circuits), for example.

[0017] Conventionally, cell-based semi-custom design methods have been widely adopted for ASIC design, and this design method aims to improve the efficiency of IC design by combining common design assets (Intellectual Property: IP) registered in libraries and using automatic placement and routing tools.

[0018] Patent Document 1 discloses a semiconductor integrated circuit designed to include a plurality of basic cells each having a predetermined function and interconnected by internal wiring, a wiring region formed on a semiconductor substrate and having external wiring connecting the basic cells, power supply wiring and ground wiring for supplying power to the semiconductor elements, a first decoupling capacitor formed on the semiconductor substrate and consisting only of pMOS transistors, and a second decoupling capacitor formed on two metal layers on the semiconductor substrate. The decoupling capacitor cell, consisting of the first decoupling capacitor and the second decoupling capacitor, is arranged in an unused region not occupied by the basic cells, and is connected to the power supply wiring and ground wiring, thereby enabling the design of a cell-based IC that can reduce power consumption and ground noise.

[0019] Meanwhile, in response to the increasing sophistication and multi-functionality of functions to be realized by semiconductor integrated circuits, technologies are also being used in which a chip (die) produced in one semiconductor manufacturing factory and another chip (die) produced in another semiconductor manufacturing factory are assembled into a single package in a post-process. For example, known technologies include "2.5D packaging technology," which uses an interposer to arrange, connect, and mount multiple semiconductor chips in parallel, and "3D packaging technology," which mounts multiple semiconductor chips, including memories and microcontrollers, by stacking them in three dimensions within a package.

[0020] In this way, when semiconductor chips produced in different semiconductor manufacturing factories are combined and implemented, the designer designs the semiconductor device using two or more PDKs (Process Design Kits) provided by the foundries that manufacture each chip.

[0021] PDK is a collection of information necessary for designing custom ICs or analog ICs for a certain semiconductor process. Foundries that handle semiconductor front-end processes (including transistor manufacturing processes such as diffusion) often provide it to designers at fabless semiconductor manufacturers or IDMs (Integrated Device Manufacturers), who are users, for each process (see Non-Patent Document 1).

[0022] Custom ICs and analog ICs may require design on a transistor-by-transistor basis, and the PDK contains the necessary information for this, such as the circuit diagram symbols for the transistors in the process, the transistor SPICE (Simulation Program with Integrated Circuit Emphasis) model, transistor mask-level data (parameterized cell data such as PCELL and QCELL data), mask layout design constraints (so-called DRC (design rule checking) rules), and parasitic parameter extraction rules.

[0023] This information is used in IC design software called EDA (electronic design automation) tools. PDKs often also include design guidelines and design examples (reference designs).

[0024] In contrast to PDKs for custom IC and analog IC design, the information provided by foundries to digital LSI designers is often simply called a "design kit." This is also prepared for each process. The basis of a design kit is various design data (models for EDA tools) for the basic design elements of that process (standard cells and macrocells). Like PDKs, it often also includes design guidelines and design examples (reference designs).

[0025] Patent Document 2 discloses a PDK creation method and a PDK creation program that enable simultaneous design of all layers of a stacked IC. Specifically, the PDK creation method of Patent Document 2 includes acquiring multiple design information libraries corresponding to multiple chips used in a semiconductor device, assigning a different identifier to each character string included in the design information library, and integrating the multiple design information libraries. By assigning a different identifier to each character string included in the design information library, the names of simulation models and the like can be made different for each design information library. Therefore, multiple design information libraries are integrated while avoiding duplication of simulation model names and the like. It is then disclosed that by using the design information library thus created, it becomes possible to simultaneously design all layers of a stacked IC.

[0026] JP 2013-201158 A JP 2017-156877 A

[0027] https: / / xtech.nikkei.com / dm / article / WORD / 20130115 / 260353 /

[0028] As explained above, compared to standard logic ICs, standard memory ICs, programmable logic devices that rewrite circuit designs, and FPGAs, ASICs can offer advantages such as a smaller mounting area, lower power consumption, faster operating speed, and lower unit cost.

[0029] However, even if a semi-custom IC is designed using standard cell technology or the like, it is still necessary to complete the wafer process, test the device, and improve the design. This means that from the perspective of users such as fabless manufacturers, there are still problems of high development costs and long development times.

[0030] Furthermore, foundry companies are focusing on mass-producing a small variety of semiconductor chips using cutting-edge or semi-cutting-edge processes, which have high profit margins, and so tend to give lower priority to the manufacture of semiconductor integrated circuits, which have looser design standards. Moreover, as the diameter of semiconductor substrates (wafers) increases, it becomes necessary to order the manufacture of a considerable number of chips from foundries for each prototype. Repeating the process of prototyping and improvement increases TAT ​​(turn-around time), which is the time required to fully complete a product, and increases development costs.

[0031] On the other hand, for example, semiconductor integrated circuits that are premised on processing analog signals from sensors, such as those used in IoT (Internet of Things), often require high-mix, low-volume production.

[0032] As a result, there is a need for a design method and a manufacturing method of semiconductor integrated circuits that are suitable for small-lot production of a wide variety of products, rather than the product development of one-of-a-kind semiconductor products according to the conventional manufacturing model.

[0033] The present invention has been made to solve the above-mentioned problems, and aims to provide a semiconductor device manufacturing method, a semiconductor device manufacturing management system, a semi-finished semiconductor substrate, and a semiconductor substrate that can shorten product development time in high-mix, low-volume production.

[0034] (Item 1) According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, in which a multilayer wiring process for forming circuits corresponding to semiconductor devices manufactured as a plurality of chips on a semiconductor substrate is divided into a pre-wiring process and a post-wiring process, the pre-wiring process is carried out at a plurality of first semiconductor manufacturing sites, and the post-wiring process is carried out at at least one second semiconductor manufacturing site, the method comprising the steps of: forming a plurality of active elements in each of regions corresponding to the chips on the semiconductor substrate at the plurality of first semiconductor manufacturing sites; and then connecting the plurality of active elements by a first wiring pattern in the pre-wiring process to form a plurality of circuit blocks on the chip; the plurality of circuit blocks are each a plurality of individual functions that constitute the overall function of the semiconductor device. and a plurality of adjustment circuit blocks provided separately from the plurality of functional circuit blocks for tuning the performance achieved by the functional circuit blocks, respectively. The pre-wiring process includes a step of stocking a plurality of semiconductor substrates formed at a plurality of first semiconductor manufacturing sites as inventory, a step of selecting a semiconductor substrate formed with a plurality of circuit blocks capable of achieving the overall function from the plurality of stocked semiconductor substrates, and a step of forming a second wiring pattern on the selected semiconductor substrate at a second semiconductor manufacturing site for connecting the plurality of circuit blocks to achieve the overall function.

[0035] (Item 2) Preferably, in the configuration of Item 1, the process of forming a plurality of circuit blocks in the pre-wiring process includes a step of performing lithography for a first wiring pattern using a divided projection exposure method, and the process of forming a second wiring pattern in the post-wiring process includes a step of performing exposure for forming the second wiring pattern that connects the circuit blocks to the semiconductor substrate using a direct writing method.

[0036] (Item 3) Preferably, in the configuration of item 1 or 2, the division projection exposure method in the pre-wiring process has a first value of alignment accuracy between masks, and the dimensions of the connection portion of the first wiring pattern in the via hole for connecting the second wiring pattern in the pre-wiring process include an overlap margin with the second wiring pattern, and the overlap margin of the dimension of the connection portion is determined by the alignment accuracy of the direct writing method and is a second value greater than the first value.

[0037] (Item 4) Preferably, in the configuration of any one of Items 1 to 3, the step of forming the second wiring pattern includes a step of forming a different wiring pattern for chips among the plurality of chips that have common patterns for the functional circuit block and the adjustment circuit block.

[0038] (Item 5) Preferably, in the configuration of Item 4, the different wiring patterns are wiring patterns that connect a common functional circuit block to different adjustment circuit blocks in a first chip and a second chip included in a chip having a common pattern.

[0039] (Item 6) Preferably, in the configuration of any one of Items 1 to 5, the step of forming the second wiring pattern includes the steps of forming a photosensitive resin film on the semiconductor substrate, directly writing the second wiring pattern on the photosensitive resin film, developing the photosensitive resin film after the direct writing, and forming a wiring layer corresponding to the second wiring pattern on the developed photosensitive resin film.

[0040] (Item 7) According to another aspect of the present invention, in a manufacturing process in which a multilayer wiring process for forming circuits on a semiconductor substrate corresponding to semiconductor devices manufactured as a plurality of chips is divided into a pre-wiring process and a post-wiring process, the pre-wiring process is performed at a plurality of first semiconductor manufacturing sites, and the post-wiring process is performed at at least one second semiconductor manufacturing site, a manufacturing management system for managing a process of stocking semiconductor substrates after the pre-wiring process, the system comprising: a storage device for receiving and storing semiconductor substrate stock information for managing the plurality of semiconductor substrates when the plurality of first semiconductor manufacturing sites stock the plurality of semiconductor substrates, each having a plurality of circuit blocks formed in an area corresponding to a chip, in a storage area; and a storage device for receiving and storing semiconductor substrate stock information for managing the plurality of semiconductor substrates from the first semiconductor manufacturing site, the plurality of circuit blocks being a plurality of individual circuits that constitute the overall function of the semiconductor device. The semiconductor device includes a plurality of functional circuit blocks for realizing at least a portion of a function on a semiconductor substrate, and a plurality of adjustment circuit blocks provided separately from the plurality of functional circuit blocks for tuning the performance realized by the functional circuit blocks, each of the plurality of functional circuit blocks having a plurality of active elements and a first wiring pattern for connecting the plurality of active elements, and further includes a processing unit for performing management processing, wherein the processing unit selects, from the plurality of stocked semiconductor substrates based on semiconductor substrate stock information, a semiconductor substrate on which a plurality of circuit blocks capable of achieving the overall function are formed, and instructs the semiconductor substrate to be transported to a second semiconductor manufacturing site where a second wiring pattern for connecting the plurality of circuit blocks is formed on the selected semiconductor substrate to achieve the overall function.

[0041] (Item 8) According to yet another aspect of the present invention, a multilayer wiring process for forming circuits on a semiconductor substrate corresponding to semiconductor devices each manufactured as a plurality of chips is divided into a pre-wiring process and a post-wiring process, and a semi-finished semiconductor substrate is temporarily stored after the pre-wiring process is performed at a plurality of first semiconductor manufacturing locations and before being received at a second semiconductor manufacturing location where the post-wiring process is performed, the semi-finished semiconductor substrate comprising a plurality of circuit blocks generated in the pre-wiring process for performing predetermined functions on the semiconductor substrate, the plurality of circuit blocks including a plurality of functional circuit blocks for respectively realizing on the semiconductor substrate at least some of a plurality of individual functions that constitute the overall function of the semiconductor device, a plurality of adjustment circuit blocks provided separately from the plurality of functional circuit blocks for tuning the performance realized by the functional circuit blocks, and at least one layer of first wiring formed in the pre-wiring process within each circuit block, the first wiring having a wiring contact portion for forming a connection by a via hole to a second wiring formed in the post-wiring process.

[0042] (Item 9) Preferably, in the configuration of Item 8, the semi-finished semiconductor substrate includes a moisture-resistant protective film covering substantially the entire top surface, and the first wiring is formed immediately before the formation of the protective film, and has a top-layer wiring in which a wiring contact portion is formed.

[0043] (Item 10) Preferably, in the configuration of item 8 or item 9, the lithography in the pre-wiring process is performed using a divided projection exposure method, the alignment accuracy between masks is a first value, the dimensions of the wiring contact portion include an overlay margin with the post-process wiring, and the overlay margin of the dimensions of the wiring contact portion is determined by the alignment accuracy of the direct writing method used to perform the lithography in the post-wiring process and is a second value greater than the first value.

[0044] (Item 11) Preferably, in the configuration of any one of items 8 to 10, the dimension of the wiring contact portion is 2.5 times or more the minimum dimension of the wiring pattern of the uppermost layer wiring.

[0045] (Item 12) Preferably, in the configuration of any one of items 8 to 11, the protective film is a silicon nitride film.

[0046] (Item 13) According to yet another aspect of the present invention, there is provided a method for manufacturing a semi-finished semiconductor substrate, in which a multilayer wiring process for forming circuits on a semiconductor substrate corresponding to semiconductor devices each manufactured as a plurality of chips is divided into a pre-wiring process and a post-wiring process, and the pre-wiring process is carried out at a plurality of first semiconductor manufacturing sites, the method comprising the steps of: forming a plurality of active elements in each of regions corresponding to the chips on the semiconductor substrate at the plurality of first semiconductor manufacturing sites; and then connecting the plurality of active elements with a first wiring pattern in the pre-wiring process to form a plurality of circuit blocks on the chip, the plurality of circuit blocks including a plurality of functional circuit blocks for realizing at least a portion of a plurality of individual functions constituting the overall function of the semiconductor device on the semiconductor substrate, and a plurality of adjustment circuit blocks provided separately from the plurality of functional circuit blocks for tuning the performance realized by the functional circuit blocks, the first wiring pattern having wiring contact portions for forming connection to second wiring formed in the post-wiring process at the second semiconductor manufacturing site; and forming a protective film covering substantially the entire outermost surface of the semiconductor substrate on which the plurality of circuit blocks have been formed.

[0047] (Item 14) Preferably, in the configuration of Item 13, the step of forming a plurality of circuit blocks in the pre-wiring step includes a step of performing lithography for the first wiring pattern by a division projection exposure method;

[0048] (Item 15) According to yet another aspect of the present invention, there is provided a semi-finished semiconductor substrate on which circuits corresponding to semiconductor devices to be manufactured as a plurality of chips are formed, the semi-finished semiconductor substrate comprising a plurality of circuit blocks for executing predetermined functions on the semiconductor substrate, the plurality of circuit blocks including a plurality of functional circuit blocks for realizing, on the semiconductor substrate, each of a plurality of individual functions that constitute the overall function of the semiconductor device, each of the functional circuit blocks having at least one layer of first wiring formed to achieve the individual function, and further including a plurality of adjustment circuit blocks provided separately from the plurality of functional circuit blocks for tuning the performance realized by the functional circuit block, the first wiring having wiring contact portions for forming connection with second wiring formed in a process after the semi-finished semiconductor substrate is stored in a storage area, and further comprising a protective film covering substantially the entire outermost surface of the semiconductor substrate on which the plurality of circuit blocks are formed.

[0049] (Item 16) In the configuration of item 15, preferably, the dimension of the wiring contact portion is 2.5 times or more the minimum dimension of the wiring pattern of the uppermost layer of the first wiring.

[0050] (Item 17) Preferably, in the configuration of item 15 or 16, the protective film is a silicon nitride film.

[0051] According to yet another aspect of the present invention, a multilayer wiring process for forming circuits corresponding to semiconductor devices each manufactured as a plurality of chips on a semiconductor substrate is divided into a pre-wiring process and a post-wiring process, and after the pre-wiring process is performed at a plurality of first semiconductor manufacturing sites, the semiconductor substrate is temporarily stored, selected according to a design of the overall function of the semiconductor device, and completed through a post-wiring process at a second semiconductor manufacturing site, the semiconductor substrate comprising a plurality of circuit blocks generated in the pre-wiring process to realize predetermined functions on the semiconductor substrate, the plurality of circuit blocks including a plurality of functional circuit blocks for realizing at least a portion of a plurality of individual functions constituting the overall function of the semiconductor device on the semiconductor substrate, a plurality of adjustment circuit blocks provided separately from the plurality of functional circuit blocks and for tuning the performance realized by the functional circuit blocks, and at least one layer of first wiring pattern formed in the pre-wiring process within each circuit block, the first wiring having wiring contact portions for forming connection by via holes with second wiring formed in the post-wiring process, and a second wiring pattern for connecting the plurality of circuit blocks formed on the selected semiconductor substrate in the post-wiring process to achieve the overall function.

[0052] (Item 19) Preferably, in the configuration of Item 18, the lithography in the pre-wiring process is performed using a divided projection exposure method, the alignment accuracy between masks is a first value, the dimensions of the wiring contact portion include an overlay margin with the post-process wiring, and the overlay margin of the dimensions of the wiring contact portion is determined by the alignment accuracy of the direct writing method used to perform the lithography in the post-wiring process and is a second value greater than the first value.

[0053] (Item 20) Preferably, in the configuration of item 18 or item 19, a moisture-resistant protective film is formed in a pre-wiring process to cover substantially the entire surface of the semiconductor substrate, the first wiring has a top layer wiring formed immediately before the formation of the protective film, and the protective film has a plurality of through holes for electrical connection to the top layer wiring.

[0054] (Item 21) Preferably, in the configuration of any one of items 18 to 20, the dimension of the wiring contact portion is 2.5 times or more the minimum dimension of the wiring pattern of the uppermost layer wiring.

[0055] (Item 22) Preferably, in the configuration of any one of items 18 to 21, the protective film is a silicon nitride film.

[0056] (Item 23) Preferably, in the configuration of any one of Items 18 to 22, the interlayer insulating film in the post-wiring process is a photosensitive resin film, and lithography for pattern formation in the post-wiring process is performed by a direct writing method.

[0057] (Item 24) According to yet another aspect of the present invention, there is provided a semiconductor substrate on which circuits corresponding to semiconductor devices each manufactured as a plurality of chips are formed, the semiconductor substrate comprising a plurality of circuit blocks for executing predetermined functions, the plurality of circuit blocks including a plurality of functional circuit blocks for realizing on the semiconductor substrate, each of a plurality of individual functions constituting the overall function of the semiconductor device, each of the functional circuit blocks having at least one first wiring pattern formed to achieve the individual function, and further including a plurality of adjustment circuit blocks provided separately from the plurality of functional circuit blocks for tuning the performance realized by the functional circuit blocks, the first wiring pattern having wiring contact portions and further including a protective film layer formed in an upper layer of the plurality of circuit blocks, the protective film layer being a silicon nitride film having a plurality of through holes in each circuit block corresponding to the wiring contact portions, an interlayer insulating film made of a photosensitive organic resin formed on the protective film layer, and a second wiring pattern connecting the plurality of circuit blocks to the wiring contact portions of the plurality of circuit blocks via via holes opened in the interlayer insulating film corresponding to the through holes to achieve the overall function.

[0058] According to the present invention, it is possible to use a semiconductor device manufacturing method, a semiconductor device manufacturing management system, a semi-finished semiconductor substrate, and a semiconductor substrate that can shorten the product development period in high-mix, low-volume production.

[0059] FIG. 1 is a conceptual diagram showing an overview of a manufacturing flow of a semiconductor device according to a first embodiment; FIG. 2 is a diagram showing an example of a cross-sectional structure of a semiconductor device according to the manufacturing flow of the present embodiment; FIG. 3 is a conceptual diagram for explaining a manufacturing process of the semiconductor device shown in FIG. 2; FIG. 4 is a first diagram for explaining the manufacturing flow of a semiconductor device as a cross-sectional structure; FIG. 5 is a diagram for explaining the manufacturing flow of a semiconductor device as a cross-sectional structure; FIG. 6 is a diagram for explaining the manufacturing flow of a semiconductor device as a cross-sectional structure; FIG. 7 is a diagram for explaining the manufacturing flow of a semiconductor device as a cross-sectional structure; FIG. 8 is a diagram for explaining the manufacturing flow of a semiconductor device as a cross-sectional structure; FIG. 9 is a diagram for explaining the manufacturing flow of a semiconductor device as a cross-sectional structure; FIG. 10 is a diagram for explaining the manufacturing flow of a semiconductor device as a cross-sectional structure; FIG. 11 is a diagram for explaining the manufacturing flow of a semiconductor device as a cross-sectional structure; FIG. 12 is a diagram for explaining the manufacturing flow of a semiconductor device as a cross-sectional structure; FIG. 13 is a conceptual diagram for explaining a configuration of a design platform of a design support system according to the present embodiment. 1 is a conceptual diagram illustrating a portion of a server device that provides a design platform. FIG. 1 is a conceptual diagram illustrating an overview of the configuration of a function / fab relationship DB1500.2. FIG. 2 is a diagram illustrating the details of the configuration of a function / fab relationship DB1500.2. FIG. 3 is a diagram illustrating the details of the configuration of a function / fab relationship DB1500.2. FIG. 4 is a diagram illustrating the details of the configuration of a function / fab relationship DB1500.2. FIG. 5 is a diagram illustrating the configuration of a functional circuit design tool provision server 1000, a post-wiring design tool provision server 2000, and designer terminals 5000.1 to 5000.P. FIG. 6 is a functional block diagram illustrating the configuration of the functional circuit design tool provision server 1000. FIG. 7 is a functional block diagram illustrating the configuration of the post-wiring design tool provision server 2000. FIG. 8 is a block diagram illustrating the hardware configuration of the functional circuit design tool provision server 1000. FIG. 9 is a flowchart illustrating the operation of the functional circuit design tool provision server 1000.1 is a flowchart for explaining the operation of the functional circuit design tool providing server 1000. FIG. 2 is a flowchart for explaining the operation of the post-wiring design tool providing server 2000. FIG. 3 is a diagram for explaining a plurality of dies formed on a semiconductor substrate after a pre-wiring process. FIG. 4 is a diagram for explaining a plurality of dies formed on a semiconductor substrate after a post-wiring process. FIG. 5 is a diagram showing design rules for the top layer wiring in a wiring group in the pre-wiring process, and design rules for the contact part between the top layer wiring M1 and the wiring M2 formed in the post-wiring process. FIG. 6 is a conceptual diagram showing various modified examples of the pattern of the contact part between the top layer wiring and the wiring formed in the post-wiring process. FIG. 7 is a conceptual diagram showing a conventional semiconductor device manufacturing process.

[0060] The following describes a semiconductor device manufacturing method, a semiconductor device manufacturing management system, a semi-finished semiconductor substrate, and the configuration of the semiconductor substrate according to an embodiment of the present invention. Note that in the following embodiments, components and processing steps denoted by the same reference numerals are the same or equivalent, and unless necessary, their description will not be repeated.

[0061] In the following description, the software for the semiconductor integrated circuit manufacturing management system executed on a computer according to the present invention will be described as a computer program that is installed on a single computer device and that executes support for circuit design.

[0062] However, the processing of the design support system may be distributed among multiple computer devices, and the computer processing may be executed by a single or multiple arithmetic units. Furthermore, the processing of the design support system is not limited to a program installed on such a general-purpose computer device, and may generally be realized as a dedicated arithmetic processing device that combines an arithmetic unit and a storage device. (Definition of Terms)

[0063] The definitions of terms used in this specification are as follows:

[0064] 1) "Semiconductor wafer": A typical example is a wafer cut from a single crystal silicon (Si) ingot and shaped to a specified thickness and diameter. However, the type of semiconductor is not limited to silicon and may be other semiconductors. Furthermore, the wafer may be made of an insulator wafer as the base material, with a semiconductor layer grown on the surface of this insulator wafer by a specified crystal growth method.

[0065] 2) "Through hole": A general term for the part in a semiconductor device that provides electrical continuity between wiring layers such as gate wiring and metal wiring. Examples include contact holes that connect the silicon substrate to upper wiring, cell contacts that connect capacitor electrodes to the substrate or wiring, and via holes that connect metal wiring.

[0066] 3) "Front-end process": A process for forming multiple integrated circuit chips (dies) on a semiconductor wafer, each chip consisting of multiple active elements (e.g., transistors) that achieve the overall function of the target semiconductor device. 4) "First semiconductor manufacturing site" and "second semiconductor manufacturing site": A "first semiconductor manufacturing site" is a site where the "front-end process" and "front-end wiring process" described below are performed in the wafer process for manufacturing the target semiconductor device. A "second semiconductor manufacturing site" is a site where the "back-end wiring process" described below is performed in the wafer process for manufacturing the target semiconductor device. The "first semiconductor manufacturing site" and the "second semiconductor manufacturing site" may be separate plants, such as a "first semiconductor factory" and a "second semiconductor factory," respectively. Alternatively, at least one of multiple "first semiconductor manufacturing sites" and the "second semiconductor manufacturing site" may be located in different areas (e.g., different buildings) within the same plant. However, as will be described later, the "semi-finished wafers" manufactured at the "first semiconductor manufacturing site" are temporarily stocked as inventory in a "wafer bank," and then, in accordance with a selection by a circuit designer in a post-wiring process, selected wafers are sent to the manufacturing process at the "second semiconductor manufacturing site." Also, the "first semiconductor manufacturing site" and the "second semiconductor manufacturing site" may each adopt different design rules and use different wiring formation process technologies.

[0067] 5) "Pre-wiring process": This pre-wiring process includes, within the first semiconductor manufacturing site, a process of forming active elements (e.g., transistors) on a semiconductor wafer (front-end process) and a process of electrically connecting multiple transistors using a wiring layer via contact holes opened in an insulating layer formed on the transistors (the first half of the back-end process). It includes at least a wiring process via cell contacts and may also include a metal wiring process via via holes. In the pre-wiring process, multiple semiconductor circuits of multiple types are formed on a semiconductor substrate, each corresponding to a separate function as an electrical circuit and including a functional circuit and an adjustment circuit.

[0068] 6) "Front-end process": A process in which active elements (e.g., transistors) are formed on a semiconductor wafer in a pre-processing step, and includes up to the metal filling step if metal filling (e.g., formation of W plugs) is performed in the contact holes of the transistor.

[0069] 7) "Back-end process": This refers to a process in the pre-processing stage in which multilayer wiring is formed after the front-end process. In silicon semiconductor processes, aluminum wiring (including alloys primarily made of Al) is often used for the lower layer wiring of multilayer wiring, while copper wiring is often used for the upper layer wiring. Furthermore, the so-called "dual damascene process" is often used for copper wiring. Note that all of the wiring layers in the back-end process may be aluminum wiring. Alternatively, all of the wiring layers in the back-end process may be copper wiring formed by the dual damascene process. However, the process for forming multilayer wiring is not limited to these examples.

[0070] 8) "Functional circuit": A plurality of circuits for realizing, on a semiconductor substrate, each of the plurality of individual functions that constitute the overall function of the semiconductor device to be manufactured.

[0071] 9) "Adjustment circuit": A plurality of circuits provided on a semiconductor substrate separately from a plurality of functional circuit blocks, for tuning the performance realized by each of the functional circuit blocks.

[0072] 10) "Post-wiring process": This refers to the process of forming wiring that connects functional circuits and adjustment circuits formed on a semiconductor chip at a second semiconductor manufacturing site different from the first semiconductor manufacturing site after the process of manufacturing transistors on a semiconductor wafer (front-end process) and the pre-wiring process are completed within a first semiconductor manufacturing site as the latter half of the back-end process among the pre-wiring processes. Although not particularly limited, the post-wiring process can be configured to include a process of forming an interlayer insulating film by direct imaging technology using a photosensitive organic insulating film and a process of forming copper wiring using dual damascene technology, which are performed as many times as necessary.

[0073] 11) "Back-end process": This includes the process in a back-end foundry where semiconductor chips (dies) are cut from wafers on which semiconductor circuits have been formed in the front-end process (front-end process + front-end wiring process + back-end wiring process), followed by bonding and assembly into packages and pre-shipment inspection. It may also include the process of forming plating wiring on the bonding pads formed in the front-end process as a base for bump formation to create a flip-chip configuration or a stacked structure. In other words, in the back-end process, a stacked structure chip connected to wafers may be formed by wafer-based flip-chip connection. The process of forming this plating wiring may also be included in the front-end process.

[0074] 12) "Design rule": In this specification, this refers to the minimum design width of wiring in a wafer process.

[0075] 13) "Semi-finished wafer": A semiconductor substrate (wafer) that is temporarily removed from the first semiconductor manufacturing site after the pre-wiring process is completed and stored in a designated storage area. Therefore, within the chip formed on the semiconductor substrate, multiple functional circuits and at least one adjustment circuit are formed through the front-end process and pre-wiring process. Preferably, a protective film, as described below, is formed over the substantially entire surface, and multiple through holes may be formed in this protective film for wiring connections in the post-wiring process.

[0076] 14) "Stock": This refers to semi-finished wafers that have completed the pre-wiring process being taken out of the first semiconductor manufacturing site and temporarily stored in a designated storage area. In the case where the "first semiconductor manufacturing site" and the "second semiconductor manufacturing site" are the "first semiconductor factory" and the "second semiconductor factory" operated by different businesses, this refers to semi-finished wafers being shipped from the first semiconductor factory and stored as inventory in a storage area (such as a storage warehouse). This storage area is called a "wafer bank."

[0077] Although the definitions of the above terms are based on typical technology at the time of filing this application, if the technical content and process flow of the semiconductor manufacturing process are improved or refined as technology advances, this does not prevent the definitions from being modified and interpreted within the scope of the spirit of the present invention as explained in the following specification.

[0078] In the first embodiment described below, a silicon semiconductor is used as an example of the semiconductor substrate, and a planar FET transistor is used as an example of the active element formed on the semiconductor substrate.

[0079] In addition, the pre-wiring process will be described assuming that aluminum wiring is used as the lower layer wiring, and the post-wiring process will be described assuming that copper wiring is formed using a direct imaging technique using a photosensitive organic insulating film as the interlayer insulating film and dual damascene technology. However, as mentioned above, the multilayer wiring process is not limited to this process flow. Also, as an example, the "first semiconductor manufacturing site" and the "second semiconductor manufacturing site" will be described assuming that they are separate factories, namely, a "first semiconductor factory" and a "second semiconductor factory." [Embodiment 1] (Outline of the manufacturing flow of embodiment 1)

[0080] FIG. 1 is a conceptual diagram showing an outline of a manufacturing flow of a semiconductor device according to the first embodiment.

[0081] Referring to FIG. 1, wafers are received and the first half of the front-end process (front-end process and pre-wiring formation process) is carried out by a plurality of semiconductor manufacturing factories corresponding to a plurality of functional circuit formation fabs 01 to N (N≧2, natural number).

[0082] As will be described later, the functional circuit fabrication fabs 01-N each use different semiconductor process technologies to form semiconductor chips on silicon wafers. Therefore, even if they are based on the same design, the functional circuits do not necessarily have the same characteristics or perform the same. Furthermore, the functional circuit fabrication fabs 01-N can manufacture different functional circuits with different performance characteristics, and the types of functional circuits they can manufacture also differ. Accordingly, the types and characteristics of the adjustment circuits formed by the functional circuit fabrication fabs 01-N also differ.

[0083] When the pre-wiring formation process is completed in the functional circuit formation fabs 01 to N, "functional circuits" and "adjustment circuits" according to the manufacturing process of each functional circuit formation fab 01 to N are formed on the semiconductor wafer.

[0084] Here, although the semiconductor wafers shipped from the functional circuit forming fabs 01-N have formed thereon the functional circuits that realize individual functions and the adjustment circuits that tune them, they do not have formed thereon the wiring that connects the functional circuits to each other, the functional circuits to the adjustment circuits, or the adjustment circuits to each other. For this reason, the "semiconductor device" that will ultimately be manufactured has not yet been formed on the semiconductor wafer, and only the individual components have been formed. Therefore, the semiconductor wafers shipped from the functional circuit forming fabs 01-N are called "semi-finished wafers."

[0085] Semi-finished wafers shipped from these multiple functional circuit forming fabs 01 to N are temporarily stored as inventory in a place called a wafer bank. Semi-finished wafers stored in a wafer bank are called "stock semiconductor wafers."

[0086] From the perspective of a designer of the "semiconductor device" that will ultimately be manufactured, there are cases where the semiconductor device that he or she has designed and is about to outsource manufacturing can be manufactured by connecting with wiring the functional circuits and adjustment circuits already formed on wafers stored in a wafer bank. In this case, it is possible to manufacture a prototype without the time required for the pre-wiring process.

[0087] Furthermore, in any of the multiple post-wiring process foundries 01 to M (M≧1, natural number), by connecting post-wiring onto stock semiconductor wafers stored in a wafer bank, it is possible to complete the prototyping of a "semiconductor device."

[0088] Furthermore, as will be explained later, the post-wiring formation process can be configured to use a direct imaging technique using a photosensitive organic insulating film as the interlayer insulating film and a dual damascene technique to form copper wiring.

[0089] In this case, the pre-wiring process can be performed using, for example, a stepper using a reticle or a step-by-step projection exposure method using reduced projection by a scanner. As a result, although the combination of functional circuits and adjustment circuits created up to the pre-wiring process can include multiple patterns within the same reticle, when viewed as a whole semiconductor wafer, the same combination pattern of functional circuits and adjustment circuits is repeated for each exposure step, the number of exposure steps using the reticle. Here, "step" refers to the process of exposing the reticle in step-by-step projection exposure. In a stepper, a square area of ​​the reticle is exposed with a single light irradiation (one shot) in one step, whereas in a scanner, the reticle and wafer are synchronized and exposed by irradiating light while moving laterally across a long, narrow slit-shaped irradiation area.

[0090] Although not particularly limited, for example, assume that multiple functional circuits and multiple adjustment circuits are formed on the same die, and multiple chips (dies) are included within a single reticle. In this case, the combination of functional circuits is common among the multiple chips (dies). However, by adjusting the connection with the adjustment circuit according to the characteristics and performance of the functional circuit, it is possible to change the "selection and connection method of adjustment circuits to be combined with functional circuits from among the multiple adjustment circuits" within a single wafer to achieve a semiconductor device with desired performance. In this case, the range of this change is at least as large as the number of chips (dies) within a reticle. In other words, however, the range of change in this case is generally limited to the number of chips within a single reticle.

[0091] On the other hand, in this embodiment, although not particularly limited, the lithography process for post-wiring is a process using a direct writing process. Furthermore, when a direct writing process is adopted, it is ultimately possible to form different post-wiring patterns based on the designer's design for each semiconductor chip manufactured on a single semiconductor wafer. In this case, there is no longer a restriction that the wiring pattern must be common between exposure steps for chips (dies) present within a reticle, as in the pre-wiring process.

[0092] In other words, for a chip (die) located at a specific position within one exposure step, if all steps up to the post-wiring process are exposed using a stepper or scanner that uses a reticle as a mask, the post-wiring will have the same pattern between different steps. In this case, the chip (die) at the specific position within the reticle has a common functional circuit pattern and adjustment circuit pattern between different steps.

[0093] On the other hand, if the post-wiring process is performed by direct writing, it is possible to provide different post-wiring connection patterns between chips (dies) on a semiconductor substrate.

[0094] As a result, the direct imaging process makes it possible to prototype a greater variety of "combinations of functional circuits" and the corresponding "selection and connection method of adjustment circuits to be combined with the functional circuits from among multiple adjustment circuits" within a single wafer than with the segmented projection exposure method.

[0095] As a result, performing the post-wiring process by direct writing is more desirable in terms of optimizing the method of connecting the post-wiring (post-wiring pattern) for one prototype lot than using the division projection exposure method.

[0096] In addition, when multi-layer wiring is performed in the pre-wiring process, the top-layer wiring in the pre-wiring process is the wiring that will be connected to the wiring in the post-wiring process. For example, direct writing technology can be used for lithography to form an etching mask for this top-layer wiring (e.g., Al wiring). In this case, the minimum lithography requirements for the top-layer wiring in the pre-wiring process are less strict than those for the lower-layer wiring. On the other hand, using direct writing technology in the pre-wiring process also has the advantage of increasing the degree of freedom in pattern variation during initial prototype production and the degree of freedom in pattern revision after the initial prototype production.

[0097] Therefore, if a semiconductor device is manufactured using the manufacturing flow shown in FIG. 1, it is possible to provide a circuit design method that can address issues identified in the initial manufacturing of a semiconductor integrated circuit in a short period of time and at low cost.

[0098] That is, depending on the issues identified in the initial manufacturing, they may be able to be addressed by changing the wiring pattern in the post-wiring process. In such cases, in the second or subsequent manufacturing runs, the results of the initial prototype in which the pattern in the post-wiring process was significantly changed can be utilized to reduce the extent of the changes, making it possible to manufacture semiconductor chips with a good yield and equipped with the desired semiconductor integrated circuits.

[0099] Here, for example, the following are assumed to be issues that may become apparent during initial manufacturing: i) Degradation of performance due to items that are not adequately described in the specifications alone (parasitic elements, parasitic capacitance, noise, etc.) ii) Items that cannot be fully verified by simulation alone (circuit oscillation, input offset voltage, etc.) iii) Items that become apparent due to insufficient simulation caused by insufficient parasitic element settings or thermal design (thermal runaway, etc.) iv) Items that become apparent after the semiconductor integrated circuit has been manufactured (ESD (Electro-Static-Discharge) tolerance, EMI (Electro-Magnetic Interference) tolerance, etc.) v) Degradation of performance due to a mismatch with the process performance (component performance) of the manufacturing line

[0100] In the manufacturing flow shown in FIG. 1, the functional circuit and the adjustment circuit are arranged independently so that after the above-mentioned problems are identified, they can be solved by revising the design, and the connection between the functional circuit and the adjustment circuit can be changed as needed in a post-wiring process.

[0101] Moreover, since such changes are made only in the post-wiring process, there is a high possibility that the problem can be solved before the design change for solving the problem leads to a complete revision of the design.

[0102] As a result, it is possible to reduce the development period and development costs. (Example of a cross-sectional structure according to the manufacturing flow of this embodiment and details of the manufacturing flow)

[0103] FIG. 2 is a diagram showing an example of a cross-sectional structure of a semiconductor device according to the manufacturing flow of this embodiment.

[0104] 3A to 3C are conceptual diagrams for explaining the manufacturing process of the semiconductor device shown in FIG.

[0105] 4 to 16 are diagrams illustrating the manufacturing flow of the semiconductor device shown in FIG. 2 in terms of cross-sectional structures.

[0106] 2, 3, and 4 to 16, in the design process, functional circuits corresponding to individual functions for achieving the overall function of the semiconductor device to be manufactured and adjustment circuits corresponding to these functional circuits are designed according to the procedure described below, thereby creating a photolithography mask for the processes (front-end process + pre-wiring process) to be carried out in the functional circuit formation fab. As described above, such a photolithography mask can be a reticle used in an optical stepper or scanner.

[0107] As shown in FIG. 2, the adjustment circuit ACKT is provided on the semiconductor substrate SUB separately from the functional circuit FCKT, and is a circuit for tuning the performance realized by the functional circuit ACKT.

[0108] FIG. 4 is a cross-sectional view showing a state in which the functional circuit block and the adjustment circuit block are formed on a semiconductor substrate.

[0109] Referring to FIG. 4 , a mask is created, and a semiconductor substrate SUB (bare wafer) is received in a functional circuit fabrication facility. After undergoing predetermined cleaning and drying processes, the surface of the silicon wafer is thermally oxidized. A silicon nitride film is formed on top of the oxide film using a low-pressure CVD (Chemical Vapor Deposition) method or the like. After that, shallow trenches are etched using a step-by-step projection exposure lithography method to form a buried oxide film. The buried oxide film is formed using a CVD method or the like. The buried oxide film is then planarized using a CMP (Chemical Mechanical Polishing) process, and the oxide film and nitride film are then removed to form an element isolation region ISO. This is called shallow trench isolation (STI) technology. Depending on the processing dimensions, other methods for forming element isolation regions, such as LOCOS (Local Oxidation of Silicon) technology, may also be used.

[0110] Next, after forming a sacrificial oxide film, a well region for forming a MOSFET is formed by ion implantation and activation annealing. In the case of CMOS, a p-type P well and an n-type N well are formed to form a twin well, but in Figure 2, a single well is assumed.

[0111] Next, a gate oxide film GOF and a polysilicon film and a silicide film that will become a gate electrode material TG are laminated, and a resist pattern of the gate electrode is formed by photolithography using a division projection exposure method, and the gate electrode is formed by etching. After the resist is removed, a drain region DL and a source region SL are formed by ion implantation and annealing using, for example, a self-alignment technique.

[0112] Subsequently, an etching stopper layer and an interlayer insulating film, which are so-called PMD (Pre Metal Dielectrics) films, are formed by, for example, plasma CVD technology, and planarization is also performed here by CMP technology.

[0113] A resist pattern is then formed by photolithography using a step-and-step projection exposure method, and contact holes to the source region SL and the drain region DL are etched. After the resist is removed, a glue layer (TiN / Ti, etc.) is formed in the contact holes by sputtering, and a blanket W film is formed by low-pressure CVD. The excess W film and glue layer on the PMD film are removed by a CMP process, forming a W plug CH in the contact hole. Although not shown in the figure, a W plug is also formed in the contact hole to the gate electrode at the same time.

[0114] Thereafter, for example, an aluminum wiring layer is formed as a first-layer metal wiring by a sputtering method or the like, and a resist pattern is formed by photolithography using a division projection exposure method. A pattern of the first-layer metal wiring M1 is formed by dry etching. After the resist is removed, an insulating film layer is formed using a silicon oxide film, and then planarized again by CMP technology. Thereafter, a silicon nitride film PLV1 is formed as a passivation film in the pre-wiring process.

[0115] Although not particularly limited, the silicon nitride film PLV1 functions as a protective film or passivation film for the circuit on the semi-finished semiconductor substrate after the pre-wiring process is completed.

[0116] Forming a silicon nitride film as a passivation film is well known, as disclosed in, for example, the following document:

[0117] The formation of the protective film prevents moisture from the outside air and impurities such as sodium from entering the circuits on the semi-finished semiconductor substrate.

[0118] 5, thereafter, via holes V1 for connecting metal wiring M2 in a post-wiring process to the top layer wiring (in this example, the first layer metal wiring M1) in the pre-wiring process are formed. The via holes V1 can be formed by dry etching using a resist pattern obtained by photolithography using a division projection exposure method.

[0119] After the via hole V1 is formed, the resist is removed.

[0120] 3, the front-end process and pre-wiring process are completed up to this point. After that, electrical characteristics of the formed functional circuits and adjustment circuits are tested, and information on the test results is stored in a predetermined common storage area (for example, storage device 2300, described later) and shipped to a wafer bank as stock semiconductor wafers. Because the silicon nitride film PLV1 is formed on the surface, even if the wafers are stocked in this way, the impact on reliability can be suppressed.

[0121] Therefore, semi-finished semiconductor substrates shipped to the wafer bank do not achieve their full functionality at the time of shipping, and are therefore called "semi-finished wafers" as described above.

[0122] Although not particularly limited, the formation of the via hole V1 may be performed at the beginning of the post-wiring process. For example, in the pre-wiring process, only the via hole V1 portion in the TEG (Test Element Group) portion may be opened to test the circuit, and the via hole V1 in the connection portion with the wiring in the post-wiring process may be opened by etching in the post-wiring process. Such etching is performed, for example, by dry etching, by forming an etching resist mask by exposure using a photomask or exposure using a direct writing technique.

[0123] A design process (not shown) for post-wiring is performed based on the test results, and stock semiconductor wafers suitable for forming the semiconductor integrated circuit as the product envisioned by the designer are searched for and selected from within the wafer bank and shipped to the post-wiring process fab.

[0124] As will be described later, the configuration may be such that a designer selects a fab capable of forming a desired semiconductor integrated circuit from among a plurality of fabs.

[0125] FIG. 6 is a diagram showing a cross-sectional structure in which an interlayer insulating film BEIL is formed on a semiconductor substrate after it has been subjected to a post-wiring process.

[0126] 6, when a stock semiconductor wafer in which via holes V1 have been formed in the pre-wiring process is received by a post-wiring process fab, an interlayer insulating film in the post-wiring process is formed from a photosensitive organic insulating film. Although not particularly limited, the photosensitive organic insulating film may be made of photosensitive polyimide or the like.

[0127] 7, in the post-wiring process, direct writing is performed on the photosensitive polyimide using, for example, a laser direct writing device. Laser direct writing (hereinafter referred to as "laser direct writing") allows direct writing to be easily performed under atmospheric pressure and is suitable as a wiring formation process in the post-wiring process. After direct writing, unnecessary portions of the photosensitive polyimide are removed by a development process to form a pattern of wiring M2 corresponding to the via hole V1, and the resulting material is cured.

[0128] Here, the technique of forming a pattern on a photosensitive resin by a laser direct writing technique is well known, as disclosed in, for example, the following documents: Publicly known document 2: Specification of JP-A-2022-41890 Publicly known document 3: Specification of JP-A-2023-119841

[0129] However, direct writing techniques may use other methods than laser light, and photosensitive resins other than photosensitive polyimides may also be used. For example, the following document discloses the use of a patterned cured film formed from a photosensitive resin composition containing a polybenzoxazole resin or a phenolic resin in addition to a polyimide resin as a surface protection film or an interlayer insulating film. Publicly known document 4: JP 2023-29564 A

[0130] Referring to FIG. 8, for example, by electroplating, a wiring metal material (for example, copper (Cu)) is deposited in the wiring grooves of the wiring M2 pattern and in the via hole V1 to simultaneously fill both.

[0131] Furthermore, the wiring metal is left only in the grooves by polishing, and multi-layer wiring is formed, that is, the wiring M2 is formed by a so-called dual damascene process.

[0132] Referring to FIG. 9, after the wiring M2 is formed, a photosensitive organic insulating film is again applied to the wafer in the same manner.

[0133] Referring to FIG. 10, a pattern of via holes V2 and a corresponding pattern (wiring groove) of wiring M3 are formed by direct writing on the applied photosensitive organic insulating film, and then cured.

[0134] Referring to FIG. 11, again, by electroplating or the like, a wiring metal material (for example, copper (Cu)) is deposited in the wiring groove of the wiring M3 pattern and in the via hole V2 to simultaneously fill both.

[0135] Referring to FIG. 12, the wiring metal is left only in the grooves by polishing, and wiring M3 is formed by a dual damascene process.

[0136] 13, a final passivation film PLV2 is then formed. The passivation film PLV2 may be, for example, a silicon nitride film formed by a plasma CVD method. A polyimide film may be formed instead of the silicon nitride film, or a polyimide film may be further formed on top of the silicon nitride film.

[0137] Referring to FIG. 14, an etching pattern for through holes in the contact portions of the bonding pads is formed by a photolithography process.

[0138] The lithography method for etching such through holes may be photolithography using a photoresist and a mask, or direct writing technology. When using such photolithography methods, it is assumed that the frame on which the chip is mounted is standardized in the subsequent process (assembly process). In other words, it is assumed that the pad positions on the chip side for wire bonding are standardized. However, there is a possibility that pads that are not wire bonded may occur due to bonding options, etc. The direct writing method can flexibly accommodate such cases, allowing for a configuration in which only the necessary through holes are opened.

[0139] Referring to FIG. 15, an opening is formed in the passivation film PLV2 in a predetermined region of the wiring M3 by an etching process.

[0140] Referring to FIG. 16, subsequently, in a wiring film formation step, bonding pads BP are formed of, for example, Al.

[0141] The semiconductor manufacturing process described above can be realized by combining currently commonly used process technologies, and therefore detailed explanations of the process conditions for each step will be omitted. Those skilled in the art will be able to set the process conditions and execute each step.

[0142] The manufacturing process described above realizes the following method for manufacturing a semiconductor device.

[0143] A multilayer wiring process for forming circuits corresponding to semiconductor devices manufactured as multiple chips on a semiconductor substrate is divided into a pre-wiring process and a post-wiring process, and the pre-wiring process is carried out in multiple functional circuit formation fabs 01 to N. Thereafter, a post-wiring process is carried out in at least one of the post-wiring process fabs 01 to M.

[0144] This semiconductor manufacturing method includes the following steps.

[0145] i) In functional circuit forming fabs 01 to N, a process of forming a plurality of active elements (e.g., transistors) in each region on a semiconductor substrate that corresponds to a chip of a semiconductor device, and then connecting the plurality of active elements with a first wiring pattern in a pre-wiring process to form a plurality of circuit blocks on the chip.

[0146] Here, the plurality of circuit blocks include a plurality of functional circuit blocks for realizing, on a semiconductor substrate, at least some of the plurality of individual functions that constitute the overall function of the semiconductor device, and a plurality of adjustment circuit blocks that are provided separately from the plurality of functional circuit blocks and that perform tuning for the performance realized by the functional circuit blocks. As will be described later, one of functional circuit forming fabs 01 to N manufactures a semiconductor substrate on which a plurality of functional circuit blocks corresponding to the individual functions for realizing the overall function of the semiconductor device are all formed, according to the overall function of the semiconductor device.

[0147] ii) A process of stocking a plurality of semiconductor substrates formed in a plurality of first semiconductor factories in a wafer bank as inventory in a pre-wiring process.

[0148] In the wafer bank, the semiconductor substrates can be stored in a clean environment, such as a nitrogen atmosphere, under controlled temperature and humidity conditions, without any particular limitation. This storage method can prevent the circuit characteristics of the semiconductor substrates from being affected during storage.

[0149] iii) A process of selecting, from among a plurality of semiconductor substrates stocked in a wafer bank, a semiconductor substrate on which a plurality of circuit blocks capable of achieving the overall function are formed, based on instructions from a designer of a post-wiring process.

[0150] iv) forming a second wiring pattern on the selected semiconductor substrate in one of the post-wiring process fabs 01 to M for connecting the plurality of circuit blocks to achieve the overall function. (Configuration of the design platform)

[0151] FIG. 17 is a conceptual diagram for explaining the configuration of a design platform of the design support system of this embodiment.

[0152] FIG. 18 is a conceptual diagram illustrating the server device that provides the design platform from the configuration shown in FIG.

[0153] 17 and 18 may be an on-premise server or a cloud server. However, from the viewpoint of sharing and using data among multiple designers, a cloud server is preferable. Here, the designers may belong to the same company or different companies.

[0154] Furthermore, the designer who designs the functional circuit and the designer who designs the semiconductor device as the final product (design of the post-wiring process) may be designers from the same company or may be designers from different companies. In Figure 17, a case is generally shown in which the designers are from different companies.

[0155] If the designer who designs the functional circuit and the designer who designs the semiconductor device as the final product are from different companies, the company who designs the functional circuit can develop a business of providing design information for the functional circuit to the company that manufactures and sells the semiconductor device as the final product. Alternatively, the company to which the designer who designs the semiconductor device as the final product belongs can develop a business of selling semi-finished wafers stocked in a wafer bank WBANK to the company that manufactures and sells the semiconductor device as the final product.

[0156] By configuring the design platform as shown in FIG. 17, it is possible to realize such a variety of business forms.

[0157] 17 and 18, the design platform is a design support system that provides tools to support the circuit design of semiconductor devices manufactured in cooperation with functional circuit formation fabs WFFAB.1 to WFFAB.N and post-wiring process fabs WLFAB.1 to WLFAB.M.

[0158] The functional circuit fabrication fabs WFFAB.1 to WFFAB.N are responsible for a first manufacturing process under a first design rule and are responsible for a pre-wiring process. The post-wiring process fabs WLFAB.1 to WLFAB.M are responsible for a second manufacturing process under a second design rule different from the first design rule and are responsible for a post-wiring process.

[0159] The functional circuit fabrication fabs WFFAB01 to WFFABN provide design reference data (PDK) to the design platform, and the storage device 1500 stores the data as pre-wiring process design reference data 1500.1.

[0160] The functional circuit design tool providing server 1000 supports the design of circuit patterns in a pre-wiring process for forming a plurality of circuit blocks on a semiconductor substrate. Here, the plurality of circuit blocks includes a plurality of functional circuit blocks for implementing, on the semiconductor substrate, a plurality of individual functions that constitute the overall function of the semiconductor device to be manufactured. Furthermore, the plurality of functional circuit blocks includes a plurality of stock circuit blocks for which design information for circuit patterns corresponding to the manufacturing process for each of the functional circuit fabrication fabs WFFAB.1 to WFFAB.N is prepared in advance based on the first design rule. The design information for the stock circuit blocks is stored in the storage device 1600 as a functional circuit design library 1600.1, and performance information (specification information) for the stock circuit blocks is stored as standard circuit performance information 1600.2.

[0161] The functional circuit design tool providing server 1000 selects a predetermined number of stock circuit blocks from a plurality of stock circuit blocks for realizing the overall function of a semiconductor device and supports the design of placing the selected circuit blocks on a semiconductor substrate for the designer terminals 5000.1 to 5000.P (P: natural number). Here, "design support" refers to support for logic design and pattern design, and can be realized, for example, by linking with an existing EDA tool.

[0162] The plurality of circuit blocks are provided on the semiconductor substrate separately from the plurality of functional circuit blocks, and each includes a plurality of adjustment circuit blocks for tuning the performance realized by the functional circuit block. Design information of the adjustment circuits is stored in an adjustment circuit design library 1600.3, and performance information of the adjustment circuits is stored as standard circuit performance information 1600.2.

[0163] After the pre-wiring process is completed, design information and specification information of the formed functional circuits, and design information and specification information of the adjustment circuits for the semi-finished wafers stored in the wafer bank WBANK are stored as an intra-wafer-bank stock information database (hereinafter referred to as an "intra-wafer-bank stock information DB") 2300.1 in the storage device 2300. Although not particularly limited, the storage of information in this intra-wafer-bank stock information DB 2300.1 and the updating of information as described below can be performed by the functional-circuit design tool providing server 1000.

[0164] If functional circuit design tool providing server 1000 determines that wafers on which functional circuits and adjustment circuits capable of achieving the overall function are formed are stocked in wafer bank WBANK, it provides designer terminals 5000.1 to 5000.P with a function of confirming through simulation that the desired overall function will be achieved by connecting the functional circuits and adjustment circuits on these wafers with post-wiring. If functional circuit design tool providing server 1000 determines as a result of the simulation that the overall function will be achieved, it selects these stocked semi-finished wafers as wafers to be sent to the post-wiring process. Information indicating this selection is stored in wafer bank stock information DB 2300.1.

[0165] Furthermore, once a specific company has selected to send a wafer stocked in wafer bank WBANK to the post-wiring process in this manner, access to the information on this wafer in wafer bank stock information DB2300.1 is managed so that it is limited to this specific company only.

[0166] On the other hand, if the functional circuit design tool providing server 1000 determines that it is difficult to achieve the overall functionality with the stocked semi-finished wafers, it supports the design of manufacturing new functional circuits and adjustment circuits that correspond to the missing functions in addition to the selected predetermined number of stock circuit blocks and corresponding adjustment circuit blocks.

[0167] As described above, it is assumed that designer terminals 5000.1 to 5000.P are installed in a company (functional circuit design company) different from the company (fabless manufacturer) that designs the post-wiring process. However, designer terminals 5000.1 to 5000.P may also be installed in the same company that designs the post-wiring process.

[0168] Furthermore, storage device 1500 stores a function-fab relation database (hereinafter referred to as the "function-fab relation DB") 1500.2 used to select and identify functional circuit formation fabs WFFAB.1 to WFFAB.N responsible for manufacturing semiconductor substrates on which semiconductor devices achieving the overall function are formed, as will be described later. Function-fab relation DB 1500.2 stores correspondence between "individual functions" for achieving the overall function based on PDK information and "design information in functional circuit design library 1600.1 and adjustment circuit design library 1600.3." "Function circuit design library 1600.1 and adjustment circuit design library 1600.3" are provided in advance corresponding to the processes of functional circuit formation fabs WFFAB.1 to WFFAB.N.

[0169] Functional circuit design library 1600.1 and adjustment circuit design library 1600.3 are collectively referred to as "IP core design information." The IP core design information includes the types of functional circuits that can be manufactured in each of the corresponding functional circuit fabrication fabs WFFAB.1 to WFFAB.N, their design information, and specifications for the functional circuits, as well as the types of adjustment circuits that can be manufactured, their design information, and specifications for the adjustment circuits. This information can be provided as a PDK.

[0170] The plurality of functional circuit blocks also includes at least one custom circuit block for which design information for a circuit pattern is designed by one of designer terminals 5000.1 to 5000.P based on a first design rule of a fab selected from among functional circuit formation fabs WFFAB.1 to WFFAB.N.

[0171] When functional circuit design tool providing server 1000 determines that multiple stock circuit blocks are insufficient to achieve overall performance, it displays a message to designer terminals 5000.1 through 5000.P performing design corresponding to the pre-wiring process, prompting them to design a custom circuit block. Then, functional circuit design tool providing server 1000 supports the logic design and pattern design of the custom circuit block and the corresponding adjustment circuit block based on the IP core design information and a first design rule corresponding to the fab selected as the fab responsible for manufacturing the semi-finished wafer that achieves the overall function. Here, when selecting the fab responsible for manufacturing the semi-finished wafer that achieves the overall function based on the IP core design information, the fab capable of producing the largest number of functional circuits corresponding to the individual functions required to achieve the overall function may be selected. When the custom circuit block design is completed, functional circuit design tool providing server 1000 provides mask data for creating a reticle to the selected fab from functional circuit formation fabs WFFAB.1 through WFFAB.N.

[0172] The company in charge of the design of the pre-wiring process may choose to add the design information of the newly designed custom circuit block and the corresponding adjustment circuit block to the "IP core design information." In this case, the newly designed custom circuit block is added as one of the stock circuit blocks.

[0173] The post-wiring design tool providing server 2000 supports the designer terminals 5100.1 to 5000.Q (Q: natural number) in designing circuit patterns in the post-wiring process for selectively connecting multiple circuit blocks formed in the pre-wiring process.

[0174] The post-wiring design tool provision server 2000 selects one of the post-wiring process fabs WLFAB.1 to WLFAB.M depending on the manufacturing process that produced the selected multiple stock circuit blocks. While the selection method is not particularly limited, for example, as described below, the selection may be performed based on the overlay margin for exposure in the post-wiring process, depending on the pattern and dimension information of the contact portion between the top-layer wiring in the pre-wiring process and the wiring formed in the post-wiring process. The post-wiring design tool provision server 2000 then executes logic design and pattern design support for the post-wiring process using a second design rule that corresponds to the first design rule of the selected stock circuit block. Here again, "design support" refers to support for logic design and pattern design, and can be realized, for example, by linking with an existing EDA tool.

[0175] Here, the selection of one of the post-wiring process fabs WLFAB.1 to WLFAB.M can be configured such that the designer, from one of designer terminals 5100.1 to 5100.Q, refers to wafer bank stock information DB 2300.1, selects a semiconductor wafer suitable for the semiconductor integrated circuit that the designer is attempting to design, and instructs (places an order for) wafer bank WBANK to send the selected semiconductor wafer to the post-wiring process.

[0176] Corresponding to the post-wiring process, the storage device 2500 stores wiring structure design reference data 2500.1 provided as PDK from the post-wiring process fabs WLFAB.1 to WLFAB.M, and adjustment circuit parameter data 2500.2 indicating performance parameters of adjustment circuits formed in the pre-wiring process. The performance parameters of the adjustment circuits can be configured to include not only design parameters but also information on the results of circuit tests performed in the pre-wiring process.

[0177] The post-wiring design tool providing server 2000 refers to the wafer bank stock information DB 2300 and performs logic design and pattern design for post-wiring for wafers flowing to the post-wiring process based on the wiring structure design reference data 2500.1 and adjustment circuit parameter data 2500.2 (including test data for functional circuits in the pre-wiring process).

[0178] The post-wiring design tool providing server 2000 provides the drawing data for direct drawing to a selected fab from the post-wiring process fabs WLFAB.1 to WLFAB.M.

[0179] Once the post-wiring process is complete, post-processing is carried out in one of the assembly process fabs ASFAB.1 to ASFAB.L that is responsible for the assembly process, and finally, the semiconductor device that will become the product is shipped.

[0180] From design terminals 5000.1 to 5000.Q, depending on the designer or the designer's company, information regarding issues discovered during prototyping and methods for resolving those issues through redesign or reprototyping can be stored as needed in problem information and solution information database (hereinafter referred to as "problem information and solution information DB") 2200.1 of storage device 2200. Once information is stored in problem information and solution information DB 2200.1, this information can be referenced from designer terminals 5000.1 to 5000.P, allowing it to be used as reference when selecting functional circuits provided by functional circuit design tool provision server 1000 and when designing circuit patterns in the pre-wiring process. In this way, by referencing information on past defects, it is possible to further shorten the construction period for prototyping.

[0181] The information stored in the problem information and solution information DB 2200.1 may be configured so that it can be referenced only from designer terminals 5000.i of companies that are permitted to reference the information through a separate contract or the like with the company in charge of designing the post-wiring process.

[0182] Alternatively, the information stored in the problem information and solution information DB 2200.1 may be made available to a wider range of companies. In any case, the extent to which companies can access the information depends on the agreement between the operator and users of the design platform.

[0183] Furthermore, in functional circuit design tool providing server 1000, it is possible to train an artificial intelligence (AI) using information stored in problem information and solution information DB 2200.1 as learning data, problem information as input, and solution methods as output. In this case, functional circuit design tool providing server 1000 can be configured to automatically respond to designer terminals 5000.1-5000.P by proposing solutions to the problems. Alternatively, the content of the AI ​​learning is not limited to this configuration. For example, if information is accumulated indicating that a problem has occurred due to a combination of specific functional circuits or a combination of a specific functional circuit and a specific adjustment circuit, a warning of a possible malfunction can be given to the designer at designer terminal 5000.1-5000.P while the designer is performing the design process.

[0184] With the above configuration, the design platform functions as a system that supports designers in their designs. However, it also has the function of managing the semiconductor wafers stocked in the wafer bank WBANK using the wafer bank stock information DB 2300.1 and managing the flow of semiconductor wafers in the manufacturing process. In this sense, the design platform also functions as a manufacturing management system as described below.

[0185] That is, in the manufacturing process managed by the manufacturing management system, the multilayer wiring process for forming circuits on a semiconductor substrate corresponding to the semiconductor devices manufactured as multiple chips is divided into a pre-wiring process and a post-wiring process, and the pre-wiring process is carried out in multiple functional circuit formation fabs 01 to N. Thereafter, the post-wiring process is carried out in at least one of the post-wiring process fabs 01 to M.

[0186] In such a manufacturing process, a manufacturing management system for managing stocked semiconductor substrates after the pre-wiring process has the following configuration.

[0187] i) In the functional circuit forming fabs 01 to N, a plurality of semiconductor substrates on which a plurality of circuit blocks are formed in each of areas corresponding to a chip are shipped and stocked in a wafer bank WBANK. In this case, a storage device receives and stores wafer bank stock information for managing the plurality of semiconductor substrates from the functional circuit forming fabs 01 to N.

[0188] ii) A processing unit for performing management operations such as:

[0189] The arithmetic processing unit selects, from among the semiconductor substrates stored in the wafer bank, a semiconductor substrate on which a plurality of circuit blocks capable of achieving the overall function is formed, based on the wafer bank stock information. Furthermore, the arithmetic processing unit instructs the shipment of the selected semiconductor substrate to at least one of the post-wiring process fabs 01-M, which will be responsible for forming a wiring pattern in the post-wiring process that connects the plurality of circuit blocks to achieve the overall function. (Conceptual diagram of function-fab relationship data)

[0190] FIG. 19 is a conceptual diagram showing an outline of the configuration of the function / fab relationship DB 1500.2.

[0191] 20 to 23 are diagrams for explaining the details of the configuration of the function / fab relationship DB 1500.2.

[0192] Referring to FIG. 19, function-fab relationship DB 1500.2 stores the following correspondence relationships.

[0193] That is, the function / fab relationship DB1500.2 includes a first correspondence relationship TBL1 that shows the relationship between the functional circuit blocks corresponding to each of the multiple individual functions that make up the overall function for realizing an application or product, and the adjustment circuits that can tune the performance of the functional circuit blocks in accordance with the functional circuit blocks, and a second correspondence relationship TBL2 that shows the performance specifications for the individual functions of the functional circuit blocks and the performance specifications of the adjustment circuit blocks, and multiple IP core design information groups for realizing each of these performance specifications.

[0194] FIG. 20 shows the details of the first correspondence table TBL1.

[0195] For example, when a motor control semiconductor integrated circuit is targeted as the semiconductor layer device that will be the final product, it is assumed that (function AA, function BB, . . . ) are required as individual functions.

[0196] These individual functions (function AA, function BB, ...) correspond to functional circuits (analog-digital conversion circuit ADC, digital-analog conversion circuit DAC, ...), and performance specifications are set for each functional circuit.

[0197] Similarly, adjustment functions (transistor capacitance adjustment, constant current source current value adjustment, phase margin adjustment, etc.) and corresponding functional circuits are set corresponding to individual functions (function AA, function BB, etc.), and the performance specifications of these are also set.

[0198] In FIG. 20, the existence of a correspondence between the adjustment circuit and the functional circuit corresponding to each required individual function and each adjustment function is indicated by a circle.

[0199] Note that the functional circuits corresponding to the individual functions are not limited to those mentioned above, and include, for example, the following circuits: OSC (oscillator circuit) RTC (real-time clock circuit) PLL (phase-locked loop circuit) VCO (voltage-controlled oscillator) OP-AMP (operational amplifier circuit) COMP (comparator) REF (reference voltage generation circuit, reference current generation circuit) POR (power-on reset circuit) REG (regulator circuit) CP (charge pump circuit) I / O (input / output circuit) MEM (small-scale memory circuit)

[0200] However, the functional circuits are not limited to these.

[0201] In addition, the corresponding adjustment circuits include the following circuits: Passive circuits such as parasitic element adjustment circuits Input offset voltage adjustment circuits Noise adjustment circuits Thermal runaway adjustment circuits ESD tolerance adjustment circuits EMI tolerance adjustment circuits Resistance / capacitance adjustment array circuits

[0202] The adjustment circuit is not limited to these.

[0203] 21 shows the relationship between the functional circuits and their specifications for achieving individual functions and the adjustment circuits and their specifications, and the IP core design information (IP core group 1, IP core group 2, ..., custom core) that can be achieved in advance. Here too, the existence of a correspondence is indicated by a circle.

[0204] The IP core group i (i: natural number) includes design information of a stock circuit block, and the custom core includes design information of a custom circuit block.

[0205] Each of the IP core design information groups includes "stock circuit block design information" for defining a preset individual circuit pattern that can realize the performance specifications for at least one of the individual functions.

[0206] 19, function-fab relationship DB1500.2 includes a correspondence table 3 between IP core design information (IP core group 1, IP core group 2, ..., custom core) as circuit design information and the IP cores that can be manufactured in the functional circuit fabrication fabs WFFAB.1 to WFFAB.N. FIG. 22 shows such correspondence table 3.

[0207] Furthermore, the function-fab relation DB 1500.2 includes a correspondence TBL4 between manufacturable IP core design information, corresponding foundries, and manufacturing processes (manufacturing processes under the first design rule). Fig. 23 shows such correspondence TBL4.

[0208] Based on the function-fab relation DB 1500.2, the functional circuit design tool provision server 1000 selects a group of IP core design information including a combination of functional circuit blocks that can realize the overall function. The functional circuit design tool provision server 1000 then identifies a fab corresponding to the selected group of IP core design information from among the functional circuit fabrication fabs WFFAB.1 to WFFAB.N, and executes logic design and pattern design based on a first design rule corresponding to the identified fab. (Configuration and Operation of Servers Constituting the Design Platform)

[0209] The configuration and operation of the servers that make up the design platform will be explained below with reference to the drawings.

[0210] 24 is a diagram showing the configuration of the functional circuit design tool providing server 1000, the post-wiring design tool providing server 2000, and the designer terminals 5000.1 to 5000.P.

[0211] Here, it is assumed that designer terminals 5000.1 to 5000.P correspond to designer terminals 5000.1 to 5000.Q, respectively, and designer terminals 5000.1 to 5000.Q are not shown in the figure. Hereinafter, when designer terminals 5000.1 to 5000.P are collectively referred to as designer terminal 5000.

[0212] As an example, the functional circuit design tool providing server 1000 and the post-wiring design tool providing server 2000 of the design platform are servers on the cloud, and are communicably connected to designer terminals 5000.1 to 5000.P via a network 2. (Configuration and Operation of the Functional Circuit Design Tool Providing Server 1000)

[0213] FIG. 25 is a functional block diagram showing the configuration of the functional circuit design tool providing server 1000.

[0214] 28 and 29 are flowcharts for explaining the operation of the functional circuit design tool providing server 1000. FIG.

[0215] Referring to FIG. 25, the functional circuit design tool providing server 1000 includes a communication interface 1002 for communicating with the outside, a processing unit 1100, and a memory 1200 that operates as a working storage area for the processing unit 1100.

[0216] The manufactured semiconductor acquisition module 1110, individual function setting module 1120, adjustment circuit setting module 1130, IP core selection module 1140, foundry selection module 1150, logic circuit design module 1160, circuit pattern design module 1170, and mask pattern generation module 1180 described in Figures 28 and 29 correspond to the functions of a CPU (Central Processing Unit) corresponding to the arithmetic processing unit 1100 executing corresponding modules in a program stored in memory when a computer operates as the functional circuit design tool provision server 1000.

[0217] 25, 28, and 29, when a designer uses the designer terminal 5000 to set the overall function of the semiconductor circuit to be designed and the specifications of the individual functions to realize it (S100), the manufactured semiconductor acquisition module 1110 and the individual function setting module 1120 of the functional circuit design tool provision server 1000 acquire information on this overall function and individual functions, and the IP core selection module 1140 searches for IP core design information that can achieve the overall function based on the specifications of the functional circuits that realize each individual function (S104).

[0218] If the IP core selection module 1140 determines that the entire function can be realized with the stocked functional circuit IP core library (Y in S106), it selects an IP core group that can realize the required functional circuit and adjustment circuit (step 108). On the other hand, if the IP core selection module 1140 determines that the entire function cannot be realized (N in S106), it proceeds to step 150 in FIG.

[0219] Returning to step 108, the foundry selection module 1150 then selects a foundry that has a process capable of realizing the selected IP core group (step S110).

[0220] In response to the selection of a foundry, the designer uses the designer terminal 5000 to set the specifications of an adjustment circuit for changing the characteristics of the functional circuit (S112).

[0221] The foundry selection module 1150 reads stock design information of the adjustment circuit corresponding to the functional circuit of the set specifications from the database in the storage device 1600 (step S114), and determines whether there are any wafers in the wafer bank on which circuits have already been formed by referring to the wafer bank stock information DB2300.1 (S116).

[0222] If the foundry selection module 1150 determines that a wafer that has already been formed exists (Y in S116), the logic circuit design module 1160 and the circuit pattern design module 1170 acquire information on the circuit layout on the wafer in the wafer bank (S118), proceed to step S164 of the process in Figure 29, and update the wafer bank stock information DB2300.1 so that the wafer to be sent to the post-wiring process is specified in the wafer bank stock information DB2300.1.

[0223] On the other hand, if the foundry selection module 1150 determines that there are no formed wafers (N in S116), the logic circuit design module 1160 and the circuit pattern design module 1170 design and determine the placement of the IP cores (functional circuits and adjustment circuits) in the IP core group within the reticle (S120).

[0224] Referring to FIG. 29, if the IP core selection module 1140 determines in step S106 that the overall function cannot be realized (N in S106), this fact is notified to the designer terminal 5000, and the designer sets the circuit specifications for the missing individual functions via the designer terminal 5000 (S150).

[0225] The logic circuit design module 1160 supports the logic design of the functional circuits of the missing individual functions and the logic design of the corresponding adjustment circuits (S152).

[0226] Next, the circuit pattern design module 1170 designs patterns for the logically designed functional circuit and adjustment circuit, stores them in the storage device 1600 as custom design information, and also updates the function / foundry relation DB (S154).

[0227] Furthermore, the logical circuit design module 1160 and the circuit pattern design module 1170 support logical design and, if necessary, pattern design for achieving the overall function based on stock design information of the stored functional circuits and adjustment circuits and the generated custom design information, and simulate the possibility of achieving the overall function (S156).

[0228] When the designer instructs the design of a circuit layout based on the structural design standards of the corresponding foundry process using the designer terminal 5000 (S158), the circuit pattern design module 1170 determines the patterns and layout of the front-end process and pre-wiring process of the functional circuit and adjustment circuit that can realize the target function (S160), and the mask pattern generation module 1180 generates and outputs mask data based on the layout information in the reticle of the functional circuit and adjustment circuit (S162).

[0229] The logic circuit design module 1160 and the circuit pattern design module 1170 update the wafer bank stock information DB in response to the completion of the pre-wiring process and the storage in the wafer bank (S164). (Configuration and Operation of the Post-wiring Design Tool Providing Server 2000)

[0230] FIG. 26 is a functional block diagram showing the configuration of the post-wiring design tool providing server 2000.

[0231] FIG. 30 is a flowchart for explaining the operation of the post-wiring design tool providing server 2000.

[0232] Referring to FIG. 26, the post-wiring design tool providing server 2000 includes a communication interface 2002 for communicating with the outside, a processing unit 2100, and a memory 2200 that operates as a working storage area for the processing unit 2100.

[0233] The manufactured semiconductor acquisition module 2110, individual function setting module 2120, adjustment circuit setting module 2130, IP core selection module 2140, foundry selection module 2150, logic circuit design module 2160, circuit pattern design module 2170, and drawing data generation module 2180 described in FIG. 30 correspond to the function of a CPU corresponding to the processing unit 2100 executing the corresponding module in the program stored in memory when the computer operates as the post-wiring design tool providing server 2000.

[0234] 26 and 30, when the overall functions of the semiconductor device to be manufactured are set in the designer terminal 5000, the target foundry is identified from the individual functions and adjustment functions by the manufactured semiconductor acquisition module 2110, the individual function setting module 2120, the adjustment circuit setting module 2130, the IP core selection module 2140, and the foundry selection module 2150, as in Fig. 25, and test result data of wafers that have completed the pre-wiring process is acquired (S200), and wafers to be sent to the post-wiring process are searched for and selected from the wafers in the wafer bank (S202). Note that if the company that designed the pre-wiring process also designs the post-wiring process, the wafers to be sent to the post-wiring process may be identified from the wafers in the wafer bank based on information obtained from the design of the pre-wiring process.

[0235] When the designer terminal 5000 refers to the wafer bank stock information DB and indicates that wafers on which circuits have already been formed exist in the wafer bank (Y in S204), the post-wiring design tool providing server 2000 first provisionally reserves, through the designer's operation, the wafers on which these circuits have already been formed for use in the designer's product application, selects adjustment circuits based on the performance margin of the functional circuits, and presents this to the designer terminal 5000 (S206). Then, when the designer terminal 5000 specifies the connection between the functional circuits and the adjustment circuits (S208), the logic circuit design module 2160 executes logic circuit design (including simulation) in the post-wiring process. Based on the results of the logic circuit design, the logic circuit design module 2160 presents to the designer terminal 5000 candidate functional circuits and adjustment circuits capable of realizing the target function (S210). In the designer terminal 5000, candidates for functional circuits and adjustment circuits that can realize the target function are selected (S212), and a wiring layout design is instructed based on the structural design criteria for the corresponding post-wiring process (S214). The circuit pattern design module 2170 generates a wiring layout in accordance with the instruction.

[0236] The designer terminal 5000 transmits a shipping instruction to at least one of the post-wiring process fabs 01-M, which will be responsible for forming the wiring pattern in the post-wiring process on the selected semiconductor substrate to achieve the overall function. While not particularly limited, for example, the post-wiring design tool providing server 2000 instructs the wafer bank WBANK to ship the selected wafer in response to the instruction from the designer terminal 5000, and cancels the tentative reservation. Furthermore, the drawing data generation module 2180 generates and outputs drawing data, which is transmitted to at least one of the post-wiring process fabs 01-M, which will be responsible for the post-wiring process (S216).

[0237] FIG. 27 is a block diagram for explaining the hardware configuration of the functional circuit design tool providing server 1000 shown in FIG.

[0238] In the following description, the functional circuit design tool providing server 1000 is assumed to operate on a server running on the cloud. However, the functional circuit design tool providing server 1000 may also operate on an on-premise server, for example.

[0239] Although the configuration of the functional circuit design tool providing server 1000 will be described below as an example, the hardware configuration of the post-wiring design tool providing server 2000 and the designer terminal 5000 is basically the same.

[0240] 27, server 1000 may be configured such that a computing device (CPU: Central Processing Unit) within its own housing executes the arithmetic processing, or such that part of the program processing is executed on another server. In the following description, it is assumed that the arithmetic device within its own housing executes the arithmetic processing.

[0241] Referring to FIG. 27, the server 1000 comprises a computer device 1010, a network communication unit 1012 for communicating with a network, and a recording medium (e.g., a memory card) 1210 for recording data from the outside and providing it to the computer device 1010.

[0242] For example, a USB memory, a memory card, or an external storage device can be used as the recording medium 1210. Also, for example, a wired LAN or wireless LAN communication function can be used as the network communication unit 1012. The network communication unit 1012 and the input / output interface 1090 constitute the communication interface 1002.

[0243] As shown in FIG. 27 , the computer main body constituting this computer device 1010 includes, in addition to a disk drive 1030 and a memory drive 1020, a CPU 1100 connected to a bus 1050, a memory 1200 including a ROM (Read Only Memory) 1200.1 and a RAM (Random Access Memory) 1200.2, a nonvolatile rewritable storage device 1300, and an input / output interface 1090 for communicating over a network and exchanging data with external devices. The nonvolatile storage device 1300 may be, for example, a hard disk drive (HDD) or a solid state drive (SSD). The following description will be given assuming an SSD. An optical disk can be inserted into the disk drive 1030. A memory card 1210 can be inserted into the memory drive 1020.

[0244] When the programs of the computer device 1010 operate, the data and programs that store the information that is the basis for the operation of the computer are stored in the SSD 1300 in the following description.

[0245] 27, the medium capable of recording information such as a program to be installed in the computer main body may be, for example, a DVD-ROM (Digital Versatile Disc), a memory card, a USB memory, etc. To accommodate such cases, the computer main body is provided with a drive device (memory drive 1020, disk drive 1030) capable of reading these media.

[0246] The main components of the computer device 1010 are computer hardware and software executed by the CPU 1100. Generally, such software is stored in a storage medium and distributed or distributed via a network, and is obtained via the disk drive 1030 or the network communication unit 1012 and temporarily stored in the SSD 1300. The software is then read from the SSD 1300 into RAM 1200.2 in memory and executed by the CPU 1100. Note that when connected to a network, the software may be directly loaded into the RAM and executed without being stored in the SSD 1300.

[0247] When distributing a program for functioning as computer system 1010, the program does not necessarily need to include an operating system (OS) that causes computer system 1010 to execute functions such as an information processing device. The program only needs to include instructions that call appropriate functions (modules) in a controlled manner and achieve the desired results. How computer system 1010 operates is well known, and a detailed description thereof will be omitted.

[0248] Furthermore, the CPU 1100 may be a single-core processor or a multi-core processor. That is, it may be a single-core processor or a multi-core processor. The server 1000 may also be configured with multiple servers to perform distributed processing. (Configuration of the die after the pre-wiring process and the die after the post-wiring process)

[0249] FIG. 31 is a diagram for explaining a plurality of dies formed on a semiconductor substrate after the pre-wiring process.

[0250] In FIG. 31, a plurality of function circuits and a plurality of adjustment circuits are formed on one die.

[0251] In FIG. 31, the functional circuits and adjustment circuits are represented by multiple layers, which indicates that, as explained in FIG. 2, multiple wiring and insulating film layers are formed sequentially when manufacturing these circuits.

[0252] FIG. 32 is a diagram for explaining a plurality of dies formed on a semiconductor substrate after a post-wiring process.

[0253] In FIG. 32, two dies are shown as examples of different die configurations.

[0254] As described above, the functional circuit design tool provision server 1000 generates optical mask patterns for performing exposure of dies on a semiconductor substrate, on which semiconductor devices are respectively formed, by a segmented projection exposure method in an exposure process at a first semiconductor manufacturing factory (functional circuit formation fab). On the other hand, the post-wiring design tool provision server 2000 generates drawing data for forming wiring patterns that connect circuit blocks to a semiconductor substrate in an exposure process at a second semiconductor manufacturing factory (post-wiring process fab).

[0255] By using direct writing, as shown in FIG. 32, different wiring patterns are formed in a post wiring process for dies among a plurality of dies that have common patterns for the functional circuit block and the adjustment circuit block.

[0256] More specifically, this different wiring pattern is a wiring pattern that connects a common functional circuit block and a different adjustment circuit block in a first die and a second die included in a die in which the patterns of the functional circuit block and the adjustment circuit block are common.

[0257] FIG. 33 is a diagram showing design rules for the uppermost layer wiring in the wiring group in the pre-wiring process, and design rules for the contact portion between the uppermost layer wiring M1 and the wiring M2 formed in the post-wiring process.

[0258] As shown in FIG. 33(a), the design rules for the top layer wiring are that the wiring interval is S (nm) and the wiring width is L (nm).

[0259] On the other hand, as shown in FIG. 33(b), in the design rules for the contact portion between the top layer wiring in the pre-wiring process and the wiring formed in the post-wiring process, the first design rule of the stock circuit block includes an overlap margin for the connection portion at the via hole for connecting the wiring formed in the pre-wiring process and the wiring formed in the post-wiring process based on the second design rule.

[0260] More specifically, although not particularly limited, for example, in the configuration shown in FIG. 33, it is desirable that the relationship be as follows: i) or ii).

[0261] Here, DR ＢＥ , D.R. ＦＥ are the minimum design dimensions of the wiring width in the pre-wiring process and the post-wiring process, respectively. The pre-wiring process has a smaller minimum design dimension as a design standard than the post-wiring process, and the alignment accuracy between masks (between processes) is also higher.

[0262] Therefore, although not particularly limited, for example, it is desirable that the planar structure of the top layer wiring formed in the pre-wiring process has a rectangular portion for forming a via hole contact, and that one side of this rectangular portion is set to 2.5 times or more the minimum width of the design criteria of the top layer wiring. Here, "2.5 times" means a typical value in the formula exemplified in ii) when DR ＢＥ = 2.0 μm, DR ＦＥ = 0.8 μm, but is not limited to this.

[0263] FIG. 34 is a conceptual diagram showing various modified examples of the pattern of the contact portion between the uppermost layer wiring in the pre-wiring process and the wiring formed in the post-wiring process.

[0264] As shown in FIG. 34, there are various possibilities for the shape of the contact formation region formed in the uppermost wiring layer in the pre-wiring step for connection with the first layer wiring layer in the post-wiring step.

[0265] Therefore, according to the design support system and design support method of the first embodiment, it is possible to shorten the product development period in the case of high-mix low-volume production.

[0266] Furthermore, by allowing designers from multiple companies to use the design support system as a design platform and share the information necessary for design, it becomes easier to further shorten the time required for design and prototyping.

[0267] Furthermore, such a design platform allows companies that supply semi-finished wafers to sell them to fabless companies that handle the post-wiring process. As a result, the design platform does not necessarily need to manage semi-finished wafers as inventory, and the entry of a variety of semi-finished wafer suppliers will further shorten the lead time and reduce costs for prototyping and mass production of a given semiconductor device.

[0268] The embodiments disclosed herein are merely examples of configurations for specifically implementing the present invention, and do not limit the technical scope of the present invention. The technical scope of the present invention is defined by the claims, not by the description of the embodiments, and is intended to include modifications within the literal scope of the claims and within the scope of equivalent meanings.

[0269] 1000 Functional circuit design tool providing server, 1002 Communication interface, 1100 Processing unit, 1200 Memory, 1110 Manufactured semiconductor acquisition module, 1120 Individual function setting module, 1130 Adjustment circuit setting module, 1140 IP core selection module, 1150 Foundry selection module, 1160 Logic circuit design module, 1170 Circuit pattern design module, 1180 Mask pattern generation module, 1500, 1600 Storage device, 2000 Post-wiring design tool providing server, 2002 Communication interface, 2100 Processing unit, 2200 Memory, 2110 Manufactured semiconductor acquisition module, 2120 Individual function setting module, 2130 Adjustment circuit setting module, 2140 IP core selection module, 2150 Foundry selection module, 2160 Logic circuit design module, 2170 Circuit pattern design module, 2180 Drawing data generation module, 2200, 2300, 2500 storage device, 5000.1 to 5000.P, 5000.1 to 5000.Q designer terminal, WFFAB.1 to WFFAB.N functional circuit formation foundry, WLFAB.1 to WLFAB.M post-wiring process foundry, WBANK wafer bank, ASFAB.1 to ASFAB.L assembly process foundry.

Claims

1. A method for manufacturing a semiconductor device, in which a multi-layer wiring process for forming circuits corresponding to semiconductor devices manufactured as a plurality of chips on a semiconductor substrate is divided into a pre-wiring process and a post-wiring process, the pre-wiring process being carried out at a plurality of first semiconductor manufacturing sites, and the post-wiring process being carried out at at least one second semiconductor manufacturing site, the method comprising the steps of: forming a plurality of active elements in each of areas on the semiconductor substrate corresponding to the chips at the plurality of first semiconductor manufacturing sites; and then, in the pre-wiring process, connecting the plurality of active elements with a first wiring pattern to form a plurality of circuit blocks on the chip, the plurality of circuit blocks including a plurality of functional circuit blocks for respectively realizing at least a portion of a plurality of individual functions constituting the overall function of the semiconductor device on the semiconductor substrate, and a plurality of adjustment circuit blocks provided separately from the plurality of functional circuit blocks for tuning the performance realized by the functional circuit blocks, the pre-wiring process comprising the steps of: stocking a plurality of semiconductor substrates formed at the plurality of first semiconductor manufacturing sites as an inventory; and selecting a semiconductor substrate on which the plurality of circuit blocks capable of achieving the overall function are formed from the plurality of stocked semiconductor substrates. and forming a second wiring pattern on the selected semiconductor substrate at the second semiconductor manufacturing site for connecting the multiple circuit blocks to achieve the overall function.

2. A method for manufacturing a semiconductor device as described in claim 1, wherein the step of forming the plurality of circuit blocks in the pre-wiring step includes a step of performing lithography for the first wiring pattern using a divided projection exposure method, and the step of forming the second wiring pattern in the post-wiring step includes a step of performing exposure for forming the second wiring pattern that connects the circuit blocks to the semiconductor substrate using a direct writing method.

3. A method for manufacturing a semiconductor device as described in claim 2, wherein the division projection exposure method in the pre-wiring process has an alignment accuracy between masks of a first value, the dimensions of a connection portion of a via hole for connecting the second wiring pattern of the first wiring pattern in the pre-wiring process include an overlap margin with the second wiring pattern, and the overlap margin of the dimensions of the connection portion is determined by the alignment accuracy of the direct writing method and is a second value greater than the first value.

4. A method for manufacturing a semiconductor device as described in claim 2, wherein the step of forming the second wiring pattern includes a step of forming a different wiring pattern for chips among the plurality of chips that have a common pattern for the functional circuit block and the adjustment circuit block.

5. A method for manufacturing a semiconductor device as described in claim 4, wherein the different wiring patterns are wiring patterns that connect the common functional circuit block and the different adjustment circuit blocks in a first chip and a second chip included in a chip having the common pattern.

6. A method for manufacturing a semiconductor device as described in claim 2, wherein the step of forming the second wiring pattern includes the steps of: forming a photosensitive resin film on the semiconductor substrate; directly drawing the second wiring pattern on the photosensitive resin film; developing the photosensitive resin film after the direct drawing; and forming a wiring layer corresponding to the second wiring pattern on the photosensitive resin film after the development.

7. A manufacturing management system for managing a process of stocking semiconductor substrates after a multi-layer wiring process for forming circuits on a semiconductor substrate corresponding to semiconductor devices manufactured as a plurality of chips, the pre-wiring process being divided into a pre-wiring process and a post-wiring process, the pre-wiring process being carried out at a plurality of first semiconductor manufacturing sites, and the post-wiring process being carried out at at least one second semiconductor manufacturing site, the system comprising a storage device for receiving from the first semiconductor manufacturing site and storing semiconductor substrate stock information for managing the plurality of semiconductor substrates when the plurality of semiconductor substrates, each having a plurality of circuit blocks formed in an area corresponding to the chip, are stocked in a storage area at the plurality of first semiconductor manufacturing sites, the plurality of circuit blocks including: a plurality of functional circuit blocks for respectively realizing at least a portion of a plurality of individual functions constituting the overall function of the semiconductor device on the semiconductor substrate; and a plurality of adjustment circuit blocks provided separately from the plurality of functional circuit blocks for tuning the performance realized by the functional circuit blocks, each of the plurality of functional circuit blocks having a plurality of active elements and a first wiring pattern for connecting the plurality of active elements, a processing unit for performing the management process, the processing unit selecting, based on the semiconductor substrate stock information, from among the plurality of stocked semiconductor substrates, a semiconductor substrate on which the plurality of circuit blocks capable of achieving the overall function are formed, and instructing the semiconductor substrate to be transported to the second semiconductor manufacturing site where a second wiring pattern connecting the plurality of circuit blocks is formed on the selected semiconductor substrate in order to achieve the overall function.

8. A semi-finished semiconductor substrate, in which a multi-layer wiring process for forming circuits on a semiconductor substrate corresponding to semiconductor devices each manufactured as a plurality of chips is divided into a pre-wiring process and a post-wiring process, and the pre-wiring process is performed at a plurality of first semiconductor manufacturing sites, and the semi-finished semiconductor substrate is temporarily stored before being received at a second semiconductor manufacturing site where the post-wiring process is performed, the semi-finished semiconductor substrate comprising a plurality of circuit blocks generated in the pre-wiring process for executing predetermined functions on the semiconductor substrate, the plurality of circuit blocks including: a plurality of functional circuit blocks for respectively realizing on the semiconductor substrate at least a portion of a plurality of individual functions that constitute the overall function of the semiconductor device; a plurality of adjustment circuit blocks provided separately from the plurality of functional circuit blocks, for tuning the performance realized by the functional circuit blocks; and at least one layer of first wiring formed in the pre-wiring process within each of the circuit blocks, the first wiring having a wiring contact portion for forming a connection by a via hole to a second wiring formed in the post-wiring process.

9. The semi-finished semiconductor substrate according to claim 8, wherein the semi-finished semiconductor substrate includes a moisture-resistant protective film covering substantially the entire outermost surface, and the first wiring is formed immediately before the formation of the protective film, and has a top layer wiring in which the wiring contact portion is formed.

10. A semi-finished semiconductor substrate as described in claim 9, wherein the lithography in the pre-wiring process is performed using a divided projection exposure method, and the alignment accuracy between masks is a first value, the dimensions of the wiring contact portion include an overlay margin with the post-process wiring, and the overlay margin of the dimensions of the wiring contact portion is determined by the alignment accuracy of a direct writing method used to perform the lithography in the post-wiring process, and is a second value greater than the first value.

11. The semi-finished semiconductor substrate according to claim 9, wherein the dimension of said wiring contact portion is 2.5 times or more the minimum dimension of the wiring pattern of said uppermost layer wiring.

12. The semi-finished semiconductor substrate according to claim 9, wherein said protective film is a silicon nitride film.

13. A method for manufacturing a semi-finished semiconductor substrate, the method comprising: dividing a multi-layer wiring process for forming circuits on a semiconductor substrate corresponding to semiconductor devices manufactured as a plurality of chips into a pre-wiring process and a post-wiring process, and carrying out the pre-wiring process at a plurality of first semiconductor manufacturing sites, the method comprising: forming a plurality of active elements in each of areas on the semiconductor substrate corresponding to the chips at the plurality of first semiconductor manufacturing sites, and then connecting the plurality of active elements with a first wiring pattern in the pre-wiring process to form a plurality of circuit blocks on the chip, the plurality of circuit blocks including a plurality of functional circuit blocks for respectively realizing at least a portion of a plurality of individual functions constituting the overall function of the semiconductor substrate, and a plurality of adjustment circuit blocks provided separately from the plurality of functional circuit blocks for tuning the performance realized by the functional circuit blocks, the first wiring pattern having wiring contact portions for forming a connection to second wiring formed in the post-wiring process at a second semiconductor manufacturing site, and the method comprising: forming a protective film covering substantially the entire outermost surface of the semiconductor substrate on which the plurality of circuit blocks are formed.

14. The method for manufacturing a semi-finished semiconductor substrate according to claim 13, wherein the process for forming the plurality of circuit blocks in the pre-wiring process includes a step of performing lithography for the first wiring pattern using a division projection exposure method, and the protective film is a silicon nitride film.

15. A semi-finished semiconductor substrate on which circuits corresponding to semiconductor devices each manufactured as a plurality of chips are formed, the semi-finished semiconductor substrate comprising a plurality of circuit blocks for executing predetermined functions on the semiconductor substrate, the plurality of circuit blocks including a plurality of functional circuit blocks for realizing on the semiconductor substrate a plurality of individual functions constituting the overall function of the semiconductor substrate, each of the functional circuit blocks having at least one layer of first wiring formed for achieving the individual function, the semi-finished semiconductor substrate further including a plurality of adjustment circuit blocks provided separately from the plurality of functional circuit blocks for tuning the performance realized by the functional circuit blocks, the first wiring having a wiring contact portion for forming a connection with a second wiring formed in a process after the semi-finished semiconductor substrate is stored in a storage area, and further comprising a protective film covering substantially the entire outermost surface of the semiconductor substrate on which the plurality of circuit blocks are formed.

16. A semi-finished semiconductor substrate according to claim 15, wherein the dimension of said wiring contact portion is 2.5 times or more the minimum dimension of the wiring pattern of the uppermost layer of said first wiring.

17. The semi-finished semiconductor substrate according to claim 15, wherein said protective film is a silicon nitride film.

18. A semiconductor substrate in which a multi-layer wiring process for forming circuits on a semiconductor substrate corresponding to semiconductor devices manufactured as a plurality of chips is divided into a pre-wiring process and a post-wiring process, the pre-wiring process being carried out at a plurality of first semiconductor manufacturing sites, the substrate being temporarily stored, selected according to a design of the overall function of the semiconductor device, and completed through the post-wiring process at a second semiconductor manufacturing site, the substrate comprising a plurality of circuit blocks generated in the pre-wiring process in order to realize a predetermined function on the semiconductor substrate, the plurality of circuit blocks including: a plurality of functional circuit blocks for respectively realizing on the semiconductor substrate at least a portion of a plurality of individual functions constituting the overall function of the semiconductor device; a plurality of adjustment circuit blocks provided separately from the plurality of functional circuit blocks and for tuning the performance realized by the functional circuit blocks; and within each of the circuit blocks, at least one layer of a first wiring pattern formed in the pre-wiring process, the first wiring having a wiring contact portion for forming a connection by a via hole with a second wiring formed in the post-wiring process, a semiconductor substrate comprising a second wiring pattern for connecting the plurality of circuit blocks, the second wiring pattern being formed in the post-wiring process on the selected semiconductor substrate to achieve the overall function; 19. A semiconductor substrate as described in claim 18, wherein the lithography in the pre-wiring process is performed using a divided projection exposure method, and the alignment accuracy between masks is a first value, the dimensions of the wiring contact portion include an overlay margin with the post-process wiring, and the overlay margin of the dimensions of the wiring contact portion is determined by the alignment accuracy of a direct writing method used to perform the lithography in the post-wiring process, and is a second value greater than the first value.

20. A semiconductor substrate as described in claim 19, including a moisture-resistant protective film formed in the pre-wiring process and covering substantially the entire surface of the semiconductor substrate, the first wiring having a top layer wiring formed immediately before the formation of the protective film, and the protective film having a plurality of through holes for electrically connecting to the top layer wiring.

21. The semi-finished semiconductor substrate according to claim 20, wherein the dimension of said wiring contact portion is 2.5 times or more the minimum dimension of the wiring pattern of said uppermost layer wiring.

22. The semiconductor substrate according to claim 20, wherein the protective film is a silicon nitride film.

23. The semiconductor substrate according to claim 18, wherein the interlayer insulating film in the post-wiring process is a photosensitive resin film, and the lithography for forming a pattern in the post-wiring process is carried out by a direct writing method.

24. A semiconductor substrate on which circuits corresponding to semiconductor devices each manufactured as a plurality of chips are formed, the semiconductor substrate comprising a plurality of circuit blocks for executing predetermined functions on the semiconductor substrate, the plurality of circuit blocks including a plurality of functional circuit blocks for realizing on the semiconductor substrate a plurality of individual functions constituting an overall function of the semiconductor device, each of the functional circuit blocks having at least one first wiring pattern formed to achieve the individual function, and further including a plurality of adjustment circuit blocks provided separately from the plurality of functional circuit blocks for tuning the performance realized by the functional circuit blocks, the first wiring pattern having wiring contact portions, the semiconductor substrate further comprising a protective film layer formed on an upper layer of the plurality of circuit blocks, the protective film layer being a silicon nitride film having a plurality of through holes in each of the circuit blocks corresponding to the wiring contact portions, an interlayer insulating film made of photosensitive organic resin formed on the protective film layer, and a second wiring pattern connecting the plurality of circuit blocks to the wiring contact portions of the plurality of circuit blocks via via holes opened in the interlayer insulating film corresponding to the through holes in order to achieve the overall function.

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