Glass substrate and multilayer wiring substrate comprising same

Abstract

The present invention provides a glass substrate and a multilayer wiring substrate. The glass substrate comprises: a glass body; a through-glass via (TGV) penetrating the glass body; and an organic reinforcement layer formed on a surface of the glass body. The multilayer wiring substrate comprises: the glass substrate; and a wiring laminate laminated on the glass substrate. The glass substrate is provided as a support substrate for the wiring laminate, thereby suppressing overall warpage of the multilayer wiring substrate, allowing the organic reinforcement layer to exert compressive force, and reducing or buffering stress caused by the tensile force of the glass body.

Description

Glass substrate and multilayer wiring substrate including the same

[0001] The present invention relates to a glass substrate and a multilayer wiring board including the same. More specifically, the present invention relates to a glass substrate including a glass body, a conductor, and an insulator, and a multilayer wiring board including the same.

[0002]

[0003] For example, a multilayer wiring board, such as a printed circuit board, is used to connect semiconductor chips such as an AP (Application Processor) chip and memory devices included in a smart phone to a circuit. The multilayer wiring board may include a plurality of insulating layers and a plurality of wiring layers repeatedly laminated therein. The AP chip or semiconductor chip can be mounted on the multilayer wiring board through soldering, wire connection, etc. using the outermost insulating layer and wiring layer.

[0004] Recently, as electronic components become more highly integrated, multilayer wiring boards may include a greater number of wiring layers. In this case, substrate warpage may occur due to differences in the coefficients of thermal expansion of the insulating and wiring layers. Furthermore, the heat generated during signal transmission to the AP chip or semiconductor chip may exacerbate this substrate warpage.

[0005] In addition, when passive elements such as capacitors, inductors, and resistors are included in the substrate, substrate warpage, substrate cracks, etc. may occur more easily due to differences in thermal expansion coefficients between the passive elements and the multilayer wiring substrate.

[0006]

[0007] An object of the present invention is to provide a glass substrate having improved mechanical stability and electrical efficiency.

[0008] An object of the present invention is to provide a multilayer wiring board having improved mechanical stability and electrical efficiency.

[0009]

[0010] 1. A glass substrate comprising a glass body; a through glass via (TGV) penetrating the glass body; and an organic reinforcement layer formed on a surface of the glass body.

[0011] 2. A glass substrate in the above 1, wherein the organic reinforcement layer includes a first organic reinforcement layer formed on the upper surface of the glass body and a second organic reinforcement layer formed on the lower surface of the glass body.

[0012] 3. A glass substrate in the above 1, wherein the organic reinforcement layer includes a via hole exposing the upper surface of the through glass via.

[0013] 4. A glass substrate further comprising a wiring-TGV via formed in the via hole and in contact with the through-glass via in the above 3.

[0014] 5. In the above 3, the width of the via hole is greater than or equal to the width of the upper surface of the through glass via, and the horizontal separation distance between the via hole and the upper surface of the through glass via is 10 μm or less.

[0015] 6. In the above 3, the width of the via hole is smaller than the width of the upper surface of the through glass via, the glass substrate.

[0016] 7. In the above 1, the organic reinforcing layer is a glass substrate having compressive force.

[0017] 8. A glass substrate including a plurality of through glass vias in the above 1, wherein the distance between adjacent through glass vias is 40 ㎛ to 1,000 ㎛.

[0018] 9. A glass substrate in the above 1, wherein the thickness of the glass body is 25 ㎛ to 1,000 ㎛, and the thickness of the organic reinforcement layer is 0.5 ㎛ to 10 ㎛.

[0019] 10. A multilayer wiring board comprising a glass substrate according to the above-described embodiments; and a wiring laminate disposed on the upper surface of the glass substrate and including repeatedly laminated wiring layers, insulating layers, and interlayer connection conductors.

[0020] 11. In the above 10, the wiring laminate is a multilayer wiring board having a passive element formed by the wiring layers, the interlayer connection conductors or the insulating layers.

[0021] 12. A multilayer wiring board according to the above 11, wherein the passive element includes at least one of a resistor, a capacitor, and an inductor.

[0022] 13. A multilayer wiring board in the above 10, wherein the compressive force of the organic reinforcing layer included in the glass substrate is greater than the compressive force of the insulating layers.

[0023] 14. A multilayer wiring board according to the above 10, wherein the glass substrate further includes a wiring-TGV via formed within the organic reinforcement layer and in contact with the upper surface of the through glass via.

[0024] 15. A multilayer wiring board according to the above 14, wherein the interlayer connecting conductor includes the wiring-TGV via and an interlayer via connecting at least one of the wiring layers to each other.

[0025]

[0026] According to embodiments of the present invention, a wiring laminate can be laminated on a glass substrate. The glass substrate serves as a support substrate for the wiring laminate, and can suppress overall warpage of the multilayer wiring substrate.

[0027] According to embodiments of the present invention, a glass substrate can be provided by forming an organic reinforcement layer on a glass body. The organic reinforcement layer has compressive strength and can reduce or buffer stress due to tensile force of the glass body.

[0028] According to exemplary embodiments, a through-glass via may be formed penetrating the glass body to electrically connect wiring layers included in the wiring laminate to the through-glass via. Accordingly, electrical signal loss from the lower surface of the glass body to the upper surface of the wiring laminate may be reduced, and high-Q characteristics may be implemented.

[0029] According to exemplary embodiments, the through-glass via can be connected to the wiring laminate through the organic reinforcement layer. Accordingly, the reliability and stability of the interconnection with the wiring laminate through the through-glass via can be enhanced.

[0030] According to exemplary embodiments, the wiring laminate may include passive components embedded therein. Therefore, the high-temperature SMT process for mounting passive components on the outer surface of the substrate can be omitted, thereby further preventing thermal damage and warpage of the substrate. Furthermore, the passive components can be designed utilizing the wiring layers included in the wiring laminate. Therefore, the manufacturing cost of the passive components can be reduced, while facilitating the design of a highly integrated circuit structure.

[0031]

[0032] FIG. 1 is a schematic cross-sectional view showing a glass substrate according to exemplary embodiments.

[0033] FIG. 2 is a schematic cross-sectional view showing a glass substrate according to exemplary embodiments.

[0034] FIG. 3 is a schematic cross-sectional view showing a glass substrate according to exemplary embodiments.

[0035] FIG. 4 is a schematic plan view showing a glass substrate according to exemplary embodiments.

[0036] FIG. 5 is a schematic cross-sectional view showing a multilayer wiring board according to exemplary embodiments.

[0037] FIG. 6 is a schematic cross-sectional view showing one implementation example of a passive component included in a multilayer wiring board according to exemplary embodiments.

[0038] FIG. 7 is a schematic cross-sectional view illustrating one implementation example of a passive component included in a multilayer wiring board according to exemplary embodiments.

[0039] FIG. 8 is a schematic perspective view illustrating implementation examples of passive components included in a multilayer wiring board according to exemplary embodiments.

[0040] FIG. 9 is a schematic plan view illustrating one implementation example of a passive component included in a multilayer wiring board according to exemplary embodiments.

[0041] FIGS. 10A and 10B are schematic perspective and cross-sectional views, respectively, illustrating one implementation example of a passive component included in a multilayer wiring board according to exemplary embodiments.

[0042]

[0043] Embodiments of the present invention provide a glass substrate including a glass body. Embodiments of the present invention provide a multilayer wiring substrate including the glass substrate and a wiring laminate.

[0044] Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings. However, the following drawings attached to this specification illustrate preferred embodiments of the present invention and, together with the contents of the invention described above, serve to further understand the technical concept of the present invention. Therefore, the present invention should not be interpreted as being limited to the matters described in such drawings.

[0045] The terms “first”, “second”, “third”, “fourth”, “first”, “other”, “top”, “bottom”, etc. used in this application do not limit absolute positions or orders, but are used in a relative sense to distinguish different components or parts.

[0046] FIG. 1 is a schematic cross-sectional view showing a glass substrate according to exemplary embodiments.

[0047] Referring to FIG. 1, the glass substrate may include a glass body (105) and an organic reinforcement layer (90).

[0048] The glass body (105) may be manufactured from a glass product or bare glass that substantially does not contain organic materials. For example, the term "glass body" as used in the present application may be used to mean excluding a structure in which glass particles or glass fibers are impregnated into an organic layer. In one embodiment, the glass body may include tempered glass.

[0049] In some embodiments, the glass body (105) may not include any vacancies or etched spaces (e.g., recesses, grooves, cavities, etc.) other than through via holes for forming through glass vias as described below.

[0050] The dielectric constant of the glass body (105) may be 1 to 10 at 1 MHz, for example, 1 to 7, 1 to 5, or 1 to 3. The loss tangent (dielectric loss) of the glass body (105) may be 0.00005 to 0.001, for example, 0.0005 to 0.001. The coefficient of thermal expansion of the glass body (105) may be 1×10 -6 / K to 10 -5 / K, for example, 1×10 -6 / K to 5×10 -6 / K could be.

[0051] The thickness of the glass body (105) may be 25 µm to 1,000 µm, 50 µm to 1,000 µm, 100 µm to 1,000 µm, or 500 µm to 1,000 µm. The thickness of the glass body (105) may be appropriately adjusted within the above range in consideration of the thickness and number of layers of the wiring laminate (107) described later.

[0052] The organic reinforcement layer (90) may be formed on the surface of the glass body (105). According to exemplary embodiments, the organic reinforcement layer (90) may be formed on the upper surface and the lower surface of the glass body (105), respectively. The organic reinforcement layer (90) may include a first organic reinforcement layer (90a) formed on the upper surface of the glass body (105) and a second organic reinforcement layer (90b) formed on the lower surface of the glass body (105).

[0053] The organic reinforcing layer (90) may include an organic resin such as an acrylic resin, an epoxy resin, a photoresist, etc. In one embodiment, the organic reinforcing layer (90) may not include an inorganic material or a ceramic material such as, for example, silicon oxide, silicon nitride, metal oxide, etc.

[0054] The glass body (105) may have inherent tensile strength. Therefore, cracks may easily occur within the glass body (105) due to external impact, and the glass body (105) may be easily broken.

[0055] The organic reinforcing layer (90) may inherently have compressive strength. Accordingly, compressive strength may be applied to the upper and lower surfaces of the glass body (105), respectively, thereby buffering or reducing the tensile stress inherent in the glass body (105). Accordingly, a glass substrate with improved mechanical durability may be provided.

[0056] According to exemplary embodiments, a composition including the organic resin may be coated on the surface of a glass body (105). Afterwards, a preliminary organic reinforcement layer may be formed through photo-curing or thermal curing. The preliminary organic reinforcement layer may be formed by, for example, 200 o C or higher or 250 o After baking at a high temperature of C or higher, an organic reinforcing layer (90) containing compressive strength can be formed by rapidly cooling.

[0057] In some embodiments, the thickness of the organic reinforcement layer (90) may be 0.5 μm to 10 μm, 1 μm to 10 μm, or 5 μm to 10 μm. Within the above range, the tensile stress of the glass body (105) can be appropriately reduced or absorbed, while preventing an increase in the coefficient of thermal expansion of the organic reinforcement layer (90).

[0058] As described above, the glass body (105) has a low dielectric loss value and can be applied as a support substrate to a multilayer wiring board described later to improve the low loss and high Q characteristics of the wiring board. In addition, the glass body (105) has a low coefficient of thermal expansion and can effectively suppress warpage occurring during high-temperature operation and build-up process of the wiring board.

[0059] Additionally, an organic reinforcing layer (90) can be formed on the surface of the glass body (105) to enhance the mechanical durability of the glass body (105). Accordingly, the brittle characteristics of the glass material can be reduced while preventing warping, thereby providing a glass substrate with improved physical properties.

[0060] The above glass substrate may further include a through glass via (TGV) (110). The through glass via (110) may extend as a single integral structure across the upper and lower surfaces of the glass body (105). The upper and lower surfaces of the through glass via (110) may be exposed to the upper and lower surfaces of the glass body (105), respectively.

[0061] For example, a through via hole penetrating the upper and lower surfaces of the glass body (105) can be formed through laser drilling, etc. The through via hole can be filled with a metal material through a plating process (e.g., copper plating) to form a through glass via (110).

[0062] As illustrated in FIG. 1, the through glass via (110) may penetrate the organic reinforcement layer (90) as well. In some embodiments, the through glass via (110) may extend in the thickness direction or the vertical direction across the second organic reinforcement layer (90b), the glass body (105), and the first organic reinforcement layer (90a).

[0063] FIG. 2 is a schematic cross-sectional view showing a glass substrate according to exemplary embodiments.

[0064] Referring to FIG. 2, a through via hole (103) is formed within the glass body (105), and a through glass via (110) can be formed within the through via hole (103).

[0065] As described with reference to FIG. 1, an organic reinforcement layer (90) is formed on a glass body (105) and a through glass via (110), and a via hole (93) can be formed by partially removing the organic reinforcement layer (90) to expose the upper surface of the through glass via (110). A wiring-TGV via (95) can be formed within the via hole (93) to contact the through glass via (110).

[0066] In some embodiments, as illustrated in FIG. 1, the wiring-TGV via (95) may be provided as a substantially integral conductive member with the through glass via (110).

[0067] The width of the via hole (93) or the wiring-TGV via (95) (e.g., the width of the bottom of the via hole (93) or the minimum diameter of the via hole (93)) may be greater than or equal to the width (or diameter) of the through glass via (110).

[0068] In one embodiment, the width of the via hole (93) or the wiring-TGV via (95) may be greater than the width of the through glass via (110).

[0069] Therefore, the upper surface of the through glass via (110) and the upper surface of the glass body (105) can be exposed together through the via hole (93). The wiring-TGV via (95) can contact the upper surface of the through glass via (110) and the upper surface of the glass body (105).

[0070] In some embodiments, the horizontal separation distance (D1) between the via hole (93) and the through glass via (110) may be 10 μm or less. Within this range, the tensile stress and bending stress of the glass body (105) due to the organic reinforcement layer (90) can be sufficiently reduced. Accordingly, when the glass substrate is bent, the separation and detachment of the through glass via (110) from the glass body (105) can be prevented.

[0071] In some embodiments, the diameter of the through glass via (110) may be 25 μm to 300 μm. Within this range, an excessive increase in the difference in thermal expansion coefficient due to an increase in the amount of conductive material can be prevented, and sufficient conductivity can be secured.

[0072] In one embodiment, the diameter of the through glass via (110) may be 50 μm to 300 μm, or 100 μm to 200 μm.

[0073] FIG. 3 is a schematic cross-sectional view showing a glass substrate according to exemplary embodiments.

[0074] Referring to FIG. 3, the width of the via hole (93) or the wiring-TGV via (95) may be smaller than the width (or diameter) of the through-glass via (110). Therefore, the upper surface of the through-glass via (110) may be exposed through the via hole (93), and the upper surface of the glass body (105) may not be exposed. The wiring-TGV via (95) may be in contact with the upper surface of the through-glass via (110) and may not be in contact with the upper surface of the glass body (105).

[0075] According to the embodiment illustrated in FIG. 3, the organic reinforcement layer (90) partially covers the upper surface of the through glass via (110), and can more effectively absorb or reduce the bending stress of the through glass via (110) and the glass body (105).

[0076] FIG. 4 is a schematic plan view showing a glass substrate according to exemplary embodiments.

[0077] Referring to FIG. 4, the glass substrate may include a plurality of through glass vias (110) and via holes (93). For example, the plurality of through glass vias (110) may be repeatedly arranged along the row direction and the column direction.

[0078] The spacing distance (D2) between adjacent through-glass vias (110) or via-holes (93) may be 40 μm to 1,000 μm. The spacing distance (D2) may be a horizontal distance between the centers of adjacent through-glass vias (110) or via-holes (93). In the above range, concentration of local thermal expansion coefficient / bending stress of the glass substrate can be prevented. In one embodiment, the spacing distance (D2) may be 100 μm to 1,000 μm, or 100 μm to 800 μm.

[0079] In some embodiments, the first organic reinforcement layer (90a) and the second organic reinforcement layer (90b) may each include a via hole (93). The diameter or size of the via hole (93) included in the first organic reinforcement layer (90a) and the via hole (93) included in the second organic reinforcement layer (90b) may be different from each other. For example, considering the density of the circuit layers disposed on the upper and lower sides of the glass substrate (100), the sizes of the via hole (93) included in the first organic reinforcement layer (90a) and the via hole (93) included in the second organic reinforcement layer (90b) may be adjusted to be different from each other.

[0080] FIG. 5 is a schematic cross-sectional view showing a multilayer wiring board according to exemplary embodiments.

[0081] Referring to FIG. 5, a multilayer wiring board (200) (hereinafter, abbreviated as wiring board) may include the glass substrate (100) described above and a wiring laminate (107) laminated on the glass substrate (100). The glass substrate (100) may include a glass body (105) and an organic reinforcement layer (90). A through glass via (110) may penetrate the glass body (105), and a wiring-TGV via (95) may be formed within the organic reinforcement layer (90) to be in contact with or connected to the through glass via (110).

[0082] The wiring laminate (107) may be laminated on the first organic reinforcement layer (90a) of the glass substrate (100). The wiring laminate (107) may be an organic substrate including wiring layers. According to exemplary embodiments, the wiring laminate (107) may include insulating layers (120) and wiring layers (130) that are repeatedly laminated from the upper surface of the first organic reinforcement layer (90a). According to exemplary embodiments, the wiring layers (130) and the insulating layers (120) may be build-up wiring layers and build-up insulating layers that are alternately and repeatedly laminated.

[0083] For example, the wiring layers (130) may include a first wiring layer (130a), a second wiring layer (130b), a third wiring layer (130c), and a fourth wiring layer (130d). The insulating layers (120) may include a first insulating layer (120a), a second insulating layer (120b), and a third insulating layer (120c).

[0084] According to exemplary embodiments, on the upper surface of the glass substrate (100), wiring layers (130) and insulating layers (120) may be alternately and repeatedly laminated in the following order: a first wiring layer (130a), a first insulating layer (120a), a second wiring layer (130b), a second insulating layer (120b), a third wiring layer (130c), a third insulating layer (120c), etc.

[0085] However, the number of wiring layers (130) and insulating layers (120) illustrated in FIG. 5 is only an example provided for convenience of explanation, and the number of layers and circuit design of the wiring laminate (107) are not limited as illustrated in FIG. 5.

[0086] The wiring layers (130) can be formed by forming a conductive layer on the upper surface of the glass substrate (100) or on any one of the insulating layers (120), and then patterning the conductive layer through an etching process. The conductive layer can be formed through a deposition process such as a plating process or a sputtering process.

[0087] In some embodiments, the wiring layers (130) may be formed through a SAP process (Semi-Additive Process), an M-SAP process (Modified Semi-Additive Process), or a tenting process.

[0088] The wiring layers (130) may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, and may include, for example, copper (Cu).

[0089] The insulating layers (120) may each be formed to cover the wiring layer (130). The insulating layers (120) may be formed using a photosensitive resin such as an acrylic resin and / or a thermosetting resin such as an epoxy resin. According to exemplary embodiments, the insulating layers (120) may have a lower compressive strength than the organic reinforcing layer (90).

[0090] The wiring laminate (107) may further include interlayer connection conductors (140) that connect the wiring layers (130) to each other. The interlayer connection conductors (140) are disposed between wiring layers (130) of different levels and refer to conductors formed within the insulating layer (120).

[0091] In some embodiments, the interlayer interconnect conductor (140) may include interlayer vias that connect wiring layers (130) arranged at different levels.

[0092] According to embodiments of the present invention, a passive element may be included within the wiring laminate (107). For example, the wiring laminate (107) may be provided as an integrated passive device (IPD) substrate having the passive element built into it.

[0093] According to exemplary embodiments, the passive component may be implemented as an inherent component formed by the arrangement of wiring layers (130) and insulating layers (120) rather than being inserted into the wiring laminate (107) as a separate chip.

[0094] The passive components may include inductors, capacitors, resistors, and the like. In some embodiments, the passive components may include a first passive component (PE1), a second passive component (PE2), and a third passive component (PE3).

[0095] The first passive element (PE1), the second passive element (PE2), and the third passive element (PE3) may each be different types of passive elements. For example, the first passive element (PE1) may include a conductor pattern included in the first wiring layer (130a) and a conductor pattern included in the second wiring layer (130b), and the conductor patterns may face each other with the first insulating layer (120a) interposed therebetween. Accordingly, the first passive element (PE1) may be provided as a capacitor.

[0096] The second passive element (PE2) may include, for example, a line pattern having a relatively large length included in the third wiring layer (130c). Accordingly, the second passive element (PE2) may be provided as a resistor.

[0097] The third passive element (PE3) may include a coil in which at least two layers of wiring layers are connected through interlayer connecting conductors (140) (e.g., interlayer vias). Accordingly, the third passive element (PE3) may be provided as an inductor.

[0098] As described above, a passive component embedded in a wiring substrate (200) or a wiring laminate (107) can be designed by utilizing the wiring layers (130), insulating layers (120) and / or interlayer connection conductors (140) included in the wiring laminate (107). According to exemplary embodiments, the passive component may not include any other configuration / structure other than the wiring layer (130), insulating layer (120) and / or interlayer connection conductor (140).

[0099] Accordingly, a separate, isolated chip-shaped passive element having a material different from that included in the wiring laminate (107) is not included, and an increase in warpage due to a difference in physical properties, such as a coefficient of thermal expansion, of the chip-shaped passive element can be prevented.

[0100] In addition, the integration density of passive components can be easily controlled by adjusting the line and space of the wiring layers (130). Accordingly, high integration density of passive components can be efficiently implemented, and an RF substrate can be effectively provided.

[0101] As described above, the passive element can be designed to be integrated with the wiring layer (130). Therefore, compared to a case where a separate chip is embedded, signal loss can be reduced and high Q characteristics can be enhanced.

[0102] According to exemplary embodiments, the wiring laminate (107) and the glass body (105) may not include a chip receiving space, such as a cavity, recess, or through hole, for inserting / embedding an electric element in the form of a chip (e.g., a passive element and an active element such as an IC chip), inside. Accordingly, mechanical defects, such as a decrease in substrate rigidity or warping due to the chip receiving space, can be prevented.

[0103] Through-glass vias (110) can be classified according to the conductive pattern included in the wiring laminate (107) to which they are connected. In some embodiments, the through-glass vias (110) can include a first through-glass via (110a), a second through-glass via (110b), and a third through-glass via (110c).

[0104] A first wiring-TGV via (95a) may be in contact with a first through-glass via (110a), and interlayer connection conductors (140) and wiring layers (130) may be alternately and sequentially stacked on the first wiring-TGV via (95a) to form a common interconnect structure (CI). For example, the common interconnect structure (CI) may provide a shortest distance electrical signal path across the glass body (105) and the wiring laminate (107) in the vertical direction or thickness direction of the wiring substrate (100).

[0105] The common interconnect structure (CI) may be provided as a substantially single pillar. For example, a virtual centerline vertically penetrating the first through-glass via (110a) may penetrate the entire common interconnect structure (CI).

[0106] The second through-glass via (110b) can be connected to a passive component. For example, it can be connected to the first passive component (PE1) through the first wiring-TGV via (95a).

[0107] The third through-glass via (110c) may be connected to the wiring layer (130). For example, the third through-glass via (110c) may be electrically connected to the first wiring layer (130a) through the first wiring-TGV via (95a).

[0108] A lower wiring layer (190) and a lower insulating layer (180) may be laminated on the lower surface of the glass substrate (100) or the second organic reinforcement layer (90b). A lower wiring via (195) may be connected or in contact with the lower wiring layer (190).

[0109] The common interconnect structure (CI) may further include a second wiring-TGV via (95b) in contact with the lower surface of the through glass via (110).

[0110] The wiring laminate (107) may be provided as an upper wiring / insulating structure of the wiring board (100). The uppermost wiring layer (e.g., the fourth wiring layer (130d)) included in the wiring laminate (107) may include a pad for mounting an electronic component. For example, an active component such as a semiconductor die, an AP chip, an IC chip, etc. may be mounted on the pad by soldering or wire bonding.

[0111] In some embodiments, the lower wiring via (195) may be connected to the motherboard via a conductive ball or soldering.

[0112] FIG. 6 is a schematic cross-sectional view illustrating an example implementation of a passive component included in a multilayer wiring board according to exemplary embodiments. For example, FIG. 6 illustrates an example implementation of a second passive component (PE2) provided as a register.

[0113] Referring to FIG. 6, a line pattern (132a) included in the wiring layers (130) may be placed on a lower insulating layer (e.g., a second insulating layer (120c)). An upper insulating layer (e.g., a third insulating layer (120c)) may be in direct contact with the line pattern (132a) and cover the line pattern (132a). Resistance may be adjusted depending on the length of the line pattern (132a), thereby providing a passive element that functions as a resistor.

[0114] A connection electrode (141) may be formed at each end of the line pattern (132a). The connection electrode (141) may penetrate the upper insulating layer and contact or be connected to the line pattern (132a). A terminal electrode (132b) may be formed on the upper insulating layer and contact or be connected to the connection electrode (141).

[0115] The line pattern (132a) is included as a configuration of one of the wiring layers (130), and can be formed at the same level with substantially the same material and the same process as the wiring layer (130). The terminal electrode (132b) is also included as a configuration of one of the wiring layers (130) (e.g., the uppermost wiring layer (e.g., the fourth wiring layer (130d))) among the wiring layers (130), and can be formed at the same level with substantially the same material and the same process as the wiring layer (130).

[0116] The connecting electrode (141) is included as a component of one layer of the interlayer connecting conductor (140) among the interlayer connecting conductors (140), and can be formed at the same level using substantially the same material and the same process as the interlayer connecting conductor (140).

[0117] FIG. 7 is a schematic cross-sectional view illustrating an example implementation of a passive component included in a multilayer wiring board according to exemplary embodiments. For example, FIG. 7 illustrates an example implementation of a first passive component (PE1) provided as a capacitor.

[0118] Referring to Fig. 7, the first electrode (131) and the second electrode (133) can be placed facing each other with an insulating layer (120) therebetween. Accordingly, a passive element of a MIM (Metal-Insulator-Metal) capacitor structure can be implemented.

[0119] The first electrode (131) and the second electrode (133) are each included as a component of one of the wiring layers (130), and can be formed at the same level using substantially the same material and the same process as the wiring layer (130).

[0120] As illustrated in FIG. 5, the first electrode (131) and the second electrode (133) may be connected to an interlayer connection conductor (140) or a first wiring-TGV via (95a), respectively (see the first passive element (PE1)). The interlayer connection conductor (140) or the first wiring-TGV via (95a) connected to the first electrode (131) and the second electrode (133) may be provided as a terminal electrode or an external electrode.

[0121] Figure 8 is a schematic perspective view illustrating implementation examples of passive components included in a multilayer wiring board according to exemplary embodiments. Figure 8 illustrates one implementation example of a capacitor as a passive component.

[0122] Referring to FIG. 8, one of the wiring layers (130) may be provided as a first terminal electrode (134) (or a first external electrode), and one of the wiring layers (130) may be provided as a second terminal electrode (136) (or a second external electrode). In one embodiment, the first terminal electrode (134) and the second terminal electrode (136) may be included in a wiring layer (130) of the same level. Alternatively, the first terminal electrode (134) and the second terminal electrode (136) may be included in wiring layers (130) of different levels.

[0123] Internal electrodes may be distributed within the insulating layer (120). For example, first internal electrodes (142) and second internal electrodes (144) may be alternately repeated in the horizontal direction.

[0124] One end of the first internal electrodes (142) can be in contact with or connected to the first terminal electrode (134). The other end of the second internal electrodes (144) (the ends opposite to the one end of the first internal electrodes (152)) can be in contact with or connected to the second terminal electrode (136).

[0125] A capacitance can be formed in the insulating layer (120) portion between the first internal electrode (142) and the second internal electrode (144) that are adjacent to each other. Accordingly, a passive element having a multilayer capacitor structure can be implemented.

[0126] The first internal electrodes (142) and the second internal electrodes (144) are included as a configuration of one layer of the interlayer connection conductor (140) among the interlayer connection conductors (140), and can be formed at the same level using substantially the same material and the same process as the interlayer connection conductor (140).

[0127] FIG. 9 is a schematic plan view illustrating an example implementation of a passive component included in a multilayer wiring board according to exemplary embodiments. For example, FIG. 9 illustrates an example implementation of a third passive component (PE3) provided as an inductor.

[0128] Referring to FIG. 9, a first coil part (138) is disposed on a lower insulating layer (not shown) (e.g., a first insulating layer (120a)), and an upper insulating layer (not shown) (e.g., a second insulating layer (120b)) may be in contact with the first coil part (138) and cover the first coil part (138). A second coil part (139) may be disposed on the upper insulating layer.

[0129] The first coil section (138) and the second coil section (139) can be connected to each other by a coil via (not shown) penetrating the upper insulating layer. Accordingly, a coil-shaped inductor having multiple turns can be implemented.

[0130] The first coil portion (138) and the second coil portion (139) are each included as a configuration of one of the wiring layers (130), and can be formed at the same level using substantially the same material and the same process as the wiring layer (130).

[0131] The above coil via is included as a component of one layer of the interlayer connection conductor (140) among the interlayer connection conductors (140), and can be formed at the same level with substantially the same material and the same process as the interlayer connection conductor (140).

[0132] Terminal electrodes (not shown) may be contacted or connected to the ends of the first coil portion (138) and the second coil portion (139), respectively. The terminal electrodes are included as a component of one layer of the interlayer connection conductors (140) among the interlayer connection conductors (140), and may be formed at the same level using substantially the same material and the same process as the interlayer connection conductor (140).

[0133] FIGS. 10A and 10B are schematic perspective and cross-sectional views, respectively, illustrating one embodiment of a passive component included in a multilayer wiring board according to exemplary embodiments. For example, FIG. 10B is a cross-sectional view taken vertically or in the thickness direction along line II' of FIG. 10A.

[0134] Referring to FIGS. 10A and 10B, one of the wiring layers (130) may include a first terminal electrode (135) (or a first external electrode) and lower connection electrodes (135a). The upper wiring layer (130) may include a second terminal electrode (137) (or a second external electrode) and upper connection electrodes (137a) with an insulating layer (120) therebetween, relative to the first terminal electrode (135) and lower connection electrodes (135a).

[0135] Coil vias (145) may be distributed within the insulating layer (120). The coil vias (145) are included as a component of one layer of the interlayer connection conductors (140) among the interlayer connection conductors (140), and may be formed at the same level using substantially the same material and the same process as the interlayer connection conductor (140).

[0136] A first terminal electrode (135) and a second terminal electrode (137) may be connected through coil vias (145) and connection electrodes (135a, 137a) to form a coil-shaped inductor. According to exemplary embodiments, neighboring coil vias (145) in the width direction may be connected to each other by an upper connection electrode (137a), and neighboring coil vias (145) in a diagonal direction with respect to the width direction may be connected to each other by a lower connection electrode (135a). Accordingly, a conductor may be repeated in a zigzag pattern across the lower and upper layers to form a coil.

[0137] The multilayer wiring board (100) described above can be applied as a circuit board for highly integrated electronic devices such as smart phones, PCs, semiconductor packages, etc. A glass body (105) and a passive component-embedded wiring laminate can be combined to provide a thin circuit board with low loss, high Q, and high speed.

[0138] Hereinafter, preferred embodiments are presented to help understand the present invention, but these embodiments are only illustrative of the present invention and do not limit the scope of the appended claims. It is obvious to those skilled in the art that various changes and modifications to the embodiments are possible within the scope and technical idea of ​​the present invention, and it is also natural that such changes and modifications fall within the scope of the appended claims.

[0139] Examples and Comparative Examples

[0140] As illustrated in Fig. 2, a through glass via (110) having a diameter of 50 μm was formed through copper plating within a 1 mm thick glass body (105). After forming an acrylic organic reinforcement layer (90) having a thickness of 10 μm on the glass body (105), it was baked at 250°C and cooled.

[0141] The glass substrates of the examples below were manufactured by changing the distance (D1) from the through glass via (110) of the via hole (93) formed in the organic reinforcement layer (90) as described in Table 1.

[0142] In the comparative example, the same glass substrate as in the examples was used except that the organic reinforcement layer (90) was omitted.

[0143] Bending stress measurement

[0144] The bending stress of the glass substrates of the examples and comparative examples was measured according to the ASTM C158 standard. Specifically, the bending stress until the through glass via in the glass substrate was removed from the through via hole was measured.

[0145] The measurement results are shown in Table 1 below.

[0146] Classification D1 (㎛) Bending stress (kgf) Example 1021.3 Example 2517.9 Example 31013.2 Comparative example -9.66

[0147] Referring to Table 1, in the examples in which the organic reinforcement layer was formed, the bending stress that the glass substrate could withstand increased. Referring to Example 3, it can be confirmed that the bending stress substantially increased compared to the comparative example when the spacing between the via holes was adjusted to 10 μm or less.

Claims

1. Glass body; A through glass via (TGV) penetrating the glass body; and A glass substrate comprising an organic reinforcing layer formed on a surface of the glass body.

2. A glass substrate according to claim 1, wherein the organic reinforcing layer includes a first organic reinforcing layer formed on the upper surface of the glass body and a second organic reinforcing layer formed on the lower surface of the glass body.

3. A glass substrate according to claim 1, wherein the organic reinforcement layer includes a via hole exposing an upper surface of the through glass via.

4. A glass substrate according to claim 3, further comprising a wiring-TGV via formed within the via hole and in contact with the through-glass via.

5. In claim 3, the width of the via hole is greater than or equal to the width of the upper surface of the through glass via, A glass substrate, wherein the horizontal separation distance between the upper surface of the via hole and the through glass via is 10 μm or less.

6. A glass substrate according to claim 3, wherein the width of the via hole is smaller than the width of the upper surface of the through glass via.

7. A glass substrate according to claim 1, wherein the organic reinforcing layer has compressive force.

8. In claim 1, comprising a plurality of said through glass vias, A glass substrate, wherein the distance between adjacent through-glass vias is 40 μm to 1,000 μm.

9. A glass substrate according to claim 1, wherein the thickness of the glass body is 25 ㎛ to 1,000 ㎛, and the thickness of the organic reinforcement layer is 0.5 ㎛ to 10 ㎛.

10. The glass substrate of claim 1; and A multilayer wiring board comprising a wiring laminate including repeatedly laminated wiring layers, insulating layers and interlayer connection conductors, which is disposed on the upper surface of the glass substrate.

11. In claim 10, the wiring laminate is a multilayer wiring board having a passive element formed by the wiring layers, the interlayer connection conductors, or the insulating layers.

12. A multilayer wiring board according to claim 11, wherein the passive component includes at least one of a resistor, a capacitor, and an inductor.

13. A multilayer wiring board according to claim 10, wherein the compressive force of the organic reinforcing layer included in the glass substrate is greater than the compressive force of the insulating layers.

14. A multilayer wiring board according to claim 10, wherein the glass substrate further includes a wiring-TGV via formed within the organic reinforcement layer and in contact with an upper surface of the through glass via.

15. A multilayer wiring board according to claim 14, wherein the interlayer connecting conductor comprises an interlayer via connecting at least one of the wiring-TGV vias and the wiring layers to each other.

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