Display substrate and display apparatus

Abstract

Provided in the present disclosure are a display substrate and a display apparatus. The display substrate comprises a base, and a first transistor and a second transistor which are arranged on the base, the second transistor comprising a gate electrode, a first electrode and a second electrode, wherein an active pattern of the first transistor and an active pattern of the second transistor are stacked on the base, or the first transistor and the second transistor share an active pattern, and a gate electrode of the first transistor and the active pattern of the second transistor are stacked on the base; a gate electrode of the first transistor is located on the side of the active pattern of the first transistor that is away from the base; and the active pattern of the second transistor is in direct contact with the first electrode of the second transistor, and the active pattern of the second transistor is in direct contact with the second electrode of the second transistor. The present disclosure can significantly save the space occupied by transistors.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] In related technologies, as display panel integration increases, multiple thin-film transistors (TFTs) need to be arranged within a single pixel, resulting in a severe shortage of space. Top-gate TFTs typically have two vias to connect the source and drain electrodes to the active pattern, making space compression difficult.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a display substrate, comprising a substrate, and a first transistor and a second transistor disposed on the substrate; the second transistor comprises a gate, a first electrode, and a second electrode;

[0005] The active pattern of the first transistor and the active pattern of the second transistor are stacked on the substrate; or the first transistor and the second transistor share an active pattern, and the gate of the first transistor and the active pattern of the second transistor are stacked on the substrate;

[0006] A gate of the first transistor is located on a side of the active pattern of the first transistor away from the substrate; the active pattern of the second transistor is in direct contact with the first electrode of the second transistor, and the active pattern of the second transistor is in direct contact with the second electrode of the second transistor.

[0007] Optionally, the active pattern of the first transistor and the active pattern of the second transistor are stacked in sequence along a direction away from the substrate.

[0008] Optionally, the first transistor and the second transistor share a gate.

[0009] Optionally, the first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the second transistor, and the second electrode of the second transistor are arranged in the same layer.

[0010] Optionally, the active pattern of the first transistor includes a semiconductor portion and a conductor portion; the first electrode of the first transistor is located in a first metal layer; the active pattern of the first transistor is located in the first semiconductor layer, the active pattern of the second transistor is located in a second semiconductor layer, and the first semiconductor layer, the second semiconductor layer, and the first metal layer are stacked in sequence in a direction away from the substrate;

[0011] At least a portion of an orthographic projection of the conductor portion on the substrate is covered by a pattern formed in the first metal layer and / or a pattern formed in the second semiconductor layer.

[0012] Optionally, the display substrate described in at least one embodiment of the present disclosure further includes a passivation layer disposed on a side of the first metal layer away from the base.

[0013] Optionally, the gate of the second transistor is a first gate, and the second transistor further includes a second gate;

[0014] The second gate is disposed on a side of the first electrode of the second transistor away from the substrate.

[0015] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a third transistor; an active pattern of the third transistor is in direct contact with the first electrode of the third transistor, and an active pattern of the third transistor is in direct contact with the second electrode of the third transistor;

[0016] The active pattern of the third transistor includes a semiconductor portion;

[0017] An orthographic projection of the gate of the third transistor on the substrate covers an orthographic projection of the semiconductor portion on the substrate.

[0018] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a third transistor; an active pattern of the third transistor is in direct contact with the first electrode of the third transistor, and an active pattern of the third transistor is in direct contact with the second electrode of the third transistor;

[0019] The active pattern of the third transistor includes a semiconductor portion;

[0020] An orthographic projection of the semiconductor portion on the substrate covers an orthographic projection of the gate of the third transistor on the substrate.

[0021] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a third transistor; an active pattern of the third transistor is in direct contact with the first electrode of the third transistor, and an active pattern of the third transistor is in direct contact with the second electrode of the third transistor;

[0022] The third transistor includes two gates;

[0023] One gate of the third transistor is arranged on the same layer as the first gate, another gate of the third transistor is arranged on the same layer as the second gate, and an active pattern of the third transistor is arranged on the same layer as the active pattern of the second transistor.

[0024] Optionally, the active pattern of the second transistor and the active pattern of the first transistor are stacked in sequence along a direction away from the substrate.

[0025] Optionally, the gate of the second transistor, the active pattern of the second transistor, the first electrode of the second transistor, the active pattern of the first transistor and the gate of the first transistor are stacked in sequence along a direction away from the substrate.

[0026] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a light-shielding pattern and a fourth transistor; the fourth transistor includes an active pattern, and the active pattern of the fourth transistor includes a semiconductor portion;

[0027] The gate of the fourth transistor is provided on the same layer as the gate of the first transistor, and the active pattern of the fourth transistor is provided on the same layer as the active pattern of the fourth transistor;

[0028] The orthographic projection of the light-shielding pattern on the substrate at least partially covers the orthographic projection of the semiconductor portion of the fourth transistor on the substrate;

[0029] The light shielding pattern and the first electrode of the second transistor are located in the same layer.

[0030] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a third transistor; the third transistor includes a first gate, a second gate, a first electrode, and a second electrode;

[0031] The first gate of the third transistor is provided in the same layer as the gate of the second transistor;

[0032] The active pattern of the third transistor is arranged in the same layer as the active pattern of the second transistor;

[0033] The second gate of the third transistor is arranged in the same layer as the gate of the first transistor.

[0034] Optionally, the first transistor includes a gate, a first electrode and a second electrode;

[0035] The first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the second transistor and the second electrode of the second transistor are arranged in the same layer;

[0036] The gate of the second transistor, the active pattern of the second transistor, the first electrode of the second transistor, the active pattern of the first transistor and the gate of the first transistor are stacked in sequence along a direction away from the substrate.

[0037] Optionally, the active pattern of the first transistor includes a first conductor portion and a second conductor portion;

[0038] The first conductor portion of the first transistor is electrically connected to the first electrode of the first transistor through a via hole, and the second conductor portion of the first transistor is electrically connected to the second electrode of the first transistor through a via hole.

[0039] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a light-shielding pattern and a fourth transistor;

[0040] The fourth transistor includes a first gate, a second gate and an active pattern;

[0041] The light shielding pattern is provided in the same layer as the first electrode of the first transistor;

[0042] The first gate of the fourth transistor is provided at the same layer as the gate of the first transistor, and the second gate of the fourth transistor is provided at the same layer as the gate of the second transistor;

[0043] The active pattern of the fourth transistor is arranged in the same layer as the active pattern of the first transistor;

[0044] An orthographic projection of the light-shielding pattern on the substrate at least partially overlaps with an orthographic projection of a semiconductor portion of the active pattern of the fourth transistor on the substrate.

[0045] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a third transistor;

[0046] The third transistor includes a first gate, a second gate, a first electrode, a second electrode and an active pattern;

[0047] The first gate is provided at the same layer as the gate of the first transistor, and the second gate is provided at the same layer as the gate of the second transistor;

[0048] The first electrode of the third transistor, the second electrode of the third transistor and the first electrode of the first transistor are arranged in the same layer;

[0049] The active pattern of the third transistor is arranged in the same layer as the active pattern of the second transistor;

[0050] The active pattern of the third transistor is in direct contact with the first electrode of the third transistor, and the active pattern of the third transistor is in direct contact with the second electrode of the third transistor.

[0051] Optionally, the first transistor and the second transistor share an active pattern; the second transistor further includes a gate, a first electrode and a second electrode;

[0052] The gate of the second transistor, the active pattern, the first electrode of the second transistor and the gate of the first transistor are arranged in sequence along a direction away from the substrate.

[0053] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes a third transistor and a fourth transistor;

[0054] The gate of the fourth transistor is provided in the same layer as the gate of the first transistor;

[0055] The third transistor includes a first gate, an active pattern, a first electrode and a second electrode;

[0056] The first gate of the third transistor is provided in the same layer as the gate of the second transistor;

[0057] The active pattern of the third transistor, the active pattern of the fourth transistor and the active pattern of the first transistor are arranged in the same layer;

[0058] The active pattern of the third transistor is in direct contact with the first electrode of the third transistor, and the active pattern of the third transistor is in direct contact with the second electrode of the third transistor.

[0059] Optionally, the third transistor further includes a second gate;

[0060] The second gate of the third transistor is provided in the same layer as the gate of the first transistor;

[0061] An orthographic projection of the second gate of the third transistor on the substrate covers an orthographic projection of a semiconductor pattern included in the active pattern of the third transistor on the substrate.

[0062] In a second aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] FIG1A is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0064] FIG1B is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0065] FIG1C is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0066] FIG1D is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0067] FIG1E is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0068] FIG2A is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0069] FIG2B is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0070] FIG2C is a planar layout diagram of a display substrate according to at least one embodiment of the present disclosure;

[0071] FIG2D is a layout diagram of the first semiconductor layer in FIG2C ;

[0072] FIG2E is a layout diagram of the first gate metal layer in FIG2C ;

[0073] FIG2F is a layout diagram of the first source / drain metal layer in FIG2C ;

[0074] FIG2G is a layout diagram of the second semiconductor layer in FIG2C ;

[0075] FIG3A is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0076] FIG3B is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0077] FIG3C is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0078] FIG4A is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0079] FIG4B is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0080] FIG4C is a planar layout diagram of a display substrate according to at least one embodiment of the present disclosure;

[0081] FIG4D is a layout diagram of the first gate metal layer in FIG4C ;

[0082] FIG4E is a layout diagram of the first semiconductor layer in FIG4C ;

[0083] FIG4F is a layout diagram of the second semiconductor layer in FIG4C ;

[0084] FIG4G is a layout diagram of the first source / drain metal layer in FIG4C ;

[0085] FIG4H is a layout diagram of the second gate metal layer in FIG4C ;

[0086] FIG5A is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0087] FIG5B is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0088] FIG5C is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0089] FIG6A is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0090] FIG6B is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0091] FIG6C is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0092] FIG6D is a planar layout diagram of a display substrate according to at least one embodiment of the present disclosure;

[0093] FIG6E is a layout diagram of the first gate metal layer in FIG6D ;

[0094] FIG6F is a layout diagram of the first semiconductor layer in FIG6D ;

[0095] FIG6G is a layout diagram of the first source / drain metal layer in FIG6D ;

[0096] FIG6H is a layout diagram of the second semiconductor layer in FIG6D ;

[0097] FIG6I is a layout diagram of the second gate metal layer in FIG6D ;

[0098] FIG7A is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0099] FIG7B is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0100] FIG7C is a planar layout diagram of a display substrate according to at least one embodiment of the present disclosure;

[0101] FIG7D is a layout diagram of the first gate metal layer in FIG7C ;

[0102] FIG7E is a layout diagram of the first semiconductor layer in FIG7C ;

[0103] FIG7F is a layout diagram of the first source / drain metal layer in FIG7C ;

[0104] FIG7G is a layout diagram of the second semiconductor layer in FIG7C ;

[0105] FIG7H is a layout diagram of the second gate metal layer in FIG7C ;

[0106] FIG8A is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0107] FIG8B is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0108] FIG8C is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0109] FIG9A is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0110] FIG9B is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0111] FIG9C is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0112] FIG9D is a planar layout diagram of a display substrate according to at least one embodiment of the present disclosure;

[0113] FIG9E is a layout diagram of the first gate metal layer in FIG9D ;

[0114] FIG9F is a layout diagram of the first semiconductor layer in FIG9D ;

[0115] FIG9G is a layout diagram of the first source / drain metal layer in FIG9D ;

[0116] FIG9H is a layout diagram of the second semiconductor layer in FIG9D ;

[0117] FIG9I is a layout diagram of the second gate metal layer in FIG9D ;

[0118] FIG10A is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0119] FIG10B is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0120] FIG11A is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0121] FIG11B is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0122] FIG11C is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0123] FIG11D is a planar layout diagram of a display substrate according to at least one embodiment of the present disclosure;

[0124] FIG11E is a layout diagram of the first gate metal layer in FIG11D ;

[0125] FIG11F is a layout diagram of the first semiconductor layer in FIG11D ;

[0126] FIG11G is a layout diagram of the first source / drain metal layer in FIG11D ;

[0127] FIG. 11H is a layout diagram of the second gate metal layer in FIG. 11D . DETAILED DESCRIPTION

[0128] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0129] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor other than the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0130] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain, and the second electrode may be a source; or, the first electrode may be a source, and the second electrode may be a drain.

[0131] The display substrate according to the embodiment of the present disclosure includes a substrate, and a first transistor and a second transistor disposed on the substrate; the second transistor includes a gate, a first electrode, and a second electrode;

[0132] The active pattern of the first transistor and the active pattern of the second transistor are stacked on the substrate; or the first transistor and the second transistor share an active pattern, and the gate of the first transistor and the active pattern of the second transistor are stacked on the substrate;

[0133] A gate of the first transistor is located on a side of the active pattern of the first transistor away from the substrate; the active pattern of the second transistor is in direct contact with the first electrode of the second transistor, and the active pattern of the second transistor is in direct contact with the second electrode of the second transistor.

[0134] In the related art, as the integration of display panels gradually increases, multiple TFTs (thin-film transistors) need to be arranged in a pixel area, resulting in a serious shortage of arrangement space. Top-gate TFTs can increase the on-current (Ion) of the TFT due to their structural advantages. However, since the top-gate TFT structure generally has two vias to achieve overlap and connectivity between the source and drain electrodes and the active pattern, further space compression is difficult and is prone to short circuits between vias. BCE (back-channel etched) TFTs are bottom-gate TFT structures. In this structure, the source and drain electrodes of the TFT can be directly electrically connected to the active pattern, which can significantly save the space occupied by the TFT. However, since the source and drain electrodes overlap with the orthographic projection of the gate electrode on the substrate, parasitic capacitance may occur, resulting in increased power consumption. Therefore, the embodiments of the present disclosure comprehensively consider the advantages and disadvantages of top-gate and bottom-gate TFT structures and propose a TFT structure that combines BCE TFTs and top-gate TFTs.

[0135] In at least one embodiment of the present disclosure, the first transistor and the second transistor may be stacked on the substrate to reduce the size occupied by the transistors, thereby saving space and reducing power consumption.

[0136] In a specific implementation, the first transistor and the second transistor may be stacked sequentially along a direction away from the substrate, or the second transistor and the first transistor may be stacked sequentially along a direction away from the substrate.

[0137] In at least one embodiment of the present disclosure, the first transistor is a top-gate transistor, and the second transistor is a BCE transistor.

[0138] In at least one embodiment of the present disclosure, the active pattern of the first transistor (a transistor with a top-gate structure) and the active pattern of the second transistor (a transistor with a BCE structure) are stacked in sequence in a direction away from the substrate.

[0139] In a specific implementation, the active pattern of the first transistor and the active pattern of the second transistor may be arranged in sequence along a direction away from the substrate.

[0140] In at least one embodiment of the present disclosure, the first transistor and the second transistor share a common gate.

[0141] In a specific implementation, the first transistor and the second transistor may share a gate to reduce the number of masks used.

[0142] In at least one embodiment of the present disclosure, the first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the second transistor, and the second electrode of the second transistor are arranged in the same layer.

[0143] In a specific implementation, the first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the second transistor and the second electrode of the second transistor can be set in the same metal layer, and the first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the second transistor and the second electrode of the second transistor can be manufactured through the same metal layer, so as to reduce the number of masks used.

[0144] In at least one embodiment of the present disclosure, the active pattern of the first transistor includes a semiconductor portion and a conductor portion; the first electrode of the first transistor is located in a first metal layer (SD layer); the active pattern of the first transistor is located in the first semiconductor layer, and the active pattern of the second transistor is located in the second semiconductor layer, and the first semiconductor layer, the second semiconductor layer, and the first metal layer are stacked in sequence in a direction away from the substrate;

[0145] At least a portion of an orthographic projection of the conductor portion on the substrate is covered by a pattern formed in the first metal layer and / or a pattern formed in the second semiconductor layer.

[0146] Optionally, the first metal layer may be a first source / drain metal layer.

[0147] The display substrate described in at least one embodiment of the present disclosure further includes a passivation layer disposed on a side of the first metal layer away from the base.

[0148] In a specific implementation, when the first transistor is an oxide transistor, when a passivation layer is formed above the second transistor, N2O (nitrous oxide) plasma surface treatment and oxygen-rich conditions may cause the conductor portion of the first transistor to be partially deconducted. Therefore, a pattern formed on the first metal layer and / or a pattern formed on the second semiconductor layer can be used to shield at least a portion of the conductor portion to improve the phenomenon of partial deconduction of the conductor portion of the first transistor.

[0149] As shown in Figure 1A, labeled 10 is the substrate, labeled 11 is the first semiconductor layer, labeled 101 is the first insulating layer, labeled 12 is the first gate metal layer, labeled 102 is the second insulating layer, labeled 13 is the second semiconductor layer, and labeled 14 is the first source and drain metal layer.

[0150] As shown in FIG1B , the active pattern A1 of the first transistor is formed in the first semiconductor layer;

[0151] The active pattern of the second transistor is labeled A2, and the active pattern of the second transistor is formed in the second semiconductor layer;

[0152] The gate of the first transistor is labeled G1, and the first transistor and the second transistor share a gate. The gate G1 of the first transistor is located in the first gate metal layer 12;

[0153] The first electrode of the first transistor is labeled S1, the second electrode of the first transistor is labeled D1, the first electrode of the second transistor is labeled S2, and the second electrode of the second transistor is labeled D2; the first electrode S1 of the first transistor, the second electrode D1 of the first transistor, the first electrode S2 of the second transistor and the second electrode D2 of the second transistor are all located in the first source and drain metal layer.

[0154] As shown in FIG1C , the semiconductor portion of the active pattern of the first transistor is labeled A10 , the first conductor portion of the active pattern of the first transistor is labeled A11 , and the second conductor portion of the active pattern of the first transistor is labeled A12 .

[0155] The active pattern of the first transistor includes a first conductor portion A11 at least partially blocked by S1 , S2 , and A2 , and a second conductor portion A12 at least partially blocked by D1 , D2 , and A2 .

[0156] As shown in FIG1D , based on FIG1A , a passivation layer 103 is provided on a side of the first source / drain metal layer 14 away from the substrate 10 .

[0157] As shown in FIG. 1B and FIG. 1C , S1 and S2 are disconnected, and D1 and D2 are disconnected.

[0158] As shown in FIG. 1E , S1 can be connected to S2 , and D1 can be connected to D2 .

[0159] The display substrate according to at least one embodiment of the present disclosure further includes a third transistor; the active pattern of the third transistor is in direct contact with the first electrode of the third transistor, and the active pattern of the third transistor is in direct contact with the second electrode of the third transistor;

[0160] The active pattern of the third transistor includes a semiconductor portion;

[0161] An orthographic projection of the gate of the third transistor on the substrate covers an orthographic projection of the semiconductor portion on the substrate.

[0162] In a specific implementation, the display substrate may further include a third transistor, which may be a transistor with a BCE structure. The orthographic projection of the gate of the third transistor on the substrate may cover the orthographic projection of the semiconductor portion included in the active pattern of the third transistor on the substrate, so that the SS (subthreshold swing) of the third transistor can be larger, allowing the third transistor to be fully turned on, and the gate of the third transistor can be used for light shielding to prevent the semiconductor pattern in the active pattern of the third transistor from being illuminated.

[0163] As shown in FIG2A , G3 is the gate electrode of the third transistor, S3 is the first electrode of the third transistor, D3 is the second electrode of the third transistor, and A3 is the active pattern of the third transistor;

[0164] G4 is a gate electrode of the fourth transistor, S4 is a first electrode of the fourth transistor, D4 is a second electrode of the fourth transistor, and A4 is an active pattern of the fourth transistor;

[0165] S3 is in direct contact with A3, D3 is in direct contact with A3, the third transistor is a transistor with a BCE structure, G4 is arranged on one side of the source and drain substrate 10 of A4, and the fourth transistor is a transistor with a top gate structure;

[0166] G1, G3 and G4 are set on the same floor;

[0167] A1 and A4 are set on the same floor, and A2 and A3 are set on the same floor;

[0168] S1, S2, D1, D2, S3, D3, S4 and D4 are set on the same layer.

[0169] In at least one embodiment shown in FIG2A , D3 and S4 are connected, but the present invention is not limited thereto. In a specific implementation, D3 and S4 may also be disconnected.

[0170] As shown in FIG2B , the length labeled L1 is the first length, and the length labeled L2 is the second length;

[0171] The first length L1 is the shortest length of G3 along the horizontal direction, and the second length L2 is the length of the semiconductor portion A30 included in the semiconductor pattern of the third transistor along the horizontal direction;

[0172] The first length L1 is greater than the second length L2.

[0173] Optionally, the first length may be greater than or equal to the second length L2.

[0174] In at least one embodiment shown in FIG2B , the orthographic projection of the gate G3 of the third transistor on the substrate covers the orthographic projection of the semiconductor portion A30 included in the semiconductor pattern of the third transistor on the substrate, so that the SS (subthreshold swing) of the third transistor can be larger, so that the third transistor can be fully turned on, and the gate G3 of the third transistor can be used for shading to prevent the semiconductor A30 pattern in the active pattern of the third transistor from being illuminated.

[0175] In at least one embodiment shown in FIG. 2A and FIG. 2B , when D3 and S4 are disconnected, D3 may be electrically connected to G4 through a via penetrating the passivation layer and the interlayer dielectric layer;

[0176] The second insulating layer 102 may be an interlayer dielectric layer, and the passivation layer may be disposed on a side of the first source / drain metal layer away from the substrate.

[0177] At least one embodiment of the display substrate shown in Figures 1A-2B of the present disclosure utilizes the advantage that transistors with a BCE structure do not require vias to connect the source and drain, and by arranging the first transistor below the second transistor and stacking the first transistor and the second transistor, space for arranging multiple transistors can be saved.

[0178] FIG. 2C is a planar layout diagram of a display substrate according to at least one embodiment of the present disclosure.

[0179] The AA' cross-sectional view in FIG2C is shown in FIG1A to FIG1E , and the BB' cross-sectional view in FIG2C is shown in FIG2A and FIG2B .

[0180] Figure 2D is a layout diagram of the first semiconductor layer in Figure 2C, Figure 2E is a layout diagram of the first gate metal layer in Figure 2C, Figure 2F is a layout diagram of the first source and drain metal layer in Figure 2C, and Figure 2G is a layout diagram of the second semiconductor layer in Figure 2C.

[0181] In at least one embodiment of the present disclosure, the gate of the second transistor is a first gate, and the second transistor further includes a second gate;

[0182] The second gate is disposed on a side of the first electrode of the second transistor away from the substrate.

[0183] In a specific implementation, the second transistor can be a dual-gate transistor, the first gate of the second transistor is arranged on the side of the first electrode of the second transistor close to the substrate, and the second gate of the second transistor is arranged on the side of the first electrode of the second transistor away from the substrate.

[0184] As shown in FIG3A , based on at least one embodiment of the display substrate shown in FIG1A , the display substrate according to at least one embodiment of the present disclosure may further include a passivation layer 103 and a second gate metal layer 15 ;

[0185] As shown in FIG3B , based on at least one embodiment of the display substrate shown in FIG1B , the display substrate according to at least one embodiment of the present disclosure may further include a passivation layer 103 and a second gate metal layer;

[0186] The second gate of the second transistor is labeled G22, and G22 is formed in the second gate metal layer.

[0187] As shown in FIG3C , based on at least one embodiment of the display substrate shown in FIG1E , the display substrate according to at least one embodiment of the present disclosure may further include a passivation layer 103 and a second gate metal layer;

[0188] The second gate of the second transistor is labeled G22, and G22 is formed in the second gate metal layer.

[0189] In at least one embodiment shown in FIG. 3A-FIG . 3B , the second transistor is a dual-gate transistor, which increases the on-current of the second transistor and further reduces the size of the transistor.

[0190] The display substrate according to at least one embodiment of the present disclosure further includes a third transistor (a transistor with a BCE structure); an active pattern of the third transistor is in direct contact with the first electrode of the third transistor, and the active pattern of the third transistor is in direct contact with the second electrode of the third transistor;

[0191] The active pattern of the third transistor includes a semiconductor portion;

[0192] An orthographic projection of the semiconductor portion on the substrate covers an orthographic projection of the gate of the third transistor on the substrate.

[0193] In a specific implementation, the third transistor can be a transistor with a BCE structure, and the active pattern of the third transistor includes a positive projection of the semiconductor part on the substrate, which can cover the positive projection of the gate of the third transistor on the substrate, so as to improve the voltage resistance of the third transistor.

[0194] The display substrate according to at least one embodiment of the present disclosure further includes a third transistor; the active pattern of the third transistor is in direct contact with the first electrode of the third transistor, and the active pattern of the third transistor is in direct contact with the second electrode of the third transistor;

[0195] The third transistor includes two gates;

[0196] One gate of the third transistor is arranged on the same layer as the first gate, another gate of the third transistor is arranged on the same layer as the second gate, and an active pattern of the third transistor is arranged on the same layer as the active pattern of the second transistor.

[0197] In a specific implementation, the third transistor is a transistor with a BCE structure, and the third transistor may be a dual-gate transistor, so as to increase the on-current of the third transistor and further reduce the size of the transistor.

[0198] As shown in FIG4A , reference numeral 10 is the base;

[0199] The first insulating layer is 101, the second insulating layer is 102, and the passivation layer is 103.

[0200] The active pattern labeled A1 is the first transistor, the active pattern labeled A2 is the second transistor, the active pattern labeled A3 is the third transistor, and the active pattern labeled A4 is the fourth transistor;

[0201] G1 is the gate of the first transistor, and the first transistor and the second transistor share a common gate;

[0202] The first gate of the third transistor is labeled G31, the second gate of the third transistor is labeled G32; the gate of the fourth transistor is labeled G4; and the second gate of the second transistor is labeled G22.

[0203] S1 is the first electrode of the first transistor, D1 is the second electrode of the first transistor, S2 is the first electrode of the second transistor, and D2 is the second electrode of the second transistor; S1 is connected to S2, and D1 is connected to D2;

[0204] S3 is a first electrode of a third transistor, D3 is a second electrode of the third transistor, S4 is a first electrode of a fourth transistor, and D4 is a second electrode of the fourth transistor;

[0205] A1 and A4 are set on the same floor, and A2 and A3 are set on the same floor;

[0206] G1, G31 and G4 are set on the same floor;

[0207] G22 and G32 are arranged on the same layer; G22 and G32 are located in the second gate metal layer;

[0208] S1, S2, S3, S4, D1, D2, D3 and D4 are set on the same floor;

[0209] D3 is connected to S4.

[0210] In at least one embodiment shown in FIG4A , the first transistor is a top-gate transistor, the second transistor is a BCE transistor, the third transistor is a BCE transistor, and the fourth transistor is a top-gate transistor.

[0211] The second transistor and the third transistor are dual-gate transistors, which can increase the on-current of the second transistor and the on-current of the third transistor, and further reduce the size of the transistors.

[0212] In FIG4B , the length labeled L1 is the first length, and the length labeled L2 is the second length;

[0213] L2 is larger than L1 to improve the voltage resistance of the third transistor.

[0214] Optionally, L2 may be greater than or equal to L1.

[0215] In at least one embodiment shown in FIG. 4B , A30 is a semiconductor pattern included in the active pattern of the third transistor, L2 is the width of A30 along the horizontal direction, and L1 is the minimum width of G3 along the horizontal direction.

[0216] FIG. 4C is a planar layout diagram of a display substrate according to at least one embodiment of the present disclosure.

[0217] The AA' cross-sectional view in FIG4C is shown in FIG3A to FIG3C, and the BB' cross-sectional view in FIG4C is shown in FIG4A and FIG4B.

[0218] Figure 4D is a layout diagram of the first gate metal layer in Figure 4C, Figure 4E is a layout diagram of the first semiconductor layer in Figure 4C, Figure 4F is a layout diagram of the second semiconductor layer in Figure 4C, Figure 4G is a layout diagram of the first source and drain metal layer in Figure 4C, and Figure 4H is a layout diagram of the second gate metal layer in Figure 4C.

[0219] In at least one embodiment of the present disclosure, the active pattern of the second transistor (transistor with a BCE structure) and the active pattern of the first transistor (transistor with a top-gate structure) are stacked in sequence in a direction away from the substrate.

[0220] Optionally, the gate of the second transistor, the active pattern of the second transistor, the first electrode of the second transistor, the active pattern of the first transistor and the gate of the first transistor are stacked in sequence along a direction away from the substrate.

[0221] In a specific implementation, the active pattern of the second transistor (transistor with a BCE structure) and the active pattern of the first transistor (transistor with a top-gate structure) are stacked in sequence along a direction away from the substrate, and the gate of the second transistor, the active pattern of the second transistor, the first electrode of the second transistor, the active pattern of the first transistor and the gate of the first transistor are stacked in sequence along a direction away from the substrate. That is, the first transistor and the second transistor can be stacked, and the second transistor and the first transistor can be stacked in sequence along a direction away from the substrate, so as to reduce the size occupied by the transistor and save space.

[0222] As shown in Figure 5A, labeled 10 is the substrate, labeled 11 is the first semiconductor layer, labeled 101 is the first insulating layer, labeled 12 is the first gate metal layer, labeled 13 is the second semiconductor layer, labeled 14 is the first source and drain metal layer, labeled 15 is the second gate metal layer, labeled 103 is the passivation layer, and labeled 104 is the third insulating layer.

[0223] As shown in FIG5B , the gate of the first transistor is labeled G2 and is formed in the first gate metal layer;

[0224] The first electrode of the first transistor is labeled S2, and the second electrode of the first transistor is labeled D2; S2 and D2 are formed in the first source-drain metal layer;

[0225] The active pattern labeled A2 is the second transistor, A2 is in direct contact with S2, and A2 is in direct contact with D2;

[0226] The active pattern labeled A1 is the first transistor, and the gate pattern labeled G1 is the first transistor;

[0227] G2, A2, S2, A1 and G1 are stacked in sequence in a direction away from the substrate 10;

[0228] The active pattern A1 of the first transistor includes a conductor portion electrically connected to a second conductive pattern TD2 formed on the first gate metal layer through a conductive pattern TD1 formed on the second gate metal layer;

[0229] The first transistor is a top-gate transistor, and the second transistor is a BCE transistor.

[0230] As shown in FIG5C , based on at least one embodiment shown in FIG5B , the semiconductor portion included in the active pattern of the first transistor is labeled A10, the first conductor portion included in the active pattern of the first transistor is labeled A11, and the second conductor portion included in the active pattern of the first transistor is labeled A12. A11 is multiplexed as the first electrode of the first transistor, and A12 is multiplexed as the second electrode of the first transistor.

[0231] In at least one embodiment shown in FIG. 5A to FIG. 5C , the first transistor and the second transistor are stacked, and the second transistor and the first transistor are stacked in sequence in a direction away from the substrate 10 .

[0232] The display substrate according to at least one embodiment of the present disclosure further includes a light-shielding pattern and a fourth transistor (TG); the fourth transistor includes an active pattern, and the active pattern of the fourth transistor includes a semiconductor portion;

[0233] The gate of the fourth transistor is provided on the same layer as the gate of the first transistor, and the active pattern of the fourth transistor is provided on the same layer as the active pattern of the fourth transistor;

[0234] The orthographic projection of the light-shielding pattern on the substrate at least partially covers the orthographic projection of the semiconductor portion of the fourth transistor on the substrate;

[0235] The light shielding pattern and the first electrode of the second transistor are located in the same layer.

[0236] In a specific implementation, the display substrate may further include a light-shielding pattern and a fourth transistor. The fourth transistor may be a transistor with a top-gate structure. The orthographic projection of the light-shielding pattern on the substrate at least partially covers the orthographic projection of the semiconductor portion of the fourth transistor on the substrate to prevent the semiconductor portion of the fourth transistor from being exposed to light. The light-shielding pattern may be located in the same layer as the first electrode of the second transistor, and the light-shielding pattern may be located in the first source-drain metal layer.

[0237] As shown in Figure 6A, labeled 10 is the substrate, labeled 11 is the first semiconductor layer, labeled 101 is the first insulating layer, labeled 12 is the first gate metal layer, labeled 13 is the second semiconductor layer, labeled 14 is the first source and drain metal layer, labeled 15 is the second gate metal layer, labeled 103 is the passivation layer, and labeled 104 is the third insulating layer.

[0238] In FIG6B , the gate of the first transistor is labeled G2, and G2 is formed in the first gate metal layer;

[0239] The first electrode of the first transistor is labeled S2, and the second electrode of the first transistor is labeled D2; S2 and D2 are formed in the first source-drain metal layer;

[0240] The active pattern labeled A2 is the second transistor, A2 is in direct contact with S2, and A2 is in direct contact with D2;

[0241] The active pattern labeled A1 is the first transistor, and the gate pattern labeled G1 is the first transistor;

[0242] G2, A2, S2, A1 and G1 are stacked in sequence in a direction away from the substrate 10;

[0243] The active pattern A1 of the first transistor includes a conductor portion electrically connected to a second conductive pattern TD2 formed on the first gate metal layer through a conductive pattern TD1 formed on the second gate metal layer;

[0244] The gate electrode of the fourth transistor is labeled G4, the first light-shielding pattern is labeled ZX1, and the active pattern of the fourth transistor is labeled A4;

[0245] The third conductive pattern is labeled TD3, the fourth conductive pattern is labeled TD4; the fifth conductive pattern is labeled TD5, and the sixth conductive pattern is labeled TD6;

[0246] G3 is the gate of the third transistor, A3 is the active pattern of the third transistor, S3 is the first electrode of the third transistor, and D3 is the second electrode of the third transistor.

[0247] G2, TD2, TD4, TD6 and G3 are all located in the first gate metal layer;

[0248] A2 and A3 are both located in the first semiconductor layer;

[0249] S2, D2, ZX1, S3 and D3 are all located in the first source and drain metal layer;

[0250] A1 and A4 are both located in the second semiconductor layer;

[0251] TD1, G1, TD3, G4 and TD5 are all located in the second gate metal layer;

[0252] TD3 is electrically connected to TD4 , and TD5 is electrically connected to TD6 .

[0253] In at least one embodiment shown in FIG. 6C , the orthographic projection of the light-shielding pattern ZX1 on the substrate at least partially covers the orthographic projection of the fourth semiconductor portion A40 on the substrate.

[0254] In at least one embodiment shown in FIG. 6A to FIG. 6C , the first transistor is disposed above the second transistor, and the second transistor and the first transistor are sequentially arranged in a direction away from the substrate 10 to save space occupied by the transistors.

[0255] In at least one embodiment shown in FIG. 6A to FIG. 6C , a gate G4 of the fourth transistor is provided above the semiconductor portion A40 of the active pattern of the fourth transistor, and a first shading pattern ZX1 is provided below the semiconductor portion A40 of the active pattern of the fourth transistor, which has a better shading effect.

[0256] In at least one embodiment shown in FIG. 6A to FIG. 6C , the third transistor is a transistor with a BCE structure, and the fourth transistor is a transistor with a top-gate structure.

[0257] FIG6D is a planar layout diagram of a display substrate according to at least one embodiment of the present disclosure.

[0258] The AA′ cross-sectional view in FIG. 6D is shown in FIG. 5A to FIG. 3C , and the BB′ cross-sectional view in FIG. 6D is shown in FIG. 6A to FIG. 6C .

[0259] Figure 6E is a layout diagram of the first gate metal layer in Figure 6D, Figure 6F is a layout diagram of the first semiconductor layer in Figure 6D, Figure 6G is a layout diagram of the first source and drain metal layer in Figure 6D, Figure 6H is a layout diagram of the second semiconductor layer in Figure 6D, and Figure 6I is a layout diagram of the second gate metal layer in Figure 6D.

[0260] The display substrate according to at least one embodiment of the present disclosure further includes a third transistor (BCE); the third transistor includes a first gate, a second gate, a first electrode, and a second electrode;

[0261] The first gate of the third transistor is provided in the same layer as the gate of the second transistor;

[0262] The active pattern of the third transistor is arranged in the same layer as the active pattern of the second transistor;

[0263] The second gate of the third transistor is arranged in the same layer as the gate of the first transistor.

[0264] In a specific implementation, the third transistor can be a dual-gate transistor, the first gate of the third transistor can be set on the same layer as the gate of the second transistor, the active pattern of the third transistor can be set on the same layer as the active pattern of the second transistor, and the second gate of the third transistor can be set on the same layer as the gate of the first transistor, so as to increase the on-current of the third transistor, further reduce the space occupied by the transistor, and improve the driving capability.

[0265] Compared with at least one embodiment shown in FIG. 6A , in at least one embodiment shown in FIG. 7A , the conductive pattern formed on the first gate metal layer is not directly electrically connected to the conductive pattern formed on the second gate metal layer, the via depth is shallower, and the process difficulty is reduced.

[0266] As shown in Figure 7A, labeled 10 is the substrate, labeled 11 is the first semiconductor layer, labeled 101 is the first insulating layer, labeled 12 is the first gate metal layer, labeled 13 is the second semiconductor layer, labeled 14 is the first source and drain metal layer, labeled 15 is the second gate metal layer, labeled 103 is the passivation layer, and labeled 104 is the third insulating layer.

[0267] In FIG7B , G2 is the gate electrode of the second transistor, A2 is the active pattern of the second transistor, S2 is the first electrode of the second transistor, and D2 is the second electrode of the second transistor;

[0268] The gate electrode of the first transistor is labeled G1, the active pattern of the first transistor is labeled A1, and the first conductive pattern is labeled TD1;

[0269] A4 is an active pattern of a fourth transistor, G4 is a gate of the fourth transistor, TD2 is a second conductive pattern, and TD4 is a fourth conductive pattern;

[0270] G31 is a first gate of the third transistor, S3 is a first electrode of the third transistor, D3 is a second electrode of the third transistor, and A3 is an active pattern of the third transistor; TD3 is a third conductive pattern, and G32 is a second gate of the third transistor.

[0271] G2 and G31 are both located in the first gate metal layer, A2 and A3 are both located in the first semiconductor layer, A1 and A4 are both located in the second semiconductor layer, G1, G4 and G32 are all located in the second gate metal layer, TD1, TD2, TD3 and G4 are all located in the second gate metal layer; TD4, S2, D2, S3 and D3 are all located in the first source and drain metal layer.

[0272] In at least one embodiment shown in FIG. 7B , the first transistor is a top-gate transistor, the second transistor is a BCE transistor, the third transistor is a BCE transistor, and the fourth transistor is a top-gate transistor.

[0273] TD1 is electrically connected to S2 , TD2 is electrically connected to TD4 , and TD3 is electrically connected to S3 .

[0274] In at least one embodiment shown in FIG. 7A and FIG. 7B , the first transistor and the second transistor are stacked, and the second transistor and the first transistor are stacked in sequence in a direction away from the substrate 10 .

[0275] FIG. 7C is a planar layout diagram of a display substrate according to at least one embodiment of the present disclosure.

[0276] The BB' cross-sectional view in FIG7C is shown in FIG7A and FIG7B.

[0277] Figure 7D is a layout diagram of the first gate metal layer in Figure 7C, Figure 7E is a layout diagram of the first semiconductor layer in Figure 7C, Figure 7F is a layout diagram of the first source and drain metal layer in Figure 7C, Figure 7G is a layout diagram of the second semiconductor layer in Figure 7C, and Figure 7H is a layout diagram of the second gate metal layer in Figure 7C.

[0278] Optionally, the first transistor includes a gate, a first electrode and a second electrode;

[0279] The first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the second transistor and the second electrode of the second transistor are arranged in the same layer;

[0280] The gate of the second transistor, the active pattern of the second transistor, the first electrode of the second transistor, the active pattern of the first transistor and the gate of the first transistor are stacked in sequence along a direction away from the substrate.

[0281] In a specific implementation, the first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the second transistor, and the second electrode of the second transistor may be provided in the same layer to reduce the number of masks used.

[0282] As shown in Figure 8A, labeled 10 is the substrate, labeled 11 is the first semiconductor layer, labeled 101 is the first insulating layer, labeled 12 is the first gate metal layer, labeled 13 is the second semiconductor layer, labeled 14 is the first source and drain metal layer, labeled 15 is the second gate metal layer, labeled 103 is the passivation layer, and labeled 104 is the third insulating layer.

[0283] As shown in FIG8B , the gate of the first transistor is labeled G1 , and the active pattern of the first transistor is labeled A1 ;

[0284] The gate of the second transistor is labeled G2, and the active pattern of the second transistor is labeled A2;

[0285] The first electrode of the second transistor is labeled S2, and the second electrode of the second transistor is labeled D2; the first electrode of the first transistor is labeled S1, and the second electrode of the first transistor is labeled D1; A2 is connected to S2, and A2 is connected to D2; G1 is arranged on the side of A1 away from the substrate 10;

[0286] The first transistor is a top-gate transistor, and the second transistor is a BCE transistor.

[0287] In at least one embodiment shown in FIG. 8B , S1 , D1 , S2 , and D2 are all located in the first source / drain metal layer 14 ;

[0288] G2 , A2 , S2 , A1 , and G1 are sequentially stacked along a side away from the substrate 10 .

[0289] In at least one embodiment shown in FIG. 8B , the first transistor is disposed above the second transistor to reduce the size occupied by the transistor and save space.

[0290] In at least one embodiment of the present disclosure, the active pattern of the first transistor includes a first conductor portion and a second conductor portion;

[0291] The first conductor portion of the first transistor is electrically connected to the first electrode of the first transistor through a via hole, and the second conductor portion of the first transistor is electrically connected to the second electrode of the first transistor through a via hole.

[0292] In a specific implementation, the active pattern of the first transistor may include a first conductor portion and a second conductor portion; the first conductor portion of the first transistor is electrically connected to the first electrode of the first transistor through a via, and the second conductor portion of the first transistor is electrically connected to the second electrode of the first transistor through a via.

[0293] As shown in FIG8C , based on at least one embodiment shown in FIG8B , the first conductor portion in the active pattern of the first transistor is labeled A11 , the second conductor portion in the active pattern of the first transistor is labeled A12 , and the semiconductor portion of the active pattern of the first transistor is labeled A10 ;

[0294] A11 is electrically connected to the first electrode S1 of the first transistor through a via in a bottom-lap manner; A12 is electrically connected to the second electrode D1 of the first transistor through a via in a bottom-lap manner, so as to save the number of masks and the size of the via, save space and achieve lower cost.

[0295] In at least one embodiment shown in Figures 8A-8C, the first electrode S1 of the first transistor is electrically connected to the first electrode S2 of the second transistor, and the second electrode D1 of the first transistor is electrically connected to the second electrode D2 of the second transistor, but the present invention is not limited thereto. In a specific implementation, the first electrode S1 of the first transistor and the first electrode S2 of the second transistor may not be electrically connected to each other, and the second electrode D1 of the first transistor and the second electrode D2 of the second transistor may not be electrically connected to each other.

[0296] The display substrate according to at least one embodiment of the present disclosure further includes a light-shielding pattern and a fourth transistor (TG);

[0297] The fourth transistor includes a first gate, a second gate and an active pattern;

[0298] The light shielding pattern is provided in the same layer as the first electrode of the first transistor;

[0299] The first gate of the fourth transistor is provided at the same layer as the gate of the first transistor, and the second gate of the fourth transistor is provided at the same layer as the gate of the second transistor;

[0300] The active pattern of the fourth transistor is arranged in the same layer as the active pattern of the first transistor;

[0301] An orthographic projection of the light-shielding pattern on the substrate at least partially overlaps with an orthographic projection of a semiconductor portion of the active pattern of the fourth transistor on the substrate.

[0302] In a specific implementation, the display substrate may further include a light-shielding pattern and a fourth transistor; the fourth transistor is a dual-gate transistor, the fourth transistor is a top-gate structure transistor, the first gate of the fourth transistor is arranged on the same layer as the gate of the first transistor, and the second gate of the fourth transistor is arranged on the same layer as the gate of the second transistor, the light-shielding pattern may be arranged on the same layer as the first electrode of the first transistor to reduce the number of masks used; the light-shielding pattern may prevent the semiconductor portion of the fourth transistor from being exposed to light.

[0303] The display substrate according to at least one embodiment of the present disclosure further includes a third transistor (BCE);

[0304] The third transistor includes a first gate, a second gate, a first electrode, a second electrode and an active pattern;

[0305] The first gate is provided at the same layer as the gate of the first transistor, and the second gate is provided at the same layer as the gate of the second transistor;

[0306] The first electrode of the third transistor, the second electrode of the third transistor and the first electrode of the first transistor are arranged in the same layer;

[0307] The active pattern of the third transistor is arranged in the same layer as the active pattern of the second transistor;

[0308] The active pattern of the third transistor is in direct contact with the first electrode of the third transistor, and the active pattern of the third transistor is in direct contact with the second electrode of the third transistor.

[0309] In a specific implementation, the display substrate may further include a third transistor, which may be a dual-gate transistor. The third transistor is a transistor with a BCE structure, wherein the first gate is arranged on the same layer as the gate of the first transistor, and the second gate is arranged on the same layer as the gate of the second transistor; the first electrode of the third transistor and the second electrode of the third transistor are arranged on the same layer as the first electrode of the first transistor; and the active pattern of the third transistor is arranged on the same layer as the active pattern of the second transistor, so as to reduce the number of masks used.

[0310] As shown in Figure 9A, labeled 10 is the substrate, labeled 11 is the first semiconductor layer, labeled 101 is the first insulating layer, labeled 12 is the first gate metal layer, labeled 13 is the second semiconductor layer, labeled 14 is the first source and drain metal layer, labeled 15 is the second gate metal layer, labeled 103 is the passivation layer, and labeled 104 is the third insulating layer.

[0311] In FIG9B , the gate of the first transistor is labeled G1 , and the active pattern of the first transistor is labeled A1 ;

[0312] The gate of the second transistor is labeled G2, and the active pattern of the second transistor is labeled A2;

[0313] The first electrode of the second transistor is labeled S2, and the second electrode of the second transistor is labeled D2; the first electrode of the first transistor is labeled S1, and the second electrode of the first transistor is labeled D1; A2 is connected to S2, and A2 is connected to D2; G1 is arranged on the side of A1 away from the substrate 10;

[0314] The first transistor is a top-gate transistor, and the second transistor is a BCE transistor;

[0315] The first gate of the fourth transistor is labeled G41, the second gate of the fourth transistor is labeled G42; the seventh conductive pattern is labeled TD7;

[0316] The second light-shielding pattern is labeled ZX2, and the active pattern of the fourth transistor is labeled A4;

[0317] The fourth transistor is a top-gate transistor;

[0318] G31 is a first gate of the third transistor, G32 is a second gate of the third transistor, A3 is an active pattern of the third transistor, S3 is a first electrode of the third transistor, and D3 is a second electrode of the third transistor; A3 is in direct contact with S3, and A3 is in direct contact with D3.

[0319] The third transistor is a transistor with a BCE structure.

[0320] As shown in Figure 9B , G2, TD7, G41, and G31 are set up on the same layer;

[0321] ZX2, S1, D1, S2, D2, S3 and D3 are set on the same layer;

[0322] GT1, G42 and G32 are set on the same level;

[0323] A2 and A3 are set on the same layer; A1 and A4 are set on the same layer.

[0324] In at least one embodiment shown in FIG9B , the first electrode S3 of the third transistor is arranged on the same layer as the second light-shielding pattern ZX2, and the active pattern A4 of the fourth transistor is electrically connected to S3 and TD7 respectively by a bottom overlap method. At least one embodiment shown in FIG9B of the present disclosure adopts a bottom overlap method, which saves the number of masks and the size of the vias, saves space and is low in cost.

[0325] As shown in FIG9C , based on at least one embodiment shown in FIG9B , the semiconductor portion of the active pattern of the fourth transistor is labeled A40 , the first conductor portion of the active pattern of the fourth transistor is labeled A41 , and the second conductor portion of the active pattern of the fourth transistor is labeled A42 .

[0326] A41 is electrically connected to TD7 through a bottom overlap, and A42 is electrically connected to S3 through a bottom overlap.

[0327] FIG. 9D is a planar layout diagram of a display substrate according to at least one embodiment of the present disclosure.

[0328] The AA′ cross-sectional view in FIG. 9D is shown in FIG. 8A to FIG. 8C , and the BB′ cross-sectional view in FIG. 9D is shown in FIG. 9A to FIG. 9C .

[0329] Figure 9E is a layout diagram of the first gate metal layer in Figure 9D, Figure 9F is a layout diagram of the first semiconductor layer in Figure 9D, Figure 9G is a layout diagram of the first source and drain metal layer in Figure 9D, Figure 9H is a layout diagram of the second semiconductor layer in Figure 9D, and Figure 9I is a layout diagram of the second gate metal layer in Figure 9D.

[0330] In FIG. 9H , the active pattern labeled A4 is the fourth transistor.

[0331] In at least one embodiment of the present disclosure, the first transistor and the second transistor share an active pattern; the second transistor further includes a gate, a first electrode, and a second electrode;

[0332] The gate of the second transistor, the active pattern, the first electrode of the second transistor and the gate of the first transistor are arranged in sequence along a direction away from the substrate.

[0333] In a specific implementation, the first and second transistors can share active patterns to minimize the number and space of masks. The first transistor is a top-gate transistor, and the second transistor is a BCE transistor. The gate of the first transistor is located on a side of the gate of the second transistor that is away from the substrate. The first and second transistors are stacked on the substrate to reduce the size occupied by the transistors and save space.

[0334] In Figure 10A, the number 10 is the substrate, the number 11 is the first semiconductor layer, the number 101 is the first insulating layer, the number 12 is the first gate metal layer, the number 14 is the first source and drain metal layer, the number 15 is the second gate metal layer, and the number 103 is the passivation layer.

[0335] As shown in FIG10B , the first transistor and the second transistor share an active pattern, and the active pattern labeled A2 is the active pattern of the second transistor. The first transistor and the second transistor share A2;

[0336] G1 is the gate of the first transistor, G2 is the gate of the second transistor, S2 is the first electrode of the second transistor, and D2 is the second electrode of the second transistor;

[0337] G1 is located in the first gate metal layer, G2 is located in the second gate metal layer, S2 is in direct contact with A2, and D2 is in direct contact with A2.

[0338] The display substrate according to at least one embodiment of the present disclosure further includes a third transistor (BCE) and a fourth transistor (TG);

[0339] The gate of the fourth transistor is provided in the same layer as the gate of the first transistor;

[0340] The third transistor includes a first gate, an active pattern, a first electrode and a second electrode;

[0341] The first gate of the third transistor is provided in the same layer as the gate of the second transistor;

[0342] The active pattern of the third transistor, the active pattern of the fourth transistor and the active pattern of the first transistor are arranged in the same layer;

[0343] The active pattern of the third transistor is in direct contact with the first electrode of the third transistor, and the active pattern of the third transistor is in direct contact with the second electrode of the third transistor.

[0344] In a specific implementation, the display substrate may further include a third transistor and a fourth transistor, the third transistor being a transistor with a BCE structure, the fourth transistor being a transistor with a top-gate structure, the active pattern of the first transistor, the active pattern of the third transistor, and the active pattern of the fourth transistor being arranged on the same layer, the gate of the second transistor and the first gate of the third transistor being arranged on the same layer, and the gate of the first transistor and the gate of the fourth transistor being arranged on the same layer, so as to reduce the number of masks used.

[0345] In at least one embodiment of the present disclosure, the third transistor further includes a second gate;

[0346] The second gate of the third transistor is provided in the same layer as the gate of the first transistor;

[0347] An orthographic projection of the second gate of the third transistor on the substrate covers an orthographic projection of a semiconductor pattern included in the active pattern of the third transistor on the substrate.

[0348] In a specific implementation, the third transistor can be a dual-gate transistor, and the third transistor can include a first gate and a second gate. The second gate of the third transistor is arranged on the same layer as the gate of the first transistor, and the orthographic projection of the second gate of the third transistor on the substrate covers the orthographic projection of the semiconductor pattern included in the active pattern of the third transistor on the substrate to block light.

[0349] In Figure 11A, the number 10 is the substrate, the number 11 is the first semiconductor layer, the number 101 is the first insulating layer, the number 12 is the first gate metal layer, the number 14 is the first source and drain metal layer, the number 15 is the second gate metal layer, and the number 103 is the passivation layer.

[0350] In FIG11B , the first transistor and the second transistor share an active pattern, labeled A2 is the active pattern of the second transistor, and the first transistor and the second transistor share A2;

[0351] G1 is the gate of the first transistor, G2 is the gate of the second transistor, S2 is the first electrode of the second transistor, and D2 is the second electrode of the second transistor;

[0352] The gate electrode of the fourth transistor is labeled G4, and the active pattern of the fourth transistor is labeled A4;

[0353] G31 is a first gate of the third transistor, G32 is a second gate of the third transistor, A3 is an active pattern of the third transistor, S3 is a first electrode of the third transistor, and D3 is a second electrode of the third transistor;

[0354] The first transistor and the fourth transistor are top-gate transistors, the second transistor and the third transistor are BCE transistors; the third transistor is a dual-gate transistor;

[0355] G2 and G31 are set on the same layer, G1, G4 and G32 are set on the same layer; A2, A4 and A3 are set on the same layer; S2, D2, S3 and D3 are set on the same layer.

[0356] As shown in FIG11C , based on at least one embodiment shown in FIG11B , the semiconductor portion of the active pattern of the fourth transistor is labeled A40 , the first conductor portion of the active pattern of the fourth transistor is labeled A41 , and the second conductor portion of the active pattern of the fourth transistor is labeled A42 .

[0357] A semiconductor portion of the active pattern of the third transistor is designated A30 , a first conductor portion of the active pattern of the third transistor is designated A31 , and a second conductor portion of the active pattern of the third transistor is designated A32 .

[0358] The orthographic projection of G32 on the substrate covers the orthographic projection of A30 on the substrate. G32 can be used to shield A30 to prevent the conductor of the top-gate structure transistor from damaging the channel of the BCE structure transistor.

[0359] In at least one embodiment shown in FIG. 11C , G32 can be connected to an electrical signal or be in a floating state.

[0360] As shown in FIG. 11C , S3 is electrically connected to A42 , but the present invention is not limited thereto.

[0361] FIG. 11D is a planar layout diagram of a display substrate according to at least one embodiment of the present disclosure.

[0362] The AA′ cross-sectional view in FIG. 11D is shown in FIG. 10A-FIG 10B , and the BB′ cross-sectional view in FIG. 11D is shown in FIG. 11A-FIG 11C .

[0363] Figure 11E is a layout diagram of the first gate metal layer in Figure 11D, Figure 11F is a layout diagram of the first semiconductor layer in Figure 11D, Figure 11G is a layout diagram of the first source and drain metal layer in Figure 11D, and Figure 11H is a layout diagram of the second gate metal layer in Figure 11D.

[0364] In FIG. 11F , the active pattern labeled A4 is the fourth transistor, and the active pattern labeled A3 is the third transistor.

[0365] In at least one embodiment of the present disclosure, the active layer material of the first transistor and the active layer material of the fourth transistor may be an oxide material or an LTPS (low temperature polysilicon) material;

[0366] The active layer pattern of the second transistor and the active layer pattern of the third transistor may be an oxide material or an amorphous silicon (a-Si) material;

[0367] The metal oxide semiconductor material may include one or more of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), and rare earth doped oxide (Ln-OS). The active layer material may be amorphous, partially crystalline, single crystal, or polycrystalline, and may have a single-layer or multi-layer structure.

[0368] Because of their relatively weak stability, BCE structure transistors are mainly used as switching transistors in pixel circuits, and only need to ensure switching characteristics and low leakage current characteristics.

[0369] The display device described in the embodiment of the present disclosure includes the above-mentioned display substrate.

[0370] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising a substrate, and a first transistor and a second transistor disposed on the substrate; the second transistor includes a gate, a first electrode, and a second electrode; The active pattern of the first transistor and the active pattern of the second transistor are stacked on the substrate; or, the first transistor and the second transistor share an active pattern, and the gate of the first transistor is stacked with the active pattern of the second transistor on the substrate; A gate of the first transistor is located on a side of the active pattern of the first transistor away from the substrate; the active pattern of the second transistor is in direct contact with the first electrode of the second transistor, and the active pattern of the second transistor is in direct contact with the second electrode of the second transistor.

2. The display substrate according to claim 1, wherein, The active pattern of the first transistor and the active pattern of the second transistor are sequentially stacked along a direction away from the substrate.

3. The display substrate according to claim 2, wherein, The first transistor and the second transistor share a gate.

4. The display substrate according to claim 3, wherein, The first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the second transistor, and the second electrode of the second transistor are disposed in the same layer.

5. The display substrate according to claim 3, wherein, The active pattern of the first transistor includes a semiconductor portion and a conductor portion; the first electrode of the first transistor is located in a first metal layer; the active pattern of the first transistor is located in a first semiconductor layer, the active pattern of the second transistor is located in a second semiconductor layer, and the first semiconductor layer, the second semiconductor layer, and the first metal layer are sequentially stacked along a direction away from the substrate; At least a part of the orthographic projection of the conductor portion on the substrate is covered by a pattern formed in the first metal layer and / or a pattern formed in the second semiconductor layer.

6. The display substrate according to claim 5, wherein, It further includes a passivation layer disposed on a side of the first metal layer away from the substrate.

7. The display substrate according to claim 3, wherein The gate of the second transistor is a first gate, and the second transistor further includes a second gate; The second gate is disposed on a side of the first electrode of the second transistor away from the substrate.

8. The display substrate according to any one of claims 2 to 7, wherein It further includes a third transistor; the active pattern of the third transistor is in direct contact with the first electrode of the third transistor, and the active pattern of the third transistor is in direct contact with the second electrode of the third transistor; The active pattern of the third transistor includes a semiconductor portion; The orthographic projection of the gate of the third transistor on the substrate covers the orthographic projection of the semiconductor portion on the substrate.

9. The display substrate according to any one of claims 2 to 7, wherein It further includes a third transistor; the active pattern of the third transistor is in direct contact with the first electrode of the third transistor, and the active pattern of the third transistor is in direct contact with the second electrode of the third transistor; The active pattern of the third transistor includes a semiconductor portion; The orthographic projection of the semiconductor portion on the substrate covers the orthographic projection of the gate of the third transistor on the substrate.

10. The display substrate according to claim 7, wherein, It further includes a third transistor; the active pattern of the third transistor is in direct contact with the first electrode of the third transistor, and the active pattern of the third transistor is in direct contact with the second electrode of the third transistor; The third transistor includes two gates; One gate of the third transistor is disposed on the same layer as the first gate, another gate of the third transistor is disposed on the same layer as the second gate, and the active pattern of the third transistor is disposed on the same layer as the active pattern of the second transistor.

11. The display substrate according to claim 1, wherein, The active pattern of the second transistor and the active pattern of the first transistor are stacked in sequence along the direction away from the substrate.

12. The display substrate according to claim 11, wherein, The gate of the second transistor, the active pattern of the second transistor, the first electrode of the second transistor, the active pattern of the first transistor, and the gate of the first transistor are stacked in sequence along the direction away from the substrate.

13. The display substrate according to claim 12, wherein, It further includes a light-shielding pattern and a fourth transistor; the fourth transistor includes an active pattern, and the active pattern of the fourth transistor includes a semiconductor portion; The gate of the fourth transistor is disposed on the same layer as the gate of the first transistor, and the active pattern of the fourth transistor is disposed on the same layer as the active pattern of the fourth transistor; The orthographic projection of the light-shielding pattern on the substrate at least partially covers the orthographic projection of the semiconductor portion of the fourth transistor on the substrate; The light-shielding pattern and the first electrode of the second transistor are on the same layer.

14. The display substrate according to claim 12, wherein, It further includes a third transistor; the third transistor includes a first gate, a second gate, a first electrode, and a second electrode; The first gate of the third transistor is disposed on the same layer as the gate of the second transistor; The active pattern of the third transistor is disposed on the same layer as the active pattern of the second transistor; The second gate of the third transistor is disposed on the same layer as the gate of the first transistor.

15. The display substrate according to claim 11, wherein, The first transistor includes a gate, a first electrode, and a second electrode; The first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the second transistor, and the second electrode of the second transistor are on the same layer; The gate of the second transistor, the active pattern of the second transistor, the first electrode of the second transistor, the active pattern of the first transistor, and the gate of the first transistor are stacked in sequence along the direction away from the substrate.

16. The display substrate according to claim 15, wherein, The active pattern of the first transistor includes a first conductor portion and a second conductor portion; The first conductor portion of the first transistor is electrically connected to the first electrode of the first transistor through a via, and the second conductor portion of the first transistor is electrically connected to the second electrode of the first transistor through a via.

17. The display substrate according to claim 15, wherein, It further includes a light-shielding pattern and a fourth transistor; The fourth transistor includes a first gate, a second gate, and an active pattern; The light-shielding pattern is on the same layer as the first electrode of the first transistor; The first gate of the fourth transistor is disposed on the same layer as the gate of the first transistor, and the second gate of the fourth transistor is disposed on the same layer as the gate of the second transistor; The active pattern of the fourth transistor is disposed on the same layer as the active pattern of the first transistor; The orthographic projection of the light-shielding pattern on the substrate and the orthographic projection of the semiconductor portion in the active pattern of the fourth transistor on the substrate at least partially overlap.

18. The display substrate according to claim 15, wherein, It further includes a third transistor; The third transistor includes a first gate, a second gate, a first electrode, a second electrode, and an active pattern; The first gate is disposed on the same layer as the gate of the first transistor, and the second gate is disposed on the same layer as the gate of the second transistor; The first electrode of the third transistor and the second electrode of the third transistor are disposed on the same layer as the first electrode of the first transistor; The active pattern of the third transistor is disposed on the same layer as the active pattern of the second transistor; The active pattern of the third transistor is in direct contact with the first electrode of the third transistor, and the active pattern of the third transistor is in direct contact with the second electrode of the third transistor.

19. The display substrate according to claim 1, wherein, The first transistor and the second transistor share an active pattern; the second transistor further includes a gate, a first electrode, and a second electrode; The gate of the second transistor, the active pattern, the first electrode of the second transistor, and the gate of the first transistor are arranged in sequence along a direction away from the substrate.

20. The display substrate according to claim 19, wherein, It further includes a third transistor and a fourth transistor; The gate of the fourth transistor is disposed on the same layer as the gate of the first transistor; The third transistor includes a first gate, an active pattern, a first electrode, and a second electrode; The first gate of the third transistor is disposed on the same layer as the gate of the second transistor; The active pattern of the third transistor and the active pattern of the fourth transistor are disposed on the same layer as the active pattern of the first transistor; The active pattern of the third transistor is in direct contact with the first electrode of the third transistor, and the active pattern of the third transistor is in direct contact with the second electrode of the third transistor.

21. The display substrate according to claim 20, wherein, The third transistor further includes a second gate; The second gate of the third transistor is disposed on the same layer as the gate of the first transistor; The orthographic projection of the second gate of the third transistor on the substrate covers the orthographic projection of the semiconductor pattern included in the active pattern of the third transistor on the substrate.

22. A display device, comprising a display substrate according to any one of claims 1 to 21.

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