Manufacturing method for printed wiring board

Abstract

Provided is a manufacturing method for a printed wiring board that makes it possible to prevent enlargement of copper particles due to heat treatment and achieve sufficient roughening via chemical etching, even at a location where there is a scratch. This manufacturing method includes: preparing a support substrate comprising an insulating layer, a peeling layer, and a copper layer, in that order; forming a wiring pattern on the copper layer; subjecting the support substrate on which the wiring pattern has been formed to heat treatment and chemical etching treatment; forming a build-up wiring layer on the copper layer; separating the insulating layer from the support substrate having the build-up wiring layer via the peeling layer; removing the copper layer by subjecting the separated build-up wiring layer to flash etching; and coating the obtained build-up wiring layer with a resin. If the copper layer used in the support substrate is scratched at a spherical tip of a metal pin on the surface thereof, and is thereafter subjected to heat treatment at 170°C for 30 minutes under an air atmosphere, the cross-sectional crystal grain size at the scratched location is 1.5 μm or less.

Description

Printed wiring board manufacturing method

[0001] The present invention relates to a method for manufacturing a printed wiring board.

[0002] A coreless build-up method has been adopted as a manufacturing method for printed wiring boards suitable for reducing weight and size, which involves forming a wiring layer on a metal layer on the surface of a support substrate (called a dummy core), forming a build-up layer, and then separating the support.Since the printed wiring board manufactured by this method is of the type in which the circuit pattern is embedded in an insulating layer, this method is called the ETS (Embedded Trace Substrate) method.

[0003] 1A and 1B show a typical example of the ETS method. In this typical example, a support substrate 10 (dummy core) is first prepared, which includes an insulating layer 12, a release layer 14, and a copper layer 16, in that order (see FIG. 1A(a)). In the illustrated example, the release layer 14 and the copper layer 16 are provided in the form of a carrier-attached copper foil 20. Therefore, a carrier 18 is present between the insulating layer 12 and the release layer 14, and the copper layer 16 corresponds to the ultrathin copper foil of the carrier-attached copper foil 20. Next, a photoresist pattern is formed on the copper layer 16, followed by pattern plating (electrolytic copper plating) and peeling of the photoresist pattern, forming a wiring pattern 22 (see FIG. 1A(b)). Then, as a pre-lamination process, the pattern plating is subjected to a roughening treatment using chemical etching to form a first wiring layer. Thereafter, an insulating layer 24 is laminated to form a build-up wiring layer 34, and, if necessary, a carrier-attached copper foil 26 (comprising a carrier 28, a release layer 30, and a copper foil 32) is laminated to serve as a seed layer for the second wiring layer (see FIG. 1A(c)). The carrier 28 is peeled off, and holes are drilled in the copper foil 32 and the insulating layer 24 directly below it using a laser or the like. Subsequently, patterning is performed using chemical copper plating, photoresist processing, electrolytic copper plating, photoresist peeling, etc. (further flash etching is performed as necessary) to form a second wiring layer as a wiring pattern 22 (see FIG. 1A(d)). This patterning and optional flash etching are repeated as necessary to form up to the nth wiring layer (n is an integer of 2 or greater), thereby forming a build-up wiring layer 34. The insulating layer 12 is then separated from the support substrate 10 with the build-up wiring layer 34 via the release layer 14, along with the carrier 18 (see FIG. 1B(e)). After removing the support substrate 10 (dummy core) in this manner, the copper layer 16 exposed between the wiring patterns 22 of the first wiring layer, and, if present, the copper foil 32, etc. exposed between the wiring patterns 22 of the nth wiring layer, are removed by flash etching to form a predetermined wiring pattern (see FIG. 1B(f)). Finally, the build-up wiring layer 34 is covered with a resin 36 such as a photo solder resist to obtain a printed wiring board 38 (see FIG. 1B(g)).

[0004] Various documents disclosing the ETS method are known. For example, Patent Document 1 (JP 2005-101137 A) discloses a method for manufacturing a package substrate for mounting a semiconductor element, including: (a) forming a support substrate for forming a circuit in which a first insulating resin is provided on the carrier foil surface of an ultra-thin copper foil with a carrier foil, (b) forming a first wiring conductor by patterned electrolytic copper plating, (c) arranging a second insulating resin so as to contact the first wiring conductor and laminating them by heating and pressurizing, (d) forming blind holes in the second insulating resin that reach the first wiring conductor, and connecting the inner walls of the blind holes by electrolytic copper plating or electroless copper plating to form second wiring conductors, (e) peeling off the support substrate with the carrier foil, and (f) removing the ultra-thin copper foil. In addition, Patent Document 2 (JP 2017-25405 A) teaches that by using a carrier-attached copper foil in which the average grain size of the crystal grains constituting the ultrathin copper layer is 1.05 μm or more and 6.5 μm or less and the ten-point mean roughness Rz of the ultrathin copper layer side surface is 0.1 μm or more and 2.0 μm or less in the ETS method, the chemical etching uniformity, adhesion to the dry film, and etching rate are improved, and as a result, circuit formability is improved.

[0005] Meanwhile, there are known methods for controlling the size of copper crystal grains constituting an electrolytic copper foil. For example, Patent Document 3 (WO2022 / 202539) describes a method for controlling the size of copper crystal grains constituting an electrolytic copper foil, using a sulfuric acid-based copper electrolyte in which the copper concentration is 40 g / L or more and 80 g / L or less, the sulfuric acid concentration is 180 g / L or more and 260 g / L or less, and the concentration of carboxybenzotriazole (CBTA) as an additive is adjusted to more than 0 ppm and 200 ppm or less, using a DSA (dimensionally stable anode) as the anode, and conducting electrolytic copper foil at a solution temperature of 35° C. or more and 60° C. or less and a current density of 3 A / dm ２ More than 60A / dm ２ It is disclosed that by electrolysis using the following method, an ultra-thin copper foil composed of copper crystal grains having a predetermined crystal size can be obtained.

[0006] JP 2005-101137 A JP 2017-25405 A WO2022 / 202539

[0007] As described above, in the ETS method, a support substrate 10 serving as a dummy core is formed by attaching a carrier-attached copper foil 20 to an insulating layer 12 with the copper layer 16 (ultrathin copper foil) facing outward (see FIG. 1A(a)). However, scratches may occur on the surface of the copper layer 16 during handling of the support substrate 10. If the copper layer 16 is made by conventional copper plating, there is a risk that stress caused by the scratches will accelerate recrystallization of copper crystals, adversely affecting subsequent processes. Specifically, as described above, after forming a wiring pattern 22 on the support substrate 10 (see FIG. 1A(b)), the support substrate 10 is subjected to heat treatment (baking) and chemical etching (roughening treatment) (between FIGS. 1A(b) and 1A(c)). 2A, if scratches S are present in the copper layer 16 (see FIG. 2A(i)), recrystallization R (due to the stress caused by the scratches S) will progress in the area of ​​the scratches S during the heat treatment (baking), causing the copper crystals to enlarge (see FIG. 2A(ii)), and the area of ​​the scratches S will not be roughened sufficiently during the subsequent chemical etching (roughening treatment). As a result, the area of ​​the copper layer 16 with the scratches S will be smoother than the area without the scratches (see FIG. 2A(iii)), which runs the risk of adversely affecting subsequent processes.

[0008] The present inventors have now discovered that, in the manufacture of printed wiring boards using the ETS method, by using a support substrate having a copper layer in which the cross-sectional crystal grain size at the scratched location is 1.5 μm or less when scratched and subjected to a specified heat treatment, it is possible to prevent the copper particles from enlarging due to heat treatment even in scratched locations, and to achieve sufficient roughening by chemical etching.

[0009] Therefore, an object of the present invention is to provide a method for manufacturing a printed wiring board that can prevent copper particles from enlarging due to heat treatment even in scratched areas and achieve sufficient roughening by chemical etching.

[0010] According to the present invention, the following aspects are provided. a heat treatment of the support substrate on which the wiring pattern is formed; a chemical etching treatment of the wiring pattern and the copper layer exposed between the wiring patterns; a build-up wiring layer formed on the copper layer that has been subjected to the chemical etching treatment, thereby producing a support substrate with a build-up wiring layer; a process of separating the insulating layer from the support substrate with the build-up wiring layer via the release layer; a process of flash etching the build-up wiring layer from which the insulating layer has been separated to remove the copper layer; and a process of covering the build-up wiring layer from which the copper layer has been removed with a resin. [Aspect 2] The method for manufacturing a printed wiring board according to Aspect 1, wherein the cross-sectional crystal grain size D of the copper layer at the scratched portion after the heat treatment at 170°C for 30 minutes is 0.1 μm or more and 1.5 μm or less. [Aspect 3] The cross-sectional crystal grain size D of the copper layer at the scratched portion after the heat treatment at 170°C for 30 minutes Ａ The cross-sectional grain size D at the unscratched portion of Ｂ The increase rate is 100% or less with respect to [(D Ａ -D Ｂ ) / D Ｂ ) × 100。 [Aspect 4] The method for manufacturing a printed wiring board according to any one of Aspects 1 to 3, wherein the support substrate includes a copper foil with a carrier, the carrier is located between the insulating layer and the release layer, and the copper foil corresponds to the copper layer.

[0011] 1A ] is a process flow diagram for explaining the ETS method. FIG. 1B is a process flow diagram (continuation of FIG. 1A ) for explaining the ETS method. FIG. 1C is a process flow diagram (continuation of FIG. 2A ) for explaining the adverse effects of scratched portions of a support substrate. FIG. 2D is a process flow diagram (continuation of FIG. 2A ) for explaining the adverse effects of scratched portions of a support substrate. FIG. 3E is a photograph showing a jig used to form scratches in Examples 1 and 2. FIG. 3F is an enlarged photograph of the metal pin shown in FIG. 3A . FIG. 3F is an SEM image taken of a cross section of a non-scratched portion of the ultra-thin copper foil after heat treatment in Example 1. FIG. 3G is an SEM image of a surface of a non-scratched portion of the ultra-thin copper foil after roughening treatment in Example 1. FIG. 3H is an SEM image of a cross section of a scratched portion of the ultra-thin copper foil after heat treatment in Example 1. FIG. 3I is an SEM image of a surface of a scratched portion of the ultra-thin copper foil after roughening treatment in Example 1. 1 is an SEM image of a cross section of a portion of the ultrathin copper foil after heat treatment in Example 2 (comparison). 2 is an SEM image of a portion of the surface of a portion of the ultrathin copper foil after roughening treatment in Example 2 (comparison). 3 is an SEM image of a cross section of a portion of the ultrathin copper foil after heat treatment in Example 2 (comparison). 4 is an SEM image of a portion of the surface of a portion of the ultrathin copper foil after roughening treatment in Example 2 (comparison).

[0012] The method for manufacturing a printed wiring board according to the present invention includes the steps of (1) preparing a support substrate, (2) forming a wiring pattern, (3) heat treatment, (4) chemical etching, (5) forming a build-up wiring layer, (6) separating an insulating layer, (7) flash etching, and (8) resin coating.

[0013] Each step will be described below with reference to the drawings.

[0014] 1A(a), a support substrate 10 is prepared, which is provided in this order with an insulating layer 12, a release layer 14, and a copper layer 16. Preferably, the support substrate 10 includes a carrier-attached copper foil 20, with the carrier 18 located between the insulating layer 12 and the release layer 14 and the copper foil corresponding to the copper layer 16. In other words, the carrier 18 is an optional component.

[0015] The insulating layer 12 preferably contains an insulating resin and is typically a resin layer. The resin layer is preferably a prepreg and / or a resin sheet. Prepreg is a general term for a composite material in which an insulating resin is impregnated into a substrate such as a synthetic resin plate, a glass plate, a woven glass fabric, a nonwoven glass fabric, or paper. Preferred examples of insulating resins include epoxy resin, cyanate resin, bismaleimide triazine resin (BT resin), polyphenylene ether resin, and phenolic resin. Examples of insulating resins constituting the resin sheet include epoxy resin, polyimide resin, and polyester resin. The resin layer may also contain filler particles made of various inorganic particles such as silica and alumina to improve insulation properties. The thickness of the insulating layer 12 (e.g., a resin layer) is not particularly limited, but is preferably 1 μm to 1000 μm, more preferably 2 μm to 400 μm, and even more preferably 3 μm to 200 μm. The insulating layer 12 (e.g., a resin layer) may be composed of multiple layers.

[0016] The release layer 14 weakens the peel strength of adjacent layers, such as the carrier 18, ensures stability of that strength, and further functions to suppress interdiffusion that may occur between adjacent layers and copper foil during high-temperature press molding. The release layer 14 may be either an organic or inorganic release layer. Examples of organic components used in the organic release layer include nitrogen-containing organic compounds, sulfur-containing organic compounds, carboxylic acids, etc. Examples of nitrogen-containing organic compounds include triazole compounds and imidazole compounds, with triazole compounds being preferred because of their stable release properties. Examples of triazole compounds include 1,2,3-benzotriazole, carboxybenzotriazole, N',N'-bis(benzotriazolylmethyl)urea, 1H-1,2,4-triazole, and 3-amino-1H-1,2,4-triazole. Examples of sulfur-containing organic compounds include mercaptobenzothiazole, thiocyanuric acid, and 2-benzimidazolethiol. Examples of carboxylic acids include monocarboxylic acids and dicarboxylic acids. On the other hand, examples of inorganic components used in the inorganic release layer include Ni, Mo, Co, Cr, Fe, Ti, W, P, Zn, chromate-treated film, etc. The thickness of the release layer is typically 1 nm or more and 1 μm or less, and preferably 5 nm or more and 500 nm or less.

[0017] Copper layer 16 is such that when the surface of copper layer 16 is scratched with the spherical tip of a metal pin and then heat treated in an air atmosphere at 170°C for 30 minutes, the cross-sectional crystal grain size at the scratched location is 1.5 µm or less. By using support substrate 10 having such copper layer 16 in the manufacture of printed wiring boards by the ETS method, it is possible to prevent copper grains from enlarging due to heat treatment even in the scratched location, and to achieve sufficient roughening by chemical etching.

[0018] That is, as mentioned above, scratches (scratches) may appear on the surface of the copper layer 16 during handling of the support substrate 10. If the copper layer 16 is made by conventional copper plating, performing a heat treatment (baking) while the scratches are present can lead to the risk of recrystallization of the copper crystals due to the stress caused by the scratches, adversely affecting subsequent processes. Specifically, as shown in FIG. 2A , if scratches S are present on the copper layer 16 (see FIG. 2A(i)), recrystallization R (due to the stress caused by the scratches S) progresses in the area of ​​the scratches S during the heat treatment step (3), causing the copper crystals to enlarge (see FIG. 2A(ii)), resulting in insufficient roughening of the scratched area during the subsequent chemical etching treatment step (4). As a result, the scratched area of ​​the copper layer 16 becomes smoother than the non-scratched area (see FIG. 2A(iii)). When an insulating layer 24 is laminated (as part of a build-up wiring layer 34) on the copper layer 16 in this state (see FIG. 2B(iv)), the adhesion to the insulating layer 24 is reduced in the areas smoothed by recrystallization R, and the insulating layer 24 is likely to lift off the copper layer 16 and blister in those areas. Furthermore, when the insulating layer 12 and any carrier 18 are separated from the insulating layer 24 and the copper layer 16 is removed by flash etching (see FIG. 2B(v)), the uneven surface of the copper layer 16 created by the chemical etching process is inherited as a replica shape on the surface of the insulating layer 24, but the scratches S and the undesirable smooth areas F caused by the recrystallization R are also inherited by the insulating layer 24. As a result, when the insulating layer 24 is covered with a resin 36 (step (8)), there is a concern that the reliability of adhesion between the insulating layer 24 and the resin 36 in those smooth areas F will be reduced (see FIG. 2B(vi)). In this regard, the copper layer 16 used in the present invention can prevent the copper particles from enlarging due to heat treatment even in areas with scratches S, and achieve sufficient roughening through chemical etching, thereby solving the above problem.

[0019] When selecting or determining a copper layer 16 usable in the present invention, scratches are formed on the copper layer 16 whose cross-sectional grain size after heat treatment is to be measured by scratching the surface of the copper layer 16 with the spherical tip of a metal pin. Figures 3A and 3B show an example of a jig 40 for making such scratches. This jig 40 has a total weight of 98 g and includes a cylindrical holder 42, a buffer material 44 filled in the holder 42, and a metal pin 46 inserted and fixed to the upper end surface of the buffer material 44 with its spherical tip facing upward. The cylindrical holder 42 has an outer diameter of 8.5 cm and an inner diameter of 8.0 cm. The material of the buffer material 44 is not particularly limited as long as it can be inserted and fixed with the end of the metal pin 46, but is, for example, polyethylene. The metal pin 46 is a stainless steel pin with a diameter of 3.8 mm and a spherical tip. 3A is held upside down in one's hand, the downward-pointing spherical tip of the metal pin 46 is brought into contact with the copper layer 16, and the jig 40 is manually slid horizontally while maintaining this contact, thereby creating scratches in the copper layer 16. It is preferable to minimize the application of force other than the jig 40's own weight so that a stable load is applied to the spherical tip of the metal pin 46. This allows for the creation of predetermined scratches with high reproducibility using a stable load that is independent of the person or method. The jig used to create the scratches is not limited to the example shown in the figure, and any jig with a spherical tip that can create scratches equivalent to the jig 40 can be used.

[0020] The depth of the scratches to be made on the surface of the copper layer 16 is preferably within a range of 40% to 60% of the thickness of the copper layer 16, more preferably 45% to 55%, and even more preferably approximately 50%. For example, if the thickness of the copper layer 16 is 5 μm, it is preferable to form scratches with a depth of 2.0 μm to 3.0 μm (i.e., approximately 2.5 μm). By adjusting the scratch depth within this range, it is possible to prevent the scratches from penetrating the copper layer 16 and eliminating the remaining thickness, thereby ensuring a minimum thickness for measuring the cross-sectional grain size after heat treatment. The depth of the scratches can be adjusted by adjusting the weight of the jig 40. For example, a weight can be attached to the jig 40 as needed. That is, the heavier the jig 40, the deeper the scratches, while the lighter the jig 40, the shallower the scratches. The cross-sectional grain size of the scratched copper layer 16 before and after heat treatment is evaluated.

[0021] The cross-sectional grain size of the copper layer 16 at the scratched portion after heat treatment at 170° C. for 30 minutes is 1.5 μm or less, preferably 0.1 μm or more and 1.5 μm or less, more preferably 0.1 μm or more and 1.0 μm or less, even more preferably 0.2 μm or more and 0.8 μm or less, and particularly preferably 0.3 μm or more and 0.5 μm or less. The cross-sectional grain size can be measured by analyzing a cross section of the copper layer 16 in the thickness direction by electron backscatter diffraction (EBSD) according to the procedure in the examples described later.

[0022] The cross-sectional grain size of the copper layer 16 at an unscratched portion after heat treatment at 170° C. for 30 minutes is preferably 0.1 μm to 1.5 μm, more preferably 0.1 μm to 1.0 μm, even more preferably 0.2 μm to 0.8 μm, and particularly preferably 0.3 μm to 0.5 μm. The cross-sectional grain size in this embodiment can also be measured by analyzing a cross section of the copper layer 16 in the thickness direction by electron backscatter diffraction (EBSD) according to the procedure in the Examples described later.

[0023] Cross-sectional grain size D of the copper layer 16 at the scratched location after heat treatment at 170°C for 30 minutes ＡThe cross-sectional grain size D at the unscratched portion of Ｂ The increase rate is preferably 100% or less, more preferably 80% or less, even more preferably 50% or less, and particularly preferably 20% or less. Ａ -D Ｂ ) / D Ｂ ) × 100. This value is called the increase rate because, since it is the same copper layer, the cross-sectional crystal grain size is essentially the same in the scratched and unscratched areas before the heat treatment, but the cross-sectional crystal grain size in the scratched areas tends to increase due to the heat treatment, so it can be said that it increases relative to the cross-sectional crystal grain size in the unscratched areas. The lower limit of the increase rate is not particularly limited and can be 0%. However, the increase rate may be slightly negative depending on the measurement location due to variations in the cross-sectional crystal grain size or measurement errors, but such cases are also considered to be essentially 0% and are acceptable.

[0024] The carrier 18 is a support for supporting the copper layer 16 to improve its handleability, and a typical carrier 18 includes a metal layer. Examples of such a carrier 18 include aluminum foil, copper foil, stainless steel foil, resin film or glass whose surface is coated with a metal such as copper, and copper foil is preferred. The copper foil may be either rolled copper foil or electrolytic copper foil, but electrolytic copper foil is preferred. The thickness of the carrier is typically 250 μm or less, and preferably 7 μm or more and 200 μm or less.

[0025] Other functional layers may be provided between the release layer 14 and the carrier 18 and / or the copper layer 16. An example of such other functional layer is an auxiliary metal layer. The auxiliary metal layer is preferably made of nickel and / or cobalt. By forming such an auxiliary metal layer on the surface side of the carrier 18 and / or the surface side of the copper layer 16, interdiffusion that may occur between the carrier 18 and the copper layer 16 during hot press molding at high temperatures or for long periods of time can be further suppressed, thereby ensuring stable peel strength of the carrier 18. The thickness of the auxiliary metal layer is preferably 0.001 μm or more and 3 μm or less.

[0026] The support substrate 10 may be obtained as a completed product and used as is, or a laminate (copper-clad laminate) may be formed by laminating the copper layer 16 or the carrier-attached copper foil 20 (carrier 18 side) on one or both sides of the insulating layer 12. This lamination may be performed according to known conditions and techniques employed for laminating copper foil and prepreg, etc. in a normal printed wiring board manufacturing process.

[0027] 1A(b), a wiring pattern 22 is formed on the copper layer 16. The formation of the wiring pattern 22 may be performed according to a known method for manufacturing a printed wiring board, and is not particularly limited. Preferably, the formation of the wiring pattern 22 is performed by (i) forming a photoresist pattern on the copper layer 16, (ii) forming electrolytic copper plating (pattern plating), and then (iii) peeling off the photoresist pattern, as described below.

[0028] (i) Formation of Photoresist Pattern First, a photoresist pattern is formed on the surface of the copper layer 16. The photoresist pattern may be formed using either a negative resist or a positive resist, and the photoresist may be either a film type or a liquid type. The developer may be sodium carbonate, sodium hydroxide, an amine-based aqueous solution, or the like, and may be formed according to any of the various techniques and conditions commonly used in the manufacture of printed wiring boards, without any particular limitations.

[0029] (ii) Electrolytic Copper Plating Next, electrolytic copper plating is applied to the copper layer 16 on which the photoresist pattern has been formed. The electrolytic copper plating may be performed according to various pattern plating techniques and conditions commonly used in the manufacture of printed wiring boards, such as a copper sulfate plating solution or a copper pyrophosphate plating solution, and is not particularly limited.

[0030] (iii) Stripping of Photoresist Pattern The photoresist pattern is stripped to form the wiring pattern 22. The photoresist pattern may be stripped using a sodium hydroxide solution, an amine-based solution, or an aqueous solution thereof, and may be stripped using any of a variety of stripping techniques and conditions commonly used in the manufacture of printed wiring boards, without any particular limitations. Thus, a wiring pattern 22 is formed directly on the surface of the copper layer 16 as a first wiring layer, with wiring portions (lines) arranged with gaps (spaces) between them. For example, to achieve finer circuitry, it is preferable to form a wiring pattern with a line / space (L / S) of 13 μm or less / 13 μm or less (e.g., 12 μm / 12 μm, 10 μm / 10 μm, 5 μm / 5 μm, or 2 μm / 2 μm).

[0031] (3) Heat Treatment Step The support substrate 10 on which the wiring pattern 22 has been formed is subjected to a heat treatment (baking). This heat treatment is a pretreatment carried out to anneal the pattern plating. The preferred temperature for the heat treatment is 100°C or higher and 200°C or lower, and more preferably 120°C or higher and 180°C or lower. The heat treatment may be carried out by holding the support substrate 10 with the wiring pattern 22 at a temperature within the above range for preferably 10 minutes or longer, and more preferably 30 minutes or longer and 120 minutes or shorter. The atmosphere in which the heat treatment is carried out is not particularly limited, and may be an air atmosphere.

[0032] (4) Chemical Etching Process The wiring pattern 22 and the copper layer 16 exposed between the wiring patterns 22 are subjected to a chemical etching process. This chemical etching is a pretreatment performed to form fine irregularities on the surfaces of the wiring pattern 22 and the copper layer 16 to ensure adhesion with the insulating layer 24. Therefore, the chemical etching process preferably includes a roughening process such as a CZ process. The CZ process can be preferably performed by using an organic acid microetchant (e.g., CZ8101, manufactured by MEC Co., Ltd.) to finely roughen the exposed surfaces of the wiring pattern 22 and the copper layer 16. This forms fine irregularities on the exposed surfaces of the wiring pattern 22 and the copper layer 16, improving adhesion with the insulating layer 24 that will be laminated later.

[0033] 1A(c) and 1A(d), a support substrate 10 with a build-up wiring layer 34 is fabricated by forming a build-up wiring layer 34 on the copper layer 16 that has been subjected to chemical etching. For example, in addition to the wiring pattern 22 as the first wiring layer already formed on the copper layer 16, an insulating layer 24 and a wiring pattern 22 as the second wiring layer may be formed in this order to form the build-up wiring layer 34. For example, to form the build-up wiring layer 34, the insulating layer 24 and the carrier-attached copper foil 26 (comprising a carrier 28, a release layer 30, and a copper foil 32) may be laminated, the carrier 28 may be peeled off, and the copper foil 32 and the insulating layer 24 directly below it may be laser-processed using a carbon dioxide laser or the like. Subsequently, patterning is performed by chemical copper plating, photoresist processing, electrolytic copper plating, photoresist peeling, etc. (flash etching may be further performed as necessary) to form a wiring pattern 22 as a second wiring layer, and this patterning and optional flash etching may be repeated as necessary to form up to the nth wiring layer (n is an integer of 2 or more).

[0034] The method for forming the build-up layers from the second wiring layer onward is not limited to the above-mentioned method, and other methods such as a subtractive method, a modified semi-additive process (MSAP) method, a semi-additive process (SAP) method, and a full-additive process can be used. For example, when the insulating layer 24 and the copper foil 32 are simultaneously bonded together by press processing, the wiring pattern 22 can be formed by etching the panel plating layer and the copper foil 32 in combination with the formation of via holes and interlayer conductive means such as panel plating. Furthermore, when only the insulating layer 24 is bonded to the surface of the copper layer 16 by press or lamination, the wiring pattern 22 can also be formed on that surface by a semi-additive method.

[0035] The above process is repeated as necessary to obtain a support substrate 10 with a build-up wiring layer 34. In this process, it is preferable to form a build-up wiring layer 34 in which insulating layers 24 and wiring layers including wiring patterns 22 are alternately stacked, thereby obtaining a support substrate 10 with a build-up wiring layer 34 formed up to an nth wiring layer (n is an integer of 2 or greater). This process may be repeated until the desired number of build-up wiring layers 34 are formed. Note that, for the sake of simplicity, only the first and second wiring layers are depicted as the wiring pattern 22 in FIGS. 1A and 1B, but this is not limiting, and it goes without saying that a multi-layer build-up wiring layer 34 formed up to an nth wiring layer (n is an integer of 2 or greater) can be employed.

[0036] 1B(e), the insulating layer 12 is separated from the support substrate 10 with the build-up wiring layer 34 via the release layer 14. At this time, if a carrier 18 is present, the carrier 18 is also separated from the support substrate 10 with the build-up wiring layer 34 together with the insulating layer 12. The separation method is preferably physical peeling, and this peeling method may be performed using a machine or a jig, manually, or a combination of these.

[0037] 1B(f), flash etching is performed on the build-up wiring layer 34 from which the insulating layer 12 has been separated to remove the copper layer 16. As a result, the copper layer 16 exposed between the wiring patterns 22 of the first wiring layer and the copper foil 32 exposed between the wiring patterns 22 of the nth wiring layer, if present, are removed by flash etching, revealing the predetermined wiring pattern 22. In other words, the wiring pattern 22 of the first wiring layer is embedded in the insulating layer 24, with only the surface exposed. In this way, a build-up wiring layer 34 having the wiring pattern 22 as an embedded circuit is obtained.

[0038] (8) Resin Coating Step: As shown in FIG. 1B(g), the build-up wiring layer 34 from which the copper layer 16 has been removed is coated with resin 36. In this way, a printed wiring board 38 is obtained. The resin 36 is not particularly limited as long as it is a resin-containing material that can be used for the printed wiring board 38. Preferred examples include prepreg, resin-coated copper foil (RCC), solder resist, and plating resist. If a build-up wiring layer is further formed, prepreg, RCC, solder resist, or a combination thereof can be used. If plating is applied to the wiring, a plating resist can be laminated. When the resin 36 is solder resist, a photo solder resist is preferred. In addition to the resin 36, the printed wiring board 38 may be subjected to various outer layer processing. For example, surface treatments such as Ni-Au plating, Ni-Pd-Au plating, and water-soluble preflux treatment may be applied as outer layer pads. Furthermore, columnar pillars or the like may be provided on the outer layer pads.

[0039] Manufacturing Method of Carrier-Attached Copper Foil As described above, the support substrate 10 used in the method of the present invention preferably includes a carrier-attached copper foil 20. In this case, the carrier 18 is located between the insulating layer 12 and the release layer 14, and the copper foil (preferably an ultra-thin copper foil) corresponds to the copper layer 16. The carrier-attached copper foil 20 can be manufactured by (1) preparing the carrier 18, (2) forming the release layer 14 on the carrier 18, and (3) forming an ultra-thin copper foil as the copper layer 16 on the release layer 14. An example of a preferred manufacturing method of a carrier-attached copper foil will be described below.

[0040] (1) Preparation of Carrier First, a carrier 18 is prepared as a support. A typical carrier 18 includes a metal layer. As described above, examples of such a carrier 18 include aluminum foil, copper foil, stainless steel foil, resin film or glass whose surface is metal-coated with copper or the like, and copper foil is preferred. The copper foil may be either rolled copper foil or electrolytic copper foil, but electrolytic copper foil is preferred. The thickness of the carrier is typically 250 μm or less, and preferably 7 μm or more and 200 μm or less.

[0041] The surface of the carrier 18 facing the release layer 14 is preferably smooth. That is, in the manufacturing process of the carrier-attached copper foil 20, an ultrathin copper foil is formed as the copper layer 16 on the surface of the carrier 18 facing the release layer 14. Therefore, by smoothing the surface of the carrier 18 facing the release layer 14, the outer surface of the copper layer 16 can also be smoothed, making it easier to uniformize the crystal growth surface of the copper layer 16. As a result, it becomes easier to obtain a copper layer 16 composed of copper crystal grains having a desired crystal size (i.e., a cross-sectional crystal grain size of 1.5 μm or less). The surface of the carrier 18 facing the release layer 14 can be smoothed, for example, by polishing the surface of the cathode used in electrolytic foil formation of the carrier 18 with a buff of a predetermined grit to adjust the surface roughness. That is, the surface profile of the cathode adjusted in this way is transferred to the electrode surface of the carrier 18, and the copper layer 16 is formed on the electrode surface of this carrier 18 via the release layer 14, making it easier to form a copper layer 16 composed of copper crystal grains of a desired crystal size. The grain size of the buff is preferably #1,000 or more and #3,500 or less, and more preferably #1,000 or more and #2,500 or less. From the viewpoint of easily controlling the crystal size of the copper crystal grains constituting the copper layer 16 within a desired range, the deposition surface of the carrier 18 electrolytically formed using an electrolyte containing an additive may be the surface of the carrier 18 on the release layer 14 side.

[0042] (2) Formation of Release Layer A release layer 14 is formed on the carrier 18. The release layer 14 may be either an organic release layer or an inorganic release layer. Preferred examples of organic release layers and inorganic release layers are as described above. The release layer 14 may be formed by contacting at least one surface of the carrier 18 with a solution containing release layer components and fixing the release layer components to the surface of the carrier. When contacting the carrier 18 with the solution containing release layer components, this contact may be performed by immersion in the solution containing release layer components, spraying the solution containing release layer components, or flowing the solution containing release layer components down. Alternatively, a method of forming a film of the release layer components using a gas phase method such as vapor deposition or sputtering can also be used. Fixation of the release layer components to the surface of the carrier 18 may be performed by adsorption or drying of the solution containing release layer components, electrodeposition of the release layer components in the solution containing release layer components, or the like. The thickness of the release layer 14 is typically 1 nm to 1 μm, preferably 5 nm to 500 nm.

[0043] (3) Formation of Ultra-Thin Copper Foil An ultra-thin copper foil is formed as the copper layer 16 on the release layer 14. For example, the copper layer 16 may be formed by a wet film formation method such as electroless copper plating and electrolytic copper plating, a dry film formation method such as sputtering and chemical vapor deposition, or a combination thereof. Preferably, the copper layer 16 is formed by electrolytic copper plating. In particular, from the viewpoint of controlling the initial deposition of the copper layer 16 and reducing the cross-sectional crystal grain size, the conditions for electrolytic foil formation of the copper layer 16 are preferably as follows: That is, a sulfuric acid-based copper electrolyte solution is used in which the copper concentration is 40 g / L or more and 80 g / L or less (more preferably 50 g / L or more and 70 g / L or less), the sulfuric acid concentration is 180 g / L or more and 260 g / L or less (more preferably 200 g / L or more and 250 g / L or less), and the concentration of carboxybenzotriazole (CBTA) as an additive is adjusted to more than 0 ppm and 200 ppm or less, a DSA (dimensionally stable anode) is used as the anode, the solution temperature is 35°C or more and 60°C or less (more preferably 40°C or more and 55°C or less), and the current density is 3 A / dm ２ 80A / dm or more ２ less than 5 A / dm ２ 80A / dm or more ２ More preferably, 6 A / dm ２ 75A / dm or more ２The desired copper layer 16 can be preferably obtained by electrolysis using a CBTA solution (hereinafter referred to as "electrolyzer") containing 0.1 ppm or more and 100 ppm or less. The CBTA concentration in the electrolytic solution is more preferably 0.1 ppm or more and 50 ppm or less, even more preferably 0.1 ppm or more and 30 ppm or less, and most preferably 0.1 ppm or more and 10 ppm or less. By adding carboxybenzotriazole (CBTA) as an additive to the electrolytic solution and performing electrolytic foil formation while controlling the current density and other factors within the above ranges, it becomes easier to form a copper layer 16 composed of copper crystal grains that have a small cross-sectional grain size and are resistant to recrystallization even when subjected to heat treatment. In particular, CBTA has the effect of preventing recrystallization of copper crystal grains during heat treatment. Therefore, even if scratches S are present in the copper layer 16 as shown in FIG. 2A, it is possible to prevent recrystallization R from progressing at the scratch S portion (due to the stress applied by the scratch S) during the heat treatment process, thereby preventing the copper crystals from becoming thicker, and to maintain the cross-sectional crystal grain size at 1.5 μm or less.

[0044] If desired, a rust-proofing treatment may be performed on the surface of the copper layer 16 to form a rust-proofing layer. The rust-proofing treatment preferably includes a zinc plating treatment. The zinc plating treatment may be either a zinc plating treatment or a zinc alloy plating treatment, with a zinc-nickel alloy plating treatment being particularly preferred. The zinc-nickel alloy plating treatment may be a plating treatment containing at least Ni and Zn, and may further contain other elements such as Sn, Cr, and Co. The Ni / Zn deposition ratio in the zinc-nickel alloy plating is preferably 1.2 to 10, more preferably 2 to 7, and even more preferably 2.7 to 4, by mass. Furthermore, the rust-proofing treatment preferably further includes a chromate treatment, and this chromate treatment is more preferably performed on the surface of the zinc-containing plating after the zinc plating treatment. This can further improve rust prevention. A particularly preferred rust-proofing treatment is a combination of a zinc-nickel alloy plating treatment followed by a chromate treatment.

[0045] The present invention is further illustrated by the following examples.

[0046] Example 1 A supporting substrate corresponding to the example was prepared and evaluated as follows.

[0047] (1) Preparation of carrier-attached copper foil (1a) Preparation of carrier Using a copper electrolyte solution having the composition shown below, a cathode, and a DSA (dimensionally stable anode) as an anode, a carrier was prepared at a solution temperature of 50°C and a current density of 70 A / dm ２ The electrolysis was carried out at 1000 W / L, and an electrolytic copper foil with a thickness of 18 μm was obtained as a carrier. At this time, an electrode whose surface had been polished with a #2000 buff to adjust the surface roughness was used as the cathode. <Composition of copper electrolyte> - Copper concentration: 80 g / L - Sulfuric acid concentration: 300 g / L - Chlorine concentration: 30 mg / L - Glue concentration: 5 mg / L

[0048] (1b) Formation of Release Layer The electrode surface of the pickled carrier was immersed in a carboxybenzotriazole (CBTA) aqueous solution containing 1 g / L of CBTA, 150 g / L of sulfuric acid, and 10 g / L of copper at a liquid temperature of 30° C. for 30 seconds to adsorb the CBTA component onto the electrode surface of the carrier. In this way, a CBTA layer was formed on the electrode surface of the carrier as an organic release layer.

[0049] (1c) Formation of auxiliary metal layer The carrier on which the organic release layer was formed was immersed in a solution containing nickel at a concentration of 20 g / L prepared using nickel sulfate, and the solution temperature was 45°C, pH 3, and current density 5 A / dm ２ A deposition amount of nickel equivalent to a thickness of 0.001 μm was deposited on the organic release layer under the conditions of: In this way, a nickel layer was formed as an auxiliary metal layer on the organic release layer.

[0050] (1d) Formation of ultra-thin copper foil (copper layer) The carrier on which the auxiliary metal layer was formed was immersed in a copper solution having the composition shown below, and the solution temperature was 50°C, and the current density was 5 A / dm ２ More than 40A / dm ２ Electrolysis was performed using the following solution to form an ultra-thin copper foil (copper layer) with a thickness of 5 μm on the auxiliary metal layer. <Solution composition> - Copper concentration: 60 g / L - Sulfuric acid concentration: 200 g / L - CBTA concentration: 6.6 ppm

[0051] (1e) Rust prevention treatment The surface of the ultra-thin copper foil with carrier obtained was subjected to rust prevention treatment consisting of zinc-nickel alloy plating treatment and chromate treatment. First, a solution containing 1 g / L of zinc, 2 g / L of nickel, and 80 g / L of potassium pyrophosphate was used, and the solution temperature was 40°C, the current density was 0.5 A / dm ２ The roughened layer and the surface of the carrier were subjected to zinc-nickel alloy plating treatment under the conditions of: Then, an aqueous solution containing 1 g / L of chromic acid was used, pH 12, current density 1 A / dm ２ The zinc-nickel alloy plated surface was then subjected to a chromate treatment under the conditions described above.

[0052] (1f) Silane coupling agent treatment A commercially available aqueous solution containing a silane coupling agent was adsorbed onto the carrier side surface of the carrier-attached copper foil, and the water was evaporated using an electric heater, thereby carrying out a silane coupling agent treatment. At this time, the silane coupling agent treatment was not carried out on the ultrathin copper foil side. In this way, a carrier-attached copper foil was obtained.

[0053] (2) Preparation of Support Substrate The support substrate 10 shown in Fig. 1A was prepared using the obtained carrier-attached copper foil as follows. First, a 0.10 mm thick prepreg (GHPL-830NS, manufactured by Mitsubishi Gas Chemical Co., Inc.) was prepared. The obtained carrier-attached copper foil was laminated on this prepreg so that the carrier surface of the prepreg was in contact with the prepreg, and pressed at a temperature of 220°C and a pressure of 4.0 MPa for 90 minutes to prepare the support substrate 10.

[0054] (3) Evaluation The ultra-thin copper foil (copper layer) of the support substrate thus obtained was scratched with the spherical tip of a metal pin as follows, and various evaluations were carried out.

[0055] 3A and 3B, a jig 40 with a total weight of 98 g was prepared for making the scratches. This jig 40 included a cylindrical holder 42, a buffer material 44 filled in the holder 42, and a metal pin 46 inserted and fixed to the upper end surface of the buffer material 44 with its spherical tip facing upward. The specifications of each component were as follows: Cylindrical holder 42: outer diameter 8.5 cm, inner diameter 8.0 cm Buffer material 44: polyethylene Metal pin 46: stainless steel pin with a spherical tip and a diameter of 3.8 mm

[0056] The jig 40 shown in FIG. 3A was held upside down in the hand, and the spherical tip of the downward-pointing metal pin 46 was brought into contact with the ultra-thin copper foil (copper layer) of the support substrate. While maintaining this contact, the jig 40 was slid horizontally by hand to scratch the ultra-thin copper foil. At this time, by minimizing the application of force other than the weight of the jig 40, a stable load was applied to the spherical tip of the metal pin 46. Five scratches were made on the ultra-thin copper foil in this way, and the depths of the five scratches were measured using a laser microscope (VK-X110, manufactured by Keyence Corporation) to measure the line roughness. The depths were 2.2 μm, 2.3 μm, 2.9 μm, 2.4 μm, and 2.5 μm, with an average value of 2.46 μm. The ultra-thin copper foil thus provided with scratches of about 2.5 μm in depth on its surface was subjected to the following evaluations 1 and 2 for both scratched and non-scratched areas.

[0057] <Various Evaluations> Evaluation 1: Measurement of Cross-Sectional Grain Size After Heat Treatment The support substrate was subjected to a heat treatment at 170°C for 30 minutes in an air atmosphere. These heat treatment conditions simulate the baking performed after pattern plating in an actual ETS process. Next, the cross-sectional grain size of copper grains present in the cross section of the ultra-thin copper foil (copper layer) of the support substrate was measured for both scratched and unscratched areas as follows.

[0058] First, a cross section of the support substrate was processed using a focused ion beam (FIB) device, and the cross section of this ultrathin copper foil was observed using an FE gun type scanning electron microscope (Crossbeam 540, manufactured by Carl Zeiss K.K.) equipped with an EBSD detector (Symmetry, manufactured by Oxford Instruments). Then, EBSD data was acquired using EBSD measurement software (AZtec 5.0 HF1, manufactured by Oxford Instruments), and the obtained EBSD data was converted into OIM format. The measurement conditions of the scanning electron microscope during observation were as follows. <Scanning electron microscope measurement conditions> - Acceleration voltage: 15 kV - Step size: 22.9 nm - Region width: 5.86 μm - Region height: 4.4 μm - Scan Phase: Cu - Sample angle: 70 °

[0059] Based on the data converted into the OIM format, the crystal distribution was measured using crystal size calculation software (OIM Analysis v7.3.1 x64, manufactured by AMETEK Corporation), and the cross-sectional size of the copper crystal grains constituting the ultra-thin copper foil (average crystal grain size, the "Grain Size - Average Area" section on the software) was calculated. The results were as shown in Table 1. In measuring the crystal distribution, a misorientation of 5° or more was considered to be a crystal grain boundary. However, since the crystal structure of copper is a cubic crystal structure, in consideration of twin grain boundaries, the following cases (i) or (ii) were not considered to be crystal grain boundaries. (i) Twin grain boundaries in an orientation relationship of 60° rotation around the <111> axis. (ii) Twin grain boundaries in an orientation relationship of 38.9° rotation around the <110> axis.

[0060] Based on the measurement results thus obtained, the cross-sectional crystal grain size D at the scratched portion was determined. Ａ The cross-sectional grain size D at the unscratched portion of Ｂ The increase rate for [(D Ａ -D Ｂ ) / D Ｂ ) × 100.

[0061] Evaluation 2: Evaluation of surface condition after roughening treatment The surface of the heat-treated ultrathin copper layer (copper layer) was treated with an organic acid microetchant (CZ8101, manufactured by MEC Co., Ltd.) to perform chemical etching (roughening treatment) to a thickness equivalent to 2 μm. The roughened surface of the ultrathin copper foil was observed with an SEM. In addition, the roughened surface was analyzed using a laser microscope (VK-X100, manufactured by Keyence Corporation) under the following conditions, and the maximum height Sz in accordance with ISO 25178 was measured as the surface roughness. <Roughness measurement conditions using a laser microscope> Objective lens: 100x Image zoom: 1x Noise removal: performed Tilt correction: performed Filter: not performed Measurement area: 7.0 μm x 30.0 μm

[0062] Example 2 (Comparative) A carrier-attached copper foil corresponding to a comparative example was produced and evaluated as follows.

[0063] (1) Preparation of Carrier-Attached Copper Foil (1a) Preparation of Carrier A carrier was prepared in the same manner as in Example 1.

[0064] (1b) Formation of release layer The carrier was immersed in a plating solution having the following composition, and the solution temperature was 30°C, and the current density was 1 A / dm ２ 4A / dm or more ２ By performing nickel-molybdenum alloy plating with a current application time of 3 seconds or more and 25 seconds or less, a deposition amount of 3000 μg / dm ２ A Ni-Mo layer of 50 g / dm was formed as an inorganic release layer. <Composition of plating solution> - Nickel sulfate hexahydrate: 50 g / dm ３ , - sodium molybdate dihydrate: 60 g / dm ３ , - sodium citrate: 90 g / dm ３

[0065] (1c) Formation of Auxiliary Metal Layer In the same manner as in Example 1, a nickel layer was formed as an auxiliary metal layer on the inorganic release layer.

[0066] (1d) Formation of ultra-thin copper foil The carrier on which the auxiliary metal layer was formed was immersed in a copper solution having the composition shown below, and the solution temperature was 50°C, and the current density was 5 A / dm ２ More than 40A / dm ２Electrolysis was performed using the following solution to form a 5 μm thick ultra-thin copper foil (copper layer) on the auxiliary metal layer. <Solution composition> - Copper concentration: 65 g / L - Sulfuric acid concentration: 200 g / L - Diallyldimethylammonium chloride concentration: 40 mg / L - Bis(3-sulfopropyl)disulfide concentration: 30 mg / L - Chlorine concentration: 30 mg / L

[0067] (1e) Rust Prevention Treatment In the same manner as in Example 1, the surface of the ultrathin copper foil of the obtained carrier-attached copper foil was subjected to rust prevention treatment consisting of zinc-nickel alloy plating treatment and chromate treatment.

[0068] (1f) Silane Coupling Agent Treatment The surface of the carrier-side of the obtained carrier-attached copper foil was treated with a silane coupling agent in the same manner as in Example 1.

[0069] (2) Preparation of Support Substrate A support substrate 10 was prepared in the same manner as in Example 1 using the obtained carrier-attached copper foil.

[0070] (3) Evaluation Scratches were formed on the ultra-thin copper foil (copper layer) of the support substrate obtained in this manner in the same manner as in Example 1, and evaluations 1 and 2 were carried out.

[0071] 4A to 7B referred to therein. From the results shown in Table 1, in Example 1 where the cross-sectional crystal grain size of the scratched portion after heat treatment (i.e., evaluation 2) was 0.39 μm (i.e., 1.5 μm or less), the maximum height Sz of the copper layer surface after roughening treatment was 4.6 μm, which is not significantly different from the Sz of the unscratched portion after roughening treatment. Therefore, it was found that the same level of adhesion to the resin layer can be expected even in the scratched portion as in the unscratched portion. In contrast, in Example 2, where the cross-sectional crystal grain size at the scratched area in Evaluation 2 is 2.3 μm (i.e., greater than 1.5 μm), the maximum height Sz of the copper layer surface after roughening treatment is 2.6 μm, which is significantly lower in roughness (i.e., smoother) than the Sz of the unscratched area after roughening treatment. Therefore, it is understood that the scratched area has inferior adhesion to the resin layer compared to the unscratched area.

[0072]

[0073] REFERENCE SIGNS LIST 10 Support substrate 12 Insulating layer 14 Release layer 16 Copper layer 18 Carrier 20 Copper foil with carrier 22 Wiring pattern 24 Insulating layer 26 Copper foil with carrier 28 Carrier 30 Release layer 32 Copper foil 34 Build-up wiring layer 36 Resin 38 Printed wiring board 40 Jig 42 Holder 44 Cushioning material 46 Metal pin S Scratch R Recrystallization F Smoothing

Claims

1. A method for manufacturing a printed wiring board, comprising: - preparing a support substrate sequentially provided with an insulating layer, a release layer, and a copper layer, wherein the copper layer has a cross-sectional crystal grain size of 1.5 μm or less at a location where a scratch is made by a spherical tip of a metal pin on the surface of the copper layer when heat-treated at 170 °C for 30 minutes in an air atmosphere; 3. The cross-sectional crystal grain size D at the scratched portion of the copper layer after the heat treatment at 170°C for 30 minutes Ａ of the cross-sectional crystal grain size D at the non-scratched portion Ｂ has an increase rate of 100% or less with respect to, and the increase rate is a value calculated by the formula [(D Ａ - D Ｂ ) / D Ｂ )] × 100. The method for manufacturing a printed wiring board according to claim 1 or 2 - forming a wiring pattern on the copper layer; - performing a heat treatment on the support substrate on which the wiring pattern is formed; - performing a chemical etching treatment on the wiring pattern and the copper layer exposed between the wiring patterns; - forming a build-up wiring layer on the copper layer subjected to the chemical etching treatment to produce a support substrate with a build-up wiring layer; - separating the insulating layer from the support substrate with the build-up wiring layer through the release layer; - performing flash etching on the build-up wiring layer from which the insulating layer has been separated to remove the copper layer; - coating the build-up wiring layer from which the copper layer has been removed with a resin.

2. The method for manufacturing a printed wiring board according to claim 1, wherein the cross-sectional crystal grain size of the copper layer at a location without a scratch after the heat treatment at 170 °C for 30 minutes is 0.1 μm or more and 1.5 μm or less.

4. The method for manufacturing a printed wiring board according to claim 1 or 2, wherein the support substrate includes a copper foil with a carrier, the carrier is located between the insulating layer and the release layer, and the copper foil corresponds to the copper layer.

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