Flexible circuit board, cof module and electronic device comprising same

Abstract

A flexible circuit board according to an embodiment comprises: a substrate; a conductive pattern unit arranged on the substrate; and a protective layer arranged on the conductive pattern unit, wherein the protective layer includes a plurality of open areas spaced apart from each other in a first direction, the conductive pattern unit includes an outermost pattern that is closest to an end of the protective layer positioned in a second direction perpendicular to the first direction, and the distance between the end of the protective layer and the outermost pattern is at least 1 mm.

Description

Flexible circuit boards, COF modules and electronic devices including the same

[0001] The present invention relates to a flexible circuit board, a COF module and an electronic device including the same.

[0002] Recently, various electronic products are becoming thinner and smaller. Consequently, there is a growing demand for high-density semiconductor chips to be mounted within the narrow spaces of these electronic products.

[0003] A COF (Chip-On-Film) comprises a substrate and a chip on the substrate. The substrate is flexible, meaning the COF is a flexible circuit board. Accordingly, the COF is applicable to flexible displays. For example, the COF can be applied to various wearable electronic devices. Furthermore, the COF has a fine pitch. Accordingly, the COF is applicable to high-resolution displays.

[0004] The chip includes a semiconductor chip. For example, the chip may be an integrated circuit (IC) chip or a large scale integrated circuit (LSI) chip.

[0005] The chip is connected to an external circuit board and display panel via a wiring pattern. For example, pads are arranged at one end and the other end of the wiring pattern, respectively. One pad is electrically connected to a terminal of the chip. The other pad is connected to a terminal of the circuit board and the display panel. Accordingly, the chip, the circuit board, and the display panel are electrically connected via the COF. As a result, a signal is transmitted to the display panel via the wiring pattern.

[0006] A protective layer is disposed on the above wiring pattern. The protective layer is disposed on an area excluding the pad.

[0007] The above protective layer is formed by a squeegee process. Therefore, the edges of the protective layer may be thicker than other areas as the protective layer material increases. Consequently, the protective layer positioned on the outermost wiring pattern of a flexible circuit board may have a large thickness.

[0008] The above flexible circuit board is manufactured in multiple pieces, and the multiple flexible circuit board modules are wound on a roller for storage. Subsequently, when the flexible circuit board is used, a process of unwinding the roller and a process of cutting the flexible circuit board into individual pieces can be performed.

[0009] The above flexible circuit board is wound under strong pressure to prevent the flexible circuit board from unraveling. Since the protective layer on the outermost pattern of the flexible circuit board is thick, the pad of the outermost pattern of the innermost flexible circuit board may be damaged when the flexible circuit board is wound.

[0010] That is, since the thickness of the protective layer on the outermost pattern is large, strong pressure is generated, and as a result, the pad on the outermost pattern may be damaged by the pressure.

[0011] Therefore, a new flexible circuit board, COF module and electronic device including the same that can solve the above problems are required.

[0012] As a patent related to the above flexible circuit board, Korean registered patent KR10-0618898 (2006.09.01) is disclosed.

[0013] Embodiments provide a flexible circuit board, a COF module, and an electronic device including the same having improved reliability.

[0014] The embodiment provides a flexible circuit board capable of mounting multiple chips, a COF module, and an electronic device including the same.

[0015] In addition, the embodiment provides a flexible circuit board with improved heat dissipation characteristics, a COF module, and an electronic device including the same.

[0016] In addition, the embodiment provides a flexible circuit board, a COF module, and an electronic device including the same, which enable a plurality of chips to operate stably.

[0017] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0018] A flexible circuit board according to an embodiment comprises: a substrate; a conductive pattern portion disposed on the substrate; and a protective layer disposed on the conductive pattern portion, wherein the protective layer includes a plurality of open areas spaced apart from each other along a first direction; the conductive pattern portion includes an outermost pattern closest to an end of the protective layer located in a second direction perpendicular to the first direction; and a distance between an end of the protective layer and the outermost pattern is 1 mm or more.

[0019] In addition, the end of the protective layer includes a first end and a second end facing in the second direction, and the outermost pattern includes a first outermost pattern arranged most adjacent to the first end, and a second outermost pattern arranged most adjacent to the second end, and the distance is a distance between the first end and the first outermost pattern or a distance between the second end and the second outermost pattern.

[0020] In addition, the conductive pattern portion includes a wiring pattern portion including a pad arranged in at least one open area among the plurality of open areas, and a dummy pattern portion spaced apart from the wiring pattern portion, wherein the first outermost pattern is the wiring pattern portion or the dummy pattern portion, and the second outermost pattern is the wiring pattern portion or the dummy pattern portion.

[0021] Additionally, the substrate includes a cutting line, and a distance between the first outermost pattern and the cutting line adjacent to the first end is greater than a distance between the first end and the first outermost pattern, and a distance between the second outermost pattern and the cutting line adjacent to the second end is greater than a distance between the second end and the second outermost pattern.

[0022] Additionally, the distance between the first outermost pattern and the cutting line adjacent to the first end or the distance between the second outermost pattern and the cutting line adjacent to the second end is 1 mm or more.

[0023] Additionally, the protective layer includes regions having different heights.

[0024] Additionally, the protective layer has a first maximum height in a region closest to the first end.

[0025] Additionally, the first outermost pattern is the wiring pattern portion, and the dummy pattern portion includes at least one dummy pattern disposed between the first end and the first outermost pattern.

[0026] Additionally, the second outermost pattern is the wiring pattern portion, and the dummy pattern portion includes at least one dummy pattern disposed between the second end and the second outermost pattern.

[0027] Additionally, the protective layer has a second maximum height in a region adjacent to the second end.

[0028] In addition, the substrate includes a first surface on which a first chip mounting area and a second chip mounting area are defined and a second surface opposite to the first surface, the protective layer includes a first protective layer disposed on the first surface of the substrate and including a first open area overlapping the first chip mounting area along a thickness direction of the substrate, and a second open area overlapping the second chip mounting area, and the dummy pattern portion includes a first dummy pattern disposed on the first surface of the substrate and disposed between the first chip mounting area and the second chip mounting area.

[0029] Additionally, at least a portion of the first dummy pattern does not overlap with the first and second open areas along the thickness direction.

[0030] In addition, the substrate includes a first side end and a second side end facing each other along a separation direction of the first chip mounting area and the second chip mounting area, the second chip mounting area being arranged closer to the first side end than to the first chip mounting area, and the dummy pattern portion further includes a second dummy pattern arranged on the first surface of the substrate and between the second chip mounting area and the first side end.

[0031] In addition, the first protective layer further includes a third open area provided adjacent to the first side end, and a fourth open area provided adjacent to the second side end, and the wiring pattern portion includes a first wiring pattern portion including at least one end disposed in the first open area; a second wiring pattern portion including at least one end disposed in the second open area; and a third wiring pattern portion having one end disposed in the third open area and the other end disposed in the fourth open area, and at least a portion of the dummy pattern portion is disposed between at least two wiring pattern portions among the first wiring pattern portion, the second wiring pattern portion, and the third wiring pattern portion.

[0032] In addition, the first wiring pattern portion includes a 1-1 wiring pattern including an upper wiring disposed on the first surface of the substrate and including a first pad disposed within the first open area and a second pad disposed within the third open area, a lower wiring disposed under the second surface of the substrate, and a plurality of via electrodes connecting the upper wiring and the lower wiring, and a 1-2 wiring pattern including a third pad disposed on the first surface of the substrate and disposed within the first open area, a fourth pad disposed on the first surface of the substrate and disposed within the fourth open area, and a first connection wiring connecting between the third pad and the fourth pad.

[0033] Additionally, the lower wiring of the first-first wiring pattern does not overlap with the second chip mounting area along the thickness direction.

[0034] In addition, the second wiring pattern portion includes a second-first wiring pattern including a fifth pad disposed on the first surface of the substrate and disposed within the second open area, a sixth pad disposed on the first surface of the substrate and disposed within the third open area, and a second connection wiring connecting between the fifth pad and the sixth pad, wherein each of the second pad and the sixth pad is provided in plurality, and the plurality of second pads are disposed to be spaced apart from each other with at least one sixth pad therebetween.

[0035] In addition, the second wiring pattern portion further includes a 2-2 wiring pattern including a seventh pad disposed on the first surface of the substrate and disposed within the second open area, an eighth pad disposed on the first surface of the substrate and disposed within the fourth open area, and a third connecting wire connecting between the seventh pad and the eighth pad; and the dummy pattern portion further includes at least one of a third dummy pattern disposed on the first surface of the substrate and disposed between the 1-2 wiring pattern and the 2-2 wiring pattern, and a fourth dummy pattern disposed on the first surface of the substrate and disposed between the first chip mounting area and the 2-2 wiring pattern.

[0036] Additionally, the dummy pattern portion further includes a fifth dummy pattern disposed on the first surface of the substrate and disposed between the second chip mounting area and the third wiring pattern portion.

[0037] In addition, the dummy pattern portion further includes a lower dummy pattern disposed under the second surface of the substrate, and the lower dummy pattern includes a first lower dummy pattern overlapping the first chip mounting area along the thickness direction, and a second lower dummy pattern overlapping the second chip mounting area along the thickness direction.

[0038] In addition, the lower dummy pattern further includes at least one of a third lower dummy pattern overlapping the 1-1 wiring pattern along the thickness direction, a fourth lower dummy pattern overlapping the 1-2 wiring pattern along the thickness direction, a fifth lower dummy pattern overlapping the 2-1 wiring pattern along the thickness direction, and a sixth lower dummy pattern overlapping the third wiring pattern portion along the thickness direction.

[0039] In addition, the first pad includes a 1-1 pad and a 1-2 pad that are alternately arranged, a leading edge of the 1-1 pad and a leading edge of the 1-2 pad are not aligned on the same line, the 1-1 pad includes a first connecting portion adjacent to the leading edge of the 1-1 pad, and a first extension portion extending from the first connecting portion, and a width of the first connecting portion is greater than a width of the first extension portion.

[0040] A flexible circuit board according to an embodiment includes a first outermost pattern and a second outermost pattern.

[0041] The first outermost pattern is spaced apart from the first end of the protective layer by a set distance, and the second outermost pattern is spaced apart from the second end (E2) of the protective layer by a set distance. Accordingly, when winding a plurality of flexible circuit boards around a roller, the first and second outermost patterns can be prevented from being damaged.

[0042] In detail, when winding the flexible circuit board module, the flexible circuit boards may be arranged in a misaligned manner. The first and second outermost patterns are spaced sufficiently apart from the first and second ends. Accordingly, when winding the flexible circuit board module, even if the flexible circuit boards are misaligned, the area of ​​the protective layer having the maximum height and the first and second outermost patterns can be prevented from overlapping.

[0043] Accordingly, the pads of the outermost pattern can be prevented from being damaged by the thick area and pressure of the protective layer.

[0044] In addition, the flexible circuit board of the embodiment includes a first chip mounting area and a second chip mounting area. In addition, a dummy pattern may be provided between the first chip mounting area and the second chip mounting area. Through this, the embodiment can minimize signal interference between the first and second semiconductor chips respectively disposed in the first chip mounting area and the second chip mounting area, and further improve the heat dissipation characteristics of the first and second semiconductor chips.

[0045] Additionally, the flexible circuit board of the embodiment may include a plurality of wiring pattern portions according to a transmission signal. Furthermore, dummy patterns may be arranged between the plurality of wiring pattern portions. Through this, the embodiment can minimize signal interference between the plurality of wiring pattern portions. Accordingly, the embodiment can enable stable signal transmission through each wiring pattern portion, thereby enabling the first and second semiconductor chips to operate stably.

[0046] Additionally, the flexible circuit board may include a dummy pattern provided on the first surface of the substrate, which overlaps the first chip mounting area and the second chip mounting area provided on the first surface of the substrate along the thickness direction. Through this, the embodiment can further improve the heat dissipation characteristics of the first and second semiconductor chips, thereby enabling the first and second semiconductor chips to operate more stably.

[0047] Additionally, the flexible circuit board may include a plurality of wiring pattern portions provided on a first surface of the substrate and a dummy pattern provided on a second surface of the substrate while overlapping along the thickness direction. Through this, the embodiment can enable stable signal transmission through each wiring pattern portion, thereby enabling the first and second semiconductor chips to operate stably.

[0048] In addition, the embodiment includes at least one of the plurality of connecting wires including an upper wire disposed on a first surface of the substrate and a lower wire disposed on a second surface of the substrate, wherein the upper wire and the lower wire are electrically connected through a via electrode. At this time, the lower wire may not overlap with the first chip mounting area and the second chip mounting area along the thickness direction. Therefore, the embodiment can further improve heat dissipation characteristics by preventing heat from being transferred to the first and second semiconductor chips through the lower wire. Furthermore, the embodiment can solve a problem in which the operational reliability of the first semiconductor chip or the second semiconductor chip is lowered due to interference with a signal transmitted through the lower wire.

[0049] Figure 1 is a top view of a flexible circuit board according to the first embodiment.

[0050] FIG. 2 is a drawing illustrating the winding of a flexible circuit board module according to the first embodiment.

[0051] Figure 3 is a cross-sectional view taken along the BB' area of ​​Figure 1.

[0052] Figure 4 is a cross-sectional view taken along the CC' area of ​​Figure 1.

[0053] Figures 5 and 6 are cross-sectional views taken along area AA' of Figure 1.

[0054] FIGS. 7A and 7B are schematic plan views showing a first surface of a flexible circuit board according to a second embodiment.

[0055] FIGS. 8A and 8B are schematic plan views illustrating a second surface of a flexible circuit board according to a second embodiment.

[0056] FIG. 9 is a cross-sectional view for explaining the signal line of the 1-1 wiring pattern shown in FIGS. 7a, 7b, 8a, and 8b.

[0057] Figure 10 is a plan view that enlarges an area of ​​Figure 7b.

[0058] Fig. 11 is a plan view showing a modified example of the first pad of the 1-1 wiring pattern of Fig. 1.

[0059] FIG. 12 and FIG. 13 are drawings for explaining the connection of a COF module and other members according to an embodiment.

[0060] FIGS. 14 to 16 are drawings of electronic devices including flexible circuit boards according to embodiments.

[0061] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the described embodiments, but may be implemented in various different forms. Within the scope of the technical concept of the present invention, one or more of the components of the embodiments may be selectively combined or substituted for use.

[0062] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0063] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “and (and) at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0064] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and are not intended to limit the nature, order, or sequence of the components.

[0065] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0066] Additionally, when it is described as being formed or disposed "above or below" each component, above or below includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or disposed between the two components.

[0067] Additionally, when expressed as “upper or lower,” it can include the meaning of not only the upward direction but also the downward direction based on one component.

[0068] In the following description, the first direction (1D) is the direction in which the pads of the display panel and the pads of the circuit board face each other. In addition, the second direction (2D) is a direction perpendicular to the first direction (1D). In addition, the first direction (1D) is a unidirectional direction of the chip mounting area, and the second direction (2D) is a longitudinal direction of the chip mounting area.

[0069]

[0070] Hereinafter, with reference to the drawings, a flexible circuit board according to a first embodiment and a COF module including the same will be described.

[0071] Referring to FIG. 1, a flexible circuit board (1000) according to the first embodiment includes a substrate (100), a conductive pattern portion, and a protective layer (300).

[0072] The above-mentioned substrate (100) includes a first surface (1S) and a second surface (2S) opposite to the first surface (1S). The conductive pattern portion and the protective layer (300) are arranged on the first surface (1S).

[0073] The substrate (100) includes a cutting line (CL). The flexible circuit board (1000) is cut along the cutting line (CL). For example, the conductive pattern portion, the protective layer, and the chip are placed on the substrate (100). Thereafter, the substrate (100) is cut along the cutting line (CL). Accordingly, a COF module is manufactured. Accordingly, the edge of the COF module becomes the cutting line (CL).

[0074] The above-mentioned substrate (100) includes an effective area (AA) and an ineffective area (UA). In detail, the first surface (1S) includes the effective area (AA) and the ineffective area (UA).

[0075] The above valid area (AA) and the non-valid area (UA) are separated by the cutting line (CL). The valid area (AA) is an area inside the cutting line (CL). In addition, the non-valid area (UA) is an area outside the cutting line (CL).

[0076] The conductive pattern portion, the protective layer, and the chip are arranged on the effective area (AA). In addition, a dummy pattern and a sprocket hole (SH) are arranged on the ineffective area (UA). The dummy pattern increases the strength of the substrate (100). In addition, the flexible circuit board (1000) is rolled or unrolled in a roll-to-roll manner by the sprocket hole (SH).

[0077] The above substrate (100) includes a chip mounting area (CHA). The chip mounting area (CHA) is disposed on the first surface (1S). The chip mounting area (CHA) is disposed on the effective area (AA). The chip (CH) is disposed on the chip mounting area (CHA). In addition, the pads of the conductive pattern portion are disposed inside the chip mounting area (CHA). In addition, the protective layer (300) is not disposed on the chip mounting area (CHA).

[0078] The substrate (100) includes a flexible material. For example, the substrate (100) may include polyimide (PI). However, the embodiment is not limited thereto. The substrate (100) may include a polymer material including polyethylene terephthalate (PET) or polyethylene naphthalate (PEN). Accordingly, the flexible circuit board can be applied to various electronic devices, including curved display devices.

[0079] The substrate (100) may have a thickness of 20 μm to 100 μm. For example, the substrate (100) may have a thickness of 25 μm to 50 μm. For example, the substrate (100) may have a thickness of 30 μm to 40 μm. When the thickness of the substrate (100) exceeds 100 μm, the overall thickness of the flexible circuit board increases. As a result, the flexible characteristics of the flexible circuit board may be reduced. In addition, when the thickness of the substrate (100) is less than 20 μm, the substrate (100) may be damaged by heat and pressure applied to the substrate when the chip is mounted on the flexible circuit board.

[0080] The conductive pattern portion and the protective layer (300) are disposed on the substrate (100). In detail, the conductive pattern portion and the protective layer (300) are disposed on the first surface (1S). In detail, the conductive pattern portion and the protective layer (300) are disposed on at least one of the effective area (AA) and the non-effective area (UA).

[0081] The above conductive pattern portion includes a wiring pattern. The wiring pattern includes a first wiring pattern (210) and a second wiring pattern (220).

[0082] Referring to FIG. 1, the first wiring pattern (210) includes a first connection wiring (211), a first pad (212a), and a second pad (212b). The first connection wiring (211), the first pad (212a), and the second pad (212b) may include the same material. In addition, the first connection wiring (211), the first pad (212a), and the second pad (212b) may be formed integrally.

[0083] The first pad (212a) is positioned within the chip mounting area (CHA). Accordingly, the first pad (212a) is connected to the terminal of the chip. As a result, the first wiring pattern (210) and the chip are connected.

[0084] The second pad (212b) is positioned outside the chip mounting area (CHA). The second pad (212b) is connected to a pad of a circuit board (3000). As a result, the first wiring pattern (210) and the circuit board (3000) are connected.

[0085] The first connection wiring (211) is arranged between the first pad (212a) and the second pad (212b). The first connection wiring (211) connects the first pad (212a) and the second pad (212b). Accordingly, the chip (CH) and the circuit board (3000) are connected. Accordingly, a signal generated from the chip (CH) is transmitted to the circuit board (3000).

[0086] The first wiring pattern (210) may further include a test pad. Specifically, a first test pad (TP1) is arranged in the non-effective area (UA). The first connection wiring (211), the first pad (212a), the second pad (212b), and the first test pad (TP1) may be formed integrally.

[0087] Before connecting the circuit board and the second pad (212b), the first wiring pattern (210) can be tested by the first test pad (TP1). For example, whether the first wiring pattern is open or shorted can be checked through the first test pad (TP1).

[0088] The second wiring pattern (220) includes a second connection wiring (221), a third pad (222a), and a fourth pad (222b). The second connection wiring (221), the third pad (222a), and the fourth pad (222b) may include the same material. In addition, the second connection wiring (221), the third pad (222a), and the fourth pad (222b) may be formed integrally.

[0089] The third pad (222a) is positioned within the chip mounting area (CHA). Accordingly, the third pad (222a) is connected to the terminal of the chip. As a result, the second wiring pattern (220) and the chip (CH) are connected.

[0090] The fourth pad (222b) is positioned outside the chip mounting area (CHA). The fourth pad (222b) is connected to a pad of an external display panel (4000). As a result, the second wiring pattern (220) and the display panel (4000) are connected.

[0091] The second connection wire (221) is arranged between the third pad (222a) and the fourth pad (222b). The second connection wire (221) connects the third pad (222a) and the fourth pad (222b). Accordingly, the chip (CH) and the display panel (4000) are connected. Accordingly, a signal generated from the chip (CH) is transmitted to the display panel (4000).

[0092] The second wiring pattern (220) may further include a test pad. Specifically, a second test pad (TP2) is disposed in the non-effective area (UA). The second test pad (TP2) is disposed outside the cutting line (CL). The second test pad (TP2) is disposed on the non-effective area (UA). The second connection wiring (221), the third pad (222a), the fourth pad (222b), and the second test pad (TP2) may be formed integrally.

[0093] Before connecting the circuit board and the fourth pad (222b), the second wiring pattern (220) can be tested by the second test pad (TP2). For example, whether the second wiring pattern is open or shorted can be checked through the second test pad (TP2).

[0094] The protective layer (300) is disposed on the effective area of ​​the first surface (1S). The protective layer (300) is disposed on the first surface (1S). Accordingly, the protective layer (300) is disposed on the first wiring pattern (210) and the second wiring pattern (220). The protective layer (300) is disposed on the first connection wiring (211), the second connection wiring (221), and the third connection wiring (231). The protective layer (300) is not disposed on the first pad (212a), the second pad (212b), the third pad (222a), and the fourth pad (222b). In addition, the protective layer (300) is not disposed on the chip mounting area (CHA).

[0095] The above conductive pattern portion includes an outermost pattern (231, 232). The outermost pattern may include a first outermost pattern (231) and a second outermost pattern (232).

[0096] The first outermost pattern (231) may be arranged on the left outermost side of the flexible circuit board (1000). The second outermost pattern (232) may be arranged on the right outermost side of the flexible circuit board (1000).

[0097] The first outermost pattern (231) and the second outermost pattern (232) may be wiring patterns. In detail, the first outermost pattern (231) and the second outermost pattern (232) may be wiring patterns through which signals or currents move.

[0098] Alternatively, the first outermost pattern (231) and the second outermost pattern (232) may be dummy patterns. In detail, the first outermost pattern (231) and the second outermost pattern (232) may be dummy patterns through which no signal or current flows.

[0099] Alternatively, one of the first outermost pattern (231) and the second outermost pattern (232) may be a wiring pattern, and the other outermost pattern may be a dummy pattern.

[0100] When the first outermost pattern (231) and the second outermost pattern (232) are wiring patterns, the first outermost pattern (231) and the second outermost pattern (231) may each include a connection wiring and a pad.

[0101] Hereinafter, it will be described as an example that the first outermost pattern (231) and the second outermost pattern (232) are wiring patterns.

[0102] The first outermost pattern (231) may include a third-first connection wiring (231a), a fifth pad (231b), and a sixth pad (231c). In addition, the second outermost pattern (232) may include a third-second connection wiring (232a), a seventh pad (232b), and an eighth pad (232c).

[0103] In Fig. 1, the fifth pad (231b) and the seventh pad (232b) are connected to the circuit board, and the sixth pad (231c) and the eighth pad (232c) are connected to the display panel.

[0104] However, the embodiment is not limited thereto. At least one of the first outermost pattern (231) and the second outermost pattern (231) may further include an additional pad connected to the chip.

[0105] Below, Fig. 1 is described as an example.

[0106]

[0107] FIG. 2 is a drawing explaining the winding of a flexible circuit board module (10000) according to the first embodiment.

[0108] Referring to FIG. 2, the flexible circuit board module (10000) includes a plurality of flexible circuit boards. For example, the flexible circuit board module (10000) may include a first flexible circuit board (10A), a second flexible circuit board (10B), a third flexible circuit board (10C), and a fourth flexible circuit board (10D).

[0109] The first flexible circuit board (10A), the second flexible circuit board (10B), the third flexible circuit board (10C), and the fourth flexible circuit board (10D) are connected. The flexible circuit board module (10000) is stored while being wound around a roller. Then, when the flexible circuit board is used, the roller is unwound and cut into individual flexible circuit boards.

[0110] When the flexible circuit board module is wound around the roller, a pressure within a set range is transmitted to fix the flexible circuit board module.

[0111] Each flexible circuit board includes a protective layer (300). The protective layer can be formed by squeezing a liquid solder resist. Accordingly, the end regions of the protective layer are formed thicker than other regions.

[0112] That is, the protective layer on the first outer area (OA1) and the second outer area (OA2) of the flexible circuit board module (10000) is placed thicker than the protective layer on the other areas.

[0113] When the above flexible circuit board module is wound around the roller, the flexible circuit boards may be partially misaligned due to external impact. Accordingly, the outermost pattern of the flexible circuit board and the thick region of the protective layer may overlap.

[0114] Accordingly, the pad of the outermost pattern may be damaged by the pressure generated when winding the flexible circuit board module and the thick area of ​​the protective layer.

[0115] Therefore, the embodiment controls the distance between the outermost pattern and the end of the protective layer (300).

[0116] Referring to FIGS. 1, 3 to 6, the end of the protective layer is spaced apart from the outermost pattern or the adjacent wiring pattern by a set range.

[0117] The above protective layer (300) includes a first end (E1), a second end (E2), a third end (E3), and a fourth end (E4).

[0118] The first end (E1) and the second end (E2) face each other in the second direction (2D). The third end (E3) and the fourth end (E4) face each other in the first direction (1D).

[0119] Referring to Fig. 3, the first outermost pattern (231) and the first end (E1) are spaced apart by a set range.

[0120] The above protective layer (300) includes a thick region at the first end (E1). Specifically, the protective layer (300) has a first maximum height (MH1) in a region adjacent to the first end (E1).

[0121] The 1-1 distance (D1-1) between the first outermost pattern (231) and the first end (E1) has a set range. The 1-1 distance (D1-1) may be greater than the width (W) of the first outermost pattern (231). The 1-1 distance (D1-1) may be greater than the widths of the first wiring pattern and the second wiring pattern. The 1-1 distance (D1-1) may be greater than the gap (S) between the outermost pattern and the second circuit.

[0122] For example, the first-first distance (D1-1) may be 1 mm or more. For example, the first-first distance (D1-1) may be 1 mm to 2 mm, 1 mm to 1.8 mm, or 1 mm to 1.5 mm.

[0123] In addition, the first-second distance (D1-2) between the first outermost pattern (231) and the cutting line (CL) adjacent to the first end (E1) has a set range. The first-second distance (D1-2) is greater than the first-first distance (D1-1). The first-second distance (D1-2) may be 1 mm or more, 1.2 mm or more, 1.3 mm or more, or 2 mm or more.

[0124] Since the first outermost pattern (231) is spaced apart from the first end (E1) by a set distance, damage to the first outermost pattern (231) can be prevented.

[0125] In detail, when the flexible circuit board module (10000) is wound, the flexible circuit boards may be arranged misaligned. The first outermost pattern (231) is spaced a sufficient distance from the first end (E1). Accordingly, even if the flexible circuit boards are misaligned when the flexible circuit board module (10000) is wound, the area of ​​the protective layer having the first maximum height (MH1) and the first outermost pattern (231) can be prevented from overlapping.

[0126] Accordingly, the pads of the first outermost pattern (231) can be prevented from being damaged by the thick area and pressure of the protective layer.

[0127] At least one dummy pattern may be placed between the first outermost pattern (231) and the first end (E1). The dummy pattern is not connected to the display panel and the circuit board.

[0128] Referring to Fig. 4, the second outermost pattern (232) and the second end (E2) are spaced apart by a set range.

[0129] The protective layer (300) includes a thick region at the second end (E2). Specifically, the protective layer (300) has a second maximum height (MH2) in a region adjacent to the second end (E2).

[0130] The 2-1 distance (D2-1) between the second outermost pattern (232) and the second end (E2) has a set range. The 2-1 distance (D2-1) may be greater than the width of the second outermost pattern (232). The 2-1 distance (D1-1) may be greater than the widths of the first wiring pattern and the second wiring pattern. The 2-1 distance (D2-1) may be greater than the gap (S) between the second outermost pattern and the second wiring pattern.

[0131] For example, the second-first distance (D2-1) may be 1 mm or more. For example, the second-first distance (D2-1) may be 1 mm to 2 mm, 1 mm to 1.8 mm, or 1 mm to 1.5 mm.

[0132] The above 1-1 distance (D1-1) and the above 2-1 distance (D2-1) may be the same or similar.

[0133] In addition, the second-second distance (D2-2) between the second outermost pattern (232) and the cutting line (CL) adjacent to the second end (E2) has a set range. The second-second distance (D2-2) is greater than the second-first distance (D2-1). The second-second distance (D2-2) may be 1 mm or more, 1.2 mm or more, 1.3 mm or more, or 2 mm or more.

[0134] The above 1-2 distance (D1-2) and the above 2-2 distance (D2-2) may be the same or similar.

[0135] Since the second outermost pattern (232) is spaced apart from the second end (E2) by a set distance, damage to the second outermost pattern (232) can be prevented.

[0136] In detail, when the flexible circuit board module (10000) is wound, the flexible circuit boards may be arranged misaligned. The second outermost pattern (232) is spaced a sufficient distance from the second end (E2). Accordingly, even if the flexible circuit boards are misaligned when the flexible circuit board module (10000) is wound, the area of ​​the protective layer having the second maximum height (MH2) and the second outermost pattern (232) can be prevented from overlapping.

[0137] Accordingly, the pads of the second outermost pattern (232) can be prevented from being damaged by the thick area and pressure of the protective layer.

[0138] Referring to FIG. 5, the second end (E2) is spaced apart from the adjacent first wiring pattern by a set range.

[0139] The protective layer (300) includes a thick region at the second end (E2). Specifically, the protective layer (300) has a second maximum height (MH2) in a region adjacent to the second end (E1).

[0140] The 2-1 distance (D2-1) between the second outermost pattern (232) and the second end (E2) has a set range. The 2-1 distance (D2-1) may be greater than the width of the second outermost pattern (232). The 2-1 distance (D1-1) may be greater than the widths of the first wiring pattern and the second wiring pattern. The 2-1 distance (D2-1) may be greater than the gap (S) between the outermost pattern and the second wiring pattern.

[0141] For example, the second-first distance (D2-1) may be 1 mm or more. For example, the second-first distance (D2-1) may be 1 mm to 2 mm, 1 mm to 1.8 mm, or 1 mm to 1.5 mm.

[0142] The above 1-1 distance (D1-1) and the above 2-1 distance (D2-1) may be the same or similar.

[0143] In addition, the second-second distance (D2-2) between the second outermost pattern (232) and the cutting line (CL) adjacent to the second end (E2) has a set range. The second-second distance (D2-2) is greater than the second-first distance (D2-1). The second-second distance (D2-2) may be 1 mm or more, 1.2 mm or more, 1.3 mm or more, or 2 mm or more.

[0144] The above 1-2 distance (D1-2) and the above 2-2 distance (D2-2) may be the same or similar.

[0145] Since the second outermost pattern (232) is spaced apart from the second end (E2) by a set distance, damage to the second outermost pattern (232) can be prevented.

[0146] In detail, when the flexible circuit board module (10000) is wound, the flexible circuit boards may be arranged misaligned. The second outermost pattern (232) is spaced a sufficient distance from the second end (E2). Accordingly, even if the flexible circuit boards are misaligned when the flexible circuit board module (10000) is wound, the area of ​​the protective layer having the second maximum height (MH2) and the second outermost pattern (232) can be prevented from overlapping.

[0147] Accordingly, the pads of the second outermost pattern (232) can be prevented from being damaged by the thick area and pressure of the protective layer.

[0148] At least one dummy pattern may be placed between the second outermost pattern (232) and the second end (E2). The dummy pattern is not connected to the display panel and the circuit board.

[0149] Referring to FIGS. 5 and 6, the wiring pattern is formed in a multilayer structure. FIGS. 5 and 6 are described focusing on the first wiring pattern. The following description applies equally to the second and third wiring patterns.

[0150] Referring to Fig. 5, the first wiring pattern is formed in multiple layers. In detail, the first connection wiring (211), the first pad (212a), and the second pad (212b) include a buffer layer (205), a metal layer (201), and a bonding layer (203).

[0151] The buffer layer (205) may include multiple layers. Specifically, the buffer layer (205) includes a first buffer layer (205a) and a second buffer layer (205b). The first buffer layer (205a) is disposed on the substrate (100). The second buffer layer (205b) is disposed on the first buffer layer (205a).

[0152] The first buffer layer (205a) includes a material having good adhesion to the substrate (100). For example, the first buffer layer (205a) may include nickel (Ni). In addition, the second buffer layer (205b) includes a material having good adhesion to the wiring pattern. For example, the second buffer layer (205b) may include chromium (Cr).

[0153] The above buffer layer (205) may have a thin film thickness in nanometer units. For example, the above buffer layer (205) may have a thickness of 20 nm or less.

[0154] The adhesion between the substrate (100) and the wiring pattern is improved by the buffer layer (205).

[0155] The metal layer (201) is disposed on the buffer layer (205). Specifically, the metal layer (201) is disposed on the second buffer layer (205b). The metal layer (201) includes a metal material. For example, the metal layer (201) may include copper (Cu).

[0156] The above metal layer (201) can be formed by electroplating using the buffer layer as a seed layer. That is, the above metal layer (201) can be a plating layer.

[0157] The thickness of the above metal layer (201) may be 10 µm to 30 µm.

[0158] The above bonding layer (203) is placed on the above metal layer (201).

[0159] The above bonding layer (203) is arranged on the side and upper surface of the metal layer (201). For example, the bonding layer (203) may be arranged to surround the metal layer (201).

[0160] The above bonding layer (203) includes a metal. For example, the bonding layer (203) may include tin (Sn). The bonding layer (203) is formed by a plating process. In detail, the bonding layer (203) may be a plating layer.

[0161] The thickness of the above bonding layer (203) may be 0.3 µm to 0.7 µm. The tin content may increase as it extends from the lower surface to the upper surface of the above bonding layer (203).

[0162] That is, the bonding layer (203) is in contact with the metal layer (201). Therefore, the tin content increases from the lower surface of the bonding layer (203) toward the upper surface. In addition, the copper content decreases from the lower surface of the bonding layer (203) toward the upper surface.

[0163] Accordingly, pure tin may remain in a thickness range of 0.1 µm to 0.3 µm from the upper surface of the bonding layer (203).

[0164] The pad can be easily bonded to the terminals of the chip, the circuit board, and the display panel by the bonding layer (203). For example, when heat and pressure are applied to the pad, the upper surface of the bonding layer melts. Pure tin remains on the upper surface of the bonding layer. Therefore, the pad can be easily bonded to the terminals of the chip, the circuit board, and the display panel.

[0165] Referring to Fig. 6, the metal layer (201) may include a first metal layer (201a) and a second metal layer (201b). The first metal layer (201a) is disposed on the buffer layer (205). The second metal layer (201b) is disposed on the first metal layer (201a). The second metal layer (201b) may be formed by electroplating using the first metal layer (201a) as a seed layer. That is, the second metal layer (201b) may be a plating layer.

[0166] The thickness of the first metal layer (201a) may be smaller than the thickness of the second metal layer (201b).

[0167] For example, the thickness of the first metal layer (201a) may be 0.7 µm to 2 µm, and the thickness of the second metal layer (201b) may be 6 µm to 25 µm.

[0168] The first metal layer (201a) and the second metal layer (201b) may include the same metal material. For example, the first metal layer (201a) and the second metal layer (201b) may include copper (Cu).

[0169] The above bonding layer (203) may include a first bonding layer (203a) and a second bonding layer (203b).

[0170] The first bonding layer (203a) is disposed on the metal layer (201). In detail, the first bonding layer (203a) is disposed on the second connection wiring (221), the third pad (222a), and the fourth pad (222b).

[0171] The second bonding layer (203b) is disposed on the first bonding layer (203a). In detail, the second bonding layer (203b) is disposed on the third pad (222a) and the fourth pad (222b).

[0172] Accordingly, the second connecting wire (221) includes the buffer layer (205), the metal layer (201), and the first bonding layer (203a). In addition, the third pad (222a) and the fourth pad (222b) include the buffer layer (205), the metal layer (201), the first bonding layer (203a), and the second bonding layer (203b).

[0173] Accordingly, the layer structure of the second connecting wire (221) is different from the layer structures of the first pad (212a) and the second pad (212b).

[0174] The first bonding layer (203a) and the second bonding layer (203b) contain metal. In detail, the first bonding layer (203a) and the second bonding layer (203b) may contain tin (Sn).

[0175] The first bonding layer (203a) and the second bonding layer (203b) are arranged with different thicknesses. Specifically, the thickness of the second bonding layer (203b) is greater than the thickness of the first bonding layer (203a).

[0176] For example, the first bonding layer (203a) has a thickness of 0.02 μm to 0.06 μm. In addition, the second bonding layer (203b) has a thickness of 0.2 μm to 0.6 μm.

[0177] Accordingly, the thickness of the first connection wiring (211) is reduced. The flexible circuit board includes a bending area (BA) that is bent in one area. The connection wiring is arranged on the bending area (BA). Accordingly, the thickness of the bonding layer on the connection wiring is formed to be small. Accordingly, when the flexible circuit board is bent, cracks can be prevented from forming in the first connection wiring (211).

[0178] The thickness of the above wiring pattern may be greater than 8 μm to 25 μm. Specifically, the thickness of the above wiring pattern may be 9 μm to 20 μm. Specifically, the thickness of the above wiring pattern may be 10 μm to 15 μm.

[0179] If the thickness of the above wiring pattern is less than 8 μm, the resistance of the above wiring pattern may increase. Furthermore, when a high current flows through the display panel, the above wiring pattern may be damaged. If the thickness of the above wiring pattern exceeds 25 μm, it becomes difficult to implement a fine pattern.

[0180]

[0181] Hereinafter, a flexible circuit board according to a second embodiment will be described. The flexible circuit board of the second embodiment may differ from the flexible circuit board of the first embodiment in that the wiring pattern is arranged on both sides of the substrate. Furthermore, the flexible circuit board of the second embodiment may differ from the flexible circuit board of the first embodiment in that it has multiple chip mounting areas.

[0182] At this time, a design structure corresponding to the outermost pattern in the flexible circuit board described in the first embodiment can be applied to the flexible circuit board of the second embodiment described below.

[0183] FIGS. 7a and 7b are plan views schematically showing a first side of a flexible circuit board according to an embodiment, FIGS. 8a and 8b are plan views schematically showing a second side of a flexible circuit board according to an embodiment, and FIG. 9 is a cross-sectional view for explaining a signal line of the 1-1 wiring pattern illustrated in FIGS. 7a, 7b, 8a, and 8b.

[0184] Specifically, Fig. 7a is a plan view schematically illustrating a first side of a flexible circuit board with the first protective layer removed, and Fig. 7b is a plan view schematically illustrating a first side of the flexible circuit board with the first protective layer disposed. In addition, Fig. 8a is a plan view schematically illustrating a second side of the flexible circuit board with the second protective layer removed, and Fig. 8b is a plan view schematically illustrating a second side of the flexible circuit board with the second protective layer disposed.

[0185] Hereinafter, a flexible circuit board of the second embodiment will be described with reference to FIGS. 7a, 7b, 8a, 8b, and 9.

[0186] A flexible circuit board (1000A) includes a substrate (1100), a conductive pattern portion (WP, DP), and a protective layer (1800).

[0187] The substrate (1100) includes a first surface (S1) and a second surface (S2) opposite to the first surface (S1). In this case, the first surface (S1) may refer to the upper surface of the substrate (1100), and the second surface (S2) may refer to the lower surface opposite to the upper surface of the substrate (1100). However, the embodiment is not limited thereto, and the first surface (S1) may refer to the lower surface of the substrate (1100), and the second surface (S2) may refer to the upper surface of the substrate (1100). Hereinafter, the first surface (S1) is described as referring to the upper surface of the substrate (1100), and the second surface (S2) is described as referring to the lower surface of the substrate (1100).

[0188] A conductive pattern portion (WP, DP) and a protective layer (1800) are arranged on the first side (S1) and the second side (S2) of the substrate (1100).

[0189] For example, the conductive pattern portion (WP, DP) may include an upper conductive pattern portion arranged on a first surface (S1) of the substrate (1100), and a lower conductive pattern portion arranged on a second surface (S2) of the substrate (1100).

[0190] At this time, as will be described later, the conductive pattern portion (WP, DP) can be divided into a wiring pattern portion (WP) and a dummy pattern portion (DP) according to function. At this time, the wiring pattern portion (WP) may mean a pattern that transmits an electrical signal. For example, the wiring pattern portion (WP) may mean a pattern that transmits a valid signal. The dummy pattern portion (DP) may mean a pattern that does not transmit an electrical signal. For example, the dummy pattern portion (DP) may mean a pattern that does not transmit a valid signal. For example, the dummy pattern portion (DP) may mean a reinforcing pattern for the rigidity of the flexible circuit board (1000A), or a heat dissipation pattern for heat dissipation.

[0191] At this time, the substrate (1100) in the drawing may not represent the final manufactured flexible circuit board (1000A). For example, the final manufactured flexible circuit board (1000A) may not include some areas of the substrate (1100) illustrated in FIGS. 7a, 7b, 8a, and 8b. For example, the substrate (1100) illustrated in FIGS. 7a, 7b, 8a, and 8b may include a cutting line (not illustrated), and thus some areas of the substrate (1100) illustrated in FIGS. 7a, 7b, 8a, and 8b may be cut and removed based on the cutting line.

[0192] For example, a conductive pattern portion (WP, DP), a protective layer (1800), and a chip (not shown) may be arranged on the first side (S1) and the second side (S2) of the substrate (1100). Thereafter, the substrate (1100) may be cut along a cutting line, and a COF module may be manufactured accordingly. Accordingly, the perimeter of the final manufactured COF module may correspond to the cutting lines of the substrate (1100) of FIGS. 7a, 7b, 8a, and 8b. For example, the perimeter of the final manufactured COF module may refer to the perimeter of the effective area (AA) illustrated in FIGS. 7a, 7b, 8a, and 8b.

[0193] In addition, a conductive pattern portion (WP, DP) and a protective layer (1800) located outside the cutting line may be provided on the first side (S1) and the second side (S2) of the substrate (1100). For example, the conductive pattern portion (WP, DP) to be removed described above may include a test pattern (not shown) for an electrical reliability test of the conductive pattern portion (WP, DP) positioned within the effective area (AA). In addition, only the conductive pattern portion (WP, DP) and the protective layer (1800) located inside the cutting line may be illustrated in FIGS. 7A, 7B, 8A, and 8B.

[0194] The substrate (1100) includes an effective area (AA) and an ineffective area (UA). In detail, the first side (S1) and the second side (S2) of the substrate (1100) include an effective area (AA) and an ineffective area (UA) excluding the effective area (AA).

[0195] The valid area (AA) and the unvalid area (UA) are separated by a cutting line. The valid area (AA) may refer to the area inside the cutting line. Furthermore, the unvalid area (UA) may refer to the area outside the cutting line.

[0196] Conductive pattern portions (WP, DP), a protective layer (1800), and chips (not shown) may be arranged on the effective area (AA) of the first surface (S1) and the second surface (S2) of the substrate (1100). In addition, a dummy pattern (not shown) and a sprocket hole (SH) may be provided on the ineffective area (UA). The dummy pattern provided in the ineffective area (UA) may have the function of increasing the strength of the substrate (1100), thereby improving process reliability in the manufacturing process of the flexible circuit board (1000A).

[0197] The substrate (1100) includes chip mounting areas (CHA1, CHA2). The chip mounting areas (CHA1, CHA2) may be provided on the first surface (S1) of the substrate (1100). The chip mounting areas (CHA1, CHA2) may be located within the effective area (AA) of the first surface (S1) of the substrate (1100). A chip (not shown) may be mounted on the chip mounting areas (CHA1, CHA2). At this time, the pads of the conductive pattern portions (WP, DP) may be located within the chip mounting areas (CHA1, CHA2).

[0198] At this time, a plurality of chip mounting areas (CHA1, CHA2) may be provided. For example, the effective area (AA) of the first surface (S1) of the substrate (1100) may include a first chip mounting area (CHA1) and a second chip mounting area (CHA2) spaced apart from each other along the first direction (1D).

[0199] That is, the specifications of the display panel connected to the flexible circuit board (1000A) are becoming higher in resolution and higher integration, and accordingly, there is a limit to controlling the display panel using a single chip. Accordingly, the flexible circuit board (1000A) of the embodiment may have a first chip mounting area (CHA1) and a second chip mounting area (CHA2) that enable a plurality of chips to be mounted. The first chip mounting area (CHA1) and the second chip mounting area (CHA2) may be spaced apart from each other in a first direction (1D) and may extend long in a second direction (2D).

[0200] At this time, each of the first chip mounting area (CHA1) and the second chip mounting area (CHA2) may refer to an area where a driving chip for driving the display panel is mounted. For example, a first semiconductor chip may be mounted in the first chip mounting area (CHA1), and a second semiconductor chip may be mounted in the second chip mounting area (CHA2).

[0201] Additionally, each of the first semiconductor chip and the second semiconductor chip may be a display driver chip (DDI) used to drive a display panel. For example, the first semiconductor chip and / or the second semiconductor chip may be a source driver chip that generates an image signal using a data signal transmitted from a timing controller and outputs the image signal to the display panel. Alternatively, the first semiconductor chip and / or the second semiconductor chip may be a gate driver chip that outputs a scan signal including an on / off signal of a transistor to the display panel.

[0202] Meanwhile, although FIGS. 7A, 7B, 8A, and 8B illustrate two chip mounting areas, the present invention is not limited thereto. For example, the effective area (AA) of the first surface (S1) of the substrate (1100) of the flexible circuit board (1000A) may be provided with three or more chip mounting areas spaced apart from each other in the first direction (1D) and / or the second direction (2D) depending on the application product.

[0203] The protective layer (1800) may be disposed on the first surface (S1) and the second surface (S2) of the substrate (1100). For example, the protective layer (1800) may include a first protective layer (1810) disposed on the first surface (S1) of the substrate (1100). Additionally, the protective layer (1800) may include a second protective layer (1820) disposed under the second surface (S2) of the substrate (1100).

[0204] The first protective layer (1810) can be disposed on the first surface (S1) of the substrate (1100) and can have a plurality of open areas.

[0205] For example, the first protective layer (1810) may include a first open area (OR1) overlapping with a first chip mounting area (CHA1) provided on a first surface (S1) of the substrate (1100) along the thickness direction of the substrate (1100). The planar area of ​​the first open area (OR1) of the first protective layer (1810) may be larger than the planar area of ​​the first chip mounting area (CHA1), but is not limited thereto. However, the planar area of ​​the first open area (OR1) of the first protective layer (1810) may be larger than the planar area of ​​the first chip mounting area (CHA1), thereby allowing the first semiconductor chip to be stably attached on pads exposed through the first open area (OR1). Accordingly, the perimeter of the inner surface of the first open area (OR1) of the first protective layer (1810) can be formed to surround the first chip mounting area (CHA1) at a location spaced apart from the first chip mounting area (CHA1). Through this, the process characteristics in the process of mounting the first semiconductor chip in the first chip mounting area (CHA1) can be improved, and the first semiconductor chip can be mounted more stably.

[0206] In addition, the first protective layer (1810) may include a second open area (OR2) overlapping with a second chip mounting area (CHA2) provided on the first surface (S1) of the substrate (1100) along the thickness direction of the substrate (1100). The planar area of ​​the second open area (OR2) of the first protective layer (1810) may be larger than the planar area of ​​the second chip mounting area (CHA2), but is not limited thereto. However, the planar area of ​​the second open area (OR2) of the first protective layer (1810) may be larger than the planar area of ​​the second chip mounting area (CHA2), and thereby, the second semiconductor chip may be stably attached on the pads exposed through the second open area (OR2). That is, the perimeter of the inner surface of the second open area (OR2) of the first protective layer (1810) can be formed to surround the second chip mounting area (CHA2) at a location spaced apart from the second chip mounting area (CHA2). Through this, the process characteristics in the process of mounting the second semiconductor chip in the second chip mounting area (CHA2) can be improved, and the second semiconductor chip can be mounted more stably.

[0207] In addition, the first protective layer (1810) may further include a third open area (OR3) and a fourth open area (OR4). That is, the substrate (1100) may include a substrate connection area (not shown) to which an external circuit board corresponding to the third open area (OR3) of the first protective layer (1810) is connected. In addition, the substrate (1100) may include a panel connection area (not shown) to which a display panel corresponding to the fourth open area (OR4) of the first protective layer (1810) is connected. For example, the substrate (1100) may include a first side end (1100E1) and a second side end (1100E2) facing each other in the first direction (1D). In addition, the substrate (1100) may include a substrate area provided in an area adjacent to the first side end (1100E1). Additionally, the substrate (1100) may include a panel connection area provided in an area adjacent to the second side (1100E2).

[0208] The first protective layer (1810) may not be disposed on the substrate connection area. That is, the first protective layer (1810) may include a third open area (OR3) that overlaps the substrate connection area in a vertical direction. In addition, the first protective layer (1810) may not be disposed on the panel connection area. That is, the first protective layer (1810) may include a fourth open area (OR4) that overlaps the panel connection area in a vertical direction.

[0209] In addition, the second protective layer (1820) may be disposed under the second surface (S2) of the substrate (1100). At this time, the conductive pattern portion (WP, DP) disposed on the second surface (S2) of the substrate (1100) may not have pads that are connected to the semiconductor chip, the display panel, and the external circuit board. Accordingly, unlike the first protective layer (1810), the second protective layer (1820) may not have an open area that opens the conductive pattern portion (WP, DP) disposed on the second surface (S2) of the substrate (1100). However, the embodiment is not limited thereto, and depending on the product design, the conductive pattern portion (WP, DP) disposed on the second surface (S2) of the substrate (1100) may include pads that are directly connected to the semiconductor chip, the display panel, and the external circuit board. In this case, the second protective layer (1820) may have an open area that opens at least a portion of the conductive pattern portion (WP, DP) provided on the second surface (S2) of the substrate (1100).

[0210] At this time, the conductive pattern portion (WP, DP) is disposed on the first surface (S1) and the second surface (S2) of the substrate (1100). For example, the conductive pattern portion (WP, DP) may be disposed in the effective area (AA) of the first surface (S1) and the second surface (S2) of the substrate (1100). In addition, the conductive pattern portion (WP, DP) may be disposed in the non-effective area (UA) of the first surface (S1) and the second surface (S2) of the substrate (1100), and the conductive pattern portion (WP, DP) provided in the non-effective area (UA) may be removed in the process of manufacturing the flexible circuit board (1000A).

[0211] The conductive pattern portion (WP, DP) may include a wiring pattern portion (WP) and a dummy pattern portion (DP) depending on the function. The wiring pattern portion (WP) and the dummy pattern portion (DP) may include the same metal material. The wiring pattern portion (WP) and the dummy pattern portion (DP) may have the same layer structure. Here, the wiring pattern portion (WP) and the dummy pattern portion (DP) may be distinguished depending on whether a valid signal is transmitted. Alternatively, the wiring pattern portion (WP) and the dummy pattern portion (DP) may be distinguished depending on whether a signal is transmitted and / or received between a plurality of components.

[0212] The wiring pattern portion (WP) may refer to a conductive pattern through which a valid signal is transmitted. Here, the valid signal may include a control signal transmitted to control a specific component, a signal acquired from a specific component, and / or a power signal. In addition, the wiring pattern portion (WP) may refer to a conductive pattern through which a signal is transmitted and / or received between a plurality of components. For example, the wiring pattern portion (WP) may electrically connect between a first semiconductor chip / second semiconductor chip and an external circuit board, or between the first semiconductor chip / second semiconductor chip and a display panel, or between an external circuit board and a display panel.

[0213] The dummy pattern portion (DP) may refer to a conductive pattern through which no valid signal is transmitted. Alternatively, the dummy pattern portion (DP) may refer to a conductive pattern that is not electrically connected between a plurality of components. For example, the dummy pattern portion (DP) may refer to a conductive pattern through which a valid signal (e.g., a test signal, etc.) may be transmitted, but which does not electrically connect between the first semiconductor chip / second semiconductor chip and the external circuit board, or between the first semiconductor chip / second semiconductor chip and the display panel, or between the external circuit board and the display panel. For example, the dummy pattern portion (DP) may be electrically connected to one of the components among the chip, the external circuit board, and the display panel, but not electrically connected to the other components. The dummy pattern portion (DP) may refer to a conductive pattern that performs at least one of a test function, a dummy function, a heat dissipation function, and a rigidity reinforcement function.

[0214] Preferably, the flexible circuit board (1000A) of the embodiment can provide a space in which a plurality of semiconductor chips are mounted. In this case, when a plurality of semiconductor chips are mounted within a limited space, signal interference between the plurality of semiconductor chips may occur, and further, operational reliability may be reduced due to heat generated during operation of the plurality of semiconductor chips.

[0215] Accordingly, the embodiment may include a dummy pattern portion (DP) for stable operation of the plurality of semiconductor chips as described above, as the plurality of semiconductor chips are mounted on the first surface (S1) of the substrate (1100), and the dummy pattern portion (DP) may block signal interference between the plurality of chips or perform a heat dissipation function.

[0216] At least one of the wiring pattern portion (WP) and the dummy pattern portion (DP) may include pads arranged within the first open area (OR1) and / or the second open area (OR2) of the first protective layer (1810). In this case, the pads arranged within the first open area (OR1) and / or the second open area (OR2) of the first protective layer (1810) may be referred to as inner pads.

[0217] In addition, at least one of the wiring pattern portion (WP) and the dummy pattern portion (DP) may be disposed between the first side end (1810E1) of the first protective layer (1810) and the first side end (1100E1) of the substrate (1100) and may include pads that are not covered by the first protective layer (1810), which may be referred to as a first outer pad. In addition, at least one of the wiring pattern portion (WP) and the dummy pattern portion (DP) may be disposed between the second side end (1810E2) of the first protective layer (1810) and the second side end (1100E2) of the substrate (1100) and may include pads that are not covered by the first protective layer (1810), which may be referred to as a second outer pad.

[0218] The wiring pattern section (WP) may include a first wiring pattern section (1200), a second wiring pattern section (1300), and a third wiring pattern section (1400) depending on the placement location and / or function.

[0219] The first wiring pattern section (1200) may include a plurality of wiring patterns. For example, the first wiring pattern section (1200) may include a first-first wiring pattern (1210) and a first-second wiring pattern (1220).

[0220] The 1-1 wiring pattern (1210) of the first wiring pattern portion (1200) may include a first end provided within a first open area (OR1) of the first protective layer (1810) and a second end provided within a third open area (OR3) of the protective layer (1810). That is, the first end of the 1-1 wiring pattern (1210) may be exposed through the first open area (OR1) of the first protective layer (1810). In addition, the second end of the 1-1 wiring pattern (1210) may be exposed through the third open area (OR3) between the first side end (1100E1) of the substrate (1100) and the first side end (1810E1) of the first protective layer (1810).

[0221] A first end of the 1-1 wiring pattern (1210) may be connected to a first semiconductor chip, and a second end of the 1-1 wiring pattern (1210) may be connected to an external circuit board. That is, the 1-1 wiring pattern (1210) may refer to a wiring pattern that electrically connects the first semiconductor chip and the external circuit board. For example, the 1-1 wiring pattern (1210) may include a first pad arranged in a first open area (OR1) of a first protective layer (1810), a second pad arranged in a third open area (OR3) of the first protective layer (1810), and an upper connection wiring and a lower connection wiring connecting the first pad and the second pad.

[0222] At this time, the 1-1 wiring pattern (1210) may extend from the first open area (OR1) toward the second chip mounting area (CHA2). At this time, the 1-1 wiring pattern (1210) may be arranged to avoid the second chip mounting area (CHA2) in order to minimize signal interference with the second wiring pattern portion (1200) connected to the second semiconductor chip.

[0223] For this purpose, the first-first wiring pattern (1210) can be placed on the first side (S1) and the second side (S2) of the substrate (1100), respectively.

[0224] Specifically, the first-first wiring pattern (1210) may include a first pad (1211) disposed in a first open area (OR1) of a first protective layer (1810). The first pad (1211) may be disposed in the first open area (OR1) and electrically connected to a terminal of a first semiconductor chip. The first pad (1211) of the first-first wiring pattern (1210) may be disposed on a first surface (S1) of a substrate (1100).

[0225] The first-first wiring pattern (1210) may include a first upper connection wiring (1212) extending from a first pad (1211). The first upper connection wiring (1212) may be arranged on a first surface (S1) of the substrate (1100). In this case, the first upper connection wiring (1212) may be arranged between a first chip mounting area (CHA1) and a second chip mounting area (CHA2) on the first surface (S1) of the substrate (1100).

[0226] The first-first wiring pattern (1210) may include a first via land (1213) connected to an end of a first upper connecting wiring (1212). The first via land (1213) may have a width greater than the width of the first upper connecting wiring (1212) and / or the first pad (1211). The first via land (1213) may be a portion connected to a via electrode (V1, V2) penetrating the first surface (S1) and the second surface (S2) of the substrate (1100) along the thickness direction of the substrate (1100). At this time, the via electrode (V1, V2) may have a width greater than a certain level in order to penetrate the substrate (1100). Accordingly, the first via land (1213) may have a width greater than the width of the first upper connection wiring (1212) and / or the first pad (1211), thereby enabling stable connection with the via electrodes (V1, V2). At this time, the first via land (1213) may be arranged between the first chip mounting area (CHA1) and the second chip mounting area (CHA2) on the first surface (S1) of the substrate (1100).

[0227] The first-first wiring pattern (1210) may include a second via land (1214). The second via land (1214) may be arranged on the second surface (S2) of the substrate (1100). The second via land (1214) may overlap the first via land (1213) along the thickness direction of the substrate (1100).

[0228] At this time, the first-first wiring pattern (1210) may include a first via electrode (V1) that is provided to penetrate the first surface (S1) and the second surface (S2) of the substrate (1100) along the thickness direction of the substrate (1100). The first via electrode (V1) may electrically connect between the first via land (1213) and the second via land (1214). For example, one surface of the first via electrode (V1) may be connected to the first via land (1213), and the other surface of the first via electrode (V1) may be connected to the second via land (1214). Through this, the first pad (1211), the first upper connection wiring (1212), and the first via land (1213) arranged on the first surface (S1) of the substrate (1100) can be electrically connected to the second via land (1214).

[0229] Additionally, the first-first wiring pattern (1210) may include a lower connection wiring (1215) extending from the second via land (1214) toward the first side end (1100E1) of the substrate (1100). The lower connection wiring (1215) may extend from the second side (S2) of the substrate (1100) toward the second chip mounting area (CHA2).

[0230] At this time, the lower connection wiring (1215) may not overlap with the second chip mounting area (CHA2) along the thickness direction of the substrate (1100). For example, the lower connection wiring (1215) may be arranged on the second surface (S2) of the substrate (1100) while avoiding an area overlapping with the second chip mounting area (CHA2). Through this, the embodiment can solve the problem of reduced operational reliability of the second semiconductor chip arranged on the second chip mounting area (CHA2) through the lower connection wiring (1215). For example, when the lower connection wiring (1215) overlaps with the second chip mounting area (CHA2) along the thickness direction, the second semiconductor chip may not operate stably due to interference with a signal transmitted through the lower connection wiring (1215). In addition, when the lower connection wiring (1215) overlaps the second chip mounting area (CHA2) along the thickness direction, heat transferred along the lower connection wiring (1215) may be transferred to the second semiconductor chip mounted in the second chip mounting area (CHA2), and thus the heat dissipation characteristics may be deteriorated. Therefore, the embodiment prevents the lower connection wiring (1215) from overlapping the second chip mounting area (CHA2) along the thickness direction, thereby solving the problem of reduced operational reliability due to signal interference, and further improving the heat dissipation characteristics.

[0231] Additionally, the first-first wiring pattern (1210) may include a third via land (1216) connected to an end of the lower connection wiring (1215). The third via land (1216) may have a width corresponding to the second via land (1214). The third via land (1216) is disposed on the second surface (S2) of the substrate (1100) and may have a width greater than the width of the end of the lower connection wiring (1215).

[0232] The first-first wiring pattern (1210) may include a fourth via land (1217). The fourth via land (1217) may be arranged on the first surface (S1) of the substrate (1100). The fourth via land (1217) may overlap with the third via land (1216) along the thickness direction of the substrate (1100).

[0233] At this time, the first-first wiring pattern (1210) may include a second via electrode (V2) that penetrates the first surface (S1) and the second surface (S2) of the substrate (1100) along the thickness direction of the substrate (1100). The second via electrode (V2) may be spaced apart from the first via electrode (V1) in the horizontal direction.

[0234] The second via electrode (V2) can be electrically connected between the third via land (1216) and the fourth via land (1217). For example, one surface of the second via electrode (V2) can be connected to the fourth via land (1217), and the other surface of the second via electrode (V2) can be connected to the third via land (1216). Through this, the lower connection wiring (1215) and the third via land (1216) arranged on the second surface (S2) of the substrate (1100) can be electrically connected to the fourth via land (1217).

[0235] Additionally, the first-first wiring pattern (1210) may include a second upper connection wiring (1218) extending from the fourth via land (1214) toward the first side end (1100E1) of the substrate (1100). The second upper connection wiring (1218) may extend from the first surface (S1) of the substrate (1100) toward the first side end (1100E1) of the substrate (1100).

[0236] Additionally, the 1-1 wiring pattern (1210) may include a second pad (1219) extending from the second upper connecting wiring (1218) and exposed through the third open area (OR3) of the first protective layer (1810). That is, the second pad (1219) of the 1-1 wiring pattern (1210) may be positioned between the first side end (1100E1) of the substrate (1100) and the first side end (1810E1) of the first protective layer (1810).

[0237] That is, the 1-1 wiring pattern (1210) may include a first pad (1211), a first upper connection wiring (1212), a first via land (1213), a first via electrode (V1), a second via land (1214), a lower connection wiring (1215), a third via land (1216), a second via electrode (V2), a fourth via land (1217), a second upper connection wiring (1218), and a second pad (1219). Through this, the 1-1 wiring pattern (1210) may be connected to the first semiconductor chip through the first pad (1211) and may be connected to an external circuit board through the second pad (1219). And, the first pad (1211), the first upper connection wiring (1212), the first via land (1213), the fourth via land (1217), the second upper connection wiring (1218), and the second pad (1219) of the 1-1 wiring pattern (1210) may be referred to as upper wirings arranged on the first surface (S1) of the substrate (1100). In addition, the second via land (1214), the lower connection wiring (1215), and the third via land (1216) of the 1-1 wiring pattern (1210) may be referred to as lower wirings arranged on the lower surface of the substrate (1100). And, the upper wiring and the lower wiring of the 1-1 wiring pattern (1210) may be electrically connected through the first via electrode (V1) and the second via electrode (V2). Furthermore, as described above, the lower wiring of the 1-1 wiring pattern (1210) does not overlap with the second chip mounting area (CHA2) along the thickness direction, and thus, the second semiconductor chip placed in the second chip mounting area (CHA2) can operate more stably.

[0238] At this time, although the drawing illustrates that the first pad (1211) and the second pad (1219) of the 1-1 wiring pattern (1210) are connected one-to-one, this is not limited thereto. For example, at least one of the connecting wires constituting the 1-1 wiring pattern (1210) may include a branch line, and the number of the first pad (1211) and the second pad (1219) of the 1-1 wiring pattern (1210) connected to each other through this may be different from each other.

[0239] The first wiring pattern section (1200) may include a first-second wiring pattern (1220). The first-second wiring pattern (1220) of the first wiring pattern section (1200) may be a wiring pattern that electrically connects the first semiconductor chip and the display panel.

[0240] The first-second wiring pattern (1220) of the first wiring pattern portion (1200) may include a third pad (1221) exposed through the first open area (OR1) of the first protective layer (1810). The third pad (1221) of the first-second wiring pattern (1220) may be connected to a terminal of the first semiconductor chip. The first-second wiring pattern (1220) may include a first connection wiring (1222) extending from the third pad (1221). The first connection wiring (1222) of the first-second wiring pattern (1220) may extend from the third pad (1221) toward the second end (1100E2) of the substrate (1100). Additionally, the first-second wiring pattern (1220) may include a fourth pad (1223) connected to the first connection wiring (1222) and arranged in the fourth open area (OR4) of the first protective layer (1810). That is, the fourth pad (1223) may be arranged between the second side end (1100E2) of the substrate (1100) and the second side end (1810E2) of the first protective layer (1810). The third pad (1221) and the fourth pad (1223) may be electrically connected through the first connection wiring (1222). The first-second wiring pattern (1220) may electrically connect the first semiconductor chip and the display panel.

[0241] That is, the first wiring pattern portion (1200) as described above may mean a wiring pattern in which at least a portion is disposed in the first open area (OR1) and / or the first chip mounting area (CHA1) of the first protective layer (1810).

[0242] In addition, the first wiring pattern portion (1200) may further include a test pattern (1230). The test pattern (1230) may be electrically connected to the 1-1 wiring pattern (1210). For example, the 1-1 wiring pattern (1210) includes a first via land (1213). And, the test pattern (1230) may be electrically connected to the first via land (1213) of the 1-1 wiring pattern (1210). To this end, the test pattern (1230) may include a test wiring (1231) connected to the first via land (1213) of the 1-1 wiring pattern (1210), and a test pad (1232) connected to the test wiring (1231). At this time, the 1-1 wiring pattern (1210) is provided in multiple numbers, and the test pattern (1230) can be connected to at least one of the multiple 1-1 wiring patterns (1210). The test pad (1232) of the test pattern (1230) can be covered with a first protective layer (1810). Then, when testing the electrical reliability of the 1-1 wiring pattern (1210) using the test pad (1232), at least a portion of the first protective layer (1810) covering the test pad (1232) can be removed. Through this, the electrical reliability of the 1-1 wiring pattern (1210) can be tested through the test pad (1232).

[0243] In addition, the wiring pattern portion (WP) may include a second wiring pattern portion (1300). The second wiring pattern portion (1300) may refer to a wiring pattern in which at least a portion is disposed in the second open area (OR2) of the first protective layer (1810) and / or the second chip mounting area (CHA2). At this time, the second wiring pattern portion (1300) may not be electrically connected to the first wiring pattern portion (1200). That is, the first wiring pattern portion (1200) and the second wiring pattern portion (1300) may be electrically insulated. Accordingly, the first semiconductor chip disposed in the first chip mounting area (CHA1) and the second semiconductor chip disposed in the second chip mounting area (CHA2) may not be electrically connected to each other on the flexible circuit board (1000A). Through this, the embodiment can enable the first semiconductor chip and the second semiconductor chip to operate more stably, and further solve the problem of reliability being reduced due to signal interference between them.

[0244] The second wiring pattern section (1300) may include a second-first wiring pattern (1310) and a second wiring pattern (1320) depending on the arrangement position.

[0245] The second-1 wiring pattern (1310) of the second wiring pattern section (1300) may be a wiring pattern that electrically connects the second semiconductor chip and the external circuit board.

[0246] The second-first wiring pattern (1310) of the second wiring pattern portion (1300) may include a fifth pad (1311) exposed through a second open area (OR2) of the first protective layer (1810). The fifth pad (1311) of the second-first wiring pattern (1310) may be connected to a terminal of the second semiconductor chip. The second-first wiring pattern (1310) may include a second connection wiring (1312) extending from the fifth pad (1311). The second connection wiring (1312) of the second-first wiring pattern (1310) may extend from the fifth pad (1311) toward the first side end (1110E1) of the substrate (1100). Additionally, the 2-1 wiring pattern (1310) may include a sixth pad (1313) connected to the second connection wiring (1312) and arranged in the third open area (OR3) of the first protective layer (1810). That is, the sixth pad (1313) may be arranged between the first side end (1100E1) of the substrate (1100) and the first side end (1810E1) of the first protective layer (1810). The fifth pad (1311) and the sixth pad (1313) may be electrically connected via the second connection wiring (1312). The 2-1 wiring pattern (1310) may electrically connect the second semiconductor chip and the external circuit board.

[0247] In addition, the 2-1 wiring pattern (1310) may be provided in multiple numbers and spaced apart along the second direction (2D). At this time, at least one 1-1 wiring pattern (1210) of the 1-1 wiring pattern portion (1200) may be arranged between the second connection wirings (1312) of the multiple 2-1 wiring patterns (1310). For example, the 4th via land (1217) and the second upper connection wiring (1218) of the 1-1 wiring pattern (1210) may be arranged between the second connection wirings (1312) of the multiple 2-1 wiring patterns (1310).

[0248] The second wiring pattern section (1300) may include a second-second wiring pattern (1320). The second-second wiring pattern (1320) of the second wiring pattern section (1300) may be a wiring pattern that electrically connects the second semiconductor chip and the display panel.

[0249] The second-second wiring pattern (1320) of the second wiring pattern portion (1300) may include a seventh pad (1321) exposed through the second open area (OR2) of the first protective layer (1810). The seventh pad (1321) of the second-second wiring pattern (1320) may be connected to a terminal of the second semiconductor chip. The second-second wiring pattern (1320) may include a third connection wiring (1322) extending from the seventh pad (1321). The third connection wiring (1322) of the second-second wiring pattern (1320) may extend from the seventh pad (1321) toward the second end (1100E2) of the substrate (1100). Additionally, the 2-2 wiring pattern (1320) may include an eighth pad (1323) connected to a third connection wiring (1322) and arranged in a fourth open area (OR4) of the first protective layer (1810). That is, the eighth pad (1323) may be arranged between the second side end (1100E2) of the substrate (1100) and the second side end (1810E2) of the first protective layer (1810). The seventh pad (1321) and the eighth pad (1323) may be electrically connected via the third connection wiring (1322). The 2-2 wiring pattern (1220) may electrically connect the second semiconductor chip and the display panel.

[0250] The wiring pattern unit (WP) may further include a third wiring pattern unit (1400). The third wiring pattern unit (1400) may be a bypass wiring pattern. For example, the third wiring pattern unit (1400) may be a power wiring line. Accordingly, the external circuit board and display panel may receive power through the third wiring pattern unit (1400).

[0251] The line width of the third wiring pattern portion (1400) may be larger than the line widths of the first and second wiring pattern portions (1200, 1300). This can enable a stable power supply.

[0252] The third wiring pattern portion (1400) may include a ninth pad (1401) exposed through a third open area (OR3) of the first protective layer (1810), a tenth pad (1402) exposed through a fourth open area (OR4) of the first protective layer (1810), and a fourth connection wiring (1403) electrically connecting the ninth pad (1401) and the tenth pad (1402).

[0253] The embodiment may further include a dummy pattern portion (DP). The dummy pattern portion (DP) may include an upper dummy pattern (1500, 1600) arranged on a first surface (S1) of the substrate (1100), and a lower dummy pattern (1700) arranged on a second surface (S2) of the substrate (1100).

[0254] The upper dummy pattern (1500, 1600) may include a first upper dummy pattern (1500) covered by a first protective layer (1810), and a second upper dummy pattern (1600) arranged in at least one open area among the first open area (OR1), the second open area (OR2), the third open area (OR3), and the fourth open area (OR4) of the first protective layer (1810).

[0255] The second upper dummy pattern (1600) will be described first as follows.

[0256] The second upper dummy pattern (1600) may include a second-first upper dummy pattern (1610), a second-second upper dummy pattern (1620), a second-third upper dummy pattern (1630), and a second-fourth upper dummy pattern (1640). At this time, each of the second-first upper dummy pattern (1610), the second-second upper dummy pattern (1620), the second-third upper dummy pattern (1630), and the second-fourth upper dummy pattern (1640) may include a dummy pad and a dummy wiring.

[0257] The 2-1 upper dummy pattern (1610) may include a first dummy pad (1611) positioned within a first open area (OR1) of a first protective layer (1810), and a first dummy wiring (1612) connected from the first dummy pad (1611) and covered with the first protective layer (1810). The 2-1 upper dummy pattern (1610) may be connected to a terminal of the first semiconductor chip. At this time, the 2-1 upper dummy pattern (1610) may be connected to the terminal of the first semiconductor chip, and may be used for testing a specific terminal of the first semiconductor chip, or may have a heat dissipation function for transferring heat generated in the first semiconductor chip.

[0258] The second-second upper dummy pattern (1620) may include a second dummy pad (1622) positioned within the second open area (OR2) of the first protective layer (1810), and a second dummy wiring (1621) connected from the second dummy pad (1622) and covered with the first protective layer (1810). The second-second upper dummy pattern (1620) may be connected to a terminal of the second semiconductor chip. At this time, the second-second upper dummy pattern (1620) may be connected to the terminal of the second semiconductor chip, and may be used for testing a specific terminal of the second semiconductor chip, or may have a heat dissipation function for transferring heat generated in the second semiconductor chip.

[0259] The 2-3 upper dummy pattern (1630) may include a third dummy pad (1631) positioned within the third open area (OR3) of the first protective layer (1810), and a third dummy wiring (1632) connected from the third dummy pad (1631) and covered with the first protective layer (1810). The 2-3 upper dummy pattern (1630) may be connected to an external circuit board. At this time, the 2-3 upper dummy pattern (1630) may be connected to the external circuit board and used for testing a specific line connected to the external circuit board, or may serve a heat dissipation function.

[0260] The 2-4 upper dummy pattern (1640) may include a fourth dummy pad (1641) positioned within the fourth open area (OR4) of the first protective layer (1810), and a fourth dummy wiring (1642) connected from the fourth dummy pad (1641) and covered with the first protective layer (1810). The 2-4 upper dummy pattern (1640) may be connected to a display panel. At this time, the 2-4 upper dummy pattern (1640) may be connected to the display panel and used for testing a specific line connected to the display panel or may have a heat dissipation function.

[0261] The first upper dummy pattern (1500) may include first to fifth dummy patterns (1510, 1520, 1530, 1540, 1550) depending on the placement position.

[0262] The first dummy pattern (1510) may be placed on the first surface (S1) of the substrate (1100). The first dummy pattern (1510) may be placed between the first chip mounting area (CHA1) and the second chip mounting area (CHA2) on the first surface (S1) of the substrate (1100). That is, the first dummy pattern (1510) may shield the area between the first chip mounting area (CHA1) and the second chip mounting area (CHA2).

[0263] For example, the first dummy pattern (1510) can resolve signal interference occurring between a first semiconductor chip mounted in a first chip mounting area (CHA1) and a second semiconductor chip mounted in a second chip mounting area (CHA2). In addition, the first dummy pattern (1510) can prevent heat from being transferred between the first semiconductor chip and the second semiconductor chip. Through this, the first dummy pattern (1510) can further improve heat dissipation characteristics while minimizing mutual interference between the first semiconductor chip and the second semiconductor chip.

[0264] In addition, the first dummy pattern (1510) may be placed between the 1-1 wiring pattern (1210) of the first wiring pattern portion (1200) and the 2-2 wiring pattern (1320) of the second wiring pattern portion (1300). Through this, the first dummy pattern (1510) may minimize signal interference that may occur between the 1-1 wiring pattern (1210) of the first wiring pattern portion (1200) and the 2-2 wiring pattern (1320) of the second wiring pattern portion (1300).

[0265] Additionally, at least a portion of the first dummy pattern (1510) may not overlap with the first chip mounting area (CHA1) and the second chip mounting area (CHA2) along the thickness direction of the substrate (1100). For example, at least a portion of the first dummy pattern (1510) may not overlap with the first open area (OR1) and the second open area (OR2) of the first protective layer (1810) along the thickness direction of the substrate (1100).

[0266] Preferably, the first dummy pattern (1510) may not overlap the first chip mounting area (CHA1) and the second chip mounting area (CHA2) along the thickness direction of the substrate (1100) as a whole. For example, the first dummy pattern (1510) may not overlap the first open area (OR1) and the second open area (OR2) of the first protective layer (1810) along the thickness direction of the substrate (1100) as a whole.

[0267] Accordingly, the embodiment can more effectively prevent signal interference occurring between a first semiconductor chip mounted in a first chip mounting area (CHA1) and a second semiconductor chip mounted in a second chip mounting area (CHA2) by using a first dummy pattern (1510).

[0268] The second dummy pattern (1520) may be placed between the 2-1 wiring patterns (1310) of the second wiring pattern section (1300). At this time, the 1-1 wiring pattern (1210) of the first wiring pattern section (1200) may be placed between the 2-1 wiring patterns (1310) of the second wiring pattern section (1300).

[0269] At this time, the 2-1 wiring pattern (1310) and the 1-1 wiring pattern (1210) arranged adjacent to each other may be wirings that transmit similar signals or wirings that transmit signals with little signal interference between them. Accordingly, the 2-1 wiring pattern (1310) and the 1-1 wiring pattern (1210) may be arranged alternately. At this time, the 2-1 wiring pattern (1310) and the 1-1 wiring pattern (1210) may be grouped based on a group in which there is no signal interference between them.

[0270] That is, the 2-1 wiring pattern (1310) and the 1-1 wiring pattern (1210) can be grouped into multiple groups, and the second dummy pattern (1520) can be placed between the multiple groups. Through this, the second dummy pattern (1520) can minimize signal interference that may occur between the multiple groups of the 2-1 wiring pattern (1310) and the 1-1 wiring pattern (1210).

[0271] The third dummy pattern (1530) may be placed between the first-second wiring pattern (1220) of the first wiring pattern portion (1200) and the third wiring pattern portion (1400) and / or the second-second wiring pattern (1320) of the second wiring pattern portion (1300). The third dummy pattern (1530) may minimize signal interference that may occur between the first-second wiring pattern (1220) of the first wiring pattern portion (1200) and the third wiring pattern portion (1400) and / or signal interference that may occur between the first-second wiring pattern (1220) of the first wiring pattern portion (1200) and the second-second wiring pattern (1320) of the second wiring pattern portion (1300).

[0272] The fourth dummy pattern (1540) may be arranged between the first chip mounting area (CHA1) and the third wiring pattern portion (1400). At this time, the third wiring pattern portion (1400) may be a signal line through which a power signal is transmitted. At this time, when the third wiring pattern portion (1400) and the first chip mounting area (CHA1) are adjacent to each other, normal operation of the first semiconductor chip mounted in the first chip mounting area (CHA1) may be difficult due to the third wiring pattern portion (1400) through which a relatively high level signal is transmitted. Therefore, the fourth dummy pattern (1540) may be arranged between the first chip mounting area (CHA1) and the third wiring pattern portion (1400) to enable the first semiconductor chip to operate more stably.

[0273] Furthermore, the fourth dummy pattern (1540) may be further arranged between the first chip mounting area (CHA1) and the second-second wiring pattern (1320) of the second wiring pattern portion (1300). Through this, the fourth dummy pattern (1540) may partition between the first chip mounting area (CHA1) and the second wiring pattern portion (1300) and the third wiring pattern portion (1400), thereby enabling the first semiconductor chip to operate more stably.

[0274] The fifth dummy pattern (1550) may be arranged between the second chip mounting area (CHA2) and the third wiring pattern portion (1400). At this time, the third wiring pattern portion (1400) may be a signal line through which a power signal is transmitted. At this time, when the third wiring pattern portion (1400) and the second chip mounting area (CHA2) are adjacent to each other, normal operation of the second semiconductor chip mounted in the second chip mounting area (CHA2) may be difficult due to the third wiring pattern portion (1400) through which a relatively high level signal is transmitted. Therefore, the fifth dummy pattern (1550) may be arranged between the second chip mounting area (CHA2) and the third wiring pattern portion (1400) to enable the second semiconductor chip to operate more stably.

[0275] Additionally, a lower dummy pattern (1700) may be arranged on the second side (S2) of the substrate (1100). The lower dummy pattern (1700) may include first to seventh lower dummy patterns (1710, 1720, 1730, 1740, 1750, 1760, 1770).

[0276] The first lower dummy pattern (1710) may be arranged on the second surface (S2) of the substrate (1100) and may overlap the first chip mounting area (CHA1) of the first surface (S1) of the substrate (1100) along the thickness direction of the substrate (1100). The first lower dummy pattern (1710) may have a function of dissipating heat from the first semiconductor chip mounted on the first chip mounting area (CHA1). Through this, the embodiment may enable the first semiconductor chip to operate more stably.

[0277] The second lower dummy pattern (1720) may be arranged on the second surface (S2) of the substrate (1100) and may overlap the second chip mounting area (CHA2) of the first surface (S1) of the substrate (1100) along the thickness direction of the substrate (1100). The second lower dummy pattern (1720) may have a function of dissipating heat from a second semiconductor chip mounted on the second chip mounting area (CHA2). Through this, the embodiment may enable the second semiconductor chip to operate more stably.

[0278] The third lower dummy pattern (1730) can overlap the first-first wiring pattern (1210) of the first wiring pattern portion (1200) arranged on the first surface (S1) of the substrate (1100) along the thickness direction of the substrate (1100). The third lower dummy pattern (1730) can dissipate heat transmitted through the first-first wiring pattern (1210), thereby enabling a signal to be transmitted more stably through the first-first wiring pattern (1210).

[0279] The fourth lower dummy pattern (1740) can overlap the first-second wiring pattern (1220) of the first wiring pattern portion (1200) arranged on the first surface (S1) of the substrate (1100) along the thickness direction of the substrate (1100). The fourth lower dummy pattern (1740) can dissipate heat transmitted through the first-second wiring pattern (1220), thereby enabling a signal to be transmitted more stably through the first-second wiring pattern (1220).

[0280] In addition, the fourth lower dummy pattern (1740) can overlap the second-second wiring pattern (1320) of the second wiring pattern portion (1300) arranged on the first surface (S1) of the substrate (1100) along the thickness direction of the substrate (1100). Therefore, the fourth lower dummy pattern (1740) can dissipate heat transmitted through the second-second wiring pattern (1320), thereby enabling a signal to be transmitted more stably through the second-second wiring pattern (1320).

[0281] The fifth lower dummy pattern (1750) can overlap the second-first wiring pattern (1310) of the second wiring pattern portion (1300) arranged on the first surface (S1) of the substrate (1100) along the thickness direction of the substrate (1100). The fifth lower dummy pattern (1750) can dissipate heat transmitted through the second-first wiring pattern (1310), thereby enabling a signal to be transmitted more stably through the second-first wiring pattern (1310).

[0282] The sixth lower dummy pattern (1760) may overlap the third wiring pattern portion (1400) arranged on the first surface (S1) of the substrate (1100) along the thickness direction of the substrate (1100). The sixth lower dummy pattern (1760) may dissipate heat transmitted through the third wiring pattern portion (1400), thereby enabling a signal to be transmitted more stably through the third wiring pattern portion (1400).

[0283] The seventh lower dummy pattern (1770) may overlap the test pattern (1230) arranged on the first surface (S1) of the substrate (1100) along the thickness direction of the substrate (1100). The seventh lower dummy pattern (1770) may dissipate heat transmitted through the test pattern (1230), thereby enabling a more stable test operation through the test pattern (1230).

[0284]

[0285] As described above, the flexible circuit board of the embodiment also includes a first chip mounting area and a second chip mounting area. In addition, a dummy pattern may be provided between the first chip mounting area and the second chip mounting area. Through this, the embodiment can minimize signal interference between the first and second semiconductor chips respectively disposed in the first chip mounting area and the second chip mounting area, and further improve the heat dissipation characteristics of the first and second semiconductor chips.

[0286] Additionally, the flexible circuit board of the embodiment may include a plurality of wiring pattern portions according to a transmission signal. Furthermore, dummy patterns may be arranged between the plurality of wiring pattern portions. Through this, the embodiment can minimize signal interference between the plurality of wiring pattern portions. Accordingly, the embodiment can enable stable signal transmission through each wiring pattern portion, thereby enabling the first and second semiconductor chips to operate stably.

[0287] Additionally, the flexible circuit board may include a dummy pattern provided on the first surface of the substrate, which overlaps the first chip mounting area and the second chip mounting area provided on the first surface of the substrate along the thickness direction. Through this, the embodiment can further improve the heat dissipation characteristics of the first and second semiconductor chips, thereby enabling the first and second semiconductor chips to operate more stably.

[0288] Additionally, the flexible circuit board may include a plurality of wiring pattern portions provided on a first surface of the substrate and a dummy pattern provided on a second surface of the substrate while overlapping along the thickness direction. Through this, the embodiment can enable stable signal transmission through each wiring pattern portion, thereby enabling the first and second semiconductor chips to operate stably.

[0289] In addition, the embodiment includes at least one of the plurality of connecting wires including an upper wire disposed on a first surface of the substrate and a lower wire disposed on a second surface of the substrate, wherein the upper wire and the lower wire are electrically connected through a via electrode. At this time, the lower wire may not overlap with the first chip mounting area and the second chip mounting area along the thickness direction. Therefore, the embodiment can further improve heat dissipation characteristics by preventing heat from being transferred to the first and second semiconductor chips through the lower wire. Furthermore, the embodiment can solve a problem in which the operational reliability of the first semiconductor chip or the second semiconductor chip is lowered due to interference with a signal transmitted through the lower wire.

[0290]

[0291] Figure 10 is a plan view that enlarges an area of ​​Figure 7b.

[0292] Specifically, FIG. 10 may illustrate pads arranged in a first open area (OR1) of a first protective layer (1810). Alternatively, FIG. 10 may illustrate pads arranged in a second open area (OR2) of a first protective layer (1810).

[0293] Referring to FIG. 10, a wiring pattern portion (1900) and an upper dummy pattern (1930) may be arranged on a first surface (S1) of a substrate (1100). Each of the wiring pattern portion (1900) and the upper dummy pattern (1930) may include a pad exposed through a first open area (OR1) or a second open area (OR2) of a protective layer (1810).

[0294] The wiring pattern portion (1900) of FIG. 10 may refer to the 1-1 wiring pattern (1210) or the 1-2 wiring pattern (1220) of the first wiring pattern portion (1200) described with reference to FIGS. 7a and 7b, and the upper dummy pattern (1930) may refer to the 2-1 upper dummy pattern (1610). In this case, the open area of ​​the first protective layer (1810) of FIG. 10 may refer to the first open area (OR1).

[0295] In contrast, the wiring pattern portion (1900) of FIG. 10 may refer to the 2-1 wiring pattern (1310) or the 2-2 wiring pattern (1320) of the 2nd wiring pattern portion (1300) described with reference to FIGS. 7a and 7b, and the upper dummy pattern (1930) may refer to the 2-2 upper dummy pattern (1620). In this case, the open area of ​​the first protective layer (1810) of FIG. 10 may refer to the second open area (OR2).

[0296] The wiring pattern section (1900) may include a first wiring pattern (1910) and a second wiring pattern (1920) alternately arranged along the second direction (2D). At this time, the first wiring pattern (1910) and the second wiring pattern (1920) may have different lengths.

[0297] For example, the first wiring pattern (1910) may include a first overlapping region (1911) overlapping an open area of ​​the first protective layer (1810) and a first non-overlapping region (1912) covered with the first protective layer (1810). Additionally, the second wiring pattern (1920) may include a second overlapping region (1921) overlapping an open area of ​​the first protective layer (1810) and a second non-overlapping region (1922) covered with the first protective layer (1810).

[0298] At this time, the planar area of ​​the first overlapping region (1911) may be different from the planar area of ​​the second overlapping region (1921). For example, the planar area of ​​the first overlapping region (1911) may be larger than the planar area of ​​the second overlapping region (1921). That is, the first wiring pattern (1910) may be arranged further inside the chip mounting region than the second wiring pattern (1920). In addition, the embodiment may alternately arrange the first wiring pattern (1910) and the second wiring pattern (1920) having planar areas of different overlapping regions. Through this, the embodiment may secure a process margin in the process of mounting a semiconductor chip, thereby improving product yield. Here, the process margin may mean an alignment tolerance between each of the first overlapping region (1911) and the second overlapping region (1921) and the terminal of the semiconductor chip in the process of mounting a semiconductor chip.

[0299] Additionally, the upper dummy pattern (1930) may include a first dummy pattern (1940) and a second dummy pattern (1950) alternately arranged along the second direction (2D). At this time, the first dummy pattern (1940) and the second dummy pattern (1950) may have different lengths.

[0300] Additionally, the first dummy pattern (1940) may include a third overlapping region (1941) overlapping the open region of the first protective layer (1810) and a third non-overlapping region (1942) covered with the first protective layer (1810). Additionally, the second dummy pattern (1950) may include a fourth overlapping region (1951) overlapping the open region of the first protective layer (1810) and a fourth non-overlapping region (1952) covered with the first protective layer (1810).

[0301] At this time, the planar area of ​​the third overlapping region (1941) may be different from the planar area of ​​the fourth overlapping region (1951). For example, the planar area of ​​the third overlapping region (1941) may be larger than the planar area of ​​the fourth overlapping region (1951).

[0302] At this time, the planar area of ​​the third overlapping region (1941) and the planar area of ​​the fourth overlapping region (1951) may each be smaller than the planar area of ​​the first overlapping region (1911). That is, the tips of the first dummy pattern (1940) and the second dummy pattern (1950) may have a step difference from the tip of the first wiring pattern (1910). Through this, the embodiment can easily distinguish between the pad of the wiring pattern and the pad of the dummy pad, thereby further improving the process characteristics in the mounting process of the semiconductor chip.

[0303] In addition, the first wiring pattern (1910) and the second wiring pattern (1920) may be spaced apart from each other by a first gap (W1). In addition, the first dummy pattern (1940) and the second dummy pattern (1950) may be spaced apart from each other by a second gap (W2) different from the first gap (W1). At this time, the first gap (W1) may be larger than the second gap (W2). Preferably, the second gap (W2) may satisfy a range of 110% to 300% of the first gap (W1). More preferably, the second gap (W2) may satisfy a range of 130% to 280% of the first gap (W1).

[0304] If the second gap (W2) is less than 110% of the first gap (W1), the heat dissipation improvement effect and / or signal interference prevention effect that occur by increasing the gap between the upper dummy patterns (1930) may be insufficient. In addition, if the second gap (W2) is greater than 300% of the first gap (W1), it may be difficult to place all of the wiring pattern portions (1900) within a limited space, and thus the size of the flexible circuit board (1000A) may increase.

[0305]

[0306] Fig. 11 is a plan view showing a modified example of the first pad of the 1-1 wiring pattern of Fig. 7a.

[0307] Referring to FIG. 11, the first-first wiring pattern (1210) is arranged in the first chip mounting area (CHA1) and includes a first pad (1211) connected to the chip.

[0308] At this time, the 1-1 wiring pattern (1210) may include a plurality of 1-1 wiring patterns spaced apart from each other along the horizontal direction. Each of the plurality of 1-1 wiring patterns may be arranged to extend long in the first direction (1D). In addition, the plurality of 1-1 wiring patterns may be arranged to be spaced apart from each other in the second direction (2D). At this time, the plurality of 1-1 wiring patterns may have different lengths and may be arranged alternately in the first and second rows.

[0309] For example, the 1-1 wiring pattern (1210) may include a plurality of 1-1 pads (P11) spaced apart and arranged in the first direction (1D). For example, the 1-1 pads (P11) may be arranged in odd or even rows.

[0310] Additionally, the first-first wiring pattern (1210) may include a plurality of first-second pads (P12) arranged between a plurality of first-first pads (P11). For example, the first-second pads (P12) may be arranged in a different column from the first-first pads (P11). For example, the first-second pads (P12) may be arranged in an even column or an odd column.

[0311] For example, the 1-1 pad (P11) may be placed in the 1st, 3rd, 5th, and 7th rows, and the 1-2 pad (P12) may be placed in the 2nd, 4th, and 6th rows. In other words, the 1-1 pad (P11) and the 1-2 pad (P12) may be placed alternately.

[0312] At this time, the first-first pad (P11) and the first-second pad (P12) may have different lengths. For example, the respective tips of the first-first pad (P11) and the first-second pad (P12) may be provided at different positions. For example, the tip of the first-first pad (P11) may be located further inside the substrate (1100) than the end of the first-second pad (P12). The tips of the first-first pad (P11) and the first-second pad (P12) may be formed in a zigzag shape and positioned at different positions.

[0313] Accordingly, the plurality of first-first pads (P11) may not overlap with the first-second pads (P12) along the second direction (2D). In contrast, the plurality of first-second pads (P12) may overlap with the plurality of first-first pads (P11) along the second direction (2D).

[0314] At this time, the planar shape of the plurality of first-1 pads (P11) may be different from the planar shape of the plurality of first-2 pads (P12). For example, the plurality of first-1 pads (P11) may include a region in which the line width changes along the first direction (1D), which is the longitudinal direction. In contrast, the plurality of first-2 pads (P12) may not have the line width change along the first direction (1D).

[0315] For example, the plurality of first-1 pads (P11) may include a region having a line width greater than the line width of the plurality of first-2 pads (P12).

[0316] That is, the 1-1 pad (P11) may include a first coupling portion (P11-1) and a first extension portion (P11-2) extending from the first coupling portion (P11-1). The first coupling portion (P11-1) of the 1-1 pad (P11) may refer to an area coupled to a terminal of the chip. In addition, the first extension portion (P11-2) of the 1-1 pad (P11) may connect between the first coupling portion (P11-1) and the connection wiring (T1) of the 1-1 pad (P11).

[0317] The line width (W3) of the first connecting portion (P11-1) may be different from the line width (W4) of the first extension portion (P11-2). Preferably, the line width (W3) of the first connecting portion (P11-1) may be greater than the line width (W4) of the first extension portion (P11-2).

[0318] That is, the first coupling portion (P11-1) does not overlap with the first-second pad (P12) along the second direction (1D). For example, the first-second pad (P12) may not be arranged on the left and right sides of the first coupling portion (P11-1). Accordingly, the spacing between adjacent coupling portions in the area where the first coupling portion (P11-1) is arranged may correspond to the spacing between adjacent first coupling portions. Accordingly, in the embodiment, even if the line width (W1) of the first coupling portion (P11-1) is increased in the area where the first coupling portion (P11-1) is arranged, there may be room for the spacing between adjacent coupling portions.

[0319] Accordingly, the embodiment allows the line width (W1) of the first bonding portion (P11-1) to have a relatively larger line width than the line widths of the other bonding portions. Through this, the embodiment can improve the contact area between the first bonding portion (P11-1) and the contact member, thereby enabling the chip to be stably mounted on the first bonding portion (P11-1). Furthermore, since the second bonding portion (P12-1) of the first-second pad (P12) adjacent to the first bonding portion (P11-1) does not exist, the spacing between the plurality of first bonding portions (P11-1) can be maintained at a certain level or more. Accordingly, the embodiment can secure a process margin in the process of mounting a semiconductor chip even if the line width (W3) of the first bonding portion (P11-1) is increased, thereby improving the product yield. Here, the process margin may mean the alignment tolerance between the first joint (P11-1) and the terminal of the semiconductor chip in the process of mounting the semiconductor chip.

[0320] The line width (W4) of the first extension portion (P11-2) may be smaller than the line width (W3) of the first bonding portion (P11-1). This is because the first extension portion (P11-2) is arranged to overlap the second bonding portion (P12-1) of the adjacent 1-2 pad (P12) along the second direction (2D). That is, when the line width (W4) of the first extension portion (P11-2) increases, the gap between the first extension portion (P11-2) of the 1-1 pad (P11) and the second bonding portion (P12-1) of the 1-2 pad (P12) may narrow. In this case, the alignment tolerance between the second bonding portion (P12-1) of the 1-2 pad (P12) and the terminal of the chip may decrease, which may result in a decrease in product yield.

[0321] The line width (W3) of the first bonding portion (P11-1) may have a range of 5 μm to 10 μm. For example, the line width (W3) of the first bonding portion (P11-1) may have a range of 5.5 μm to 9.5 μm. For example, the line width (W3) of the first bonding portion (P11-1) may have a range of 6 μm to 9 μm. If the line width (W3) of the first bonding portion (P11-1) is less than 5 μm, the contact area between the first bonding portion (P11-1) and the adhesive member may not be secured, and thus, it may be difficult to stably mount the chip on the first bonding portion (P11-1). In addition, if the line width (W3) of the first bonding portion (P11-1) exceeds 10 μm, the gap between adjacent first bonding portions (P11-1) may be reduced. In addition, if the spacing between adjacent first joints (P11-1) is reduced, it may be difficult to secure a process margin in the chip mounting process, and thus the product yield may decrease.

[0322] The line width (W4) of the first extension portion (P11-2) may be smaller than the line width (W3) of the first joining portion (P11-1). For example, the line width (W4) of the first extension portion (P11-2) may satisfy a range of 40% to 95% of the line width (W3) of the first joining portion (P11-1). For example, the line width (W4) of the first extension portion (P11-2) may satisfy a range of 42% to 93% of the line width (W3) of the first joining portion (P11-1). For example, the line width (W4) of the first extension portion (P11-2) may satisfy a range of 45% to 90% of the line width (W3) of the first joining portion (P11-1). At this time, if the line width (W4) of the first extension portion (P11-2) is less than 40% of the line width (W3) of the first coupling portion (P11-1), the signal transmission characteristics may deteriorate due to the difference in line widths between the first coupling portion (P11-1) and the first extension portion (P11-2). In addition, if the line width (W4) of the first coupling portion (P11-1) exceeds 95% of the line width (W3) of the first coupling portion (P11-1), the gap between the first extension portion (P11-2) and the second coupling portion (P12-1) may decrease, and thus, it may be difficult to secure a process margin in the chip mounting process.

[0323] The first-second pad (P12) may include a second joining portion (P12-1) and a second extension portion (P12-2). At this time, the first-second pad (P12) may not have a change in width along the longitudinal direction. For example, even if the first-second pad (P12) has a change in width along the longitudinal direction, the degree of change in width of the first-second pad (P12) may be less than the degree of change in width of the first-first pad (P11) in the longitudinal direction. Preferably, the line width (W5) of the second joining portion (P12-1) and the second extension portion (P12-2) of the first-second pad (P12) may be the same, but is not limited thereto.

[0324] In the embodiment, the width of the first-second pad (P12) arranged in a relatively circuit-dense area is smaller than the width of the first-first pad (P11). Through this, the embodiment can ensure sufficient process margin in the process of mounting a chip on the first-second pad (P12), thereby improving product yield.

[0325] For example, the line width (W3) of the second coupling portion (P12-1) may be smaller than the line width (W3) of the first coupling portion (P11-1). Preferably, the line width (W3) of the second coupling portion (P12-1) may satisfy a range of 40% to 95% of the line width (W3) of the first coupling portion (P11-1). For example, the line width (W5) of the second coupling portion (P12-1) may satisfy a range of 42% to 93% of the line width (W3) of the first coupling portion (P11-1). For example, the line width (W5) of the second coupling portion (P12-1) may satisfy a range of 45% to 90% of the line width (W3) of the first coupling portion (P11-1). At this time, if the line width (W5) of the second bonding portion (P12-1) is less than 40% of the line width (W3), it may be difficult to secure a contact area between the second bonding portion (P12-1) and the adhesive material, and thus, it may be difficult to stably mount the chip. In addition, if the line width (W5) of the second bonding portion (P12-1) exceeds 95% of the line width (W3) of the first bonding portion (P11-1), the gap between the second bonding portion (P12-1) and the first extension portion (P11-2) may decrease, and thus, it may be difficult to secure a process margin in the process of mounting the chip.

[0326]

[0327] FIG. 12 and FIG. 13 are drawings for explaining the connection of a COF module and other members according to an embodiment.

[0328] Referring to FIGS. 12 and 13, one end of the COF module (2000) is connected to the display panel (4000), and the other end is connected to the circuit board (3000).

[0329] Referring to FIG. 12, the display panel (4000) and the circuit board (3000) are disposed on one surface of the COF module (2000). That is, in the flexible circuit board according to the first embodiment, the display panel (4000) and the circuit board (3000) are disposed on the same surface of the COF module (2000).

[0330] Referring to FIG. 13, the display panel (4000) and the circuit board (3000) are disposed on different surfaces of the COF module (2000). That is, in the flexible circuit board according to the second embodiment, the display panel (4000) and the circuit board (3000) are disposed on different surfaces of the COF module (2000).

[0331] Since the COF module (2000) includes a flexible substrate, it has a rigid shape and a bent shape between the display panel (3000) and the circuit board (4000). That is, the COF module (2000) may include a bending area (BA).

[0332] The COF module (2000) connects the display panel (4000) and the circuit board (3000), which are arranged opposite each other, in a curved manner. Therefore, the thickness of the electronic device is reduced. Furthermore, the design freedom of the electronic device is enhanced. Furthermore, the COF module (2000) prevents wiring from breaking even when in a curved configuration. Consequently, the reliability of the electronic device is enhanced.

[0333] Since the above COF module is flexible, it can be used in various electronic devices.

[0334] FIGS. 14 to 16 are drawings of electronic devices including flexible circuit boards according to embodiments.

[0335] For example, referring to FIG. 14, the COF module can be applied to a flexible touch window. Accordingly, a touch device device including the COF module can be a flexible touch device. Accordingly, the user can bend or fold it by hand. Such a flexible touch window can be applied to a wearable touch, etc.

[0336] Referring to FIG. 15, the COF module can be applied to various wearable touch devices including curved displays. Accordingly, an electronic device including the COF module can be slimmed down or made lighter.

[0337] Referring to Fig. 16, the COF module can be used in various electronic devices having a display portion, such as a TV, monitor, or laptop. In this case, the COF module can also be used in an electronic device having a curved display portion.

[0338]

[0339] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as falling within the scope of the present invention.

[0340] In addition, although the above description focuses on embodiments, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. Description; A conductive pattern portion arranged on the above-mentioned substrate; and Including a protective layer disposed on the conductive pattern portion, The above protective layer comprises a plurality of open areas spaced apart from each other along the first direction, The conductive pattern portion includes an outermost pattern closest to the end of the protective layer located in a second direction perpendicular to the first direction, A flexible circuit board, wherein the distance between the end of the protective layer and the outermost pattern is 1 mm or more.

2. In paragraph 1, The ends of the above protective layer include first ends and second ends facing in the second direction, The outermost pattern above is, a first outermost pattern positioned most adjacent to the first end, and Including a second outermost pattern arranged most adjacent to the second end, A flexible circuit board, wherein the distance is a distance between the first end and the first outermost pattern or a distance between the second end and the second outermost pattern.

3. In paragraph 2, The above conductive pattern portion, A wiring pattern portion including a pad arranged in at least one open area among the plurality of open areas, and Including a dummy pattern portion spaced apart from the above wiring pattern portion, The above first outermost pattern is the wiring pattern portion or the dummy pattern portion, A flexible circuit board, wherein the second outermost pattern is the wiring pattern portion or the dummy pattern portion.

4. In paragraph 2, The above description includes a cutting line, The distance between the first outermost pattern and the cutting line adjacent to the first end is greater than the distance between the first end and the first outermost pattern, A flexible circuit board, wherein the distance between the second outermost pattern and the cutting line adjacent to the second end is greater than the distance between the second end and the second outermost pattern.

5. In paragraph 4, A flexible circuit board, wherein the distance between the first outermost pattern and the cutting line adjacent to the first end or the distance between the second outermost pattern and the cutting line adjacent to the second end is 1 mm or more.

6. In paragraph 4, A flexible circuit board, wherein the protective layer includes regions having different heights.

7. In paragraph 6, A flexible circuit board, wherein the protective layer has a first maximum height in a region closest to the first end.

8. In paragraph 7, The above first outermost pattern is the wiring pattern portion, A flexible circuit board, wherein the dummy pattern portion includes at least one dummy pattern arranged between the first end and the first outermost pattern.

9. In paragraph 7, The above second outermost pattern is the wiring pattern portion, A flexible circuit board, wherein the dummy pattern portion includes at least one dummy pattern arranged between the second end and the second outermost pattern.

10. In paragraph 7, A flexible circuit board having a second maximum height in a region closest to the second end, wherein the protective layer has a second maximum height.

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