Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a base substrate (10) and a first electrode layer (50). At least one first through-hole (501) is provided on the first electrode layer (50). The first through-hole (501) passes through the first electrode layer (50) in a direction perpendicular to the base substrate (10), and an orthographic projection of the first through-hole (501) on the base substrate (10) is within an isolation dam region (10e) and does not overlap with an orthographic projection of an isolation dam (204) on the base substrate (10). The display apparatus comprises the display substrate.

Description

Display substrate and display device

[0001] This application claims priority to the Chinese patent application filed on January 9, 2024, with application number 202410032875.3 and invention name “Display Substrate and Display Device”, the content of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to, but is not limited to, the field of display devices, and in particular to a display substrate and a display apparatus. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] Currently, the first electrode layer covering the driving circuit layer is peeling off, which affects the yield of the product.

[0005] Summary of the Invention

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] An embodiment of the present disclosure provides a display substrate, comprising:

[0008] a substrate, the substrate comprising a display area, a driving circuit area, and an isolation dam area, wherein the driving circuit area is located between the display area and the isolation dam area;

[0009] a driving circuit layer, the driving circuit layer being disposed on the substrate, the driving circuit layer comprising an isolation dam, an orthographic projection of the isolation dam on the substrate being located within the isolation dam region;

[0010] a first electrode layer, the first electrode layer being located on a side of the driving circuit layer away from the substrate, and an orthographic projection of the first electrode layer on the substrate being located at least within the isolation dam region;

[0011] The first electrode layer is provided with at least one first through hole, which penetrates the first electrode layer in a direction perpendicular to the substrate, and the orthographic projection of the first through hole on the substrate is located within the isolation dam area, and the orthographic projection of the first through hole on the substrate is set to not overlap with the orthographic projection of the isolation dam on the substrate.

[0012] In some exemplary embodiments, a breathable insulating layer is further included, and the insulating layer is disposed in the first through hole.

[0013] In some exemplary embodiments, one end of the insulating layer away from the substrate protrudes out of the first through hole, and the insulating layer wraps around an edge of the first through hole away from the substrate.

[0014] In some exemplary embodiments, the insulating layer is made of polyimide glue.

[0015] In some exemplary embodiments, the isolation dam includes a first isolation dam and a second isolation dam, the first isolation dam is located on a side of the second isolation dam close to the display area, and the orthographic projection of at least one first through hole on the substrate is arranged between the orthographic projection of the first isolation dam on the substrate and the driving circuit area.

[0016] In some exemplary embodiments, the driving circuit layer includes a wiring layer, and an orthographic projection of the wiring layer on the substrate is located within the isolation dam area;

[0017] The first electrode layer covers the surface of the routing layer away from the substrate, the orthographic projection of the first through hole on the substrate is located within the orthographic projection of the routing layer on the substrate, and one end of the first through hole close to the substrate extends to the routing layer.

[0018] In some exemplary embodiments, the routing layer includes a first routing layer, a second routing layer, and a third routing layer stacked in sequence in a direction away from the substrate, and the first electrode layer is located on a side of the third routing layer away from the second routing layer.

[0019] In some exemplary embodiments, the first isolation dam is provided on an end surface of the routing layer away from the substrate, and the first electrode layer is provided to cover the first isolation dam;

[0020] The first electrode layer is provided with a second through hole, and an orthographic projection of the second through hole on the substrate at least partially overlaps with an orthographic projection of the first isolation dam on the substrate.

[0021] In some exemplary embodiments, a plurality of the first through holes are provided, and an orthographic projection of at least one of the first through holes on the substrate is disposed between an orthographic projection of the first isolation dam on the substrate and an orthographic projection of the second isolation dam on the substrate.

[0022] In some exemplary embodiments, a plurality of the first through holes are provided, and the plurality of the first through holes are arranged in a linear arrangement, an array arrangement, or an irregular arrangement on a plane parallel to the substrate.

[0023] In some exemplary embodiments, the first through hole is configured to extend in a direction perpendicular to the substrate, and a cross-section of the first through hole in a direction parallel to the substrate is configured to be rectangular, circular, elliptical, triangular, diamond-shaped, or irregular.

[0024] In some exemplary embodiments, a total area of ​​an orthographic projection of the first through-hole on the substrate is set to be no less than 10% of an area of ​​the isolation dam region.

[0025] In some exemplary embodiments, the first electrode layer is provided with a third through hole, the orthographic projection of the first electrode layer on the substrate is at least located in the driving circuit area, and the orthographic projection of the third through hole on the substrate is at least located in the driving circuit area.

[0026] An embodiment of the present disclosure provides a display device, which includes the above-mentioned display substrate.

[0027] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0028] Summary of the Figures

[0029] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0030] FIG1 is a schematic structural diagram of a display device;

[0031] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0032] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0033] FIG4 is a schematic diagram of a display substrate according to this exemplary embodiment;

[0034] FIG5 is a schematic cross-sectional view of point A in FIG4 ;

[0035] FIG6 is a cross-sectional view taken along line BB in FIG5 ;

[0036] FIG7 is a schematic diagram of another display substrate according to this exemplary embodiment;

[0037] FIG8 is a schematic diagram of another display substrate of this exemplary embodiment;

[0038] FIG9 is a partial enlarged schematic diagram of point C in FIG8 ;

[0039] FIG10 is a schematic diagram of another display substrate of this exemplary embodiment;

[0040] FIG11 is a schematic diagram of another display substrate of this exemplary embodiment;

[0041] FIG12 is a schematic diagram of a first preparation method of a display substrate according to this exemplary embodiment;

[0042] FIG. 13 is a second schematic diagram of preparing the display substrate of this exemplary embodiment.

[0043] Details

[0044] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0045] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0046] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0047] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0048] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0049] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0050] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0051] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0052] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0053] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0054] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0055] The term "about" in the embodiments of the present disclosure does not strictly define the limits and allows for numerical values ​​within the range of process and measurement errors.

[0056] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, and the pixel driving circuit may be connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-row basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0057] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each sub-pixel may include a circuit unit and a light-emitting device. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a light-emitting signal line, and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0058] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a triangular pattern, although this disclosure is not limited thereto.

[0059] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0060] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate. As shown in FIG3 , in a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 20 disposed on a base 10, a light-emitting structure layer 30 disposed on a side of the driving circuit layer 20 away from the base 10, and an encapsulation structure layer 40 disposed on a side of the light-emitting structure layer 30 away from the base 10. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0061] In an exemplary embodiment, the substrate 10 may be a flexible substrate or a rigid substrate. The driving circuit layer 20 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 30 may include a plurality of light-emitting devices, each of which may include at least an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the drive of the anode and cathode. The organic light-emitting layer may be a tandem OLED structure. The encapsulation structure layer 40 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can prevent external water vapor from entering the light-emitting structure layer 30, but is not limited thereto. For example, the first encapsulation layer, the second encapsulation layer, and the third encapsulation layer may all be made of inorganic materials or organic materials.

[0062] Currently, the first electrode layer in the border area is subject to peeling. Specifically, the first electrode layer covering the drive circuit layer is partially separated from the drive circuit layer. This increases resistance, affects the conductive effect of the first electrode layer, and reduces the product yield. Through research and experiments, the applicant has discovered the cause of the first electrode layer peeling. During the patterning process, the first electrode layer is typically exposed to high temperatures. High temperatures release water vapor, which the first electrode layer blocks. Consequently, the first electrode layer is lifted by the water vapor, causing the first electrode layer to peel.

[0063] FIG4 is a schematic diagram of a display substrate according to an exemplary embodiment, FIG5 is a schematic cross-sectional view taken along line A in FIG4 , and FIG6 is a cross-sectional view taken along line BB in FIG5 . In some exemplary embodiments, a display substrate, as shown in FIG4 to FIG6 , includes a substrate 10, a drive circuit layer 20, and a first electrode layer 50. The substrate 10 includes a display area 10a, a drive circuit area 10d, and an isolation dam area 10e, with the drive circuit area 10d located between the display area 10a and the isolation dam area 10e. The drive circuit layer 20 is disposed on the substrate 10 and includes an isolation dam. The orthographic projection of the isolation dam 204 on the substrate 10 is located within the isolation dam area 10e. The first electrode layer 50 is located on a side of the drive circuit layer 20 away from the substrate 10, with the orthographic projection of the first electrode layer 50 on the substrate 10 at least located within the isolation dam area 10e. The first electrode layer 50 is provided with at least one first through hole 501. The first through hole 501 penetrates the first electrode layer 50 in a direction perpendicular to the substrate 10 (i.e., the first direction). The orthographic projection of the first through hole 501 on the substrate 10 is located within the isolation dam area 10e and is arranged to not overlap with the orthographic projection of the isolation dam 204 on the substrate 10. Therefore, the display substrate of this example, by adding the first through hole 501 to the first electrode layer 50, allows water vapor to be released through the first through hole 501 in a timely manner, thereby preventing the first electrode layer 50 from detaching.

[0064] In some exemplary embodiments, as shown in Figures 4 to 6, the substrate 10 may include a display area 10a and a non-display area. The non-display area may include a binding area 10c located on one side of the display area 10a and a border area 10b located on the other side of the display area 10a. In an exemplary embodiment, the display area 10a may include a plurality of sub-pixels arranged in a matrix, and the sub-pixels may include a pixel driving circuit and a light-emitting device. The binding area 10c may include at least an isolation dam and a binding circuit that connects the signal lines of the plurality of sub-pixels to an external driving device. The border area 10b may include at least an isolation dam, a gate driver on array (GOA), and a power line that transmits voltage signals to the plurality of sub-pixels. The isolation dam of the binding area 10c and the border area 10b form a ring structure surrounding the display area 10a. In a plane parallel to the substrate 10, the border area 10b includes a driving circuit area 10d and an isolation dam area 10e arranged in sequence along a direction away from the display area 10a, such that the driving circuit area 10d is located between the isolation dam area 10e and the display area 10a.

[0065] In some exemplary embodiments, as shown in FIG6 , the driving circuit layer 20 may be disposed on one side of the substrate 10 in a first direction. The driving circuit layer 20 may include a first flat layer 201, a second flat layer 202, and a third flat layer 203 stacked sequentially in a direction away from the substrate 10. The driving circuit layer 20 may include a fourth through hole 211 within the isolation dam region 10e. The driving circuit layer 20 may include a routing layer 207, which may be disposed within the fourth through hole 211 such that the orthographic projection of the routing layer 207 on the substrate 10 is located within the isolation dam region 10e. The routing layer 207 may include a first routing layer 208, a second routing layer 209, and a third routing layer 210 stacked sequentially in a direction away from the substrate 10. The first routing layer 208, the second routing layer 209, and the third routing layer 210 are all made of conductive materials. The driving circuit layer 20 includes at least a gate driving circuit in the driving circuit region 10d. The gate driving circuit can be connected to the first scan line and the second scan line of the pixel driving circuit in the display region 10a. The driving circuit layer 20 includes at least a power line in the isolation dam region 10e. The power line can be connected to the second power line VSS of the pixel driving circuit in the display region 10a.

[0066] In some exemplary embodiments, as shown in FIG6 , the isolation dam 204 may include a first isolation dam 205 and a second isolation dam 206 . The first isolation dam 205 and the second isolation dam 206 may both extend in a direction parallel to the edge of the display area 10a. The first isolation dam 205 and the second isolation dam 206 are configured to block moisture from entering the display area 10a from the border area 10b. In the second direction, the distance between the first isolation dam 205 and the edge of the display area 10a is less than the distance between the second isolation dam 206 and the edge of the display area 10a, that is, the first isolation dam 205 is located on the side of the second isolation dam 206 closer to the display area 10a. The first isolation dam 205 may be arranged on the end surface of the wiring layer 207 away from the substrate 10, that is, on the surface of the third wiring layer 210 away from the second wiring layer 209, and the second isolation dam 206 protrudes from the surface of the third wiring layer 210 away from the second wiring layer 209.

[0067] In some exemplary embodiments, as shown in FIG6 , the first electrode layer 50 may cover the surface of the wiring layer 207 facing away from the substrate 10. Specifically, the first electrode layer 50 is located on the side of the third wiring layer 207 facing away from the second wiring layer 207. The first electrode layer 50 also covers the portion of the driver circuit layer 20 facing away from the substrate 10, located within the driver circuit area 10d and the display area 10a. The first electrode layer 50 may be made of a conductive material and may be arranged on the same layer as the anode of the light-emitting device. The first electrode layer 50 also covers the entire surface of the first isolation dam 205, except for the surface facing the wiring layer 207, thereby encapsulating the first isolation dam 205. As a result, the orthographic projection of the first electrode layer 50 on the substrate 10 may partially overlap with the isolation dam area 10e, and the orthographic projection of the first electrode layer 50 on the substrate 10 may also overlap with the driver circuit area 10d. The low voltage (VSS) required by the pixel driving circuit in the display area 10a is introduced from the binding pad of the binding area 10c and is transmitted to the second power line VSS of each pixel driving circuit through the power line. Since the power line needs to be transmitted through the first electrode layer 50, the impedance of the first electrode layer 50 is high, and there is a voltage drop in the voltage signal transmission. The voltage loss of the power line reduces the display brightness uniformity of the display area 10a, affecting the high-quality display.

[0068] In some exemplary embodiments, as shown in FIG6 , at least one first through-hole 501 is provided in the first electrode layer 50. The first through-hole 501 extends along a first direction and penetrates the first electrode layer 50. The orthographic projection of the at least one first through-hole 501 on the substrate 10 is located within the orthographic projection of the routing layer 207 on the substrate 10. One end of the first through-hole 501 near the substrate 10 extends to the third routing layer 210. The orthographic projection of the at least one first through-hole 501 on the substrate 10 may be located between the orthographic projection of the first isolation dam 205 on the substrate 10 and the driving circuit area 10 d.

[0069] In some exemplary embodiments, as shown in Figures 5 and 6, a plurality of first through holes 501 are provided, and the orthographic projections of the plurality of first through holes 501 on the substrate 10 are all located between the orthographic projection of the first isolation dam 205 on the substrate 10 and the driving circuit area 10d. The hole shape and size of the plurality of first through holes 501 are consistent, and the cross-sections of the plurality of first through holes 501 in the direction parallel to the substrate 10 are set to be rectangular, so that the first through holes 501 are rectangular holes, but are not limited to this. For example, the first through holes 501 may be circular holes, trapezoidal holes, triangular holes, diamond holes, polygonal holes, irregular holes, etc. Multiple first through holes 501 are rectangular holes and are arranged linearly on a plane parallel to the substrate 10. Multiple first through holes 501 are arranged at equal intervals along the second direction, and the second direction is parallel to the substrate 10 and perpendicular to the first direction, but is not limited to this. For example, multiple first through holes 501 are arranged at non-equal intervals along the second direction, and for example, multiple first through holes 501 are staggered in the third direction, and for example, multiple first through holes 501 are arranged in an array or irregularly, and the third direction is parallel to the substrate 10 and perpendicular to the second direction.

[0070] FIG7 is another schematic diagram of a display substrate according to an exemplary embodiment. In some exemplary embodiments, as shown in FIG5 and FIG7 , a plurality of first through holes 501 are provided, and the hole shape and size of the plurality of first through holes 501 are consistent. The cross-sections of the plurality of first through holes 501 in the direction parallel to the substrate 10 are set to be circular, so that the first through holes 501 are circular holes, but are not limited to this. For example, the first through holes 501 can be trapezoidal holes, triangular holes, diamond holes, polygonal holes, irregular holes, etc. For another example, the hole shapes of the plurality of first through holes 501 are inconsistent, and some of the first through holes 501 can be circular holes, while other portions of the first through holes 501 can be rectangular holes. The plurality of first through holes 501 are circular and arranged linearly in a plane parallel to the substrate 10 (a plane formed by the second direction and the third direction), but are not limited to this. For example, the plurality of first through holes 501 can be irregularly arranged in a plane parallel to the substrate 10 (a plane formed by the second direction and the third direction).

[0071] In some exemplary embodiments, as shown in Figures 5 and 6, a plurality of first through holes 501 are provided, and the orthographic projections of the plurality of first through holes 501 on the substrate 10 are all located between the orthographic projection of the first isolation dam 205 on the substrate 10 and the driving circuit area 10d, and the total area of ​​the orthographic projections of the plurality of first through holes 501 on the substrate 10 is set to be no less than 10% of the total area of ​​the isolation dam area 10e.

[0072] FIG8 is a schematic diagram of another display substrate of this exemplary embodiment, and FIG9 is a partially enlarged schematic diagram of point C in FIG8 . In some exemplary embodiments, as shown in FIG8 and FIG9 , the display substrate may include a breathable insulating layer 60. The insulating layer 60 may be located in the first through hole 501, so that the insulating layer 60 fills the first through hole 501. In addition, the insulating layer 60 may be made of polyimide (PI) glue. PI glue has good air permeability and can pass through water vapor, so that water vapor can pass through the insulating layer 60 and be discharged from the first through hole. PI glue is a polymer material with excellent comprehensive performance. It is one of the best heat-resistant varieties of engineering plastics at present. It has extremely high high temperature resistance, which can reach above 400°C, and its long-term use temperature range is between -200°C and 300°C. PI glue also exhibits good electrical insulation performance and flame retardant grade, so it is widely used in various fields. Insulating layer 6 0 fills each first through hole 501. The end of the insulating layer 60 closest to the substrate 10 is attached to the third wiring layer 210, and the end of the insulating layer 60 away from the substrate 10 protrudes out of the first through hole 501. The edge of the first through hole 501 away from the substrate 10 is set as a first edge 502. The insulating layer 60 wraps around the first edge 502, preventing the first electrode layer 500 from warping at the edge of the first through hole 501. The insulating layer 60 is made of the same material as the pixel definition layer in the light-emitting structure layer 30 and is provided on the same layer as the pixel definition layer. The insulating layer 60 can be manufactured through the patterning process of the pixel definition layer.

[0073] FIG10 is a schematic diagram of another display substrate according to this exemplary embodiment. In some exemplary embodiments, as shown in FIG10 , a plurality of first through-holes 501 are provided. The orthographic projections of all first through-holes 501 on the substrate 10 may be located within the orthographic projection of the routing layer 207 on the substrate 10. However, the plurality of first through-holes 501 are located on both sides of the first isolation dam 205 in the second direction. Specifically, the orthographic projections of some first through-holes 501 on the substrate 10 may be located between the orthographic projection of the first isolation dam 205 on the substrate 10 and the driving circuit area 10 d, while the orthographic projections of other first through-holes 501 may be located between the first isolation dam 205 and the second isolation dam 206. This ensures that at least one first through-hole 501 has its orthographic projection on the substrate 10 located between the orthographic projections of the first isolation dam 205 and the second isolation dam 206 on the substrate 10. The hole type, opening size, and arrangement of the first through holes 501 on both sides of the second direction of the first isolation dam 205 may be the same, or at least one of the hole type, opening size, and arrangement of the first through holes 501 on both sides of the second direction of the first isolation dam 205 may be different. For example, the first through hole 501 on one side of the first isolation dam 205 is a rectangular hole, and the first through hole 501 on the other side is a circular hole, but the opening size and arrangement of the first through holes 501 on both sides are the same.

[0074] FIG11 is a schematic diagram of another display substrate according to an exemplary embodiment. In some exemplary embodiments, as shown in FIG11 , in addition to the first through-hole 501, the first electrode layer 50 may also have a second through-hole 503 and a third through-hole 504. Both the second through-hole 503 and the third through-hole 504 extend through the first electrode layer 50. The first electrode layer 50 is provided with at least one first through-hole 501. The orthographic projection of the at least one first through-hole 501 on the substrate 10 is located within the orthographic projection of the routing layer 207 on the substrate 10. The end of the first through-hole 501 closest to the substrate 10 extends to the routing layer 207. The orthographic projection of the at least one first through-hole 501 on the substrate 10 may be located between the orthographic projection of the first isolation dam 205 on the substrate 10 and the driving circuit area 10 d. Furthermore, an insulating layer 60 is provided within the first through-hole 501. The second through-holes 503 are arranged corresponding to the first isolation dam 205. The second through-holes 503 extend to the surface of the first isolation dam 205, allowing water vapor to be discharged through the second through-holes 503. The orthographic projection of the second through-hole 503 on the substrate 10 is located within the orthographic projection of the first isolation dam 205 on the substrate 10. In addition, a plurality of second through-holes 503 are provided, and the plurality of second through-holes 503 have the same hole shape and size. The plurality of second through-holes 503 are circular holes, but the invention is not limited thereto. For example, the second through-holes 503 may be rectangular holes, trapezoidal holes, triangular holes, diamond holes, polygonal holes, irregular holes, etc., and the plurality of second through-holes 503 may be arranged linearly. The third through-hole 504 is located in the portion of the first electrode layer 50 covering the driving circuit area 10d. The third through-hole 504 extends perpendicular to the substrate 10 and extends to the end surface of the driving circuit layer 20 facing away from the substrate 10, that is, to the end surface of the third planar layer 203 facing away from the substrate 10. This allows moisture to escape through the third through-hole 504. The orthographic projection of the third through-hole 504 on the substrate 10 lies within the driving circuit area 10d. Furthermore, multiple third through-holes 504 are provided, each having a consistent shape and size. While the third through-holes 504 are circular, this is not limiting. For example, the third through-holes 504 may be rectangular, trapezoidal, triangular, diamond-shaped, polygonal, or irregularly shaped. The third through-holes 504 may be arranged in an array.

[0075] FIG12 is a schematic diagram of a first preparation process for a display substrate according to this exemplary embodiment, and FIG13 is a schematic diagram of a second preparation process for a display substrate according to this exemplary embodiment. In some exemplary embodiments, as shown in FIG11 , FIG12 , and FIG13 , a preparation method is applied to the display substrate shown in FIG10 . The preparation method may include preparing a driving circuit layer 20 on a substrate 10, preparing a first electrode layer 50 on the driving circuit layer 20, and preparing an insulating layer 60. In the process of preparing the driving circuit layer 20 on the substrate 10, a first flat layer 201, a second flat layer 202, a third flat layer 203, a wiring layer 207, etc. need to be prepared on the substrate 10 through processes such as coating, deposition, and etching to form the driving circuit layer 20. The driving circuit layer 20 covers the substrate 10, and the first isolation dam 205 and the second isolation dam 206 are also formed in this process. In the process of preparing the first electrode layer 50 on the driving circuit layer 20, it is necessary to first deposit an electrode film 505 on the driving circuit layer 20, as shown in FIG12 ; then, photoresist is coated on the electrode film 505, and after pre-baking, it is exposed to ultraviolet light using a mask. After development, only the photoresist pattern remains at the first electrode layer 50 position. After post-baking, etching, and stripping of the photoresist, an electrode layer pattern 506 is obtained. As shown in FIG13 , the electrode layer pattern 506 includes the first electrode layer 50 having a first through hole 501, a second through hole 503, and a third through hole 504. The process of obtaining the electrode layer pattern 506 is the patterning process of the first electrode layer 50. The mask used in the patterning process of the first electrode layer 50 needs to match the first electrode layer 50 having the first through hole 501, the second through hole 503, and the third through hole 504. In the patterning process of the first electrode layer 50, the pre-baking, post-baking, etching and other processes all require a high-temperature environment. In this environment, water vapor can be promptly removed from the first through-hole 501, the second through-hole 503 and the third through-hole 504 to avoid peeling. In the process of preparing the insulating layer 60, the insulating layer 60 can be made by the patterning process of the pixel definition layer in the light-emitting structure layer 30. First, an insulating film is deposited on the electrode layer pattern 506, and then a photoresist is coated on the insulating film, exposed, developed, etched, and debonded to obtain a pixel definition layer pattern. The pixel definition layer pattern includes the insulating layer 60. The mask used in this process needs to match the insulating layer 60. Subsequently, the preparation of the light-emitting structure layer 30 and the encapsulation structure layer 40 is completed to complete the production of the display substrate. The organic light-emitting layer in the light-emitting structure layer 30 can be a tandem OLED structure.

[0076] In some exemplary embodiments, a display device includes the aforementioned display substrate, and the display device may be an OLED display device. The display device provided by the embodiments of the present disclosure can be applied to electronic devices, such as mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigation systems, and in-vehicle displays. It can also be any product or component with a display function, such as a wearable device, such as a smartwatch, smart bracelet, smart glasses, smart headphones, smart clothing, or a head-mounted display. In this example, the display device is a mobile phone.

[0077] In conjunction with the above embodiments, the display substrate of this example adds a first through hole 501 to the first electrode layer 50, allowing moisture to be released promptly from the first through hole 501 during the display substrate manufacturing process, thereby preventing the first electrode layer 50 from detaching. The first through hole 501 is covered with an insulating layer 60, which seals the first through hole 501 and prevents the upper structure from directly connecting to the wiring layer. The insulating layer 60 is breathable and does not affect the escape of moisture. Furthermore, the insulating layer 60 wraps around the edge of the first through hole 501, preventing the edge of the first through hole 501 from warping.

[0078] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A display substrate, wherein, Comprising: A substrate, the substrate including a display area, a driving circuit area, and a dam area, the driving circuit area being located between the display area and the dam area; A driving circuit layer, the driving circuit layer being disposed on the substrate, the driving circuit layer including a dam, a positive projection of the dam on the substrate being located within the dam area; A first electrode layer, the first electrode layer being located on a side of the driving circuit layer away from the substrate, a positive projection of the first electrode layer on the substrate being at least located within the dam area; The first electrode layer is provided with at least one first through hole, the first through hole penetrating the first electrode layer in a direction perpendicular to the substrate, a positive projection of the first through hole on the substrate being within the dam area, and the positive projection of the first through hole on the substrate being set not to overlap with the positive projection of the dam on the substrate.

2. The display substrate according to claim 1, wherein, It further includes a breathable insulating layer, the insulating layer being disposed within the first through hole.

3. The display substrate according to claim 2, wherein, One end of the insulating layer away from the substrate protrudes from the first through hole, and the insulating layer wraps an edge on a side of the first through hole away from the substrate.

4. The display substrate according to claim 2, wherein, The material of the insulating layer includes polyimide glue.

5. The display substrate according to claim 1, wherein The dam includes a first dam and a second dam, the first dam being located on a side of the second dam close to the display area, and a positive projection of at least one of the first through holes on the substrate being set between the positive projection of the first dam on the substrate and the driving circuit area.

6. The display substrate according to claim 5, wherein, The driving circuit layer includes a wiring layer, a positive projection of the wiring layer on the substrate being located within the dam area; The first electrode layer covers a surface of the wiring layer away from the substrate, a positive projection of the first through hole on the substrate being located within the positive projection of the wiring layer on the substrate, and one end of the first through hole close to the substrate extending to the wiring layer.

7. The display substrate according to claim 6, wherein, The wiring layer includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked in a direction away from the substrate, and the first electrode layer is located on a side of the third wiring layer away from the second wiring layer.

8. The display substrate according to claim 6, wherein, The first dam is disposed on an end surface of the wiring layer away from the substrate, and the first electrode layer is set to cover the first dam; The first electrode layer is provided with a second through hole, and a positive projection of the second through hole on the substrate at least partially overlaps with the positive projection of the first dam on the substrate.

9. The display substrate according to claim 5, wherein, There are multiple first through holes, and a positive projection of at least one of the first through holes on the substrate is set between the positive projection of the first dam on the substrate and the positive projection of the second dam on the substrate.

10. The display substrate according to claim 5, wherein, There are multiple first through holes, and the multiple first through holes are set to be linearly arranged, arrayed, or irregularly arranged in a plane parallel to the substrate.

11. The display substrate according to claim 5, wherein, The first through hole is set to extend in a direction perpendicular to the substrate, and a cross-section of the first through hole in a direction parallel to the substrate is set to be rectangular, circular, elliptical, triangular, rhombic, or irregular.

12. The display substrate according to claim 5, wherein, The total area of the positive projection of the first through hole on the substrate is set to be not less than 10% of the area of the dam area.

13. The display substrate according to any one of claims 1 to 12, wherein The first electrode layer is provided with a third through hole, a positive projection of the first electrode layer on the substrate is at least located in the driving circuit region, and a positive projection of the third through hole on the substrate is at least located in the driving circuit region.

14. A display device, wherein, A display substrate includes any one of claims 1 to 13.

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