Transistor, chip, and electronic device

Abstract

Embodiments of the present application disclose a transistor, a chip, and an electronic device. The transistor comprises: a substrate, a channel, a first electrode, a gate, a second electrode, and a spacer layer; the channel is provided on the substrate; the first electrode, the gate, and the second electrode are stacked in a first direction, and the gate is provided around the channel; the first electrode is provided on the substrate, and the first direction is a direction perpendicular to the substrate; the spacer layer is provided between the first electrode and the gate; and the spacer layer comprises: a first spacer layer and a second spacer layer stacked in the first direction, wherein the wet etching rate of the second spacer layer is lower than that of silicon dioxide (SiO2), and the dielectric constant of the first spacer layer is less than that of the second spacer layer. Thus, corrosion resistance of the spacer layer is improved, parasitic capacitance of the transistor is reduced, and device performance is improved.

Description

Transistor, Chip and Electronic Device This application claims the priority of a Chinese patent application with the application number 202410052279.1 and the application title "Transistor, Chip and Electronic Device" filed with the National Intellectual Property Administration on January 12, 2024, the entire content of which is incorporated herein by reference. Technical Field Embodiments of this application relate to the field of semiconductors, and in particular, to a transistor, a chip, and an electronic device. Background Art The channel of a vertical transport transistor (VTFET) is perpendicular to the wafer. Its channel can utilize the space in the vertical direction and can be used in miniaturized devices, which is conducive to reducing the contacted gate pitch (CGP) and increasing the density of transistors in the chip. To avoid transistor short - circuit, an interlayer needs to be provided between the gate electrode of the transistor and the source - drain electrodes at the bottom, and this interlayer needs to be resistant to the corrosion generated by subsequent wet etching processes. Summary of the Invention Embodiments of this application provide a transistor, a chip, and an electronic device, which can reduce the corrosion of the interlayer by the wet etching process. To achieve the above - mentioned purpose, the embodiments of this application adopt the following technical solutions: In a first aspect of the embodiments of this application, a transistor is provided, including: a substrate, a channel, a first electrode, a gate electrode, a second electrode, and an interlayer; the channel is disposed on the substrate, the first electrode, the gate electrode, and the second electrode are stacked along a first direction, and the gate electrode surrounds the channel. Among them, the first electrode is disposed on the substrate, and the first direction is perpendicular to the substrate; the interlayer is disposed between the first electrode and the gate electrode, and the interlayer includes: a first interlayer and a second interlayer stacked along the first direction. The wet etching rate of the second interlayer is lower than the wet etching rate of silicon dioxide SiO2, and the dielectric constant of the first interlayer is less than the dielectric constant of the second interlayer. Thus, the wet etching rate of the interlayer is lower than the wet etching rate of silicon dioxide. This reduces the corrosion of the interlayer by the wet etching process when removing the silicon dioxide attached to the surface of the channel in subsequent processes, improves the corrosion resistance of the interlayer, and further improves the stability and uniformity of the interlayer. At the same time, the first interlayer uses a low - dielectric - constant material, so that the total dielectric constant of the interlayer is less than a preset value, reducing the parasitic capacitance of the transistor and improving the device performance. In an alternative implementation, the dielectric constant of the spacer layer is less than 7.6. When the equivalent dielectric constant K of the spacer layer is 7.6, it is equivalent to the entire spacer layer being made of SiN. The embodiment of the present application adopts a composite structure of two spacer layers. The first spacer layer is made of a low dielectric constant material, which can make the equivalent dielectric constant K of the spacer layer less than 7.6. Compared with using a pure SiN spacer layer, the parasitic capacitance decreases and the performance improves. In an alternative implementation, the material of the first spacer layer includes SiO2, and the material of the second spacer layer includes: SiOx, where X is less than 2. Thus, the dielectric constant of the first spacer layer can be made smaller, and the second spacer layer has better corrosion resistance. In an alternative implementation, the first spacer layer is formed by atomic layer deposition, and the second spacer layer is formed by implanting Si ions into the surface layer of the first spacer layer. Thus, the process is simple, easy to form, and there are no new elements, which will not affect the reliability, mobility, source-drain resistivity of the dielectric layer (caused by thermal diffusion), and will not contaminate the previous machine tool and affect the production line. In an alternative implementation, the spacer layer further includes: a third spacer layer and a fourth spacer layer. The third spacer layer is disposed between the first electrode and the first spacer layer, and the fourth spacer layer is disposed on the surface of the channel between the first electrode and the gate electrode. Thus, the protection of the channel is better. In an alternative implementation, the materials of the third spacer layer, the fourth spacer layer, and the second spacer layer are the same. Thus, the third spacer layer, the fourth spacer layer, and the second spacer layer use the same material and can be integrally formed, reducing the processing difficulty. In an alternative implementation, the material of the first spacer layer includes SiO2, silicon nitride SiN, SiOx, SiOyNz, silicon carbide SiC, calcium carbon oxide SiOC, silicon carbonitride SiCN, silicon carbonitride oxide SiCNO, silicon boron nitride SiBN, SiBCN, and the material of the second spacer layer includes: silicon nitride SiN, SiOx, SiOyNz, silicon carbide SiC, calcium carbon oxide SiOC, silicon carbonitride SiCN, silicon carbonitride oxide SiCNO, silicon boron nitride SiBN, SiBCN. Where X is less than 2. Thus, the dielectric constant of the first spacer layer can be made smaller, and the second spacer layer has better corrosion resistance. In an alternative implementation, the first spacer layer, the second spacer layer, the third spacer layer, and the fourth spacer layer are formed by deposition. Thus, the first spacer layer, the second spacer layer, the third spacer layer, and the fourth spacer layer adopt the same forming method, reducing the process difficulty. In the second aspect of the embodiments of the present application, a transistor is provided, including: a substrate, a channel, a first electrode, a gate electrode, a second electrode, and a spacer layer; the channel is disposed on the substrate, the first electrode, the gate electrode, and the second electrode are stacked along a first direction, and the gate electrode surrounds the channel, wherein the first electrode is disposed on the substrate, and the first direction is perpendicular to the substrate; the wet etching rate of the spacer layer is lower than that of silicon dioxide (SiO2). In an alternative implementation, the dielectric constant of the spacer layer is less than 7.6. In an alternative implementation, the material of the spacer layer includes SiOx, where X is less than 2. In the third aspect of the embodiments of the present application, a chip is provided, and the chip includes: the transistor as described above. In an alternative implementation, the chip includes: logic, an analog chip, a memory chip, or a static random access memory. In the fourth aspect of the embodiments of the present application, an electronic device is provided, including: a circuit board, and the chip as described above, and the chip is disposed on the circuit board. In the fifth aspect of the embodiments of the present application, a method for manufacturing a transistor is provided, and the method includes: etching the substrate to form a channel; forming a first electrode on the substrate; forming a spacer layer on the first electrode; the spacer layer includes: a first spacer layer and a second spacer layer stacked along a first direction, the first spacer layer is close to the first electrode, and the wet etching rate of the second spacer layer is lower than that of silicon dioxide (SiO2); the first direction is perpendicular to the substrate; forming a dummy gate electrode on the spacer layer, and the dummy gate electrode surrounds the channel; forming a second electrode on the dummy gate electrode; removing the dummy gate electrode; and forming a gate electrode between the first electrode and the second electrode. In an alternative implementation, the material of the first spacer layer includes SiO2, and the material of the second spacer layer includes: SiOx, where X is less than 2. In an alternative implementation, the step of forming a spacer layer on the first electrode includes: depositing a first spacer layer on the surfaces of the first electrode and the channel; depositing a protective layer on the first spacer layer; etching the protective layer so that the thickness of the protective layer on the first electrode is less than the thickness of the protective layer on the channel; implanting Si ions into the first spacer layer on the first electrode to form a second spacer layer; and removing the protective layer. In an alternative implementation, the spacer layer further includes: a third spacer layer and a fourth spacer layer, the third spacer layer is disposed on the surface of the gate electrode close to the first electrode, and the fourth spacer layer is disposed on the surface of the channel between the first electrode and the gate electrode. In an alternative implementation, the material of the first spacer layer includes SiO2, silicon nitride SiN, SiOx, SiOyNz, silicon carbide SiC, calcium silicon oxide SiOC, silicon carbonitride SiCN, silicon carbonitride oxide SiCNO, silicon boron nitride SiBN, SiBCN, and the material of the second spacer layer includes: silicon nitride SiN, SiOx, SiOyNz, silicon carbide SiC, calcium silicon oxide SiOC, silicon carbonitride SiCN, silicon carbonitride oxide SiCNO, silicon boron nitride SiBN, SiBCN, where X is less than 2. In an alternative implementation, forming a spacer layer on the first electrode includes: depositing a sacrificial layer on the first electrode and the channel surface; depositing a protective layer on the surface of the sacrificial layer on the channel; etching the sacrificial layer on the first electrode so that the first electrode, the channel, the sacrificial layer, and the protective layer enclose a groove; depositing the first spacer layer, the second spacer layer, the third spacer layer, and the fourth spacer layer in the groove; where the second spacer layer is formed on the surface of the first electrode, the third spacer layer is formed on the surface of the gate electrode close to the first electrode, the fourth spacer layer is formed on the surface of the channel between the first electrode and the gate electrode, and the first spacer layer is formed in the region enclosed by the second spacer layer, the third spacer layer, and the fourth spacer layer; removing the protective layer and the sacrificial layer. Description of the Drawings FIG. 1 is a schematic structural diagram of an electronic device provided by an embodiment of the present application; FIG. 2 is a schematic structural diagram of a circuit board provided by an embodiment of the present application; FIG. 3 is a schematic structural diagram of a transistor; FIG. 4 is a schematic structural diagram of a transistor provided by an embodiment of the present application; FIG. 5 is a schematic structural diagram of another transistor provided by an embodiment of the present application; FIG. 6 is a schematic structural diagram of yet another transistor provided by an embodiment of the present application; FIG. 7 is a schematic equivalent circuit diagram of the bottom spacer layer shown in FIG. 6; FIG. 8 is a graph showing the change of the equivalent dielectric constant of the spacer layer with the SiN thickness; FIG. 9 is a flowchart of a method for manufacturing a transistor provided by an embodiment of the present application; FIGS. 10, 11, 12, 13, 14, 15, 16, and 17 are schematic structural diagrams of products obtained after performing each step in FIG. 9; FIG. 18 is a flowchart of a method for manufacturing another transistor provided by an embodiment of the present application; FIG. 19 is a schematic structural diagram of a product obtained after performing each step in FIG. 18; FIG. 20 is a flowchart of a method for manufacturing yet another transistor provided by an embodiment of the present application; Figure 21 is a schematic diagram of the product structure obtained after performing the steps in Figure 20; Figure 22 is a flowchart of a method for manufacturing another transistor provided by an embodiment of the present application; Figure 23 is a schematic diagram of the product structure obtained after performing the steps in Figure 22; Figure 24 is a flowchart of a method for manufacturing a spacer layer provided by an embodiment of the present application; Figures 25, 26, 27, 28, 29, and 30 are respectively schematic diagrams of the product structure obtained after performing the steps in Figure 24; Figure 31 is a schematic diagram of the state of ion implantation provided by an embodiment of the present application; Figure 32 is a flowchart of a method for manufacturing a spacer layer provided by an embodiment of the present application; Figures 33, 34, 35, 36, 37, and 38 are respectively schematic diagrams of the product structure obtained after performing the steps in Figure 32. Detailed Embodiment In order to make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. Hereinafter, terms such as "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise stated, the meaning of "a plurality" is two or more. In addition, in the present application, orientation terms such as "upper" and "lower" are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, which are used for relative description and clarification, and they may change correspondingly according to the change of the orientation of the components placed in the accompanying drawings. An embodiment of the present application provides an electronic device. Figure 1 is a schematic diagram of the structure of the electronic device provided by an embodiment of the present application. As shown in Figure 1, the electronic device 1 may be a mobile phone. The embodiment of the present application does not limit the specific form of the electronic device. For example, the electronic device includes: a tablet computer (pad), a personal digital assistant (PDA), a television, intelligent wearable products (such as intelligent watches, intelligent bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, small household appliances for charging (such as soybean milk machines, floor sweeping robots), drones, radars, aerospace devices, and vehicle-mounted devices, etc. Figure 2 is a schematic structural diagram of a circuit board provided by an embodiment of the present application. In some embodiments, the electronic device 1 in Figure 1 includes, for example, a printed circuit board 10 as shown in Figure 2, and a chip 20 disposed on the circuit board. The chip may be a logic chip, an analog chip, a memory chip, or a static random access memory (SRAM). Among them, in the core logic device of the logic chip, in the input / output (I / O) device of the memory chip, or in the strobe of the static random access memory chip, transistors are integrated. Figure 3 is a schematic structural diagram of a transistor. As shown in Figure 3, the transistor 200 is a vertical transport transistor. The transistor includes: a substrate (not shown), a channel 204, a first electrode 201, a gate electrode 202, and a second electrode 203. Among them, the channel 204 is disposed on the substrate, and the first electrode 201, the gate electrode 202, and the second electrode 203 are stacked along a first direction (z direction), and the first electrode 201 is disposed on the substrate. The first direction is a direction perpendicular to the substrate. The material of the substrate includes: silicon (Si). The embodiments of the present application do not limit the types of the first electrode 201 and the second electrode 203. In some embodiments, the first electrode 201 is a source electrode (S), the second electrode 203 is a drain electrode (D), and the gate electrode is G. In other embodiments, the first electrode 201 is a drain electrode, and the second electrode 203 is a source electrode. The present embodiment does not limit the doping type of the transistor. In some embodiments, the transistor includes: an N-type metal-oxide-semiconductor (NMOS) transistor, a PMOS transistor, a junctionless (JL) transistor, an inversion mode (IM) transistor, a nanowire (NW) transistor, and a nanosheet (NS) transistor. Among them, the NMOS transistor includes an n-type dopant, for example, dopants such as phosphorus, arsenic, antimony, bismuth, selenium, tellurium, or a combination thereof. The PMOS transistor includes a p-type dopant, for example, dopants such as boron, methoxyboron difluoride, or a combination thereof. In some embodiments, the material of the channel 204 includes: silicon (Si), silicon germanide (SiGe), germanium (Ge). In some embodiments, the transistor is a Gate All Around (GAA) transistor, which is a transistor structure in which the entire channel 204 is wrapped by a ring-shaped gate electrode, and the gate electrode 202 is disposed around the channel 204. The ring-shaped gate structure has better gate control ability. In the embodiments of the present application, a vertical ring-shaped gate structure is used. The embodiments of the present application do not limit the structure of the ring-shaped gate. The ring-shaped gate transistor includes at least one of a nanosheet transistor and a nanowire transistor. In the vertical transport transistor provided by the embodiments of the present application, the channel 204 is perpendicular to the substrate, which can make full use of the space in the vertical direction and can be used in miniaturized devices, which is beneficial to reducing the gate pitch and increasing the density of transistors in the chip. FIG. 4 is a schematic structural diagram of a transistor provided by an embodiment of the present application. Referring to FIG. 4 and in combination with FIG. 3, the transistor 200 further includes a spacer layer, which is divided into a bottom spacer layer 205 and a top spacer layer 206 (not shown in FIG. 3). In some embodiments, the bottom spacer layer 205 is disposed at the connection between the first electrode 201 and the gate electrode 202, and the top spacer layer 206 is disposed at the connection between the gate electrode 202 and the second electrode 203. Exemplarily, as shown in FIG. 4, the bottom spacer layer 205 is disposed between the first electrode 201 and the gate electrode 202 and surrounds the channel 204. In other embodiments, the bottom spacer layer 205 may also be partially disposed around the channel 204 and partially disposed around the first electrode. Correspondingly, in some embodiments, the top spacer layer 206 may be disposed between the second electrode 203 and the gate electrode 202 and surround the channel 204. In other embodiments, the bottom spacer layer 205 may also be partially disposed around the channel 204 and partially disposed around the second electrode 203. Wherein, the spacer layer (205, 206) is a dielectric layer, which can provide electrical isolation between the gate electrode 202 and the first electrode 201 to prevent transistor short circuit. To reduce the corrosion of the spacer layer during the subsequent wet etching process, the spacer layer (205, 206) may be made of a corrosion-resistant material. In some embodiments, the wet etch rate (WER) of the spacer layer (205, 206) may be lower than the wet etch rate of silicon dioxide (SiO2). That is to say, the corrosion resistance of the spacer layer (205, 206) is greater than the corrosion resistance of silicon dioxide (SiO2). Among them, silicon dioxide (SiO₂) has good electrical insulation, thermal stability and chemical stability. It is used for electrical isolation layers, mask layers, and can be used as the gate oxide layer in the transistor manufacturing process, etc. In subsequent processes, the gate oxide layer (silicon dioxide) attached to the surface of the channel 204 can be removed through a wet etching process. In this embodiment, it is defined that the wet etching rate of the spacer layers (205, 206) is lower than that of silicon dioxide (SiO₂). This makes it more difficult to corrode the spacer layers (205, 206) when removing the gate oxide layer on the surface of the channel 204 through the wet etching process in subsequent processes, improving the corrosion resistance of the spacer layers (205, 206), and thus improving the stability and uniformity of the spacer layers (205, 206). Among them, the forming process of silicon dioxide (SiO₂) includes: thermal oxidation process, plasma enhanced chemical vapor deposition (PECVD) process, etc. Among them, the silicon dioxide (SiO₂) formed by the thermal oxidation process has better corrosion resistance and lower wet etching rate. In this embodiment, the wet etching rate of the spacer layers (205, 206) can be made lower than that of the silicon dioxide (SiO₂) formed by the thermal oxidation process. Thus, the wet etching rate of the spacer layers (205, 206) provided in this embodiment is lower than that of silicon dioxide (SiO₂). This reduces the corrosion of the spacer layers (205, 206) by the wet etching process when removing the silicon dioxide (SiO₂) attached to the surface of the channel 204 through the wet etching process in subsequent processes, improving the corrosion resistance of the spacer layers (205, 206), and thus improving the stability and uniformity of the spacer layers (205, 206). The embodiments of the present application do not limit the material of the spacer layers (205, 206). In some embodiments, the material of the spacer layers (205, 206) includes: SiOx, where X in SiOx should be less than 2. In some embodiments, SiOx can be formed by implanting Si ions into SiO₂. In this embodiment, the wet etching rate of SiOx is lower than that of SiO₂. The difference in their wet etching rates is due to their chemical bonds. The chemical bond of SiO₂ is the O-Si-O bond, while there is a Si-O-Si bond in SiOx. The bonding difference between SiOx and SiO₂ can be distinguished by X-ray photoelectron spectroscopy (XPS) and Raman spectroscopy. In some embodiments, the spacer layers (205, 206) can be made of a low dielectric constant material. For example, the dielectric constant of the spacer layers (205, 206) is less than 7.6. Among them, the dielectric constant, which can refer to the relative dielectric constant, is a measure of the response of a material to an electric field or the dielectric property of the material. The lower the relative dielectric constant, the weaker the charge storage ability, and the higher the relative dielectric constant, the stronger the charge storage ability. Materials with a relatively low dielectric constant (also known as low-K materials) usually have a dielectric constant less than 4.0. Materials with a relatively high dielectric constant (also known as high-k materials) have a dielectric constant significantly greater than 4.0, and sometimes even close to or exceeding 20. The number of layers of the spacer layers (205, 206) is not limited in the embodiments of the present application. In the above embodiments, the spacer layers (205, 206) are one layer, and in some other embodiments, the spacer layers (205, 206) are multiple layers. FIG. 5 is a schematic structural diagram of another transistor provided by an embodiment of the present application. As shown in FIG. 5, the spacer layer 205 includes a first spacer layer 2001 and a second spacer layer 2002 stacked along a first direction. For the convenience of description below, taking the bottom spacer layer 205 as an example, the structure of the top spacer layer 206 can refer to the description of the bottom spacer layer 205. In some embodiments, in the bottom spacer layer 205, the first spacer layer 2001 is disposed close to the first electrode 201, and the second spacer layer 2002 is disposed on a side of the first spacer layer 2001 away from the first electrode 201. Among them, the wet etching rate of the second spacer layer 2002 is lower than that of silicon dioxide (SiO2), that is to say, the corrosion resistance of the second spacer layer 2002 is greater than that of silicon dioxide (SiO2). In some embodiments, the first spacer layer 2001 can be made of a low-K material, and the first spacer layer 2001 and the second spacer layer 2002 can be regarded as two parallel capacitors. In some embodiments, the dielectric constant of the first spacer layer can be made less than that of the second spacer layer. The total dielectric constant of the first spacer layer 2001 and the second spacer layer 2002 is less than 7.6. In some embodiments, the material of the first spacer layer 2001 includes SiO2, and the material of the second spacer layer 2002 includes: SiOx, where X is less than 2. Thus, by providing two spacer layers (205, 206) and making the corrosion resistance of the second spacer layer 2002 closer to the gate electrode 202 better than that of silicon dioxide (SiO2), it is possible to avoid the corrosion of the spacer layers (205, 206) and the first electrode 201 caused by wet etching with hydrofluoric acid (HF) during the preparation of the gate electrode 202. At the same time, the first spacer layer 2001 uses a low-K material, so that the total dielectric constant of the spacer layers (205, 206) is less than a preset value, reducing the parasitic capacitance of the transistor and improving the device performance. The embodiment of the present application places no restrictions on the process of the second spacer layer 2002. By way of example, the second spacer layer 2002 is formed by implanting Si ions into the surface layer of the first spacer layer. The embodiment of the present application places no restrictions on the process of the first spacer layer 2001. By way of example, the first spacer layer 2001 is formed by atomic layer deposition. FIG. 6 is a schematic structural diagram of another transistor provided by the present application. As shown in FIG. 6, the bottom spacer layer 205 includes: a first spacer layer 2001, a second spacer layer 2002, a third spacer layer 2003, and a fourth spacer layer 2004. For the descriptions of the first spacer layer 2001 and the second spacer layer 2002, reference may be made to the above embodiments, which will not be elaborated here. The first spacer layer 2001, the second spacer layer 2002, and the third spacer layer 2003 are stacked along a first direction. The first spacer layer 2001 is disposed close to the first electrode 201, the third spacer layer 2003 is disposed close to the gate electrode 202, and the fourth spacer layer 2004 is disposed on the surface of the channel 204 between the first electrode 201 and the gate electrode 202. In some embodiments, the third spacer layer 2003, the fourth spacer layer 2004, and the second spacer layer 2002 are made of the same material. Among them, the wet etching rate of the second spacer layer 2002 can be made lower than that of silicon dioxide (SiO2). Among them, the wet etching rate of the second spacer layer 2002 is lower than that of silicon dioxide (SiO2), that is to say, the corrosion resistance of the second spacer layer 2002 is greater than that of silicon dioxide (SiO2). In some embodiments, the first spacer layer 2001 may use a low-K material, and the first spacer layer 2001 and the second spacer layer 2002 can be regarded as two parallel capacitors. In some embodiments, the dielectric constant of the first spacer layer can be made less than that of the second spacer layer, so that the total dielectric constant of the first spacer layer 2001 and the second spacer layer 2002 is less than 7.6. In some embodiments, the material of the first spacer layer 2001 includes SiO2, silicon nitride SiN, SiOx, SiOyNz, silicon carbide SiC, calcium silicon oxide SiOC, silicon carbonitride SiCN, silicon carbonitride oxide SiCNO, silicon boron nitride SiBN, SiBCN, and the material of the second spacer layer 2002 includes: silicon nitride SiN, SiOx, SiOyNz, silicon carbide SiC, calcium silicon oxide SiOC, silicon carbonitride SiCN, silicon carbonitride oxide SiCNO, silicon boron nitride SiBN, SiBCN. Wherein, X is less than 2. Thus, by providing a plurality of spacer layers and making the corrosion resistance of the second spacer layer 2002 close to the gate electrode 202 better than that of silicon dioxide (SiO2), corrosion of the spacer layer and the first electrode 201 caused by wet etching with hydrofluoric acid during the preparation of the gate electrode 202 can be avoided. At the same time, the first spacer layer 2001 uses a low-K material, so that the total dielectric constant of the spacer layer is less than a preset value, reducing the parasitic capacitance of the transistor and improving the device performance. FIG. 7 is a schematic diagram of the equivalent circuit structure of the bottom spacer layer shown in FIG. 6. As shown in FIG. 7, the overall capacitance C0 of the spacer layer shown in FIG. 6 can be equivalently a parallel connection of the right C4 and the left series structure, and the left capacitance is formed by the series connection of C1, C2, and C3. Among them, C4 can be equivalently the fourth spacer layer 2004, C1 can be equivalently the first spacer layer 2001, C2 can be equivalently the second spacer layer 2002, and C3 can be equivalently the third spacer layer 2003. FIG. 8 is a graph showing the variation of the equivalent dielectric constant of the spacer layer with the SiN thickness. As shown in FIG. 8, when the equivalent dielectric constant K of the spacer layer is 3.9, it is equivalent that the entire spacer layer uses SiO2, and when the equivalent dielectric constant K of the spacer layer is 7.6, it is equivalent that the entire spacer layer uses SiN. The embodiment of the present application adopts a composite structure of SiN and SiO2, and the dielectric constant of the first spacer layer is less than that of the second spacer layer, which can make the equivalent dielectric constant K of the spacer layer less than 7.6. Compared with the pure SiN spacer layer, the parasitic capacitance decreases and the performance improves. In this embodiment, the dielectric constant K value of the spacer layer is not limited. In some embodiments, the equivalent dielectric constant K of the spacer layer can be made less than 5. The embodiment of the present application does not limit the forming process of the spacer layer. In some embodiments, the first spacer layer 2001, the second spacer layer 2002, the third spacer layer 2003, and the fourth spacer layer 2004 are integrally formed by deposition. The present application also provides a method for manufacturing a transistor. FIG. 9 is a flowchart of a method for manufacturing a transistor provided by an embodiment of the present application. As shown in FIG. 9, the method includes: ​S101. Etch the substrate to form channels (204a, 204b) as shown in FIG. 10. In some embodiments, the material of the substrate includes: silicon (Si). This application places no restrictions on the substrate structure. In some embodiments, a wafer with a

[0100] ,

[0110] or other crystal orientation can be used as the substrate. Among them, the direction indicated by the line connecting any two atoms / molecules / ions in the unit cell is called the crystal orientation. Taking a certain lattice point O of the unit cell as the origin, set the coordinate axes X / Y / Z passing through the origin O, use the length of the lattice vector of the unit cell as the length unit of the coordinate axes, draw a straight line OP passing through the origin O, require that the point P is the closest to the point O, and make it parallel to the to-be-determined crystal orientation AB, determine the three coordinate values of the point P, convert the three values into the smallest integers u, v, w, and add parentheses, [uvw] is the crystal orientation index of the to-be-determined crystal orientation AB. The size of the wafer is not restricted in this embodiment. Among them, the channels (204a, 204b) are perpendicular to the substrate. In this embodiment, the channels (204a, 204b) are arranged on the substrate along the Z direction. S102. As shown in FIG. 11, form the first electrodes (201a, 201b) on the substrate. In some embodiments, the first electrodes (201a, 201b) are source electrodes. In other embodiments, the first electrodes (201a, 201b) are drain electrodes. This embodiment places no restrictions on the doping type of the first electrode 201. In some embodiments, 201a is an n-type doped layer. Exemplarily, 201a includes n-type dopants, such as dopants like phosphorus, arsenic, antimony, bismuth, selenium, tellurium, etc. or combinations thereof. In some embodiments, the substrate includes a well region (not shown), the conductivity type of which is different from that of 201a, and extends from the upper surface of the substrate into the substrate. In some embodiments, 201a is located on and in contact with the well region. In some embodiments, the well region is a p-type well region. In other embodiments, 201b is a p-type doped layer. Exemplarily, 201b includes p-type dopants, such as dopants like boron, methoxydifluoroboron, etc. or combinations. In some embodiments, the substrate includes a well region (not shown), the conductivity type of which is different from that of 201b, and extends from the upper surface of the substrate into the substrate. In some embodiments, 201b is located on and in contact with the well region. In some embodiments, the well region is an n-type well region. S103. As shown in FIG. 12, form the bottom spacer layer 205 on the first electrode 201. Among them, the wet etching rate of the bottom spacer layer 205 can be made lower than that of silicon dioxide (SiO2). That is to say, the corrosion resistance of the bottom spacer layer 205 is greater than that of silicon dioxide (SiO2). In addition, the bottom spacer layer 205 can be made of a low dielectric constant material. For example, the dielectric constant of the bottom spacer layer 205 is less than 7.6. S104. As shown in FIG. 13, a dummy gate electrode 200b is formed on the bottom spacer layer 205. In some embodiments, the material of the dummy gate electrode 200b includes amorphous silicon. The dummy gate electrode 200b can be formed by deposition. S105. As shown in FIG. 14, a second electrode (203a, 203b) is formed on the dummy gate electrode 200b. In some embodiments, the second electrode (203a, 203b) has the same doping type as the first electrode (201a, 201b). When the first electrode (201a, 201b) is a source electrode, the second electrode (203a, 203b) is a drain electrode. When the first electrode (201a, 201b) is a drain electrode, the second electrode (203a, 203b) is a source electrode. The material of the second electrode (203a, 203b) includes Si and SiGe. This embodiment does not limit the forming method of the second electrode (203a, 203b), and it can be formed by ion implantation, epitaxial growth or other methods. S106. As shown in FIG. 15, a top spacer layer (206a, 206b) is formed at the connection position between the second electrode (203a, 203b) and the dummy gate electrode 200b. The forming process of the top spacer layer (206a, 206b) can refer to that of the bottom spacer layer 205, which will not be elaborated here. S107. As shown in FIG. 16, the dummy gate electrode 200b is removed. In some embodiments, it can be removed by wet etching. Among them, a hydrofluoric acid solution can be used for etching. S108. As shown in FIG. 17, a gate electrode (202a, 202b) is formed between the bottom spacer layer 205 and the top spacer layers 206a, 206b. Among them, the gate electrode 202a is disposed around the channel 204a, and the gate electrode 202b is disposed around the channel 204b. In some embodiments, the gate electrode surrounds a part of the channel. In other embodiments, the gate electrode surrounds the entire channel. In some examples of this embodiment, when the first electrodes (201a, 201b) are n-type doped layers, the channels (204a, 204b) are n-type doped layers. In some embodiments, the channels (204a, 204b) include n-type dopants. In other examples of this embodiment, when the first electrodes (201a, 201b) are p-type doped layers, the channels (204a, 204b) are p-type doped layers. In some embodiments, the channels (204a, 204b) include p-type dopants. This application also provides a method for manufacturing a transistor. FIG. 18 is a flowchart of another method for manufacturing a transistor provided by an embodiment of this application. As shown in FIG. 18, before step S101, the method further includes: S1011. As shown in FIG. 19, form a shallow trench isolation (STI) 200a on a substrate. Among them, when forming the shallow trench isolation 200a, a layer of silicon nitride can be first deposited on the substrate, and then this silicon nitride layer is patterned to form a hard mask. Then, the substrate is etched to form trenches between adjacent transistor devices, and oxides are filled in the trenches to form an element isolation structure. The shallow trench isolation 200a is, for example, parallel to the x direction, and the devices in this application are formed on the substrate along the Z direction. In some embodiments, an inter-layer dielectric layer 200c (Inter-layer dielectic, ILD) is provided between adjacent transistors. This application also provides a method for manufacturing a transistor. FIG. 20 is a flowchart of yet another method for manufacturing a transistor provided by an embodiment of this application. As shown in FIG. 20, after step S108, the method further includes: S1091. As shown in FIG. 21, deposit an inter-layer dielectric layer 200c between adjacent transistors. Thus, the inter-layer dielectric layer 200c can form a partition between devices. In some embodiments, the material of the inter-layer dielectric layer 200c includes: dielectric materials such as silicon nitride, silicon oxynitride, or other suitable insulating materials. In some embodiments, the transistor further includes: a connection layer 2031. This application also provides a method for manufacturing a transistor. FIG. 22 is a flowchart of still another method for manufacturing a transistor provided by an embodiment of this application. As shown in FIG. 22, after step S1091, the method further includes: S1092. As shown in FIG. 23, form a connection layer (2031a, 2031b) on the second electrode. Among them, the connection layer (2031a, 2031b) can be made of a conductive material such as metal. The connection layer (2031a, 2031b) can achieve the interconnection between transistors. This application does not limit the structure of the spacer layer. In some embodiments, the spacer layer formed in step S103 is a single-layer structure. In other embodiments, the spacer layer formed in step S103 includes: a first spacer layer 2001 and a second spacer layer 2002 stacked along a first direction. The first spacer layer 2001 is close to the first electrode 201, and the wet etching rate of the second spacer layer 2002 is lower than that of silicon dioxide (SiO2). Among them, the wet etching rate of the second spacer layer 2002 is lower than that of silicon dioxide (SiO2), that is to say, the corrosion resistance of the second spacer layer 2002 is greater than that of silicon dioxide (SiO2). In some embodiments, the material of the channel 204 includes Si, the material of the first spacer layer 2001 includes SiO2, and the material of the second spacer layer 2002 includes: SiOx, where X is less than 2. In this embodiment, the wet etching rate of SiOx is lower than that of SiO2, and the difference in their wet etching rates is due to their chemical bonds. The chemical bond of SiO2 is an O-Si-O bond, while there is a Si-O-Si bond in SiOx. The bonding difference between SiOx and SiO2 can be distinguished by X-ray photoelectron spectroscopy (XPS) and Raman spectroscopy. In this way, by setting two spacer layers and making the spacer layer close to the gate electrode 202 have better corrosion resistance than silicon dioxide (SiO2), it is possible to avoid the corrosion of the spacer layer and the first electrode 201 caused by wet etching with hydrofluoric acid when preparing the gate electrode 202. In some embodiments, the spacer layer can be made of a low dielectric constant material. For example, the dielectric constant of the spacer layer is less than 7.6. The first spacer layer 2001 is formed by atomic layer deposition, and the second spacer layer 2002 is formed by ion implantation. FIG. 24 is a flowchart of a method for preparing a spacer layer provided by an embodiment of the present application. As shown in FIG. 24, taking the spacer layer including a first spacer layer 2001 and a second spacer layer 2002 as an example, the method for preparing the spacer layer includes the following steps: S103a. As shown in FIG. 26, deposit a first spacer layer 2001 on the surfaces of the first electrode 201 and the channel 204 shown in FIG. 25. The material of the first spacer layer 2001 includes SiO2. S103b. As shown in FIG. 27, deposit a protective layer 20b on the first spacer layer 2001. The material of the protective layer 20b includes but is not limited to materials such as amorphous silicon (aSi), titanium nitride (TiN), and aluminum oxide (Al2O3). Only aSi is taken as an example below. S103c. As shown in FIG. 28, etch the protective layer 20b. Among them, the thickness of the protective layer 20b on the first electrode 201 and the thickness of the protective layer 20b on the channel 204 can be independently controlled. The thickness of the protective layer 20b on the channel 204 is determined by the thickness of the protective layer 20b deposited in step S103b. The thickness of the protective layer 20b on the first electrode 201 is determined by the etching depth in step S103c. It can be made that the thickness of the protective layer 20b on the first electrode 201 is less than the thickness of the protective layer 20b on the channel 204. In this embodiment, a protective layer 20b is provided on the surface of the channel 204 to prevent the first spacer layer 2001SiO2 on the channel 204 from being implanted with Si ions and becoming SiOx, where X is less than 2. S103d. As shown in FIG. 29, implant Si ions into the surface layer of the first spacer layer 2001 on the first electrode 201 to form a second spacer layer 2002 in the surface layer first spacer layer 2001. Among them, when performing ion implantation, the ion implantation angle is usually inclined with respect to the surface to be implanted, that is, the ions are not perpendicular, which makes the shielding distance of the protective layer 20b on the first electrode 201 different from the shielding distance of the protective layer 20b on the channel 204. Referring to FIG. 31, the total tilt angle (Total tiltangle) α1 of the ion implantation = the fin angle (fin angle) α2 + the implant tilt angle (implant tiltangle) α3. Among them, the fin angle is the offset angle between the channel 204 and the vertical direction. The implant tilt angle is the included angle between the ion implantation angle and the normal of the surface to be implanted. In this embodiment, the fin angle is 3°, the implant tilt angle is 7°, and the total tilt angle of the ion implantation is 10°. D(screen) = d(aSi) / sin(10°) ≈ 5d(aSi). Among them, D(screen) is the shielding distance. d(aSi) is the thickness of the protective layer 20b. sin(Total tiltangle) = D(screen) / d(aSi). Based on the above, in the case where the implant tilt angle is 7°, depositing 4 nm of aSi provides a shielding distance of 20 nm for blocking implantation, which is equivalent to the shielding effect of a 20 nm protective layer 20b. Among them, the shielding effect can be reflected by the blocking distance of the ion implantation. It should be noted that only the SiO2 on the plane will form SiOx, and the side surfaces are removed. In this embodiment, SiOx is formed by implanting Si ions into SiO2. In other embodiments, SiOx can also be formed by Physical Vapor Deposition (PVD) or Molecular beam epitaxy (MBE) deposition. S103e. As shown in FIG. 30, the protective layer 20b is removed. The protective layer 20b and the channel 204 can be removed by etching. In some embodiments, the protective layer 20b on the upper surface of the channel 204 also forms SiOx, which can be polished flat by Chemical Mechanical Polishing (CMP) when forming the interlayer dielectric layer 200c above. The transistors formed in this embodiment are subjected to a simulation test to obtain SiOx. For example, after implanting Si ions, the ratio of silicon (Si) to oxygen (O) in SiOx is 1:9. For SiOx and SiO2 with a thickness of 13 nm each, after etching SiO2 in a 1:100 hydrofluoric acid solution for 2 minutes, 6.4 nm remains, and after etching SiOx under the same conditions, 12.87 nm remains. The spacer layer in the embodiment of the present application adopts a sandwich structure in which the first spacer layer and the second spacer layer are alternately arranged, and its material only uses common elements N, Si, and O. SiOx only changes the elemental ratio of SiO2 and does not add new elements. It will not affect the reliability, mobility, source-drain resistivity of the dielectric layer (caused by thermal diffusion), and will not contaminate the machine and affect the production line. After step S103e, steps S104 - S108 are continued to obtain the transistor shown in FIG. 5. In the above embodiment, the spacer layer includes: a first spacer layer 2001 and a second spacer layer 2002. In other embodiments, the spacer layer includes: a first spacer layer 2001, a second spacer layer 2002, a third spacer layer 2003, and a fourth spacer layer 2004. The descriptions of the first spacer layer 2001 and the second spacer layer 2002 can refer to the above embodiment and will not be elaborated here. The first spacer layer 2001, the second spacer layer 2002, and the third spacer layer 2003 are stacked along the first direction. The first spacer layer 2001 is disposed close to the first electrode 201, the third spacer layer 2003 is disposed close to the gate electrode 202, and the fourth spacer layer 2004 is disposed on the surface of the channel 204 between the first electrode 201 and the gate electrode 202. The wet etching rate of the second spacer layer 2002 is lower than that of silicon dioxide (SiO2). Among them, the wet etching rate of the second spacer layer 2002 is lower than that of silicon dioxide (SiO2), that is to say, the corrosion resistance of the second spacer layer 2002 is greater than that of silicon dioxide (SiO2). In this way, by setting two spacer layers and making the corrosion resistance of the spacer layer close to the gate electrode 202 better than that of silicon dioxide (SiO2), it is possible to avoid the corrosion of the spacer layer and the first electrode 201 caused by wet etching with hydrofluoric acid when preparing the gate electrode 202. In some embodiments, the third spacer layer 2003, the fourth spacer layer 2004 and the second spacer layer 2002 are made of the same material. Exemplarily, the material of the first spacer layer 2001 includes SiO2, and the materials of the second spacer layer 2002 include: silicon nitride SiN, SiOx, SiOyNz, silicon carbide SiC, calcium silicon oxide SiOC, silicon carbonitride SiCN, silicon carbonitride oxide SiCNO, silicon boron nitride SiBN, SiBCN. The first spacer layer 2001, the second spacer layer 2002, the third spacer layer 2003, and the fourth spacer layer 2004 are formed by deposition. In some embodiments, the spacer layer can be made of a low dielectric constant material. Exemplarily, the dielectric constant of the spacer layer is less than 7.6. FIG. 32 is a flowchart of another method for preparing a spacer layer provided by an embodiment of the present application. In step S103, a bottom spacer layer is formed on the first electrode 201, including the following steps: S1031. As shown in FIG. 34, a sacrificial layer 20a is deposited on the surfaces of the first electrode 201 and the channel 204 shown in FIG. 33. In some embodiments, the material of the sacrificial layer 20a includes SiO2. S1032. As shown in FIG. 35, a protective layer 20b is deposited on the surface of the sacrificial layer 20a on the channel 204. In some embodiments, the material of the protective layer 20b includes amorphous silicon aSi. S1033. As shown in FIG. 36, the sacrificial layer 20a on the first electrode 201 is etched so that the first electrode 201, the channel 204, the sacrificial layer 20a, and the protective layer 20b enclose a groove. In some embodiments, dry etching, i.e., plasma etching, can be used to etch the sacrificial layer 20a. During dry etching, the material can be removed by bombarding the surface of the sacrificial layer 20a with excited plasma. For example, a chemical gas etching (certas) machine tool can be used for etching. S1034. As shown in FIG. 37, a first spacer layer 2001, a second spacer layer 2002, a third spacer layer 2003, and a fourth spacer layer 2004 are deposited in the groove. Among them, the materials of the second spacer layer 2002, the third spacer layer 2003, and the fourth spacer layer 2004 include: The material of the first spacer layer 2001 includes SiO2, silicon nitride SiN, SiOx, SiOyNz, silicon carbide SiC, calcium carbon oxide SiOC, silicon carbonitride SiCN, silicon carbonitride oxide SiCNO, silicon boron nitride SiBN, SiBCN. The material of the second spacer layer 2002 includes: silicon nitride SiN, SiOx, SiOyNz, silicon carbide SiC, calcium carbon oxide SiOC, silicon carbonitride SiCN, silicon carbonitride oxide SiCNO, silicon boron nitride SiBN, SiBCN. The first spacer layer 2001, the second spacer layer 2002, the third spacer layer 2003, and the fourth spacer layer 2004 are formed by deposition. In this embodiment, the materials of the second spacer layer 2002, the third spacer layer 2003, and the fourth spacer layer 2004 are taken as SiN as an example for illustration. Depositing the first spacer layer 2001, the second spacer layer 2002, the third spacer layer 2003, and the fourth spacer layer 2004 in the groove includes: Forming the second spacer layer 2002 on the surface of the first electrode 201, forming the third spacer layer 2003 on the surface of the gate electrode 202 close to the first electrode 201, and forming the fourth spacer layer 2004 on the surface of the channel 204 between the first electrode 201 and the gate electrode 202. The second spacer layer 2002, the third spacer layer 2003, and the fourth spacer layer 2004 enclose a second groove. Then, the first spacer layer 2001 is deposited in the second groove. The material of the first spacer layer 2001 includes: SiO2. S1035. As shown in FIG. 38, the protective layer 20b and the sacrificial layer 20a are removed. Among them, the protective layer 20b and the sacrificial layer 20a can be removed by etching. The spacer layer in the embodiment of the present application has better thermal stability, supports possible subsequent high-temperature processes, and has better uniformity in process and structure. The second spacer layer 2002, the third spacer layer 2003, and the fourth spacer layer 2004 are respectively disposed on the surface of the connection position between the first electrode and the gate electrode. The corrosion resistance of the second spacer layer 2002, the third spacer layer 2003, and the fourth spacer layer 2004 is better than that of silicon dioxide (SiO2), which can avoid the corrosion of the spacer layer and the first electrode 201 caused by wet etching with hydrofluoric acid when fabricating the gate electrode 202. At the same time, the first spacer layer 2001 is made of a low-K material, so that the total dielectric constant of the spacer layer is less than a preset value, reducing the parasitic capacitance of the transistor and improving the device performance. Moreover, the material of the spacer layer only uses common elements of N, Si, and O, without metals and no new elements added. It will not affect the reliability, mobility, and source-drain resistivity of the dielectric layer (caused by thermal diffusion), nor will it contaminate the previous machine tool and affect the production line. The first spacer layer 2001 can be selectively retained at the bottom, with no residue on the sidewalls of the silicon channel, and can be removed by common processes. After step S1035, steps S104 - S108 are continued to obtain the transistor shown in Figure 6. As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claimed rights.

Claims

1. A transistor, characterized in that, Comprising: a substrate, a channel, a first electrode, a gate electrode, a second electrode, and a spacer layer; the channel is disposed on the substrate, the first electrode, the gate electrode, and the second electrode are stacked along a first direction, and the gate electrode surrounds the channel, wherein the first electrode is disposed on the substrate, and the first direction is perpendicular to the substrate; the spacer layer is disposed between the first electrode and the gate electrode, and the spacer layer includes: a first spacer layer and a second spacer layer stacked along the first direction, the wet etching rate of the second spacer layer is lower than that of silicon dioxide SiO2, and the dielectric constant of the first spacer layer is less than that of the second spacer layer.

2. The transistor according to claim 1, characterized in that, The dielectric constant of the spacer layer is less than 7.

6.

3. The transistor according to claim 1, wherein, The material of the first spacer layer includes SiO2, and the material of the second spacer layer includes: SiOx, where X is less than 2.

4. The transistor according to claim 3, wherein The first spacer layer is formed by atomic layer deposition, and the second spacer layer is formed by implanting Si ions into the surface layer of the first spacer layer.

5. The transistor according to any one of claims 1-4, characterized in that The spacer layer further includes: a third spacer layer and a fourth spacer layer, the third spacer layer is disposed between the first electrode and the first spacer layer, and the fourth spacer layer is disposed on the surface of the channel between the first electrode and the gate electrode.

6. The transistor according to claim 5, characterized in that, The materials of the third spacer layer, the fourth spacer layer, and the second spacer layer are the same.

7. The transistor according to claim 6, wherein The material of the first spacer layer includes SiO2, SiN, SiOx, SiOyNz, SiC, SiOC, SiCN, SiCNO, SiBN, SiBCN, and the material of the second spacer layer includes: SiN, SiOx, SiOyNz, SiC, SiOC, SiCN, SiCNO, SiBN, SiBCN, where X is less than 2.

8. The transistor according to claim 7, wherein The first spacer layer, the second spacer layer, the third spacer layer, and the fourth spacer layer are formed by deposition.

9. A transistor, characterized in that, Comprising: a substrate, a channel, a first electrode, a gate electrode, a second electrode, and a spacer layer; the channel is disposed on the substrate, the first electrode, the gate electrode, and the second electrode are stacked along a first direction, and the gate electrode surrounds the channel, wherein the first electrode is disposed on the substrate, and the first direction is perpendicular to the substrate; The wet etching rate of the spacer layer is lower than that of silicon dioxide SiO2.

10. The transistor according to claim 9, wherein, The dielectric constant of the spacer layer is less than 7.

6.

11. The transistor according to claim 9 or 10, characterized in that, The material of the spacer layer includes SiOx, where X is less than 2.

12. A chip, characterized in that, The chip includes: a transistor according to any one of claims 1-11.

13. The chip according to claim 12, wherein The chip includes: a logic chip, an analog chip, a memory chip, or a static random access memory.

14. An electronic device, characterized in that, Comprising: a circuit board, and a chip according to claim 12 or 13, the chip being disposed on the circuit board.

15. A method for manufacturing a transistor, characterized in that, The method includes: etching the substrate to form a channel; forming a first electrode on the substrate; A spacer layer is formed on the first electrode; the spacer layer includes: a first spacer layer and a second spacer layer stacked in a first direction, the first spacer layer is close to the first electrode, and the wet etching rate of the second spacer layer is lower than that of silicon dioxide (SiO2); the first direction is a direction perpendicular to the substrate; A dummy gate electrode is formed on the spacer layer, and the dummy gate electrode surrounds the channel; A second electrode is formed on the dummy gate electrode; The dummy gate electrode is removed; A gate electrode is formed on the spacer layer.

16. The method according to claim 15, wherein The material of the first spacer layer includes SiO2, and the material of the second spacer layer includes: SiOx, where X is less than 2.

17. The method according to claim 16, wherein The forming of the spacer layer on the first electrode includes: Depositing a first spacer layer on the first electrode and the surface of the channel; Depositing a protective layer on the first spacer layer; Etching the protective layer so that the thickness of the protective layer on the first electrode is less than the thickness of the protective layer on the channel; Injecting Si ions into the first spacer layer on the first electrode to form a second spacer layer; Removing the protective layer.

18. The method according to claim 15, wherein The spacer layer further includes: a third spacer layer and a fourth spacer layer, the third spacer layer is disposed on the surface of the gate electrode close to the first electrode, and the fourth spacer layer is disposed on the surface of the channel between the first electrode and the gate electrode.

19. The method according to claim 18, wherein The material of the first spacer layer includes SiO2, SiN, SiOx, SiOyNz, SiC, SiOC, SiCN, SiCNO, SiBN, SiBCN, and the material of the second spacer layer includes: SiN, SiOx, SiOyNz, SiC, SiOC, SiCN, SiCNO, SiBN, SiBCN, where X is less than 2.

20. The method according to claim 18 or 19, characterized in that, The forming of the spacer layer on the first electrode includes: Depositing a sacrificial layer on the first electrode and the surface of the channel; Depositing a protective layer on the surface of the sacrificial layer on the channel; Etching the sacrificial layer on the first electrode so that a groove is formed by enclosing the first electrode, the channel, the sacrificial layer and the protective layer; Depositing the first spacer layer, the second spacer layer, the third spacer layer and the fourth spacer layer in the groove; wherein, the second spacer layer is formed on the surface of the first electrode, the third spacer layer is formed on the surface of the gate electrode close to the first electrode, the fourth spacer layer is formed on the surface of the channel between the first electrode and the gate electrode, and the first spacer layer is formed in the area surrounded by the second spacer layer, the third spacer layer and the fourth spacer layer; Removing the protective layer and the sacrificial layer.

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