Double-sided packaged chip and manufacturing method therefor, and electronic device

Abstract

The present application provides a double-sided packaged chip (10) and a manufacturing method therefor, and an electronic device (100). In the double-sided packaged chip (10), first electronic components (12) and second electronic components (13) are respectively provided on a first surface (11a) and a second surface (11b) of a substrate (11), a first encapsulation layer (14) encloses the first electronic components (12) and the first surface (11a), and the thickness of metal bumps (151) on the first surface (11a) of the substrate (11) is less than the thickness of the first encapsulation layer (14). In the process of manufacturing the double-sided packaged chip (10), the first encapsulation layer (14) is ground and thinned, and the metal bumps (151) do not need to be ground, so that the amount of grinding and cutting of a metal material or the grinding resistance to the metal material is reduced, thereby improving production efficiency. In the manufacturing method for the double-sided packaged chip (10), a frame comprising connection layers (152) and multiple metal bumps (151) is provided on the substrate (11), so that the multiple metal bumps (151) are connected to the first surface (11a) of the substrate (11), and the first encapsulation layer (14) is provided on the first surface (11a) to enclose the first electronic components (12). The connection layers (152) are made of a flexible non-metallic material, and the connection layers (152) can be easily removed after or before molding, so that the amount of grinding and cutting or the grinding resistance is reduced, thereby achieving relatively high production efficiency.

Description

Double-sided packaged chip, preparation method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on January 11, 2024, with application number 202410047315.5 and application name “A double-sided packaged chip, its preparation method, and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a double-sided packaged chip, a preparation method thereof, and an electronic device. Background Art

[0003] Double-sided packaged chips allow electronic components to be arranged on opposite sides of a substrate, with high integration and small package thickness. Related technology In the process of manufacturing double-sided packaged chips, multiple metal bumps are arranged on one side of the substrate, and a packaging layer wraps the metal bumps and the metal bump side of the substrate. One side of the packaging layer is ground and thinned, and part of the metal bump area is removed to expose the metal bump to the packaging layer. The metal bump is used to electrically connect to a predetermined circuit structure (such as a motherboard). In the case where the metal bumps of the double-sided packaged chip are solder balls, the packaging layer is ground to expose the solder balls to the packaging layer, and the production efficiency is low. The industry needs a method for preparing double-sided packaged chips, which can easily expose the metal bumps to the packaging layer and has high production efficiency. Summary of the Invention

[0004] The embodiments of the present application provide a double-sided packaged chip, a preparation method thereof, and an electronic device, which solve the problem of low production efficiency caused by grinding the packaging layer during the production of double-sided packaged chips in related technologies, where solder balls are exposed to the packaging layer.

[0005] The embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, embodiments of the present application provide a double-sided packaged chip, comprising: a substrate, a first electronic component, a second electronic component, and a first packaging layer. The substrate has a first surface and a second surface disposed opposite each other, with a plurality of metal bumps disposed on the first surface. The first electronic component is disposed on the first surface; the second electronic component is disposed on the second surface. The first packaging layer at least partially encapsulates the first electronic component and the first surface, the thickness of the plurality of metal bumps being less than the maximum thickness of the first packaging layer, and the plurality of metal bumps are exposed to the first packaging layer at end surfaces facing away from the substrate.

[0007] The double-sided packaged chip provided in the embodiment of the present application has a first electronic component and a second electronic component respectively provided on the first surface and the second surface of the substrate, a first packaging layer encapsulating the first electronic component and the first surface, and the thickness of the metal bumps on the first surface of the substrate is less than the thickness of the first packaging layer. During the production of the double-sided packaged chip, the first packaging layer is ground and thinned, eliminating the need to grind the metal bumps, thereby reducing the amount of grinding or grinding resistance on the metal material and improving production efficiency. The end face of the metal bump away from the substrate is exposed to the first packaging layer, allowing the metal bump to be connected and conductive to the predetermined circuit structure.

[0008] In an optional implementation, a plastic encapsulation material may be used to cover the first surface of the substrate and the first electronic component. The plastic encapsulation material is cured to form a first packaging layer, thereby forming a protective structure for the first electronic component.

[0009] In one optional implementation, a connection layer is provided on the side of the first encapsulation layer facing away from the substrate. The end surface of the connection layer facing away from the substrate is spaced apart from the end surface of the metal bump facing away from the substrate. A frame is used to connect multiple metal bumps to the first surface of the substrate. The first encapsulation layer is provided on the first surface, and the first encapsulation layer and portions of the connection layer are ground and thinned. This solution easily forms multiple metal bumps on the substrate.

[0010] In an optional implementation, the metal bumps and the connection layer are made of different materials. The metal bumps can be made of metal or metal alloy, and the connection layer can be made of a flexible non-metallic material. A frame having multiple metal bumps and connection layers is easy to manufacture.

[0011] In an optional implementation, the metal bump can be used as a pin or a heat conduction structure. The metal bump can be made of various metals or metal alloy materials such as copper, copper alloy, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, and tungsten.

[0012] In one optional implementation, the connecting layer, which serves as the connecting portion connecting the multiple metal bumps, can be made of a flexible non-metallic material that is easily processed and removed. The flexible non-metallic material can be a polymer such as polyimide, polydimethylsiloxane, polyvinylidene fluoride, benzocyclobutene, polyethylene terephthalate, polymethyl methacrylate, and the like. The connecting layer in the frame can be made of a flexible non-metallic material, which can be easily removed after or before plastic packaging, reducing grinding wear and tear and grinding resistance, thereby increasing production efficiency.

[0013] In an optional implementation, when the connecting layer is removed after molding, a first packaging layer is formed on the first surface of the substrate by molding, and the first packaging layer wraps the first electronic component and the frame. A grinding wheel can be used to grind and thin part of the connecting layer and the first packaging layer to remove part of the connecting layer.

[0014] In an optional implementation, when the connecting layer is removed before molding, the connecting layer can be peeled off and removed by high temperature or mechanical means (for example, tearing off), and then the first surface of the substrate is molded to form a first packaging layer, and the first packaging layer can be ground and thinned using a grinding wheel.

[0015] In an optional implementation, at least two metal bumps have different cross-sectional areas and / or cross-sectional shapes, thereby achieving differentiation of the cross-sectional areas of the metal bumps.

[0016] In one optional implementation, the cross-sectional areas of the metal bumps are set to different sizes. The metal bumps arranged in an array (such as the first bump) are set to have a smaller cross-sectional area, and these metal bumps with small cross-sectional areas serve as pins. Some metal bumps (such as the second bump) where efficient heat dissipation is required are set to have a larger cross-sectional area. By arranging the metal bumps with large cross-sectional areas opposite to high-heat-generating electronic components (such as power amplifiers), the heat of the high-heat-generating electronic components is conducted through the substrate and the metal bumps with large cross-sectional areas, thereby improving the heat dissipation effect.

[0017] In one optional implementation, the cross-sectional shapes of the metal bumps are configured to be different. The cross-sectional shapes of the metal bumps arranged in an array are configured to be circular or rectangular, and the cross-sectional shape of the metal bump at at least one end position is a chamfered rectangle or other specific shape. The metal bump of the specific shape is used as the first pin.

[0018] In one optional implementation, the cross-sectional shape of the arrayed metal bumps is configured to be rectangular (including square), so that the metal bumps with a rectangular cross-section have better directionality. At the same spacing between the metal bumps, the metal bumps with a rectangular cross-section have a larger cross-sectional area, resulting in a better connection between the metal bumps and the substrate (or predetermined circuit structure).

[0019] In one optional implementation, the cross-sectional shapes of the multiple metal bumps include one or more of rectangular, circular, and elliptical shapes. Metal bumps of varying cross-sectional shapes can be directly formed on the connection layer. A frame comprising the connection layer and the multiple metal bumps is positioned on the substrate, such that the multiple metal bumps are connected to the first surface of the substrate. Metal bumps of varying cross-sectional shapes can correspondingly form solder pads of varying shapes, such as square, circular, and elliptical solder pads, thereby satisfying the need for configuring solder pads of varying shapes on the substrate.

[0020] In one optional implementation, the distance between the end surface of the metal bump facing away from the substrate and the end surface of the first packaging layer can range from 5 to 10 microns. This facilitates conductive connection between the metal bump and the predetermined circuit structure. After the first packaging layer is ground and thinned, the first packaging layer region or the connection layer region corresponding to the metal bump is processed to expose the first packaging layer on the end surface of the metal bump facing away from the substrate, thereby improving production efficiency.

[0021] In an optional implementation, the end face of the first electronic component may be exposed to the first packaging layer; or the first packaging layer may cover the first electronic component. Both methods can effectively protect the first electronic component.

[0022] In one optional implementation, a second encapsulation layer is further included, at least partially encapsulating the second electronic component and the second surface. A plastic encapsulation material can be used to encapsulate the second surface of the substrate and the second electronic component. The plastic encapsulation material is cured to form the second encapsulation layer, thereby forming a protective structure for the second electronic component.

[0023] In one optional implementation, a first surface of a substrate is provided with a metal bump and a first electronic component, which are encapsulated by a first packaging layer, with the metal bump exposed to the first packaging layer. A second surface of the substrate is provided with a second electronic component, which is encapsulated by a second packaging layer. The double-sided packaged chip forms a double-sided molded ball grid array package.

[0024] In an optional implementation, the first electronic component may include one or more of a low noise amplifier, a radio frequency switch, a power amplifier, and a controller.

[0025] In an optional implementation, the radio frequency low noise amplifier, radio frequency switch, power amplifier, and controller are chips and can be flip-chip mounted on the first surface of the substrate.

[0026] In an optional implementation, the second electronic component may include one or more of a chip capacitor, a filter, and a power amplifier.

[0027] In an optional implementation, a low-noise amplifier, a radio frequency switch and other second electronic components are provided on the first surface of the substrate, and a chip capacitor, a filter, a power amplifier and other second electronic components are provided on the second surface of the substrate. Multiple electronic components are connected through lines on the substrate to form a predetermined radio frequency front-end circuit.

[0028] In one optional implementation, the plurality of metal bumps include a first bump and a second bump, wherein the cross-sectional area of ​​the first bump is smaller than the cross-sectional area of ​​the second bump, and the first bump is electrically connected to the substrate. A mounting hole is provided on the substrate corresponding to at least one second electronic component, wherein a heat conducting portion is provided within the mounting hole, and the second bump and the heat conducting portion are connected. Heat from the high-heat-generating second electronic component is conducted to the second bump via the heat conducting portion. The heat conducting portion and the second bump have a large area, which can reduce the thermal resistance of the heat dissipation channel, reduce local hot spots, and achieve efficient heat dissipation.

[0029] In an optional implementation, the heat conducting portion can be made of copper or other metals, and can be directly embedded in the mounting hole of the substrate, or the heat conducting portion can be formed in the mounting hole of the substrate using an electroplating process.

[0030] In a second aspect, embodiments of the present application provide an electronic device comprising a circuit structure and the aforementioned double-sided packaged chip, wherein a plurality of metal bumps in the double-sided packaged chip are connected to the circuit structure. The circuit structure may comprise one or more of a circuit board and a first package structure.

[0031] In an optional implementation, when the circuit structure is a circuit board, the double-sided packaged chip and the circuit board can be assembled to form a circuit board assembly, thereby achieving electrical connection between the double-sided packaged chip and the circuit board.

[0032] In an optional implementation, when the circuit structure is a first packaging structure, the double-sided packaging chip and the first packaging structure can be assembled to form a stacked packaging structure to achieve conduction between the double-sided packaging chip and the first packaging structure.

[0033] In an optional implementation, the first packaging structure includes a first substrate and a first chip connected to the first substrate, and a plurality of metal bumps in the double-sided packaging chip are soldered to the first substrate of the first packaging structure.

[0034] In an optional implementation, when a plurality of metal bumps and a circuit structure in a double-sided packaged chip are connected, the metal bumps and the circuit structure may be conductively connected via a bonding material (such as solder).

[0035] In a third aspect, an embodiment of the present application provides a method for preparing a double-sided packaged chip, comprising: providing a frame, the frame comprising a connecting layer and a plurality of metal bumps connected to the same side of the connecting layer, the material of the connecting layer comprising a flexible non-metallic material; arranging a first electronic component on the first surface of the substrate; arranging the frame on the first surface so that the plurality of metal bumps are connected to the first surface; arranging a first packaging layer on the first surface, the first packaging layer wrapping the first electronic component; grinding and thinning the first packaging layer so that the plurality of metal bumps are exposed to the first packaging layer away from the end surface of the substrate; and arranging a second electronic component on the second surface of the substrate.

[0036] The method for preparing a double-sided packaged chip provided in an embodiment of the present application is to set a frame having a connecting layer and a plurality of metal bumps on a substrate, so that the plurality of metal bumps are connected to the first surface of the substrate, and set a first packaging layer on the first surface to wrap the first electronic component. The material of the connecting layer can be a flexible non-metallic material, and the connecting layer can be easily removed after or before plastic packaging, thereby reducing the amount of grinding or grinding resistance, and having high production efficiency. The end faces of the plurality of metal bumps away from the substrate are exposed to the first packaging layer, and the metal bumps can be connected and conducted with a predetermined circuit structure. A second electronic component is set on the second surface of the substrate. The method for preparing a double-sided packaged chip is compatible with the traditional double-sided packaged chip process flow, does not require the addition of additional steps, can achieve small-pitch, high-reliability metal bumps, has low cost, and high production efficiency.

[0037] In an optional implementation, a first packaging layer is provided on the first surface, and the first packaging layer wraps the first electronic component, specifically including: removing the connection layer, and providing the first packaging layer on the first surface, and the first packaging layer wraps the first electronic component and the plurality of metal bumps.

[0038] The connecting layer can be removed by high temperature or mechanical means, and then the first surface of the substrate is plastic-sealed to form a first packaging layer, which can be ground and thinned using a grinding wheel. This embodiment has a small grinding amount or grinding resistance and high production efficiency.

[0039] In one optional implementation, after removing the connection layer and providing a first encapsulation layer on the first surface, laser or etching grooves are formed in portions of the first encapsulation layer corresponding to the metal bumps, exposing the end faces of the multiple metal bumps facing away from the substrate to the first encapsulation layer. The end faces of the metal bumps facing away from the substrate are retracted a certain distance relative to the end face of the first encapsulation layer, thereby meeting the need for configuring pads of different shapes on the substrate.

[0040] In one optional implementation, after removing the connection layer and providing a first packaging layer on the first surface, the first packaging layer is ground and thinned to align the end surface of the plurality of metal bumps facing away from the substrate with the end surface of the first packaging layer. A second electronic component and a second packaging layer are provided on the second surface of the substrate, thereby obtaining a double-sided packaged chip.

[0041] In an optional implementation, a first packaging layer is provided on the first surface, and the first packaging layer wraps the first electronic component, specifically including: providing the first packaging layer on the first surface, and the first packaging layer wraps the first electronic component and the frame.

[0042] A first encapsulation layer is formed by plastic encapsulation on the first surface of the substrate. The first encapsulation layer encapsulates the first electronic component and the frame. A grinding wheel can be used to grind and thin portions of the connection layer and the first encapsulation layer, thereby removing portions of the connection layer. The connection layer can be made of a flexible non-metallic material. This embodiment reduces the amount of grinding or grinding resistance, resulting in high production efficiency.

[0043] In one optional implementation, when the first packaging layer encapsulates the first electronic component and the frame, laser or etching grooves are formed in portions of the connection layer corresponding to the metal bumps, exposing the end surfaces of the multiple metal bumps facing away from the substrate to the first packaging layer. This allows the end surfaces of the metal bumps facing away from the substrate to be retracted a certain distance relative to the outer surface of the portion of the connection layer remaining, thereby meeting the need for configuring pads of different shapes on the substrate.

[0044] In one optional implementation, when the first packaging layer encapsulates the first electronic component and the frame, the first packaging layer and the connection layer are ground and thinned to align the end surface of the plurality of metal bumps facing away from the substrate with the end surface of the first packaging layer. A second electronic component and a second packaging layer are then disposed on the second surface of the substrate to obtain a double-sided packaged chip.

[0045] In one optional implementation, multiple substrates are arranged and connected in a straight line, and multiple frames are arranged and connected in a straight line. Surface mount technology is used to mount the frames on the substrates. Using a strip process, multiple frames can be quickly mounted on multiple substrates, resulting in high production efficiency.

[0046] In one optional implementation, multiple substrates are connected in an array, and multiple frames are connected in an array. Surface mount technology is used to mount the frames on the substrates. Using wafer-level packaging technology, multiple frames can be quickly mounted on multiple substrates, resulting in high production efficiency.

[0047] In an optional implementation, a first hollow portion is provided on the connection layer corresponding to the first electronic component. The plastic encapsulation material has a good filling effect, and after the plastic encapsulation material is cured, a reliable first packaging layer is formed, which has a good protection effect on the first electronic component.

[0048] In one optional implementation, the connecting layer includes a second hollowed-out area corresponding to the area between two adjacent metal bumps. The plastic encapsulation material provides a good filling effect, and after curing, forms a reliable first encapsulation layer, which effectively protects the metal bumps and reduces short circuits between the metal bumps.

[0049] In an optional implementation, a first hollow position and a second hollow position are set on the connecting layer, which can be achieved by laser grooving or punching tools, and are easy to form.

[0050] In an optional implementation, the connection layer may not be provided with the first hollow position or the second hollow position. When the first surface of the substrate is plastic-sealed, the plastic sealing material can be filled on the first surface to achieve plastic sealing of the first electronic component and the metal bump.

[0051] In one optional implementation, a frame is disposed on the first surface, and the plurality of metal bumps are connected to the first surface. Specifically, the method includes: using a rigid clamp with elastic force to clamp the substrate and the frame along the thickness direction of the substrate; and using surface mount technology to dispose the frame on the substrate, so that the plurality of metal bumps are connected to the first surface. The rigid clamp with elastic force may include a fixed portion, a movable portion, and an elastic portion, wherein the movable portion is movable relative to the fixed portion, and the fixed portion and the movable portion are used to clamp the substrate and the frame, respectively.

[0052] The substrate and frame are compressed between the fixed and movable sections, ensuring that the connection locations between the multiple metal bumps and the substrate achieve a predetermined coplanarity. Surface mount technology is used to connect the multiple metal bumps to the first surface of the substrate. Reflow melts the bonding material (e.g., solder) between the metal bumps and the first surface. After the bonding material solidifies, the metal bumps are connected to the predetermined locations on the first surface.

[0053] In an optional implementation, a frame is provided, specifically comprising: forming a metal layer on a connection layer; and etching the metal layer to obtain a plurality of metal bumps. The frame having the connection layer and the plurality of metal bumps is prepared at a low cost.

[0054] In one optional implementation, providing a framework specifically includes: forming a metal seed layer on a connection layer; applying photoresist on the metal seed layer; performing exposure and development to remove portions of the photoresist corresponding to metal bumps, thereby forming filling grooves in the photoresist; forming metal bumps in the filling grooves by electroplating; and removing the photoresist and the metal seed layer in areas other than the metal bumps. The metal bumps have a smaller cross-sectional area and a smaller pitch between the metal bumps, thereby reducing the overall footprint of the double-sided packaged chip.

[0055] In one optional implementation, a method for preparing a double-sided packaged chip includes: placing a first electronic component on a first surface of a substrate; placing a frame on the first surface; placing a first packaging layer on the first surface, and grinding and thinning the first packaging layer; placing a second electronic component on a second surface of the substrate; and placing a second packaging layer on the second surface. The first surface of the substrate is processed first, followed by the second surface.

[0056] In an optional implementation, a method for preparing a double-sided packaged chip includes: setting a second electronic component on the second surface of a substrate; setting a second packaging layer on the second surface; setting a first electronic component on the first surface of the substrate; setting a first frame on the first surface; setting a first packaging layer on the first surface, and grinding and thinning the first packaging layer; in this embodiment, the second surface of the substrate is processed first, and then the first surface is processed. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] FIG1 is a schematic structural diagram of a double-sided packaged chip in the related art;

[0058] FIG2 is a schematic structural diagram of another double-sided packaged chip in the related art;

[0059] FIG3 is a schematic structural diagram of another double-sided packaged chip in the related art;

[0060] FIG4 is a schematic structural diagram of a double-sided packaged chip provided in an embodiment of the present application;

[0061] FIG5 is a schematic structural diagram of a double-sided packaged chip provided by another embodiment of the present application;

[0062] Figures 6(a) and (b) are respectively a front view and a top view of a frame used in the preparation process of a double-sided packaged chip provided in an embodiment of the present application;

[0063] (a) and (b) in FIG7 are respectively a front view and a top view of the frame arranged on the substrate;

[0064] Figures (a) to (e) in Figure 8 are schematic structural diagrams of the processing process of the first surface of the substrate of the double-sided packaging chip provided in an embodiment of the present application;

[0065] FIG9 is a bottom view of a double-sided packaged chip provided by another embodiment of the present application;

[0066] FIG10 is a cross-sectional view of the double-sided packaged chip of FIG9 along line AA;

[0067] FIG11 is a simulation structure diagram of a double-sided packaged chip provided in an embodiment of the present application;

[0068] FIG12 is a thermodynamic simulation diagram of a double-sided packaged chip in the related art;

[0069] FIG13 is a thermodynamic simulation diagram of the double-sided packaged chip of FIG11 ;

[0070] FIG14 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0071] Figures 15(a) to (e) are schematic structural diagrams of a processing process of a first surface of a substrate of a double-sided packaged chip according to another embodiment of the present application;

[0072] FIG16 is a top view of the double-sided packaged chip in (d) of FIG15 ;

[0073] Figures 17(a) and 17(b) are respectively a front view and a top view of a partial structure of a double-sided packaged chip provided in another embodiment of the present application;

[0074] FIG18 is a schematic structural diagram of a double-sided packaged chip provided in an embodiment of the present application;

[0075] Figures 19(a) to (e) are schematic structural diagrams of the processing process of the first surface of the substrate of the double-sided packaged chip provided in an embodiment of the present application;

[0076] FIG20 is a schematic diagram of a structure in which a rigid fixture is used to clamp a substrate and a frame during the preparation of a double-sided packaged chip according to an embodiment of the present application;

[0077] Figures 21(a) to (c) are schematic structural diagrams of the framework preparation process provided in an embodiment of the present application;

[0078] Figures 22(a) to (f) are schematic structural diagrams of a frame preparation process according to another embodiment of the present application;

[0079] FIG23 is a schematic diagram of a process for preparing a double-sided packaged chip according to an embodiment of the present application;

[0080] Figures 24 (a) to (c) are schematic structural diagrams of the second surface processing process of the substrate of the double-sided packaged chip provided in an embodiment of the present application;

[0081] FIG25 is a schematic flow chart of a method for preparing a double-sided packaged chip according to another embodiment of the present application;

[0082] Figures 26 (a) to (c) are schematic structural diagrams of a second surface processing process of a double-sided packaged chip substrate according to another embodiment of the present application;

[0083] (a) to (e) in FIG27 are schematic structural diagrams of the processing process of the first surface of the substrate of the double-sided packaging chip provided in another embodiment of the present application.

[0084] Explanation of the accompanying drawings: 1-double-sided packaged chip; 1a-substrate; 1b-metal bump; 1c-electronic component; 1d-high-heat-generating electronic component; 1e, 1f-packaging layer; 2-double-sided packaged chip; 2a-substrate; 2b-metal bump; 2c-electronic component; 2d-high-heat-generating electronic component; 2e, 2f-packaging layer; 3-double-sided packaged chip; 3a-substrate; 3b-metal bump; 3c-electronic component; 3d, 3e-packaging layer; 4-circuit structure; 10-double-sided packaged chip; 11-substrate; 11a-first surface; 11b-second surface; 111-mounting hole; 112-heat-conducting portion; 11c-thermal via; 12-first electronic component; 12a-low-noise amplifier; 12b-RF switch; 12c-controller; 12d-power amplifier; 12e-chip; 12f-solder pad; 13-second electronic component; 13a-chip capacitor; 13b-filter; 13c-power amplifier; 14-first packaging layer; 14a-end face; 15-frame; 151-metal bump; 151a-end face; 151b-first bump; 151c-second bump; 151d-metal bump; 151e-metal layer; 151f-metal seed layer; 152-connecting layer; 152a-end face; 1521-first hollow position; 1522-second hollow position; 153-photoresist; 1531-filling groove; 16-second packaging layer; 16a-end face; 20-circuit structure; 30-rigid fixture; 31-fixed part; 32-movable part; 33-elastic part; 100-electronic device. DETAILED DESCRIPTION

[0085] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application clearer, the application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application. Although the description of this application will be introduced in conjunction with some embodiments, this does not mean that the features of this application are limited to this embodiment. On the contrary, the purpose of introducing the application in conjunction with the embodiment is to cover other options or modifications that may be extended based on the claims of this application. In order to provide an in-depth understanding of the application, the following description will contain many specific details. This application can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of this application, some specific details will be omitted in the description. It should be noted that the embodiments in this application and the features in the embodiments can be combined with each other unless there is a conflict.

[0086] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0087] It should be understood that in the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. The orientation or positional relationship indicated by the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0088] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0089] In the embodiments of this application, "and / or" is simply a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0090] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0091] Referring to FIG. 1 , a double-sided packaged chip 1 in the related art includes a substrate 1a, metal bumps 1b, electronic components 1c, and packaging layers (1e, 1f). Electronic components 1c can be placed on both sides of substrate 1a. Multiple metal bumps 1b are provided on one side of substrate 1a for conductive connection to a predetermined circuit structure 4 (e.g., a motherboard). High-heat-generating electronic components 1d and metal bumps 1b can be provided on opposite sides of substrate 1a. Metal bumps 1b are solder balls, which can be made of SAC305 lead-free alloy solder with a low thermal conductivity of 58 watts / meter-degree (W / mK). Packaging layer 1e wraps around the solder ball side of substrate 1a, while packaging layer 1f wraps around the non-solder ball side of substrate 1a. The packaging layer uses a plastic encapsulation material with an even lower thermal conductivity of 1 W / mK. To prevent short circuits between solder balls, a certain amount of spacing must be reserved. The solder balls have a small cross-sectional area, and the position of the solder ball array is relatively fixed. The high-heat-generating electronic component 1d may not be arranged directly opposite the solder ball. The heat of the high-heat-generating electronic component 1d can be conducted to the predetermined circuit structure 4 through the substrate 1a and the solder ball (the arrow in Figure 1 indicates the direction of heat conduction). The thermal resistance on the solder ball side of the substrate 1a is large, and the heat dissipation effect is poor.

[0092] Referring to Figure 2, another double-sided packaged chip 2 in the related art includes a substrate 2a, metal bumps 2b, electronic components 2c, and packaging layers (2e, 2f). Metal bumps 2b are prefabricated copper pins, which are mounted on substrate 2a. The prefabricated copper pins have a small spacing, making it easy to place the high-heat-generating electronic component 2d and the copper pins directly opposite each other. Heat from the high-heat-generating electronic component 2d can be transferred to the predetermined circuit structure 4 through substrate 2a and the copper pins. The thermal resistance on the copper pin side of substrate 2a is low, improving the heat dissipation effect. However, the processing cost of the copper pins is high, the mounting efficiency of the copper pins is low, and they are prone to tilting during mounting (as shown by the copper pin at the far right in Figure 2). Moreover, the cross-sectional shape of the copper pins can only be circular, making it difficult to batch process copper pins of different cross-sectional areas or shapes. To achieve identification of the first pin (pin 1), the copper pin array must be arranged asymmetrically, such as with missing or misaligned copper pins at the end.

[0093] Referring to FIG3 , another double-sided packaged chip 3 in the related art includes a substrate 3a, a metal bump 3b, an electronic component 3c, and a packaging layer (3d, 3e). The metal bump 3b is a copper pillar formed by electroplating on the substrate 3a, which has a good heat dissipation effect and high assembly efficiency, and can solve the problem of tilting of prefabricated copper needles mounted on the substrate. However, when electroplating multiple copper pillars at the same time, the difference in cross-sectional area or shape of the multiple copper pillars should be relatively small. Otherwise, the copper pillar with a larger cross-sectional area will grow faster and the molding height will be higher, making it difficult to meet the height requirements of multiple copper pillars. Processing on the copper pillar side of the substrate 3a is more difficult than processing on the non-copper pillar side, and the difficult-to-process copper pillar side must be completed first. First, copper pillars are electroplated on the copper pillar side of substrate 3a. Then, electronic components 3c are mounted on this copper pillar side using a single assembly method. This is because the uneven surface of the copper pillars after electroplating makes it difficult to achieve full-panel assembly using surface mount technology. Next, a thicker encapsulation layer 3d is formed on the copper pillar side. Finally, the outer surface of this encapsulation layer 3d serves as a support surface for mounting electronic components 3c on the non-copper pillar side of substrate 3a and then encapsulating them with plastic. This restricts the processing sequence and increases production costs.

[0094] Referring to FIG. 4 , an embodiment of the present application provides a double-sided packaged chip 10, comprising: a substrate 11, a first electronic component 12, a second electronic component 13, and a first packaging layer 14. The substrate 11 has a first surface 11a and a second surface 11b disposed opposite each other, with a plurality of metal bumps 151 disposed on the first surface 11a. The first electronic component 12 is disposed on the first surface 11a; the second electronic component 13 is disposed on the second surface 11b. The first packaging layer 14 at least partially encapsulates the first electronic component 12 and the first surface 11a. The thickness A of the plurality of metal bumps 151 is less than the maximum thickness B of the first packaging layer 14, and the plurality of metal bumps 151 are exposed to the first packaging layer 14 at end surfaces 151a away from the substrate 11.

[0095] The thickness A of the metal bump 151 refers to the dimension of the metal bump 151 in the thickness direction of the substrate 11. The maximum thickness B of the first encapsulation layer 14 refers to the maximum dimension of the first encapsulation layer 14 in the thickness direction of the substrate 11. The thickness A of the metal bump 151 is less than the maximum thickness B of the first encapsulation layer 14, so that the end surface 151a of the metal bump 151 away from the substrate 11 is retracted a certain distance relative to the end surface 14a of the first encapsulation layer 14.

[0096] In the double-sided packaged chip 10 provided in the embodiment of the present application, the first surface 11a and the second surface 11b of the substrate 11 are respectively provided with a first electronic component 12 and a second electronic component 13. The first package layer 14 wraps around the first electronic component 12 and the first surface 11a. The thickness A of the metal bump 151 on the first surface 11a of the substrate 11 is less than the thickness B of the first package layer 14. During the manufacturing process of the double-sided packaged chip 10, the first package layer 14 is ground and thinned, eliminating the need to grind the metal bump 151, thereby reducing the amount of grinding or grinding resistance on the metal material and improving production efficiency. The end surface 151a of the metal bump 151 away from the substrate 11 is exposed to the first package layer 14, allowing the metal bump 151 to be connected and conductive to the predetermined circuit structure.

[0097] When providing the first encapsulation layer 14, referring to FIG. 4 , a plastic encapsulation material may be used to coat the first surface 11a of the substrate 11 and the first electronic component 12. The plastic encapsulation material is cured to form the first encapsulation layer 14, which provides a protective structure for the first electronic component 12. The first encapsulation layer 14 enhances the connection strength between the first electronic component 12 and the substrate 11, protects the first electronic component 12 and the first surface 11a from corrosion and damage, and improves the stability of the first electronic component 12. The plastic encapsulation material may be a filler such as epoxy resin.

[0098] In order to facilitate the arrangement of multiple metal bumps 151 on the substrate 11, in some embodiments, referring to FIG. 5 , a connecting layer 152 is provided on the side of the first packaging layer 14 away from the substrate 11, and an end surface 152a of the connecting layer 152 away from the substrate 11 and an end surface 151a of the metal bump 151 away from the substrate 11 are spaced apart.

[0099] A frame 15 is used to connect multiple metal bumps 151 to the first surface 11a of the substrate 11. A first encapsulation layer 14 is provided on the first surface 11a, and the first encapsulation layer 14 and a portion of the connection layer 152 are ground and thinned. This solution easily forms multiple metal bumps 151 on the substrate 11. In conjunction with Figures 6 (a) and (b), a frame 15 having a connection layer 152 and multiple metal bumps 151 is provided, and the multiple metal bumps 151 are provided on the same side of the connection layer 152. In conjunction with Figures 7 and 8 (a) and (b), the frame 15 is provided on the first surface 11a of the substrate 11, so that the multiple metal bumps 151 are connected to the first surface 11a. In conjunction with Figure 8 (c), a first encapsulation layer 14 is provided on the first surface 11a, so that the first encapsulation layer 14 encapsulates the first electronic component 12 and the frame 15. In conjunction with step (d) of FIG8 , the first encapsulation layer 14 and a portion of the connection layer 152 are ground and thinned, leaving a portion of the connection layer 152 connected to the first encapsulation layer 14. In conjunction with step (e) of FIG8 , the area of ​​the connection layer 152 corresponding to the metal bump 151 is processed, such as by laser grooving or etching, so that the end surface of the metal bump 151 facing away from the substrate 11 exposes the first encapsulation layer 14, and the end surface 151a of the metal bump 151 facing away from the substrate 11 is retracted a certain distance relative to the end surface 152a of the remaining connection layer 152.

[0100] When setting the materials of the metal bumps 151 and the connecting layer 152, the metal bumps 151 and the connecting layer 152 can be made of different materials. The metal bumps 151 can be made of metal or metal alloy, and the connecting layer 152 can be made of a flexible non-metallic material. The frame 15 having multiple metal bumps 151 and connecting layers 152 is easy to manufacture.

[0101] The metal bump 151 can be used as a pin or a heat conduction structure. The metal bump 151 can be made of various metals or metal alloy materials such as copper, copper alloy, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, and tungsten.

[0102] The connection layer 152, which serves as a connection portion connecting the plurality of metal bumps 151, can be made of a flexible non-metallic material that is easily processed and removed. The flexible non-metallic material can be a polymer such as polyimide (PI), polydimethylsiloxane (PDMS), polyvinylidene fluoride (PVDF), benzocyclobutene (BCB), polyethylene glycol terephthalate (PET), polymethyl methacrylate (PMMA), and the like.

[0103] In the related technology, an all-metal frame is set on the substrate. The metal bumps and connection layers in the all-metal frame are all made of metal materials. After one side of the all-metal frame is plastic-sealed, the plastic-sealed side needs to be ground and thinned. A grinding wheel is used to grind and remove all the connection layers made of metal so that the metal bumps are exposed to the packaging layer, and each metal bump is independent of each other without short circuit. The grinding cutting amount or grinding resistance of the metal connection layer is large, and the production efficiency is low.

[0104] In this embodiment, the connection layer 152 in the frame 15 can be made of a flexible non-metallic material. The connection layer 152 can be easily removed before or after plastic packaging, thereby reducing the amount of grinding or grinding resistance and improving production efficiency.

[0105] In the case where the connecting layer 152 is removed after plastic packaging, refer to (c) in Figure 8 , a first packaging layer 14 is formed by plastic packaging on the first surface 11a of the substrate 11, and the first packaging layer 14 wraps the first electronic component 12 and the frame 15. Combined with (d) in Figure 8 , a grinding wheel can be used to grind and thin part of the connecting layer 152 and the first packaging layer 14 to remove part of the connecting layer 152.

[0106] In the case where the connecting layer 152 is removed before molding, the connecting layer 152 can be peeled off and removed by high temperature or mechanical means (for example, tearing off), and then the first surface 11a of the substrate 11 is molded to form the first packaging layer 14, and the first packaging layer 14 can be ground and thinned using a grinding wheel.

[0107] When the cross-sections of the metal bumps 151 are differentiated, as shown in Figures 9 and 10 , at least two of the metal bumps 151 have different cross-sectional areas and / or cross-sectional shapes. The frame 15 is a prefabricated structure, and the cross-sectional areas and cross-sectional shapes of the metal bumps 151 can be different, thereby achieving cross-sectional differentiation of the metal bumps 151.

[0108] The cross-sectional areas of the metal bumps 151 are set to different sizes. For example, the metal bumps arranged in an array (such as the first bump 151b) are set to have a smaller cross-sectional area, and these metal bumps with small cross-sectional areas serve as pins; some metal bumps (such as the second bump 151c) are set to have a larger cross-sectional area where efficient heat dissipation is required. By arranging the metal bumps with large cross-sectional areas and high-heat-generating electronic components (such as the power amplifier 12d) opposite each other, the heat of the high-heat-generating electronic components is conducted through the substrate 11 and the metal bumps with large cross-sectional areas, thereby improving the heat dissipation effect.

[0109] The cross-sectional shape of the metal bumps 151 is set to different shapes. For example, the cross-sectional shape of the metal bumps 151 arranged in an array is set to a circular, rectangular, or other shape, and the cross-sectional shape of the metal bump 151d at at least one end position is a rectangular with chamfered corners or other specific shapes. The metal bump 151d of the specific shape serves as the first pin (pin1).

[0110] When the cross-sectional shape of the arrayed metal bumps 151 is set to a rectangular (including square) shape, the frame 15 is a prefabricated structure, and the arrayed metal bumps 151 are fabricated on the connection layer 152. This allows the metal bumps 151 with rectangular cross-sections to have better directionality. With the same spacing between the metal bumps 151, the metal bumps 151 with rectangular cross-sections have a larger cross-sectional area, resulting in a better connection between the metal bumps 151 and the substrate 11 (or the predetermined circuit structure).

[0111] To verify the excellent heat dissipation performance of the metal bump side of the double-sided packaged chip of this embodiment, thermodynamic finite element simulations were performed on the double-sided packaged chip of this embodiment and a related art double-sided packaged chip. The junction-to-board thermal resistance (Theta-JB) model was used, assuming the temperature of the board adjacent to the package is known.

[0112] The double-sided packaged chip of this embodiment has a similar structure to the double-sided packaged chip of the related art. As shown in Figure 11, in the double-sided packaged chip of this embodiment, a metal bump 151 is provided on the first surface 11a of the substrate 11, and a chip 12e, serving as a heat source, is provided on the second surface 11b of the substrate 11. The metal bump 151 and the pad 12f of the chip 12e are arranged opposite each other, and heat is conducted between them through the thermal via 11c of the substrate 11. The end of the metal bump 151 away from the substrate 11 serves as a constant temperature surface.

[0113] The metal bumps in the double-sided packaged chip of the related art are solder balls. The metal bumps 151 in the double-sided packaged chip of this embodiment are columnar or block-shaped bumps. The cross-sectional area of ​​the metal bumps 151 of this embodiment is larger than the cross-sectional area of ​​the solder balls of the related art.

[0114] FIG12 and FIG13 respectively show the thermodynamic temperature distribution diagrams of the double-sided packaged chip of the related art and the double-sided packaged chip of this embodiment. The unit of thermodynamic temperature is Kelvin, and the symbol is K. The conversion relationship between thermodynamic temperature T and Celsius temperature t is:

[0115] T(K)=273.15+t(℃)

[0116] Simulations show that the solder ball temperature of the related art double-sided packaged chip is 78 degrees Celsius (°C), as shown in FIG12 , while the temperature of the metal bumps 151 of the double-sided packaged chip of this embodiment is 51°C, as shown in FIG13 . The temperature of the metal bumps 151 of this embodiment is approximately 35% lower than that of the related art solder balls, demonstrating that the metal bump side of the double-sided packaged chip of this embodiment exhibits superior heat dissipation.

[0117] When setting the cross-sectional shape of the metal bumps 151, referring to FIG9 , the cross-sectional shapes of the multiple metal bumps 151 include one or more of rectangular, circular, and elliptical shapes. Referring to FIG6 (a), metal bumps 151 of different cross-sectional shapes can be directly formed on the connection layer 152. The frame 15 having the connection layer 152 and the multiple metal bumps 151 is placed on the substrate 11, so that the multiple metal bumps 151 are connected to the first surface 11a of the substrate 11. The metal bumps 151 of different cross-sectional shapes can form pads of different shapes, such as square pads, circular pads, and elliptical pads, to meet the need for configuring pads of different shapes on the substrate 11 and enhance chip design flexibility.

[0118] When setting the distance between the end surface 151a of the metal bump 151 and the end surface 14a of the first packaging layer 14, referring to FIG. 4 , the distance between the end surface 151a of the metal bump 151 away from the substrate 11 and the end surface 14a of the first packaging layer 14 may be in the range of 5 μm to 10 μm.

[0119] The end face 151a of the metal bump 151 and the end face 14a of the first packaging layer 14 are arranged within the aforementioned spacing range to facilitate conductive connection between the metal bump 151 and the predetermined circuit structure. Referring to (d) and (e) of FIG8 , after the first packaging layer 14 is ground and thinned, the region of the first packaging layer 14 or the region of the connecting layer 152 corresponding to the metal bump 151 is processed, such as by laser grooving or etching, so that the end face of the metal bump 151 facing away from the substrate 11 exposes the first packaging layer 14. The region of the first packaging layer 14 or the region of the connecting layer 152 within the aforementioned spacing range is easy to process, and has high production efficiency.

[0120] Among them, laser grooving uses the high energy of the laser beam to process the material to achieve material grooving.

[0121] Etching can be done by either wet or dry etching. In wet etching, chemicals in the etching solution react with substances on the surface of the target material, dissolving them and creating grooves. In dry etching, the target material is placed in a vacuum chamber and a high-energy ion beam or plasma is used to remove some of the surface material, creating grooves.

[0122] For example, the distance between the end surface 151 a of the metal bump 151 and the end surface 14 a of the first packaging layer 14 may be in the range of 5 microns, 6 microns, 7 microns, 8 microns, 9 microns, 10 microns, etc., which may be set as required.

[0123] When the first packaging layer 14 is provided, the end surface of the first electronic component 12 may be exposed to the first packaging layer 14; or the first packaging layer 14 may cover the first electronic component 12. Both methods can effectively protect the first electronic component 12.

[0124] In order to protect the second electronic component 13 , in some embodiments, referring to FIG. 4 and FIG. 5 , a second packaging layer 16 is further included. The second packaging layer 16 at least partially wraps the second electronic component 13 and the second surface 11 b .

[0125] A plastic encapsulation material can be used to coat the second surface 11b of the substrate 11 and the second electronic component 13. The plastic encapsulation material is cured to form a second encapsulation layer 16, which provides a protective structure for the second electronic component 13. The second encapsulation layer 16 can enhance the connection strength between the second electronic component 13 and the substrate 11, protect the second electronic component 13 from corrosion and damage, and improve the stability of the second electronic component 13. The plastic encapsulation material can be a filler such as epoxy resin.

[0126] In some embodiments, referring to Figures 4 and 5 , a first surface 11a of a substrate 11 is provided with a metal bump 151 and a first electronic component 12. A first encapsulation layer 14 surrounds the metal bump 151 and the first electronic component 12, with the metal bump 151 exposed from the first encapsulation layer 14. A second electronic component 13 is disposed on a second surface 11b of the substrate 11, which is surrounded by a second encapsulation layer 16. The double-sided packaged chip 10 forms a double-sided molded ball grid array (DSMBGA) package, which features a high level of integration and a small package thickness.

[0127] When setting the first electronic component 12, referring to Figures 4, 5, and 7, the first electronic component 12 may include one or more of a low noise amplifier (LNA) 12a, a radio frequency switch (SW) 12b, a power amplifier (PA) 12d, and a controller (CTR) 12c.

[0128] The RF low-noise amplifier 12a is a chip in the RF front end that amplifies the signal received from the antenna for processing by the subsequent electronic device 100. The RF switch 12b is a chip in the RF front end that switches between signals of different frequencies or different communication formats on the signal transmission path. The power amplifier 12d is a chip in the RF front end that can amplify the power of the RF signal generated by the modulation circuit for output to the antenna for radiation. The controller 12c is used to electrically connect to the RF low-noise amplifier 12a, the RF switch 12b, the power amplifier 12d, and other components to control multiple components.

[0129] The RF low noise amplifier 12 a , the RF switch 12 b , the power amplifier 12 d , and the controller 12 c are chips that can be flip-chip mounted on the first surface 11 a of the substrate 11 .

[0130] When the second electronic component 13 is provided, referring to FIG. 4 and FIG. 5 , the second electronic component 13 may include one or more of a chip capacitor 13 a , a filter 13 b , and a power amplifier 13 c .

[0131] Chip capacitor 13a is a multilayer ceramic capacitor (MLCC). Chip capacitor 13a is made of ceramic dielectric diaphragms with printed inner electrodes stacked in an offset manner, sintered at high temperature to form a ceramic chip, and then sealed with outer electrodes at both ends of the chip.

[0132] Filter 13b is a chip in the RF front end that filters out frequency components within a predetermined frequency range and outputs a signal with a predetermined frequency from among the multiple input RF signals. Filter 13b can be a surface acoustic wave (SAW) filter or a bulk acoustic wave (BAW) filter.

[0133] The filter 13 b and the power amplifier 13 c are chips and can be flip-chip mounted on the second surface 11 b of the substrate 11 .

[0134] In some embodiments, referring to Figures 4 and 5, a low-noise amplifier 12a, a radio frequency switch 12b and other second electronic components 13 are provided on the first surface 11a of the substrate 11, and a chip capacitor 13a, a filter 13b, a power amplifier 13c and other second electronic components 13 are provided on the second surface 11b of the substrate 11. Multiple electronic components are connected through the lines on the substrate 11 to form a predetermined radio frequency front-end circuit.

[0135] To achieve efficient heat dissipation through metal bumps 151, in some embodiments, referring to Figures 9 and 10, multiple metal bumps 151 include a first bump 151b and a second bump 151c. The cross-sectional area of ​​first bump 151b is smaller than the cross-sectional area of ​​second bump 151c. First bump 151b is electrically connected to substrate 11. Mounting holes 111 are defined on substrate 11 corresponding to at least one second electronic component 13. A heat conducting portion 112 is disposed within mounting hole 111, and second bump 151c is connected to heat conducting portion 112.

[0136] The first bump 151b has a relatively small cross-sectional area and serves as a pin for the substrate 11. The second bump 151c has a relatively large cross-sectional area and serves as a heat dissipation channel for a portion of the high-heat-generating second electronic components 13 (such as the power amplifier 13c) on the substrate 11. The second bump 151c and a portion of the high-heat-generating second electronic components 13 are directly opposite each other, and the heat conducting portion 112 in the substrate 11 is located between the high-heat-generating second electronic components 13 and the second bump 151c. Heat from the high-heat-generating second electronic components 13 is conducted to the second bump 151c through the heat conducting portion 112. The large area of ​​the heat conducting portion 112 and the second bump 151c reduces the thermal resistance of the heat dissipation channel, reduces local hot spots, and achieves efficient heat dissipation.

[0137] The heat conducting portion 112 can be made of copper or other metals and can be directly embedded in the mounting hole 111 of the substrate 11 or formed in the mounting hole 111 of the substrate 11 by electroplating.

[0138] 14 , an embodiment of the present application provides an electronic device 100 , including a circuit structure 20 and the double-sided packaged chip 10 described above, wherein a plurality of metal bumps 151 in the double-sided packaged chip 10 are connected to the circuit structure 20 .

[0139] The circuit structure 20 may include one or more of a circuit board and a first packaging structure.

[0140] In the case where the circuit structure 20 is a circuit board, the double-sided packaged chip 10 and the circuit board are assembled to form a circuit board assembly, thereby achieving electrical connection between the double-sided packaged chip 10 and the circuit board.

[0141] In the case where the circuit structure 20 is a first packaging structure, the double-sided packaging chip 10 and the first packaging structure are assembled to form a stacked packaging structure, thereby achieving electrical connection between the double-sided packaging chip 10 and the first packaging structure.

[0142] The first package structure can adopt various packaging structures. For example, the first package structure includes a first substrate and a first chip connected to the first substrate. Multiple metal bumps 151 in the double-sided packaged chip 10 are soldered and connected to the first substrate of the first package structure. Connecting the first package structure and the double-sided packaged chip 10 to form a stacked package structure can improve the integration of electronic components, achieve high performance, and reduce power consumption.

[0143] When the plurality of metal bumps 151 in the double-sided packaged chip 10 are connected to the circuit structure 20 , the metal bumps 151 and the circuit structure 20 may be conductively connected via a bonding material (such as solder).

[0144] The electronic device 100 may be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, and the like. Among them, consumer electronic products may be mobile phones, tablet computers, laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (such as smart watches and smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, and the like. Home electronic products may be smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (such as soybean milk machines and robot vacuums), and the like. Vehicle-mounted electronic products may be vehicle-mounted navigation systems, vehicle-mounted high-density digital video discs (DVDs), and the like. Financial terminal products may be automated teller machines (ATMs), self-service terminals, and the like. Communication electronic products may be communication equipment such as servers, storage devices, radars, and base stations.

[0145] When determining the double-sided packaged chip 10 or electronic device 100 of the example of the present application, the double-sided packaged chip 10 can be disassembled and analyzed, and the metal bumps 151 at the first surface 11a of the double-sided packaged chip 10 can be flattened and longitudinally sectioned. Using a focused ion beam (FIB) microscope or a transmission electron microscope (TEM), it can be observed that the thickness A of the metal bumps 151 is less than the maximum thickness B of the first packaging layer 14.

[0146] The present invention provides a method for preparing a double-sided packaged chip, comprising:

[0147] 6 (a) and (b), a frame 15 is provided. The frame 15 includes a connection layer 152 and a plurality of metal bumps 151 connected to the same side of the connection layer 152. The connection layer 152 is made of a flexible non-metallic material.

[0148] 7 (a), (b) and FIG. 8 (a), a first electronic component 12 is provided on the first surface 11a of the substrate 11;

[0149] 8 (b), the frame 15 is disposed on the first surface 11a, so that the plurality of metal bumps 151 are connected to the first surface 11a;

[0150] 8 (c), a first encapsulation layer 14 is provided on the first surface 11a, and the first encapsulation layer 14 wraps the first electronic component 12;

[0151] 8 (d), (e), the first packaging layer 14 is ground and thinned, so that the end surface 151a of the plurality of metal bumps 151 away from the substrate 11 is exposed to the first packaging layer 14;

[0152] 4 , a second electronic component 13 is disposed on the second surface 11 b of the substrate 11 .

[0153] The method for preparing a double-sided packaged chip 10 provided in an embodiment of the present application comprises placing a frame 15 having a connection layer 152 and multiple metal bumps 151 on a substrate 11, connecting the multiple metal bumps 151 to the first surface 11a of the substrate 11. A first packaging layer 14 is then provided on the first surface 11a to encapsulate a first electronic component 12. The connection layer 152 can be made of a flexible non-metallic material and is easily removable after or before plastic packaging, reducing grinding effort or resistance and improving production efficiency. The multiple metal bumps 151 are exposed to the first packaging layer 14 at the end surfaces 151a away from the substrate 11, allowing the metal bumps 151 to connect and conduct with a predetermined circuit structure. A second electronic component 13 is then provided on the second surface 11b of the substrate 11. This method for preparing the double-sided packaged chip 10 is compatible with conventional double-sided packaged chip processes, eliminating the need for additional steps. It can achieve fine-pitch, highly reliable metal bumps 151, resulting in low cost and high production efficiency.

[0154] There are multiple optional implementations for manufacturing the first encapsulation layer 14 , and two implementations are exemplified below.

[0155] The first implementation method of the first packaging layer 14 is: referring to Figure 15, a first packaging layer 14 is set on the first surface 11a, and the first packaging layer 14 wraps the first electronic component 12, specifically including: as shown in (b) and (c) in Figure 15, the connecting layer 152 is removed, and as shown in (d) in Figure 15, a first packaging layer 14 is set on the first surface 11a, and the first packaging layer 14 wraps the first electronic component 12 and multiple metal bumps 151.

[0156] The connection layer 152 can be removed by peeling it off at high temperature or mechanically (e.g., by tearing it off), and then the first surface 11a of the substrate 11 is plastic-encapsulated to form the first encapsulation layer 14. The first encapsulation layer 14 can be ground and thinned using a grinding wheel. Compared to the related art that uses an all-metal frame on the substrate and requires a grinding wheel to grind off all metal connection layers, this embodiment reduces the amount of grinding or grinding resistance, and has higher production efficiency.

[0157] In some embodiments, after removing the connection layer 152 and disposing the first encapsulation layer 14 on the first surface 11a, as shown in FIG15(e) and FIG16 , laser or etching grooves are formed in the portions of the first encapsulation layer 14 corresponding to the metal bumps 151, so that the end surfaces 151a of the plurality of metal bumps 151 facing away from the substrate 11 are exposed to the first encapsulation layer 14. The thickness A of the metal bumps 151 is less than the maximum thickness B of the first encapsulation layer 14, that is, the end surfaces 151a of the metal bumps 151 facing away from the substrate 11 are retracted a certain distance relative to the end surface 14a of the first encapsulation layer 14. Laser grooving the portions of the first encapsulation layer 14 corresponding to the metal bumps 151 can form pads of various shapes, such as square pads, circular pads, and oval pads, thereby satisfying the need to configure pads of various shapes on the substrate 11.

[0158] In other embodiments, referring to (a) and (b) of FIG. 17 , after removing the connection layer 152 and then providing the first packaging layer 14 on the first surface 11a, the first packaging layer 14 is ground and thinned so that the end surface 151a of the plurality of metal bumps 151 away from the substrate 11 is flush with the end surface 14a of the first packaging layer 14. Referring to FIG. 18 , the second electronic component 13 and the second packaging layer 16 are provided on the second surface 11b of the substrate 11, thereby obtaining a double-sided packaged chip.

[0159] The second implementation method of the first packaging layer 14 is: referring to Figure 8, the first packaging layer 14 is set on the first surface 11a, and the first packaging layer 14 wraps the first electronic component 12, specifically including: as shown in (c) in Figure 8, the first packaging layer 14 is set on the first surface 11a, and the first packaging layer 14 wraps the first electronic component 12 and the frame 15.

[0160] A first packaging layer 14 is formed by plastic encapsulation on the first surface 11a of the substrate 11. The first packaging layer 14 encapsulates the first electronic component 12 and the frame 15. As shown in (d) of Figure 8 , a grinding wheel can be used to grind and thin a portion of the connection layer 152 and the first packaging layer 14, thereby removing a portion of the connection layer 152. The connection layer 152 can be made of a flexible non-metallic material. Compared to the related art in which an all-metal frame is provided on the substrate and a grinding wheel is used to grind and remove the entire metal connection layer, this embodiment reduces the amount of grinding or grinding resistance, thereby increasing production efficiency.

[0161] In some embodiments, when the first packaging layer 14 encapsulates the first electronic component 12 and the frame 15, as shown in (e) of FIG8 , a laser groove or etching groove is performed on a portion of the connection layer 152 corresponding to the metal bumps 151, so that the end surfaces 151a of the multiple metal bumps 151 away from the substrate 11 are exposed to the first packaging layer 14. The end surfaces 151a of the metal bumps 151 away from the substrate 11 are retracted a certain distance relative to the outer surface of the portion of the connection layer 152 that remains. Laser grooves are performed on the portion of the connection layer 152 corresponding to the metal bumps 151 to form pads of different shapes, such as square pads, circular pads, and elliptical pads, to meet the need for configuring pads of different shapes on the substrate 11.

[0162] In other embodiments, referring to (a) and (b) of FIG. 17 , when the first packaging layer 14 encapsulates the first electronic component 12 and the frame 15, the first packaging layer 14 and the connecting layer 152 are ground and thinned so that the end surface 151a of the plurality of metal bumps 151 away from the substrate 11 is flush with the end surface 14a of the first packaging layer 14. Referring to FIG. 18 , the second electronic component 13 and the second packaging layer 16 are disposed on the second surface 11b of the substrate 11, thereby obtaining a double-sided packaged chip.

[0163] There are multiple optional implementations for manufacturing the double-sided packaged chip 10 , and two implementations are exemplified below.

[0164] The first implementation method of the double-sided packaging chip 10 is: multiple substrates 11 are arranged in a straight line and connected in sequence, multiple frames 15 are arranged in a straight line and connected in sequence, and the multiple frames 15 are correspondingly arranged on the multiple substrates 11 using surface mounting technology.

[0165] This embodiment adopts strip operation, that is, a strip-shaped mother substrate and a strip-shaped mother frame are matched. The mother substrate has multiple substrate 11 areas arranged in a strip shape and connected as a whole, and the mother frame has multiple frames 15 arranged in a strip shape and connected as a whole. The multiple frames 15 are installed on the multiple substrates 11 one by one, so that the multiple frames 15 can be quickly mounted on the multiple substrates 11. After setting electronic components and plastic sealing on both sides of the mother substrate, multiple double-sided packaged chips 10 are formed by cutting, and the production efficiency is relatively high.

[0166] The second implementation of the double-sided packaging chip 10 is as follows: multiple substrates 11 are connected in an array arrangement, multiple frames 15 are connected in an array arrangement, and the multiple frames 15 are correspondingly arranged on the multiple substrates 11 using surface mounting technology.

[0167] This embodiment adopts a wafer level package (WLP) process. The wafer has multiple substrate 11 areas arranged in an array. A mother frame with a size comparable to the wafer is used. The mother frame has multiple frames 15 arranged in an array and connected as a whole. The multiple frames 15 are installed on the multiple substrates 11 in a one-to-one correspondence, so that the multiple frames 15 can be quickly mounted on the multiple substrates 11. After electronic components are set on both sides of the wafer and plastic sealing processes are carried out, multiple double-sided packaged chips 10 are formed by cutting, and the production efficiency is relatively high.

[0168] In order to facilitate filling of the molding material into the first surface 11 a of the substrate 11 during molding, in some embodiments, referring to FIG. 6 , FIG. 7 , and FIG. 19 , a first hollow portion 1521 is formed on the connection layer 152 corresponding to the first electronic component 12 .

[0169] When the first surface 11a of the substrate 11 is plastic-sealed, the molten plastic material can pass through the first hollow position 1521 of the connecting layer 152 and fill the area between the first electronic component 12 and the substrate 11 and between adjacent first electronic components 12. The plastic material has a good filling effect. After the plastic material is solidified, a reliable first packaging layer 14 is formed, which has a good protection effect on the first electronic component 12.

[0170] To facilitate filling of the molding material into the first surface 11 a of the substrate 11 during molding, in some embodiments, referring to FIG. 6 , FIG. 7 , and FIG. 19 , the connecting layer 152 has a second hollow portion 1522 corresponding to the area between two adjacent metal bumps 151 .

[0171] When the first surface 11a of the substrate 11 is molded, the molten molding material can pass through the second hollow position 1522 of the connecting layer 152 and fill the area between two adjacent metal bumps 151. The molding material has a good filling effect. After the molding material is solidified, a reliable first packaging layer 14 is formed, which has a good protection effect on the metal bumps 151 and reduces the short circuit between the metal bumps 151.

[0172] When setting the first hollow position 1521 and the second hollow position 1522 on the connecting layer 152, laser slotting or punching tooling can be used to achieve easy forming. The shape of the first hollow position 1521 and the second hollow position can be rectangular, circular, elliptical, etc., as required.

[0173] In other embodiments, the connection layer 152 may not be provided with the first hollow position 1521 or the second hollow position 1522. When the first surface 11a of the substrate 11 is plastic-sealed, the plastic sealing material can be filled on the first surface 11a to achieve plastic sealing of the first electronic component 12 and the metal bump 151.

[0174] In order to meet the coplanarity between the multiple metal bumps 151 and the substrate 11, in some embodiments, referring to Figure 20, the frame 15 is set on the first surface 11a, so that the multiple metal bumps 151 are connected to the first surface 11a, specifically including: using a rigid clamp 30 with elastic force to clamp the substrate 11 and the frame 15 along the thickness direction of the substrate 11; using surface mounted technology (SMT) to set the frame 15 on the substrate 11, so that the multiple metal bumps 151 are connected to the first surface 11a.

[0175] The elastic rigid clamp 30 may include a fixed portion 31, a movable portion 32, and an elastic portion 33. The movable portion 32 is movable relative to the fixed portion 31 and is used to clamp the substrate 11 and the frame 15, respectively. The fixed portion 31 and the movable portion 32 each have a clamping surface for abutting against the substrate 11 and the frame 15. The elastic portion 33 may be a spring or other elastic structure, which is used to provide elastic force to the movable portion 32, allowing it to move away from the fixed portion 31.

[0176] External pressure acts on the movable portion 32, causing it to move closer to the fixed portion 31. The elastic portion 33 compresses and stores energy, pressing the substrate 11 and frame 15 between the fixed portion 31 and the movable portion 32. This allows the connection positions between the multiple metal bumps 151 and the substrate 11 to achieve a predetermined coplanarity. Surface mount technology is used to connect the multiple metal bumps 151 to the first surface 11a of the substrate 11. Reflow melts the bonding material (e.g., solder) between the metal bumps 151 and the first surface 11a. After the bonding material solidifies, the metal bumps 151 are connected to the first surface 11a at predetermined positions. The external pressure on the movable portion 32 is removed, causing the elastic portion 33 to expand and release energy. The movable frame moves away from the fixed portion 31, and the rigid clamp 30 is opened. The connected substrate 11 and frame 15 are removed, preparing for the subsequent plastic encapsulation process.

[0177] There are multiple optional implementations when preparing the frame 15 , and two implementations are given below as examples.

[0178] The first method of preparing the frame 15 is: providing the frame 15, specifically including: as shown in (a) in Figure 21, making a metal layer 151e on the connecting layer 152; as shown in (b) in Figure 21, etching the metal layer 151e to obtain multiple metal bumps 151.

[0179] The above method allows for the cost-effective fabrication of a frame 15 having a connection layer 152 and multiple metal bumps 151. The metal layer 151e on the connection layer 152 can be fabricated using a physical vapor deposition (PVD) process, such as vacuum evaporation or sputtering. An etching solution reacts with predetermined locations on the metal layer 151e to form a pattern, thereby forming multiple metal bumps 151.

[0180] As shown in (c) of FIG. 21 , a first hollow position 1521 and a second hollow position 1522 may be provided on the connection layer 152 , which may be easily formed by using a laser grooving or a punching tool.

[0181] The second implementation method of preparing the frame 15 is: providing the frame 15, specifically including: as shown in (a) and (b) in Figure 22, making a metal seed layer 151f on the connecting layer 152; as shown in (c) in Figure 22, setting a photoresist 153 on the metal seed layer 151f; as shown in (d) in Figure 22, exposing and developing to remove part of the photoresist 153 corresponding to the metal bump 151, and forming a filling groove 1531 on the photoresist 153; as shown in (e) in Figure 22, electroplating to form a metal bump 151 in the filling groove 1531; as shown in (f) in Figure 22, removing the photoresist 153 and removing the metal seed layer 151f in the area outside the metal bump 151.

[0182] The frame 15 prepared in the above manner has a smaller cross-sectional area of ​​the metal bumps 151 and a smaller spacing between the metal bumps 151, resulting in a smaller overall structure for the double-sided packaged chip 10. As shown in Figures 22(a) and 22(b), the metal seed layer 151f on the connecting layer 152 can be produced using a physical vapor deposition process, such as vacuum evaporation or sputtering. The function of the metal seed layer 151f is to improve the adhesion between the electroplated metal bumps 151 and the connecting layer 152. As shown in Figure 22(c), a photoresist 153 is applied to the metal seed layer 151f. The pattern of the photoresist plate is adapted to the shape of the filling grooves 1531. The assembly of the connecting layer 152, metal seed layer 151f, and photoresist 153 is placed on a photolithography machine, aligned with the photoresist plate, and then exposed. As shown in Figure 22(d), the photoresist 153 is removed by development at the locations corresponding to the metal bumps 151, transferring the pattern of the photoresist plate to the photoresist 153. As shown in FIG22(e), metal is electroplated on one side of the photoresist 153, for example, sequentially forming different metal layers 151e of copper, nickel, and tin stacked in sequence, to form metal bumps 151. As shown in FIG22(f), the metal seed layer 151f outside the photoresist 153 and the metal bumps 151 is removed, resulting in a frame 15 having a connection layer 152 and a plurality of metal bumps 151.

[0183] The preparation method of the double-sided packaged chip of this embodiment does not limit the process flow sequence. The first surface 11a or the second surface 11b of the substrate 11 can be processed first, which is convenient for first making the difficult-to-process side of the substrate 11, such as setting small-pitch metal bumps 151, mounting large-sized electronic components, etc., making chip production more flexible.

[0184] In some embodiments, referring to FIG. 23 , a method for preparing a double-sided packaged chip includes:

[0185] Step 210 , as shown in FIG8 ( a ), disposing a first electronic component 12 on the first surface 11 a of the substrate 11 ;

[0186] Step 220 , as shown in FIG8 ( b ), a frame 15 is provided on the first surface 11 a ;

[0187] Step 230 , as shown in (c) to (e) of FIG8 , a first encapsulation layer 14 is provided on the first surface 11 a , and the first encapsulation layer 14 is ground and thinned;

[0188] Step 240 , as shown in (a) and (b) of FIG. 24 , disposing a second electronic component 13 on the second surface 11 b of the substrate 11 ;

[0189] Step 250 , as shown in FIG. 24 ( c ), a second encapsulation layer 16 is provided on the second surface 11 b .

[0190] In this embodiment, the first surface 11a of the substrate 11 is processed first, followed by the second surface 11b. After the first encapsulation layer 14 is disposed on the first surface 11a of the substrate 11 and then ground and thinned, the end surface 14a of the first encapsulation layer 14, away from the substrate 11, forms a support surface, facilitating the placement of the second electronic component 13 and the second encapsulation layer 16 on the second surface 11b of the substrate 11.

[0191] In some embodiments, referring to FIG. 25 , a method for preparing a double-sided packaged chip includes:

[0192] Step 310 , as shown in (a) and (b) of FIG. 26 , a second electronic component 13 is provided on the second surface 11 b of the substrate 11 ;

[0193] Step 320 , as shown in FIG. 26 ( c ), providing a second encapsulation layer 16 on the second surface 11 b ;

[0194] Step 330 , as shown in FIG. 27 ( a ), disposing a first electronic component 12 on the first surface 11 a of the substrate 11 ;

[0195] Step 340: As shown in FIG. 27( b ), a first frame 15 is provided on the first surface 11 a .

[0196] Step 350 , as shown in (c) to (e) of FIG. 27 , a first encapsulation layer 14 is provided on the first surface 11 a , and the first encapsulation layer 14 is ground and thinned;

[0197] In this embodiment, the second surface 11b of the substrate 11 is processed first, followed by the first surface 11a. After the second electronic component 13 and the second packaging layer 16 are disposed on the second surface 11b of the substrate 11, the second packaging layer 16 forms a support surface away from the end surface 16a of the substrate 11, facilitating the placement of the first electronic component 12 and the first packaging layer 14 on the first surface 11a of the substrate 11.

[0198] It should be noted that the above embodiments of the double-sided packaged chip 10 are applicable to the preparation method of the double-sided packaged chip 10 of the embodiment of the present application and will not be described in detail.

[0199] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A double-sided encapsulated chip, characterized in that, Comprising: a substrate, a first electronic component, a second electronic component, and a first encapsulation layer; the substrate has a first surface and a second surface disposed opposite to each other, and a plurality of metal bumps are provided on the first surface; the first electronic component is disposed on the first surface; the second electronic component is disposed on the second surface; the first encapsulation layer at least partially wraps the first electronic component and the first surface, the thicknesses of the plurality of metal bumps are less than the maximum thickness of the first encapsulation layer, and the end faces of the plurality of metal bumps away from the substrate are exposed to the first encapsulation layer.

2. The dual-sided encapsulated chip according to claim 1, wherein a connection layer is provided on a side of the first encapsulation layer away from the substrate, and the end face of the connection layer away from the substrate and the end face of the metal bump away from the substrate are spaced apart.

3. The dual-sided encapsulated chip according to claim 2, wherein the materials of the metal bump and the connection layer are different, the material of the metal bump is metal or metal alloy, and the material of the connection layer is a flexible non-metallic material.

4. The dual-sided encapsulated chip according to any one of claims 1 to 3, characterized in that, the cross-sectional areas and / or cross-sectional shapes of at least two of the metal bumps are different; and / or, the cross-sectional shapes of the plurality of metal bumps include one or more of a rectangle, a circle, and an ellipse; and / or, the cross-sectional shape of the metal bump at at least one end position is a rectangle with chamfers; and / or, the spacing range between the end face of the metal bump away from the substrate and the end face of the first encapsulation layer is 5 micrometers to 10 micrometers.

5. The dual-sided encapsulated chip according to any one of claims 1 to 4, characterized in that, further comprising a second encapsulation layer, the second encapsulation layer at least partially wraps the second electronic component and the second surface.

6. The dual-sided encapsulated chip according to any one of claims 1 to 5, wherein the plurality of metal bumps include a first bump and a second bump, the cross-sectional area of the first bump is smaller than the cross-sectional area of the second bump, the first bump is electrically connected to the substrate; there is a mounting hole corresponding to at least one of the second electronic components on the substrate, and a heat conducting portion is provided in the mounting hole, and the second bump is connected to the heat conducting portion.

7. An electronic device, characterized in that, Comprising a circuit structure and a dual-sided encapsulated chip according to any one of claims 1 to 6, wherein the plurality of metal bumps in the dual-sided encapsulated chip are connected to the circuit structure.

8. A method for preparing a double-sided encapsulated chip, characterized in that Comprising: providing a frame, the frame includes a connection layer and a plurality of metal bumps connected to the same side of the connection layer, and the material of the connection layer includes a flexible non-metallic material; disposing a first electronic component on a first surface of a substrate; disposing the frame on the first surface such that the plurality of metal bumps are connected to the first surface; disposing a first encapsulation layer on the first surface, the first encapsulation layer wrapping the first electronic component; grinding and thinning the first encapsulation layer to expose the end faces of the plurality of metal bumps away from the substrate to the first encapsulation layer; disposing a second electronic component on a second surface of the substrate.

9. The manufacturing method of the dual-sided encapsulated chip according to claim 8, characterized in that, The step of disposing a first encapsulation layer on the first surface, the first encapsulation layer wrapping the first electronic component, specifically includes: removing the connection layer, and disposing a first encapsulation layer on the first surface, the first encapsulation layer wrapping the first electronic component and the plurality of metal bumps; Or, a first encapsulation layer is provided on the first surface, and the first encapsulation layer wraps the first electronic component, specifically including: providing a first encapsulation layer on the first surface, and the first encapsulation layer wraps the first electronic component and the frame.

10. The manufacturing method of the double-sided encapsulated chip according to claim 9, characterized in that, In the case of providing the first encapsulation layer on the first surface after removing the connection layer, laser grooving or etching grooving is performed on a partial area of the first encapsulation layer corresponding to the metal bumps, so that the end faces of the plurality of metal bumps away from the substrate are exposed to the first encapsulation layer; Or, in the case where the first encapsulation layer wraps the first electronic component and the frame, laser grooving or etching grooving is performed on a partial area of the connection layer corresponding to the metal bumps, so that the end faces of the plurality of metal bumps away from the substrate are exposed to the first encapsulation layer.

11. The method for preparing a double-sided encapsulated chip according to any one of claims 8 to 10, characterized in that, The plurality of substrates are arranged in a straight line and connected in sequence, the plurality of frames are arranged in a straight line and connected in sequence, and the plurality of frames are correspondingly arranged on the plurality of substrates by using surface mount technology; Or, the plurality of substrates are connected in an array arrangement, the plurality of frames are connected in an array arrangement, and the plurality of frames are correspondingly arranged on the plurality of substrates by using surface mount technology.

12. The preparation method of the double-sided encapsulated chip according to any one of claims 8 to 11, characterized in that, There is a first hollow position on the connection layer corresponding to the first electronic component; And / or, there is a second hollow position on the connection layer corresponding to the area between two adjacent metal bumps; And / or, the step of arranging the frame on the first surface so that the plurality of metal bumps are connected to the first surface specifically includes: using a rigid fixture with elasticity to clamp the substrate and the frame along the thickness direction of the substrate; The frame is arranged on the substrate by using surface mount technology so that the plurality of metal bumps are connected to the first surface.

13. The manufacturing method of the double-sided encapsulated chip according to any one of claims 8 to 12, characterized in that, The step of providing the frame specifically includes: fabricating a metal layer on the connection layer; etching the metal layer to obtain a plurality of metal bumps; Or, the step of providing the frame specifically includes: fabricating a metal seed layer on the connection layer; providing a photoresist on the metal seed layer; performing exposure and development to remove a part of the photoresist corresponding to the metal bumps, forming a filling groove on the photoresist; electroplating in the filling groove to form the metal bumps; removing the photoresist and removing the metal seed layer in the area other than the metal bumps.

14. The manufacturing method of the dual-sided encapsulated chip according to any one of claims 8 to 13, characterized in that, First, a first electronic component and a frame are provided on the first surface of the substrate, a first encapsulation layer is provided on the first surface, and the first encapsulation layer is ground and thinned; then, a second electronic component is provided on the second surface of the substrate, and a second encapsulation layer is provided on the second surface; Or, first, a second electronic component is provided on the second surface of the substrate, and a second encapsulation layer is provided on the second surface; Then, a first electronic component and a frame are provided on the first surface of the substrate, a first encapsulation layer is provided on the first surface, and the first encapsulation layer is ground and thinned.

15. The method for preparing a double-sided encapsulated chip according to any one of claims 8 to 14, characterized in that, The cross-sectional areas and / or cross-sectional shapes of at least two of the metal bumps are different; And / or, the cross-sectional shapes of the plurality of metal bumps include one or more of a rectangle, a circle, and an ellipse; And / or, the cross-sectional shape of the metal bump at at least one end position is a rectangle with chamfers; And / or, the spacing range between the end face of the metal bump away from the substrate and the end face of the first encapsulation layer is 5 micrometers to 10 micrometers; And / or, the plurality of metal bumps include a first bump and a second bump, the cross-sectional area of the first bump is smaller than the cross-sectional area of the second bump, and the first bump is electrically connected to the substrate; there are mounting holes corresponding to at least one of the second electronic components on the substrate, and a heat conduction part is arranged in the mounting holes, and the second bump is connected to the heat conduction part.

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