Power semiconductor element and power conversion device including same

Abstract

A power semiconductor element and a power conversion device including same, according to an embodiment, comprise: a substrate; a first conductivity-type epitaxial layer disposed on the substrate; a second conductivity-type well disposed on the first conductivity-type epitaxial layer; a first conductivity-type source region disposed on the second conductivity-type well; a trench formed by removing a portion of the first conductivity-type source region and a portion of the second conductivity-type well; a high dielectric constant layer disposed to have a predetermined height from the bottom of the trench; a trench gate disposed on the high dielectric constant layer in the trench; and a gate insulating layer surrounding the trench gate and disposed on a sidewall of the trench, wherein the dielectric constant of the high dielectric constant layer may be greater than the dielectric constant of the trench gate.

Description

Power semiconductor devices and power conversion devices including the same

[0001] The present invention relates to a power semiconductor device and a power conversion device including the same.

[0002] Power semiconductors are one of the key elements that determine the efficiency, speed, durability, and reliability of power electronics systems.

[0003] With the recent development of the power electronics industry, research is actively being conducted on WBG (Wide Bandgap) power semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) to replace the existing silicon (Si) power semiconductors that have reached their physical limits.

[0004] WBG power semiconductor devices have a bandgap energy approximately three times that of Si power semiconductor devices, resulting in lower intrinsic carrier concentration, higher breakdown field (approximately 4 to 20 times), higher thermal conductivity (approximately 3 to 13 times), and larger electron saturation velocity (approximately 2 to 2.5 times).

[0005] These characteristics enable operation in high-temperature, high-voltage environments, high switching speeds, and low switching losses. Among these, gallium nitride (GaN) power semiconductor devices can be used in low-voltage systems, while silicon carbide (SiC) power semiconductor devices are suitable for high-voltage systems.

[0006]

[0007] According to the structure, conventional SiC MOSFETs can be classified into MOSFETs with a trench structure, MOSFETs with a vertical doubly implanted structure (DIMOSFET), or MOSFETs with a lateral diffused structure.

[0008]

[0009] Among these, the Trench MOSFET is a structure in which a channel is formed on the trench sidewall, and for this purpose, a gate insulating film is formed on the trench sidewall and a gate electrode is formed in the trench.

[0010]

[0011] SiC MOSFETs have high on-resistance due to low channel mobility and large channel resistance. To reduce this, trench MOSFETs were proposed. Trench MOSFETs have the advantage of increasing channel density by forming a channel on the trench sidewalls.

[0012] However, trench MOSFETs have a problem in that a very large electric field is applied to both ends of the trench gate oxide, and in particular, the electric field is concentrated at the trench edge, so the gate oxide breakdown occurs quickly, resulting in a decrease in insulation breakdown or BV (Breakdown voltage).

[0013] For example, in the case of SiC Trench MOSFETs, the breakdown field strength is 10 times that of silicon (Si), so SiC semiconductor devices are used with a voltage nearly 10 times that of Si devices. Because of this, the gate insulating film formed within the trench is also subjected to an electric field 10 times that of a silicon device, which causes the gate insulating film to be easily destroyed at the corners and bottom of the trench.

[0014] One of the technical challenges of the embodiment is to prevent insulation breakdown and electric field concentration at the corners and bottom of the trench.

[0015] Additionally, one of the technical challenges of the embodiment is to reduce the cell pith of the power semiconductor device.

[0016] Additionally, one of the technical challenges of the embodiment is to improve the switching speed of the power semiconductor device.

[0017] Additionally, one of the technical challenges of the embodiment is to improve the ruggedness of power semiconductor devices.

[0018] Additionally, one of the technical challenges of the embodiment is to simplify the manufacturing process of power semiconductor devices.

[0019] The technical problems of the embodiment are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0020] A power semiconductor device according to an embodiment and a power conversion device including the same include: a substrate; an epi layer of a first conductivity type disposed on the substrate; a well of a second conductivity type disposed on the epi layer of the first conductivity type; a source region of the first conductivity type disposed on the well of the second conductivity type; a trench in which a portion of the source region of the first conductivity type and the well of the second conductivity type are removed; a high-k dielectric layer disposed to have a predetermined height from a bottom of the trench; a trench gate disposed on the high-k dielectric layer within the trench; and a gate insulating layer surrounding the trench gate and disposed on a sidewall of the trench, wherein a dielectric constant of the high-k dielectric layer may be greater than a dielectric constant of the trench gate.

[0021] Additionally, in the embodiment, the upper surface of the high-k dielectric layer may include a first region in contact with the trench gate and a second region in contact with the gate insulating layer.

[0022] Additionally, in the embodiment, the high-k dielectric layer may include any one of HfO2, TiO2, and Al2O3.

[0023] Additionally, in the embodiment, the upper surface of the high-k dielectric layer may be positioned lower than the lower surface of the second conductive well.

[0024] Additionally, in the embodiment, the trench gate includes a first trench gate and a second trench gate disposed below the first trench gate, and the second trench gate may be surrounded by the high-k layer.

[0025] Additionally, in an embodiment, the horizontal width of the second trench gate may be smaller than the horizontal width of the first trench gate.

[0026] Additionally, in an embodiment, the horizontal width of the second trench gate may be the same as the horizontal width of the first trench gate.

[0027] Additionally, in the embodiment, the vertical distance from the surface of the second trench gate to the inner wall of the trench may correspond to the horizontal distance from the surface of the second trench gate to the inner wall of the trench.

[0028] Additionally, in an embodiment, the horizontal width of the high-k dielectric layer may be greater than the horizontal width of the second trench gate.

[0029] A power semiconductor device according to an embodiment and a power conversion device including the same have a technical effect of preventing electric field concentration at a corner of a trench.

[0030] For example, embodiments may place a high-k material at the bottom of a trench to prevent electric field concentration at the trench corners and to enable the trench gate to withstand the electric field.

[0031] In addition, the embodiment has a technical effect that can reduce the cell pith of a power semiconductor device.

[0032] For example, the embodiment can reduce cell pitch by not having to consider margins by separate pn junctions because the high-k material prevents electric field concentration in the trench.

[0033] In addition, the embodiment has a technical effect of improving the switching speed of a power semiconductor device.

[0034] For example, embodiments may form a second trench gate within a high-k layer to control capacitance and thereby improve the switching speed of the device.

[0035] In addition, the embodiment has a technical effect that can improve the ruggedness of a power semiconductor device.

[0036] For example, the embodiment can improve the ruggedness of the device by forming a second trench gate within the high-k layer to control capacitance.

[0037] In addition, the embodiment has a technical effect that can simplify the manufacturing process of power semiconductor devices.

[0038] For example, the embodiment can simplify the manufacturing process because it does not require forming a separate pn junction around the trench and thus does not require an implant process.

[0039] The technical effects of the embodiments are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0040] Fig. 1 is an example diagram of the configuration of a power conversion device according to an embodiment.

[0041] Fig. 2 is a cross-sectional view of a power semiconductor device according to an embodiment.

[0042] Figure 3 is a cross-sectional view of a power semiconductor device being studied internally.

[0043] Fig. 4 is a cross-sectional view of a power semiconductor device according to the first embodiment.

[0044] Figures 5a to 5e are manufacturing process diagrams of a power semiconductor device according to the first embodiment.

[0045] Figures 6a and 6b are manufacturing process diagrams of a power semiconductor device according to the second embodiment.

[0046] Figure 7 is an enlarged view of area A in Figure 6b.

[0047] Hereinafter, an invention according to an embodiment for solving the above problem will be described in more detail with reference to the drawings.

[0048] The suffixes "module" and "part" used in the following description are given solely for the convenience of writing this specification and do not impart any particularly significant meaning or role to the components themselves. Therefore, the terms "module" and "part" may be used interchangeably.

[0049] Terms that include ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by these terms. These terms are used solely to distinguish one component from another.

[0050] Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0051] In this application, it should be understood that terms such as “include,” “have,” or “comprising” are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0052]

[0053] Figure 1 is an example diagram of the configuration of a power conversion device (1000) according to an embodiment.

[0054] A power conversion device (1000) according to an embodiment can receive DC power from a battery or a fuel cell, convert it into AC power, and supply AC power to a predetermined load. For example, the power conversion device (1000) according to an embodiment can include an inverter, and can receive DC power from a battery, convert it into three-phase AC power, and supply it to a motor (M), and the motor (M) can provide power to an electric vehicle, a fuel cell vehicle, etc.

[0055] A power conversion device (1000) according to an embodiment may include a power semiconductor device (100). The power semiconductor device (100) may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited thereto, and may include an IGBT (Insulated Gate Bipolar Transistor).

[0056] For example, the power conversion device (1000) may include a plurality of power semiconductor elements (100a, 100b, 100c, 100d, 100e, 100f) and may include a plurality of diodes (not shown). Each of the plurality of diodes may be embedded in the power semiconductor elements (100a, 100b, 100c, 100d, 100e, 100f) in the form of an internal diode, but is not limited thereto, and may be arranged separately.

[0057] The embodiment can convert DC power into AC power through on-off control for a plurality of power semiconductor elements (100a to 100f). For example, the power conversion device (1000) according to the embodiment can supply positive power to the motor (M) by turning on the first power semiconductor element (100a) and turning off the second power semiconductor element (100b) in a first time section of one cycle, and can supply negative power to the motor (M) by turning off the first power semiconductor element (100a) and turning on the second power semiconductor element (100b) in a second time section of one cycle.

[0058] In an embodiment, a group of power semiconductor devices arranged in series on the high-voltage line and the low-voltage line of the input side may be referred to as an arm. For example, a first power semiconductor device (100a) and a second power semiconductor device (100b) may constitute a first arm, a third power semiconductor device (100c) and a fourth power semiconductor device (100d) may constitute a second arm, and a fifth power semiconductor device (100e) and a sixth power semiconductor device (100f) may constitute a third arm.

[0059] In the above arm, the upper power semiconductor element and the lower power semiconductor element can be controlled so as not to be turned on simultaneously. For example, in the first arm, the first power semiconductor element (100a) and the second power semiconductor element (100b) can be turned on and off alternately without being turned on simultaneously.

[0060] Each power semiconductor element (100a to 100f) can receive a high voltage while in an off state. For example, when the second power semiconductor element (100b) is turned off while the first power semiconductor element (100a) is turned on, the input voltage can be applied as is to the second power semiconductor element (100b). The voltage input to the second power semiconductor element (100b) can be a relatively high voltage, and the withstand voltage of each power semiconductor element (100a to 100f) can be designed to be at a high level so as to withstand such a high voltage.

[0061] Each power semiconductor element (100a to 100f) can conduct a high current when turned on. The motor (M) is driven by a relatively high current, and this high current can be supplied to the motor (M) through the turned-on power semiconductor element.

[0062] A high voltage applied to each power semiconductor element (100a to 100f) may cause high switching loss. A high current flowing through the power semiconductor element (100a to 100f) may cause high conduction loss. To dissipate the heat generated by such loss, the power semiconductor elements (100a to 100f) may be packaged into a power semiconductor module including a heat dissipation means.

[0063] The power semiconductor device (100) of the embodiment may be a silicon carbide (SiC) power semiconductor device, and may be capable of operating in a high temperature, high voltage environment and may have a high switching speed and low switching loss.

[0064]

[0065] Meanwhile, the power conversion device (1000) according to the embodiment may include a plurality of power semiconductor modules.

[0066] For example, a plurality of power semiconductor devices (100a to 100f) illustrated in FIG. 1 may be packaged into one power semiconductor module, or the power semiconductor devices constituting each arm may be packaged into one power semiconductor module.

[0067] For example, the first power semiconductor element (100a), the second power semiconductor element (100b), the third power semiconductor element (100c), the fourth power semiconductor element (100d), the fifth power semiconductor element (100e), and the sixth power semiconductor element (100f) illustrated in FIG. 1 can be packaged into one power semiconductor module.

[0068] Additionally, to increase the current capacity, additional power semiconductor devices may be placed in parallel with each power semiconductor device (100a to 100f). In this case, the number of power semiconductor devices included in the power semiconductor module may exceed six.

[0069] The power conversion device (1000) according to the embodiment may include, in addition to the transistor-type power semiconductor elements (100a to 100f), a diode-type power semiconductor element. For example, a first diode (not shown) may be arranged in parallel with a first power semiconductor element (100a), and a second diode (not shown) may be arranged in parallel with a second power semiconductor element (100b). In addition, these diodes may also be packaged together in a single power semiconductor module. In addition, the diodes may be arranged in the form of internal diodes in each power semiconductor element.

[0070] Next, the power semiconductor devices that make up each arm can be packaged into a single power semiconductor module.

[0071] For example, the first power semiconductor element (100a) and the second power semiconductor element (100b) constituting the first arm may be packaged as a first power semiconductor module, the third power semiconductor element (100c) and the fourth power semiconductor element (100d) constituting the second arm may be packaged as a second power semiconductor module, and the fifth power semiconductor element (100e) and the sixth power semiconductor element (100f) constituting the third arm may be packaged as a third power semiconductor module.

[0072] In addition, in order to increase the current capacity, there may be additional power semiconductor elements arranged in parallel with each power semiconductor element (100a to 100f), in which case the number of power semiconductor elements included in each power semiconductor module may be more than two. In addition to the transistor-type power semiconductor elements (100a to 100f), each arm may also include a diode-type power semiconductor element (not shown), and these diodes may also be packaged together in one power semiconductor module. In addition, the diode may be arranged in the form of an internal diode in each power semiconductor element.

[0073]

[0074] Next, FIG. 2 is a cross-sectional view of one of the power semiconductor devices (100) according to the embodiment.

[0075] A power semiconductor device (100) according to an embodiment may include a source electrode (190), a gate electrode (175) disposed on an upper side of a predetermined semiconductor epi layer (120), and a drain electrode (105) disposed on a lower side of the semiconductor epi layer (120).

[0076] In the form of a MOSFET, the source electrode (190) or the gate electrode (175) may include an Al series metal, and the drain electrode (105) may include a Ti / Ni / Ag metal including a Ti layer, a Ni layer, and an Ag layer, or NiV / Ag, V(vanadium) / Ni / Ag, etc., but is not limited thereto.

[0077]

[0078] Figure 3 is a cross-sectional view of a power semiconductor device being studied internally.

[0079] The power semiconductor device of the internal technology may include at least one of a drain electrode (105), a substrate (111), an epi layer (113) of a first conductivity type, a well (121) of a second conductivity type, an ion implantation region (122) of a second conductivity type, a source region (123) of a first conductivity type, a source electrode (155), a source contact layer (153), a gate insulating layer (135), and an interlayer insulating layer (150).

[0080] Referring to FIG. 3, a power semiconductor device, which is a Trench MOSFET, may include a trench disposed between a source region (123) of a first conductivity type and an ion implantation region (121) of a second conductivity type, and a trench gate (132) may be disposed within the trench.

[0081] As the trench gate (132) is formed, a gate insulating layer (135) can be formed between the trench and the trench gate (132). SiO2 is mainly used as the gate insulating layer (135).

[0082]

[0083] Meanwhile, a strong electric field may be formed in the area in contact with the first conductive epi layer (113) at the lower end of the trench. In particular, the electric field is concentrated in the corner area (R) of the trench (130), which causes a problem in that the trench gate cannot operate normally.

[0084]

[0085] Accordingly, in order to block the strong electric field at the bottom of the trench, the internal technology indirectly protected the trench by forming a second well (108) of the second conductive type on both sides of the trench to form a separate pn junction.

[0086] However, the second well (108) of the second conductivity type is formed below the well (121) of the second conductivity type, and requires an ion implantation process. Since the second well (108) of the second conductivity type is formed deeper than the depth of the trench, a high-energy ion implantation process is required, which may cause damage to the power semiconductor device and significantly increases the difficulty of the process. In addition, since the second well (108) of the second conductivity type is formed in consideration of the distance from the trench, there is a problem that the cell pitch increases.

[0087]

[0088] Hereinafter, an embodiment for solving the above problem will be described.

[0089] Fig. 4 is a cross-sectional view showing a power semiconductor device according to the first embodiment.

[0090] Referring to FIG. 4, the power semiconductor device according to the first embodiment may include at least one of a drain electrode (105), a substrate (111), an epi layer (113) of a first conductivity type, a well (121) of a second conductivity type, an ion implantation region (122) of a second conductivity type, a source region (123) of a first conductivity type, a source electrode (155), a source contact layer (153), a gate insulating layer (135), and an interlayer insulating layer (150).

[0091] The first conductive type may be N-type, and the second conductive type may be P-type, but is not limited thereto. The substrate (111) and the epilayer (113) of the first conductive type may include SiC (Silicon Carbide), but are not limited thereto.

[0092] Specifically, a power semiconductor device (100) according to an embodiment includes a substrate (111), a first conductivity type epi layer (113) disposed on the substrate (111), a second conductivity type well (121) disposed on the first conductivity type epi layer (113), a second conductivity type ion implantation region (122) partially disposed on the second conductivity type well (121), and a first conductivity type source region (123), and may include a trench disposed between the first conductivity type source regions (123). The trench may extend between the second conductivity type wells (121) and may be positioned lower than the second conductivity type wells (121).

[0093] Additionally, a trench gate (132) and a gate insulating layer (135) may be placed within the trench (130). An interlayer insulating layer (150) may be placed on the trench gate (132), and a source region (155) may be placed to surround the interlayer insulating layer (150).

[0094]

[0095] Meanwhile, a high-k dielectric layer (140) may be disposed in a lower region of the trench (130). The high-k dielectric layer (140) may be disposed below the trench gate (132). The upper surface of the high-k dielectric layer (140) may include a first region in contact with the trench gate (132) and a second region in contact with the gate insulating layer (135). In addition, the high-k dielectric layer (140) may be in contact with the inner wall of the trench (130). The upper surface of the high-k dielectric layer (140) may be positioned lower than the lower surface of the second conductive type well (121), but is not limited thereto.

[0096] At this time, the permittivity of the high-k dielectric layer (140) may be greater than the permittivity of the trench gate (132). The high-k dielectric layer (140) may include a high-k material. The high-k dielectric layer (140) may include any one of HfO2, TiO2, and Al2O3, but is not limited thereto. In detail, the permittivity of the high-k dielectric layer (140) may be 9 or more. In addition, the permittivity of the high-k dielectric layer (140) may be 20 or more. In addition, the permittivity of the high-k dielectric layer (140) may be 40 or more.

[0097]

[0098]

[0099]

[0100] Meanwhile, if the permittivity of the lower portion of the trench increases according to Gauss's law in Equation 1 above, the electric field applied to the trench may decrease. Therefore, the embodiment has a technical effect of suppressing the electric field concentrated at the lower portion of the trench (130) by the high-k dielectric layer (140) formed at the lower portion of the trench (130). Accordingly, the embodiment has a technical effect of protecting the trench gate insulating film by preventing the electric field concentration at the lower portion of the trench by using a high-k material.

[0101] In addition, the embodiment does not require a separate pn junction because the trench gate (132) can withstand a high electric field on its own, so the implant process is unnecessary, which can significantly reduce the difficulty of the process. In addition, there is a technical effect that the resistance characteristics can be improved because a parasitic JFET region is not created. In addition, there is a special technical effect that the cell pitch can be reduced without considering the margin of a separate pn junction, thereby realizing miniaturization and high density of power semiconductors.

[0102]

[0103] This is a manufacturing process diagram of a power semiconductor device with reference to FIGS. 5A to 5E. First, referring to FIG. 5A, a first conductive type epi layer (113) may be formed on a substrate (111). The first conductive type epi layer (113) may include a first conductive type buffer layer (not shown) and a first conductive type drift layer (not shown). The substrate (111) and the first conductive type epi layer (113) may include, but are not limited to, SiC (Silicon Carbide).

[0104] In addition, the first challenge type epi layer (113) may include multiple layers having different concentrations and may have a current spreading layer (CSL) function.

[0105] Next, ions are implanted on the first conductive epi layer (113) to form a second conductive well (121). In addition, a first conductive source region (123) can be formed on the second conductive well (121). For example, the first conductive source region (123) may be formed by implanting about 1×10 N-type dopants such as nitrogen or phosphorus. 18 cm-3 to about 7×10 19 It can be formed by self-aligning ion implantation at a concentration of cm-3.

[0106] In addition, a second conductive type ion implantation region (122) can be formed in a part of the first conductive type source region (123) using an ion implantation mask. The second conductive type ion implantation region (122) can then contact the source electrode. In addition, the second conductive type ion implantation region (122) can have the function of maintaining the zero potential of the second conductive type well (121) and can function as a body diode.

[0107]

[0108] Next, referring to FIG. 5b, a trench (130) may be formed by partially removing a source region (123) of the first conductive type, a well (121) of the second conductive type, and an epi layer (113) of the first conductive type. The trench (130) may be formed deeper than the well (121) of the second conductive type.

[0109] Additionally, a drain electrode (105) may be formed under the substrate (111). The drain electrode (105) may include Ti / Al, but is not limited thereto.

[0110]

[0111] Next, referring to FIG. 5c, a high-k dielectric layer (140) can be deposited within the trench (130). The high-k dielectric layer (140) can have a predetermined height from the bottom surface of the trench (130). The height of the upper surface of the high-k dielectric layer (140) can correspond to the height of the bottom surface of the second conductive type well (121).

[0112] Meanwhile, the dielectric constant of the high-k dielectric layer (140) may be greater than the dielectric constant of the trench gate (132) to be formed later. The high-k dielectric layer (140) may include a high-k material. For example, the high-k dielectric layer (140) may include any one of HfO2, TiO2, and Al2O3, but is not limited thereto.

[0113]

[0114] Next, referring to FIG. 5d, a gate insulating layer (135) may be formed within the trench. Thereafter, a trench gate (132) may be formed on a high-k layer (140). The horizontal width of the trench gate (132) may be smaller than the horizontal width of the trench. A gate insulating layer (135) may be disposed on both sides of the trench gate (132). In addition, a source contact layer (153) may be formed on the ion implantation region (122) of the second conductivity type. The source contact layer (153) may then be connected to a source electrode. The source contact layer (153) may be in contact with the gate insulating layer (135).

[0115]

[0116] Next, referring to FIG. 5e, an interlayer insulating layer (150) may be formed on the trench gate (132) and the gate insulating layer (135). The interlayer insulating layer (150) may be formed of, but is not limited to, an oxide film or a nitride film. In addition, a source electrode (155) may be formed on the source contact layer (153). The source electrode (155) may be formed to cover the interlayer insulating layer (150). The source electrode (155) may be formed of, but is not limited to, Al. In addition, the source electrode (155) may further include a barrier metal layer.

[0117]

[0118] Figures 6a and 6b are drawings showing a process diagram of a power semiconductor device according to a second embodiment. First, referring to Figure 6a, a high-k dielectric layer (140) can be formed within a trench (130). The high-k dielectric layer (140) can include a high-k material. The high-k dielectric layer (140) can include any one of HfO2, TiO2, and Al2O3, but is not limited thereto.

[0119] The high-k dielectric layer (140) may be formed through a deposition process. The high-k dielectric layer (140) may be formed to have a predetermined height from the bottom surface of the trench (130). In addition, the upper surface of the high-k dielectric layer (140) may be formed lower than the lower surface of the second conductive type well (121). Meanwhile, a part of the high-k dielectric layer (140) may be etched to form a second trench (131). The second trench (131) may be surrounded by the high-k dielectric layer (140).

[0120]

[0121] Next, referring to FIG. 6b, a gate insulating layer (135) can be formed within the trench. Thereafter, a trench gate (132) can be formed within the trench.

[0122] The above trench gate (132) may include poly-si, but is not limited thereto.

[0123] The trench gate (132) may include a first trench gate (132a) formed within the trench and a second trench gate (132b) formed within the second trench. The second trench gate (132b) may be formed of the same material as the first trench gate (132a), but is not limited thereto. In addition, the permittivity of the high-k layer (140) may be greater than the permittivity of the trench gate (132).

[0124] Accordingly, the second embodiment has a technical effect of preventing insulation breakdown and electric field concentration at the corner and lower portion of the trench gate (132) as a high-k dielectric layer (140) having a higher dielectric constant than the gate insulating layer (135) is formed at the lower portion of the trench.

[0125] In addition, the embodiment does not require a separate pn junction because the trench gate (132) can withstand a high electric field on its own, so the implant process is unnecessary, which can significantly reduce the difficulty of the process. In addition, there is a technical effect that the resistance characteristics can be improved because a parasitic JFET region is not created. In addition, there is a special technical effect that the cell pitch can be reduced without considering the margin of a separate pn junction, thereby realizing miniaturization and high density of power semiconductors.

[0126]

[0127] Fig. 7 is a detailed drawing of area A in Fig. 6b. Referring to Fig. 7, a high-k layer (140) may be placed within a trench (130), and a trench gate (132) may be placed on the high-k layer (140). The upper surface of the high-k layer (140) may include a first region (140a) in contact with the trench gate (132) and a second region (140b) in contact with the gate insulating layer (135).

[0128] Meanwhile, the trench gate (132) may include a first trench gate (132a) disposed on the high-k dielectric layer (140) and a second trench gate (132b) disposed within the high-k dielectric layer (140).

[0129] The second trench gate (132b) may include the same material as the first trench gate (132a). In addition, the second trench gate (132b) may include a different material from the first trench gate (132a). In addition, the horizontal width of the second trench gate (132b) may be smaller than the horizontal width of the first trench gate (132a). In addition, the horizontal width of the second trench gate (132b) may be the same as the horizontal width of the first trench gate (132a). In addition, the horizontal width of the high-k layer (140) may be larger than the horizontal width of the second trench gate (132b). In addition, the horizontal width of the high-k layer (140) may be smaller than the horizontal width of the second trench gate (132b).

[0130] The second trench gate (132b) may have a predetermined distance from the inner wall of the trench. The area between the second trench gate (132b) and the inner wall of the trench may be considered as a capacitance region of the gate and drain.

[0131] In detail, the second trench gate (132b) may have a first separation distance (D1), a second separation distance (D2), and a third separation distance (D3) with respect to the inner wall of the trench. The second separation distance (D2) and the third separation distance (D3) may be the same. In addition, the first separation distance (D1) may be the same as the second separation distance (D2) and the third separation distance (D3). In addition, the first separation distance (D1) may be different from the second separation distance (D2) and the third separation distance (D3).

[0132] Meanwhile, the capacitance between the gate and the drain can be determined by the distance between the trench gate and the epi layer of the first conductivity type. Accordingly, the second embodiment can control the capacitance by forming a second trench gate (132b) having a smaller horizontal width than the first trench gate (132a). Meanwhile, in power semiconductor devices being studied internally, the switching speed and ruggedness have been studied as a trade-off relationship. Ruggedness is a characteristic indicating the reliability of a power device in high current and high voltage situations. On the other hand, the second embodiment has a special technical effect of simultaneously improving the switching speed and ruggedness characteristics by forming a second trench gate (132b) under the first trench gate (132a) and positioning a high-k layer (140) including a high-k material between the second trench gate (132b) and the epi layer of the first conductivity type.

[0133]

[0134] The power semiconductor device according to the embodiment and the power conversion device including the same have a technical effect of preventing insulation breakdown and electric field concentration at the corner and bottom of a trench.

[0135] For example, embodiments may place a high-k material at the bottom of a trench to prevent electric field concentration at the trench corners and to enable the trench gate to withstand the electric field.

[0136] In addition, the embodiment has a technical effect that can reduce the cell pith of a power semiconductor device.

[0137] For example, the embodiment can reduce cell pitch by not having to consider margins by separate pn junctions because the high-k material prevents electric field concentration in the trench.

[0138] In addition, the embodiment has a technical effect of improving the switching speed of a power semiconductor device.

[0139] For example, embodiments may form a second trench gate within a high-k layer to control capacitance and thereby improve the switching speed of the device.

[0140] In addition, the embodiment has a technical effect that can improve the ruggedness of a power semiconductor device.

[0141] For example, the embodiment can improve the ruggedness of the device by forming a second trench gate within the high-k layer to control capacitance.

[0142] In addition, the embodiment has a technical effect that can simplify the manufacturing process of power semiconductor devices.

[0143] For example, the embodiment can simplify the manufacturing process because it does not require forming a separate pn junction around the trench and thus does not require an implant process.

[0144]

[0145] Although the present invention has been described above with reference to embodiments thereof, it will be readily understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

[0146] The power semiconductor device according to the embodiment and the power conversion device including the same can be used in inverters or converters for computers, home appliances, automobiles, solar power, smart grids, etc. In addition, the power conversion device according to the embodiment can be applied to an automobile inverter for driving a motor. Here, the automobile includes a hybrid electric vehicle (HEV), a plug-in hybrid electric vehicle (PHEV), an electric vehicle (EV), a fuel cell electric vehicle (PCEV), etc.

Claims

1. Substrate; A first challenge type epi layer disposed on the above substrate; A second challenge type well disposed on the first challenge type epi layer; A source region of the first challenge type disposed on the well of the second challenge type; A trench in which a portion of the source region of the first challenge type and a portion of the well of the second challenge type are removed; A high-dielectric constant layer arranged to have a predetermined height from the bottom of the trench; A trench gate disposed on the high-k dielectric layer within the trench; and A gate insulating layer is disposed on the sidewall of the trench and surrounds the trench gate, A power semiconductor device, wherein the dielectric constant of the high-k dielectric layer is greater than the dielectric constant of the trench gate.

2. In paragraph 1, A power semiconductor device, wherein the upper surface of the high-k dielectric layer includes a first region in contact with the trench gate and a second region in contact with the gate insulating layer.

3. In paragraph 1, A power semiconductor device, wherein the high-k dielectric layer comprises one of HfO2, TiO2, and Al2O3.

4. In paragraph 1, A power semiconductor device, wherein the upper surface of the high-k dielectric layer is positioned lower than the lower surface of the second challenge type well.

5. In paragraph 1, A power semiconductor device, wherein the trench gate includes a first trench gate and a second trench gate disposed below the first trench gate, and at least a portion of the second trench gate is surrounded by the high-k dielectric layer.

6. In paragraph 5, A power semiconductor device, wherein the horizontal width of the second trench gate is smaller than the horizontal width of the first trench gate.

7. In paragraph 5, A power semiconductor device, wherein the horizontal width of the second trench gate is the same as the horizontal width of the first trench gate.

8. In paragraph 5, A power semiconductor device, wherein a vertical distance from the surface of the second trench gate to the inner wall of the trench corresponds to a horizontal distance from the surface of the second trench gate to the inner wall of the trench.

9. In paragraph 5, A power semiconductor device, wherein the horizontal width of the high-k dielectric layer is larger than the horizontal width of the second trench gate.

10. A power conversion device comprising a power semiconductor device according to any one of claims 1 to 9.

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