Analog signal processing circuit and method for high-precision ADC, chip and device

Abstract

The present disclosure relates to the technical field of integrated circuits, and in particular to an analog signal processing circuit and method for a high-precision ADC, a chip and a device. The circuit comprises: a main amplifier module, a main ADC module, an auxiliary amplifier module, an auxiliary ADC module and a first switch; the auxiliary ADC module is configured to convert a conditioned analog signal to be converted and output a converted first digital code by means of a digital output end; and the main ADC module is configured to establish the input voltage of the main ADC module to a target precision on the basis of said conditioned analog signal and the first digital code so as to sample the analog signal. According to the circuit, when the input voltage of the main ADC module changes greatly, the power consumption and the area overhead of the analog signal processing circuit are saved due to the power consumption and the area overhead of an auxiliary ADC and an auxiliary amplifier being very small while the main amplifier module is protected against rapid charging interference.

Description

Analog signal processing circuit, method, chip and device for high-precision ADC Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and in particular to an analog signal processing circuit, method, chip, and device for high-precision ADC. Background Art

[0002] An analog-to-digital converter (ADC) converts continuously varying analog signals into discrete digital signals and is used in various data acquisition systems. The charge-sharing successive approximation register (SAR) ADC is a commonly used ADC architecture for high-precision conversion. It boasts high conversion efficiency, a small footprint, and excellent real-time performance, making it widely used in industrial, measurement, and medical applications.

[0003] For traditional SAR ADCs, the analog signal to be converted must first pass through an amplifier to adjust the signal to an appropriate range and increase the signal's drive capability, thereby effectively driving the ADC's sampling circuit. However, during the charging process of the internal sampling capacitor, especially in multiplexed systems or discrete-time sampling conditions, large voltage steps are generated at the SAR ADC's input nodes. The instantaneous high current generated by the sampling capacitor charging and discharging can cause significant disturbances in the amplifier or input signal source. Increasing the amplifier's bandwidth to improve signal settling speed can also increase noise. To address this issue, a high-precision ADC input signal processing circuit in the related art is designed to form a unity-gain buffer by adding an auxiliary amplifier module and connecting the inverting input and output of the auxiliary amplifier module. Therefore, during the ADC sampling phase, the buffer can be used to quickly establish the ADC input voltage to a value close to the output voltage of the main amplifier module. Subsequently, when the output of the main amplifier module is directly connected to the input of the ADC, the ADC input voltage can be accurately established, so that the output voltage of the main amplifier module remains stable and is not affected by the rapid charging of the sampling capacitor. In addition, since there is no need to increase the bandwidth of the main amplifier module to improve the signal establishment speed, the noise introduced by the ADC analog signal processing circuit is reduced.

[0004] However, in the sampling phase of the above circuit, the pre-charging process of the sampling capacitor is completely completed by the pre-charging buffer. If the pre-charging time is to be shortened as much as possible, the amplifier serving as the pre-charging buffer needs to have a large slew rate and bandwidth. The amplifier itself will generate high power consumption and occupy a large area, resulting in high power consumption and area overhead of the circuit.

[0005] Summary of the Invention

[0006] In order to solve the problems in the related art, the embodiments of the present disclosure provide an analog signal processing circuit, method, chip and device for a high-precision ADC.

[0007] In a first aspect, an embodiment of the present disclosure provides an analog signal processing circuit for a high-precision ADC, the analog signal processing circuit comprising: a main amplifier module, a main ADC module, an auxiliary amplifier module, an auxiliary ADC module, and a first switch;

[0008] The input end of the auxiliary amplifier module is connected to the input signal end, and the output end is connected to the analog input end of the auxiliary ADC module. The auxiliary amplifier module is used to condition the analog signal to be converted input by the input signal end and output a first conditioned analog signal to be converted through the output end;

[0009] The digital output terminal of the auxiliary ADC module is connected to the digital input terminal of the main ADC module, and the auxiliary ADC module is used to convert the first conditioned analog signal to be converted and output the converted first digital code through the digital output terminal, wherein the first digital code includes information of the analog signal to be converted;

[0010] The input end of the main amplifier module is connected to the input signal end, and the output end is connected to the first terminal of the first switch. The main amplifier module is used to condition the analog signal to be converted input by the input signal end and output a second conditioned analog signal to be converted through the output end;

[0011] The analog input terminal of the main ADC module is connected to the second terminal of the first switch, and the main ADC module is used to establish the input voltage of the main ADC module to an input voltage that meets the target accuracy requirement based on the second conditioned analog signal to be converted received through the analog input terminal and the first digital code received through the digital input terminal, so as to achieve sampling of the analog signal at the input voltage;

[0012] The number of bits of the main ADC module is greater than the number of bits of the auxiliary ADC module.

[0013] In one implementation of the present disclosure, when the main ADC module is in a sampling phase and the first switch is in an off state, the main ADC module is configured to operate according to information of the analog signal to be converted contained in the first digital code to generate a sampling pre-charge voltage; wherein a difference between the sampling pre-charge voltage and a voltage at the output end of the main amplifier module is less than or equal to a preset error threshold.

[0014] In one implementation of the present disclosure, when the first switch is switched from an open state to a closed state, the main ADC module is configured to charge according to the second conditioned analog signal to be converted based on the sampled pre-charge voltage, so that the input voltage of the main ADC module is the same as the voltage at the output end of the main amplifier module.

[0015] In an implementation of the present disclosure, the main ADC module includes: a sampling capacitor array, a sampling switch array corresponding to the sampling capacitor array, a second switch, a comparator, and a control logic module;

[0016] The upper plates of each sampling capacitor in the sampling capacitor array are connected together and connected to the first terminal of the second switch and the inverting input terminal of the comparator, and the lower plates of each sampling capacitor are respectively connected to the first terminal of the corresponding sampling switch;

[0017] The second connection terminals of each sampling switch in the sampling switch array are connected together and connected to a first voltage input terminal, and the first voltage input terminal is connected to the second connection terminal of the first switch;

[0018] The third terminals of each sampling switch are connected together and connected to the second voltage input terminal; wherein the second voltage input terminal is used to input the first reference voltage;

[0019] The fourth terminals of each sampling switch are connected together and connected to the third voltage input terminal; wherein the third voltage input terminal is used to input a ground voltage;

[0020] The second connection terminal of the second switch is connected to the fourth voltage input terminal;

[0021] The positive input terminal of the comparator is connected to the fifth voltage input terminal, and the output terminal is connected to the first input terminal of the control logic module; wherein the fourth voltage input terminal and the fifth voltage input terminal are both used to input the second reference voltage;

[0022] The output end of the control logic module is connected to the sampling switch array, and the second input end is connected to the digital output end of the auxiliary ADC module; wherein the connection direction between the auxiliary ADC module and the control logic module is from the output end of the auxiliary ADC module to the second input end of the control logic module.

[0023] In one implementation of the present disclosure, the control logic module is configured to control the connectivity of the sampling switches in the sampling switch array according to the first digital code when the first switch is in an open state and the second switch is in a closed state, so that the logic states of M sampling capacitors in high positions in the sampling capacitor array are consistent with the first digital code, and then control the connectivity between the first terminal and the second terminal of each sampling switch so that the sampling capacitor array generates a sampling pre-charge voltage; wherein the value of M is the same as the number of bits in the first digital code, and M is a positive integer.

[0024] In one implementation of the present disclosure, when the first switch is switched from an open state to a closed state, the sampling capacitor array is configured to be charged based on the sampling pre-charge voltage according to the second conditioned analog signal to be converted, so that the voltage of the lower plate of the sampling capacitor array is established to be the same as the voltage of the output end of the main amplifier module.

[0025] In an implementation of the present disclosure, the sampling capacitor array is any one of the following: a single-ended capacitor array, a differential capacitor array.

[0026] In a second aspect, an embodiment of the present disclosure provides an analog signal processing circuit for a high-precision ADC, the analog signal processing circuit comprising: a main amplifier module, a third switch, a main ADC module, and an auxiliary ADC module;

[0027] The input end of the main amplifier module is connected to the input signal end, and the output end is connected to the first terminal of the third switch and the analog input end of the auxiliary ADC module. The main amplifier module is used to condition the analog signal to be converted input by the input signal end and output the conditioned analog signal to be converted through the output end;

[0028] The digital output terminal of the auxiliary ADC module is connected to the digital input terminal of the main ADC module, and the auxiliary ADC module is used to convert the conditioned analog signal to be converted and input the converted second digital code through the digital output terminal;

[0029] The analog input terminal of the main ADC module is connected to the second terminal of the third switch, and the main ADC module is used to establish the input voltage of the main ADC module to an input voltage that meets the target accuracy requirement based on the conditioned analog signal to be converted received through the analog input terminal and the second digital code received through the digital input terminal, so as to achieve sampling of the analog signal at the input voltage;

[0030] The number of bits of the main ADC module is greater than the number of bits of the auxiliary ADC module.

[0031] In a third aspect, an embodiment of the present disclosure provides an analog signal processing method for a high-precision ADC, which is applied to a circuit as described in any one of all implementations of the first aspect above, the method comprising:

[0032] When the main ADC module in the circuit is in a sampling phase, acquiring an analog signal to be converted;

[0033] Conditioning the analog signal to be converted by the main amplifier module and the auxiliary amplifier module in the circuit, converting the analog signal to be converted after being conditioned by the auxiliary amplifier module by the auxiliary ADC module in the circuit to obtain a conversion result, and sending the conversion result to the main ADC module;

[0034] According to the analog signal to be converted after conditioning by the main amplifier module and the conversion result, the input voltage of the main ADC module is established to an input voltage that meets the target accuracy requirement, so as to realize sampling of the analog signal at the input voltage.

[0035] In an implementation of the present disclosure, the step of establishing the input voltage of the main ADC module to an input voltage that meets target accuracy requirements based on the analog signal to be converted conditioned by the main amplifier module and the conversion result, so as to sample the analog signal at the input voltage, includes:

[0036] When a first switch located between the main ADC module and the main amplifier module is in an off state, the logic states of M sampling capacitors in high positions in the main ADC module are adjusted to be consistent with the conversion result according to the conversion result, and then the lower plates of all sampling capacitors in the main ADC module are short-circuited to generate a sampling pre-charge voltage; wherein the difference between the sampling pre-charge voltage and the voltage at the output end of the main amplifier module is less than or equal to a preset error threshold; and the value of M is the same as the number of bits of the conversion result, and M is a positive integer;

[0037] Switching the first switch to a closed state;

[0038] The sampling capacitor in the main ADC module is charged according to the analog signal to be converted after conditioning by the main amplifier module, so that the input voltage of the main ADC module is established from the sampling pre-charge voltage to the same voltage as the output end of the main amplifier module.

[0039] In a fourth aspect, an embodiment of the present disclosure provides an analog signal processing method for a high-precision ADC, which is applied to a circuit as described in any one of all implementations of the second aspect above, the method comprising:

[0040] When the main ADC module in the circuit is in a sampling phase, acquiring an analog signal to be converted;

[0041] Conditioning the analog signal to be converted by a main amplifier module in the circuit, converting the conditioned analog signal to be converted by an auxiliary ADC module in the circuit to obtain a conversion result, and sending the conversion result to the main ADC module;

[0042] According to the conditioned analog signal to be converted and the conversion result, the input voltage of the main ADC module is established to an input voltage that meets the target accuracy requirement, so as to achieve sampling of the analog signal at the input voltage.

[0043] In a fifth aspect, an embodiment of the present disclosure provides a chip comprising a circuit as in any one of all implementations of the first and second aspects above.

[0044] In a sixth aspect, an embodiment of the present disclosure provides an electronic device comprising the chip as described in the fifth aspect.

[0045] According to an embodiment of the present disclosure, an analog signal processing circuit for a high-precision ADC is provided. The circuit includes: a main amplifier module, a main ADC module, an auxiliary amplifier module, an auxiliary ADC module, and a first switch. This circuit structure forms two parallel signal chains. The first switch can be controlled to disconnect and rapidly convert the analog signal through the auxiliary amplifier module and auxiliary ADC module chain to obtain a digital signal. This digital signal is then transmitted to the main ADC module, enabling rapid pre-charging within the main ADC module to generate a sampled pre-charge voltage. The first switch is then controlled to conduct to accurately establish the input voltage of the main ADC module based on the pre-charge. Thus, this circuit protects the main amplifier module from rapid charging interference when the input voltage of the main ADC module experiences large swings. Compared to conventional circuits where the amplifier acting as a pre-charge buffer requires a higher slew rate and bandwidth, the circuit provided by the embodiment of the present disclosure has a low number of auxiliary ADC bits, resulting in low power consumption and area overhead. This also reduces the load provided to the auxiliary amplifier, allowing the auxiliary amplifier to achieve high-speed design while operating at low current, thereby saving circuit power consumption and area overhead.

[0046] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0048] FIG1 shows one of schematic diagrams of an analog signal processing circuit for a high-precision ADC according to an embodiment of the present disclosure;

[0049] FIG2 shows a second schematic diagram of an analog signal processing circuit for a high-precision ADC according to an embodiment of the present disclosure;

[0050] FIG3 shows a third schematic diagram of an analog signal processing circuit for a high-precision ADC according to an embodiment of the present disclosure;

[0051] FIG4 shows a fourth schematic diagram of an analog signal processing circuit for a high-precision ADC according to an embodiment of the present disclosure;

[0052] FIG5 shows a fifth schematic diagram of an analog signal processing circuit for a high-precision ADC according to an embodiment of the present disclosure;

[0053] FIG6 shows a sixth schematic diagram of an analog signal processing circuit for a high-precision ADC according to an embodiment of the present disclosure;

[0054] FIG7 shows a flowchart of an analog signal processing method for a high-precision ADC according to an embodiment of the present disclosure;

[0055] FIG8 shows a flowchart of yet another analog signal processing method for a high-precision ADC according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0057] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, actions, components, parts, or combinations thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof exist or are added.

[0058] It should also be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0059] In this disclosure, if it involves operations of obtaining user information or user data or displaying user information or user data to others, such operations are all authorized and confirmed by the user, or actively selected by the user.

[0060] As mentioned above, an analog-to-digital converter (ADC) is a device that converts continuously varying analog signals into discrete digital signals and is used in various data acquisition systems. Among them, the charge-sharing successive approximation register (SAR) ADC is a commonly used ADC architecture for achieving high-precision conversions. It features high conversion efficiency, a small footprint, and excellent real-time performance, making it widely used in industrial, measurement, and medical fields.

[0061] For traditional SAR ADCs, the analog signal to be converted must first pass through an amplifier to adjust the signal to an appropriate range to increase the signal's drive capability, thereby effectively driving the ADC's sampling circuit. However, during the charging process of the internal sampling capacitor, especially in multiplexed systems or discrete-time sampling conditions, large voltage steps are generated at the SAR ADC's input nodes. The instantaneous high current generated by the sampling capacitor charging and discharging can cause significant disturbances in the amplifier or input signal source. Increasing the amplifier's bandwidth to improve signal settling speed can also increase noise. To address this issue, a high-precision ADC input signal processing circuit in the related art is designed to form a unity-gain buffer by adding an auxiliary amplifier module and connecting the inverting input and output of the auxiliary amplifier module. During the ADC sampling phase, the buffer can be used to quickly establish the ADC input voltage close to the output voltage of the main amplifier module. Subsequently, when the output of the main amplifier module is directly connected to the input of the ADC, the ADC input voltage can be accurately established, so that the output voltage of the main amplifier module remains stable and is not disturbed by the charging of the sampling capacitor. In addition, since there is no need to increase the bandwidth of the main amplifier module to improve the signal establishment speed, the noise introduced by the ADC analog signal processing circuit is reduced.

[0062] However, in the sampling phase of the above circuit, the pre-charging process of the sampling capacitor is completely completed by the pre-charging buffer. If the pre-charging time is to be shortened as much as possible, the amplifier serving as the pre-charging buffer needs to have a large slew rate and bandwidth. The amplifier itself will generate high power consumption and occupy a large area, resulting in high power consumption and area overhead of the circuit.

[0063] To address the aforementioned technical deficiencies, an analog signal processing circuit for a high-precision ADC is provided according to an embodiment of the present disclosure. The circuit comprises: a main amplifier module, a main ADC module, an auxiliary amplifier module, an auxiliary ADC module, and a first switch. This circuit structure forms two parallel signal chains. The first switch can be controlled to disconnect, and the analog signal can be rapidly converted through the auxiliary amplifier module and auxiliary ADC module chain to obtain a digital signal. This digital signal is then transmitted to the main ADC module, enabling rapid pre-charging within the main ADC module to generate a sampled pre-charge voltage. The first switch is then controlled to conduct, accurately establishing the input voltage of the main ADC module based on the pre-charge. Thus, this circuit protects the main amplifier module from rapid charging interference when the input voltage of the main ADC module experiences large swings. Compared to conventional circuits where the amplifier acting as a pre-charge buffer requires a higher slew rate and bandwidth, the circuit provided by the embodiment of the present disclosure has a low number of auxiliary ADC bits, resulting in low power consumption and area overhead. This also reduces the load provided to the auxiliary amplifier, allowing the auxiliary amplifier to achieve high-speed design while operating at low current, thereby saving circuit power consumption and area overhead.

[0064] Figure 1 shows an analog signal processing circuit for a high-precision ADC according to an embodiment of the present disclosure. As shown in Figure 1, the analog signal processing circuit includes a main amplifier module 100, a main ADC module 200, an auxiliary amplifier module 300, an auxiliary ADC module 400, and a first switch 500;

[0065] The input terminal L1 of the auxiliary amplifier module 300 is connected to the input signal terminal L2, and the output terminal L3 is connected to the analog input terminal L4 of the auxiliary ADC module. The auxiliary amplifier module 300 is used to condition the analog signal to be converted inputted from the input signal terminal and output a first conditioned analog signal to be converted through the output terminal L3.

[0066] The digital output terminal L5 of the auxiliary ADC module 400 is connected to the digital input terminal L6 of the main ADC module. The auxiliary ADC module 400 is used to convert the conditioned analog signal to be converted and output a first digital code after conversion through the digital output terminal L5, wherein the first digital code includes information of the analog signal to be converted;

[0067] The input terminal L7 of the main amplifier module 100 is connected to the input signal terminal L2, and the output terminal L8 is connected to the first connection terminal L9 of the first switch 500. The main amplifier module 100 is used to condition the analog signal to be converted input by the input signal terminal L2 and output a second conditioned analog signal to be converted through the output terminal L8;

[0068] The analog input terminal L of the main ADC module 200 10 connected to the second terminal L of the first switch 11 The main ADC module 200 is used to generate an analog input signal according to the analog input terminal L 10 The received second conditioned analog signal to be converted and the first digital code received through the digital input terminal L6 establish the input voltage of the main ADC module 200 to an input voltage that meets the target accuracy requirement, so as to implement sampling of the analog signal at the input voltage;

[0069] The number of bits of the main ADC module 100 is greater than the number of bits of the auxiliary ADC module 400 .

[0070] In one embodiment of the present disclosure, each ADC module includes a sampling phase and a conversion phase. This embodiment only involves the sampling phase and conversion phase of the auxiliary ADC module and the sampling phase of the main ADC module, and does not limit the conversion phase of the main ADC module.

[0071] In one embodiment of the present disclosure, the main amplifier module has a high-precision feature and has no limitation on bandwidth requirements.

[0072] In one embodiment of the present disclosure, the main ADC module is typically a charge-sharing successive approximation ADC with high precision. The number of bits of the main amplifier module is typically 14 to 20 bits, but is not limited to 14 to 20 bits.

[0073] In one embodiment of the present disclosure, the auxiliary amplifier module has the characteristics of high speed and low precision requirement, and the input range of the auxiliary amplifier module is consistent with the input range of the main amplifier module.

[0074] In one embodiment of the present disclosure, the auxiliary ADC module may be a successive approximation ADC, a flash ADC, or a pipeline ADC, etc., which has a smaller number of bits, that is, a relatively lower precision.

[0075] In one embodiment of the present disclosure, the first switch may be a transmission gate switch, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) switch, or the like.

[0076] In one embodiment of the present disclosure, the input signal terminal is connected to an external signal source for inputting an analog signal to be converted. The input signal terminal can be a single-ended input, a differential input, or a pseudo-differential input, which is not limited in this embodiment of the present application.

[0077] It should be understood that after the auxiliary amplifier conditions the analog signal to be converted, the resulting first conditioned analog signal to be converted matches the input range of the auxiliary ADC module, thereby being sufficient to drive the auxiliary ADC module to perform signal conversion. Similarly, the function of the main amplifier module is similar, and this embodiment of the present application will not be further described.

[0078] In one embodiment of the present disclosure, when the main ADC module is in a sampling phase and the first switch is in an off state, the main ADC module is configured to operate according to information of the analog signal to be converted contained in the first digital code to generate a sampling pre-charge voltage; wherein a difference between the sampling pre-charge voltage and a voltage at the output end of the main amplifier module is less than or equal to a preset error threshold.

[0079] In this embodiment, during the sampling phase of the main ADC module, when the first switch is turned off, the auxiliary amplifier module 300 drives the auxiliary ADC to convert the signal at its analog signal input terminal, generating a first digital code containing information about the analog signal to be converted. The number of bits in this first digital code is the same as that of the auxiliary ADC, and the first digital code is then transmitted to the main ADC module. In this process, due to the low precision and high speed of the auxiliary amplifier module and the auxiliary ADC module, a rough conversion of the input analog signal to be converted is performed in a very short time to obtain a conversion result.

[0080] After that, after the main ADC module receives the first digital code, the circuit inside the main ADC module operates according to the first digital code and charges the sampling capacitor inside it to generate a sampling pre-charge voltage. It should be noted that the difference between the sampling pre-charge voltage and the voltage at the output end of the main amplifier module is V fs / 2 m Within; among them, V fs is the analog signal input range of the main ADC module, and m is the number of bits of the first digital code. That is, the preset error threshold can be set to V fs / 2 m , or less than V fs / 2 m .

[0081] It should be noted that during the pre-charge voltage generation stage when the main ADC module samples, since the first switch is in the off state, it serves to isolate the main ADC module from the main amplifier module, thereby protecting the main amplifier module from interference from the fast charging process of the capacitor when the input voltage on the main ADC module undergoes a large swing.

[0082] In one embodiment of the present disclosure, when the first switch is switched from an open state to a closed state, the main ADC module is configured to be charged based on the sampled pre-charge voltage according to the second conditioned analog signal to be converted, so that the input voltage of the main ADC module is the same as the voltage at the output end of the main amplifier module.

[0083] In this embodiment, when the first switch is switched from an open state to a closed state, the main amplifier module begins charging the sampling capacitor in the main ADC module. Previously, the input voltage of the main ADC module has been established as a sampling pre-charge voltage. Therefore, based on the sampling pre-charge voltage, the input voltage of the main ADC module can be established to the same voltage as the output voltage of the main amplifier module. Finally, the sampling phase of the main ADC module ends.

[0084] In the above process, before the main amplifier module is directly connected to the main ADC module, the input voltage of the main ADC module, i.e., the sampling pre-charge voltage, is already very close to the voltage at the output of the main amplifier module. Therefore, when the input voltage of the main ADC module is established to a sufficient accuracy, no large voltage step will be generated at the output of the main amplifier module, thereby preventing the internal circuit of the high-precision amplifier from being disturbed by the capacitor charging process. Moreover, even if the bandwidth of the main amplifier module is small, it does not take a long time to establish the final input voltage of the main ADC module to a sufficient accuracy.

[0085] In this embodiment, since the auxiliary ADC module has a low number of bits, its own power consumption and area overhead are also small, and the load provided to the auxiliary amplifier module is also small. Therefore, when the load is small, the auxiliary amplifier module can achieve high-speed design with very small power consumption and area overhead.

[0086] In one embodiment of the present disclosure, if the conversion step of the auxiliary ADC module is started before the conversion of the main ADC module is completed, the time for the auxiliary amplifier module and the auxiliary ADC module to process the analog signal does not occupy the sampling time of the main ADC module, thereby further reducing the speed requirement of the auxiliary amplifier module.

[0087] According to an embodiment of the present disclosure, an analog signal processing circuit for a high-precision ADC is provided. The circuit includes: a main amplifier module, a main ADC module, an auxiliary amplifier module, an auxiliary ADC module, and a first switch. This circuit structure forms two parallel signal chains. The first switch can be controlled to disconnect and rapidly convert the analog signal through the auxiliary amplifier module and auxiliary ADC module chain to obtain a digital signal. This digital signal is then transmitted to the main ADC module, enabling rapid pre-charging within the main ADC module to generate a sampled pre-charge voltage. The first switch is then controlled to conduct to accurately establish the input voltage of the main ADC module based on the pre-charge. Thus, this circuit protects the main amplifier module from rapid charging interference when the input voltage of the main ADC module experiences large swings. Compared to conventional circuits where the amplifier acting as a pre-charge buffer requires a higher slew rate and bandwidth, the circuit provided by the embodiment of the present disclosure has a low number of auxiliary ADC bits, resulting in low power consumption and area overhead. This also reduces the load provided to the auxiliary amplifier, allowing the auxiliary amplifier to achieve high-speed design while operating at low current, thereby saving circuit power consumption and area overhead.

[0088] FIG2 shows a schematic diagram of another analog signal processing circuit for a high-precision ADC according to an embodiment of the present disclosure. The main ADC module 200 includes a sampling capacitor array 201, a sampling switch array 202 corresponding to the sampling capacitor array, a second switch 203, a comparator 204, and a control logic module 205.

[0089] The upper plates of each sampling capacitor in the sampling capacitor array are connected together and connected to the first terminal of the second switch 203 and the inverting input terminal of the comparator 204, and the lower plates of each sampling capacitor are respectively connected to the first terminal of the corresponding sampling switch;

[0090] The second terminals of each sampling switch in the sampling switch array are connected together and connected to the first voltage input terminal 111, and the first voltage input terminal 111 is connected to the second terminal L of the first switch. 11 ;

[0091] The third terminals of each sampling switch are connected together and connected to the second voltage input terminal 112; wherein the second voltage input terminal 112 is used to input the first reference voltage;

[0092] The fourth terminals of each sampling switch are connected together and connected to the third voltage input terminal 113; wherein the second voltage input terminal is used to input a ground voltage;

[0093] The second connection terminal of the second switch 203 is connected to the fourth voltage input terminal 114;

[0094] The positive input terminal of the comparator 204 is connected to the fifth voltage input terminal 115, and the output terminal is connected to the first input terminal L of the control logic module. 12 ; Wherein, the fourth voltage input terminal and the fifth voltage input terminal are both used to input a second reference voltage;

[0095] The output terminal L of the control logic module 205 13 Connected to the sampling switch array, the second input terminal L 14 Connected to the output terminal L5 of the auxiliary ADC module; wherein, the connection direction between the auxiliary ADC module and the control logic module is from the output terminal of the auxiliary ADC module to the second input terminal of the control logic module.

[0096] In one embodiment of the present disclosure, the number of sampling capacitors in the sampling capacitor array is equal to the number of sampling switches in the sampling switch array, i.e., each sampling capacitor corresponds to a sampling switch. The number of sampling capacitors in the sampling capacitor array determines the number of bits in the main ADC module. Schematic 2 above illustrates an 8-bit main ADC module and a 4-bit auxiliary ADC module, but in actual circuits, these numbers are not limited.

[0097] In one embodiment of the present disclosure, the sampling capacitor array may be a binary capacitor array, a segmented capacitor array, a binary capacitor array with redundancy, or a non-binary capacitor array.

[0098] In one embodiment of the present disclosure, the connection direction between the control logic module and the sampling switch array is from its output end to the sampling switch array, so the control logic module is used to control the opening and closing actions of the sampling switches in the sampling switch array.

[0099] In one embodiment of the present disclosure, the output of the control logic module can be connected to each sampling switch in the sampling switch array, and the connectivity of the sampling switches is controlled based on the output of the output of the control logic module. Of course, a controller can also be provided in the sampling switch array, which can be connected to the control logic module and used to control the connectivity of the sampling switches based on the output of the output of the control logic module. It should be noted that the above description is exemplary, and the specific connection between the output of the control logic module and the sampling switch array can be determined based on actual conditions, and this embodiment of the present disclosure is not limited to this.

[0100] Taking Figure 2 above as an example, the auxiliary ADC module has 4 bits and the main ADC module has 8 bits for exemplary description. As shown in Figure 2, the sampling capacitor array includes sampling capacitors 121, 122, 123, 124, 125, 126, 127, and 128, and the sampling switch array includes sampling switches 131, 132, 133, 134, 135, 136, 137, and 138. The capacitor array composed of sampling capacitors 121 to 128 is a binary capacitor array, that is, the capacitance of the high-order capacitor is twice the capacitance of the adjacent low-order capacitor. Sampling capacitor 121 is the highest-order capacitor, and its capacitance is 2 n-1 C u , the capacitance of sampling capacitors 122 to 128 are 2 n-2 C u , 2 n-3 C u , 2 n-4 C u , 2 n-5 C u , 2 n-6 C u , 2 n-7 C u , 2 n-8 C u ; Where n is the number of bits of the main ADC module, C u is the unit capacitance.

[0101] The upper plates of the sampling capacitors 121 to 128 are connected together and connected to the first terminal of the second switch and the inverting input terminal of the comparator. The lower plates of the sampling capacitors 121 to 128 are respectively connected to the first terminals of the corresponding sampling switches 131 to 138. The second terminals of the sampling switches 131 to 138 are connected together and connected to the first voltage input terminal 111. The first voltage input terminal 111 is connected to the second terminal of the second switch. The third terminals of the sampling switches 131 to 138 are connected together and connected to the second voltage input terminal 112. The first reference voltage input to the second voltage input terminal 112 is V REF The fourth terminals of the sampling switches 131 to 138 are connected together and connected to the third voltage input terminal 113. The ground voltage input to the third voltage input terminal is GND. The second terminal of the second switch is connected to the fourth voltage input terminal 114. The second reference voltage input to the fourth voltage input terminal 114 is V CM The positive input terminal of the comparator module is connected to the fifth voltage input terminal 115, and the output terminal 116 is connected to the first input terminal L of the control logic module 205 12 The second input terminal L of the control logic module 205 is connected; 14 Connect to the digital output of the auxiliary ADC module.

[0102] With reference to FIG. 2 , during the sampling phase of the main ADC, when the first switch is disconnected, the auxiliary amplifier module drives the auxiliary ADC module to convert the first conditioned analog signal to be converted, obtains a corresponding 4-bit digital code, i.e., the first digital code, and sends it to the second input terminal of the control logic module.

[0103] In one embodiment of the present disclosure, the control logic module is configured to control the connectivity of the sampling switches in the sampling switch array according to the first digital code when the first switch is in an open state and the second switch is in a closed state, so that the logic states of M sampling capacitors in high positions in the sampling capacitor array are consistent with the first digital code, and then control the connectivity between the first terminal and the second terminal of each sampling switch so that the sampling capacitor array generates a sampling pre-charge voltage; wherein the value of M is the same as the number of bits in the first digital code, and M is a positive integer.

[0104] Still taking FIG. 2 as an example, after the main ADC module receives the 4-bit first digital code, the second switch 203 is closed. At this time, the upper plates of the sampling capacitors 121 to 128 are connected to the voltage V CM , the connectivity states of the sampling switches 131 - 134 corresponding to the high-bit sampling capacitors are controlled according to the first digital code.

[0105] Specifically, if the highest bit of the first digital code is 1, the sampling switch 131 connected to the highest bit sampling capacitor 121 is connected to the voltage input terminal 112, so that the lower plate voltage of the sampling capacitor 121 is switched to the first reference voltage V REF If the most significant bit of the first digital code is 0, the sampling switch 131 connected to the most significant bit sampling capacitor 121 is connected to the voltage input terminal 113, thereby switching the voltage on the lower plate of the sampling capacitor 121 to the ground voltage GND. Thus, bits 2 through 4 of the first digital code correspond to the states of the sampling capacitors 122 through 124 and the sampling switches 132 through 134, respectively, and operations can be performed in the manner described above.

[0106] FIG3 shows another schematic diagram of an analog signal processing circuit for a high-precision ADC, specifically a schematic diagram of a different stage from that shown in FIG2. As shown in FIG3, if the first digital code is 1010, the lower plate voltage of the sampling capacitor 121 can be switched to the first reference voltage V REF , connect the sampling switch 132 connected to the sampling capacitor 122 to the voltage input terminal 113, and so on, until the logic state of the upper 4-bit sampling capacitor in the main ADC module is adjusted to be the same as the first digital code.

[0107] After the logic state of the upper 4-bit sampling capacitors in the main ADC module matches the first digital code, the sampling switches 131-138 are connected to the first voltage input terminal 111. Since the first switch is in the off state, the lower plates of the sampling capacitors 121-128 are short-circuited together, generating a sampling pre-charge voltage. At this time, the charge of the sampling capacitors does not change. According to the law of charge conservation, the following formula is obtained:

[0108] Among them, V precharge Indicates the sampling pre-charge voltage, C i is the i-th sampling capacitor in the main ADC module. In this embodiment, the sampling capacitors 121 to 128 are the n-th to (n-7)-th sampling capacitors of the main ADC (from high to low). i is the logic state of the sampling switch connected to the lower plate of the i-th sampling capacitor, D i =1 means the sampling switch is connected to V REF Connectivity, D i =0 means the sampling switch is connected to GND, D i The upper 4 bits are the conversion result of the auxiliary ADC module. i The remaining bits in C can maintain the status of the last conversion result of the main ADC module, or can be any value, which is not limited in the embodiment of the present disclosure; total is the total capacitance of the sampling capacitor array in the main ADC, and n is the number of sampling capacitors, which is 8 here. The total capacitance of the sampling capacitor array in the main ADC also satisfies the following relationship:

[0109] Combining the above formula (1) and formula (2), we get the following formula:

[0110] According to the principle that the main ADC is a successive approximation ADC, the voltage V at the output of the main amplifier module is charge It can be expressed as the following formula:

[0111] Among them, V res It is the difference between the voltage corresponding to the result of the SARADC completing the n-bit analog-to-digital conversion and the input analog voltage, and V res ≤V REF / 2 n .

[0112] Because D i The upper 4 bits are the conversion result of the auxiliary ADC module, which corresponds to the first digital code, so there is D n =D' n , D n-1 =D' n-1 , D n-2 =D'n-2 , D n-3 =D' n-3 Subtracting the above formula (4) from formula (3) yields the following formula:

[0113] In the embodiment of the present disclosure, C i =2 (n-i) C u , substituting it into the above formula (5), we can get the following: |V charge -V precharge |≤V REF 2 -4

[0114] In this way, after the lower-level boards of the sampling capacitors 121 to 128 are short-circuited, the sampling pre-charge voltage generated on the lower-level boards differs from the voltage at the output end of the main amplifier module by V REF / 2 4 That is, the sampled pre-charge voltage is close to the voltage at the output of the main amplifier module. Therefore, even if the bandwidth of the main amplifier is small, it does not take a long time to establish sufficient accuracy. At the same time, because the voltage swing at the output of the main amplifier is very small during the charging process, the output transistor of the amplifier can be maintained at a relatively stable operating point, avoiding the internal circuit of the high-precision amplifier being disturbed by the capacitor charging process and requiring additional establishment time to restore accuracy.

[0115] In one embodiment of the present disclosure, when the first switch is switched from an open state to a closed state, the sampling capacitor array is configured to be charged based on the sampling pre-charge voltage and in accordance with the second conditioned analog signal to be converted, so that the voltage of the lower plate of the sampling capacitor array is established to be the same as the voltage at the output end of the main amplifier module.

[0116] In conjunction with Figures 2 and 3 , Figure 4 illustrates another schematic diagram of an analog signal processing circuit for a high-precision ADC according to an embodiment of the present disclosure, specifically illustrating a different stage from that shown in Figures 2 and 3 . As shown in Figure 4 , when first switch 500 is closed, the second conditioned analog signal to be converted obtained by main amplifier module 100 charges sampling capacitors 121-128 in main ADC module 200, thereby establishing the voltage of the lower-stage board of the sampling capacitor array to be the same as the voltage at the output of the main amplifier module. This ensures that the final input voltage of the main ADC module reaches an input voltage that meets sufficient accuracy requirements.

[0117] In one embodiment of the present disclosure, the sampling capacitor array is any one of the following: a single-ended capacitor array, a differential capacitor array.

[0118] The above Figures 2-4 are exemplified by using the sampling capacitor array as a single-ended capacitor array. Figure 5 shows a schematic diagram of another analog signal processing circuit for a high-precision ADC provided by an embodiment of the present disclosure. As shown in Figure 5, when the sampling capacitor array is a differential capacitor array, the pre-charge information is transmitted to the control logic module in the main ADC module via the output digital signal of the auxiliary ADC module. The control logic module controls both capacitor arrays simultaneously, that is, the pre-charge process is implemented by the original circuit structure in the main ADC, and compared with the case of a single-ended capacitor array, there is no increase in the signal processing circuit overhead.

[0119] Compared with the traditional pre-charge buffer method used in the related art, when the sampling capacitor array is a differential capacitor array, the traditional pre-charge buffer method requires adding two buffer modules between the main amplifier and the main ADC. The pre-charging of the analog signal processing circuit provided in the embodiment of the present application is realized by the original circuit structure in the main ADC, and only requires a set of auxiliary amplifiers and auxiliary ADCs, that is, no additional devices are added. Therefore, the analog signal processing circuit provided in the embodiment of the present application has more significant power consumption and area advantages.

[0120] 6 shows a schematic diagram of another analog signal processing circuit for a high-precision ADC according to an embodiment of the present application. The analog signal processing circuit includes an amplifier module 101 , a third switch 102 , a main ADC module 103 , and an auxiliary ADC module 104 .

[0121] The input terminal S1 of the amplifier module 101 is connected to the input signal terminal 105, and the output terminal S2 is connected to the first terminal S3 of the third switch 102 and the analog input terminal S4 of the auxiliary ADC module. The amplifier module 101 is used to condition the analog signal to be converted input from the input signal terminal 105, and output the conditioned analog signal to be converted through the output terminal S2.

[0122] The digital output terminal S5 of the auxiliary ADC module 104 is connected to the digital input terminal S6 of the main ADC module. The auxiliary ADC module is used to convert the conditioned analog signal to be converted and output the converted second digital code through the digital output terminal S5.

[0123] The analog input terminal S7 of the main ADC module 103 is connected to the second terminal S8 of the third switch. The main ADC module is configured to establish an input voltage of the main ADC module to an input voltage that meets a target accuracy requirement based on the conditioned analog signal to be converted received through the analog input terminal S7 and the second digital code received through the digital input terminal S6, so as to sample the analog signal at the input voltage.

[0124] The number of bits of the main ADC module is greater than the number of bits of the auxiliary ADC module.

[0125] In one embodiment of the present disclosure, each ADC module includes a sampling phase and a conversion phase. This embodiment only involves the sampling phase and conversion phase of the auxiliary ADC module and the sampling phase of the main ADC module, and does not limit the conversion phase of the main ADC module.

[0126] In one embodiment of the present disclosure, the main amplifier module has a high-precision feature and has no limitation on bandwidth requirements.

[0127] In one embodiment of the present disclosure, the primary ADC module is typically a charge-sharing successive approximation ADC (SAR) with high precision. The primary amplifier module typically has a bit count of 14 to 20 bits, but is not limited to 14 to 20 bits. The auxiliary ADC module can be a SAR ADC, a flash ADC, or a pipeline ADC, etc., with fewer bits and, therefore, relatively lower precision. However, the analog input range of the auxiliary ADC module is the same as that of the primary ADC module.

[0128] In one embodiment of the present disclosure, the third switch may be a transmission gate switch, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) switch, or the like.

[0129] In one embodiment of the present disclosure, the input signal terminal is connected to an external signal source for inputting an analog signal to be converted. The input signal terminal can be a single-ended input, a differential input, or a pseudo-differential input, which is not limited in this embodiment of the present application.

[0130] In the circuit shown in FIG6 , the analog signal to be converted is conditioned by the main amplifier. The conditioned analog signal to be converted matches the input range of the main ADC module and the auxiliary ADC module, thereby being sufficient to drive the main ADC module and the auxiliary ADC module. That is, the circuit further saves area overhead by reusing the main amplifier module as the driver of the auxiliary ADC module.

[0131] In this embodiment, during the sampling phase of the main ADC module, when the third switch is disconnected, the main amplifier module drives the auxiliary ADC to convert the signal at its analog signal input terminal, generating a second digital code containing information about the analog signal to be converted. The second digital code has the same number of bits as the auxiliary ADC, and the second digital code is then transmitted to the main ADC module. In this process, due to the low precision and high speed of the auxiliary ADC module, a rough conversion of the input analog signal to be converted is performed in a very short time to obtain a conversion result.

[0132] After that, after the main ADC module receives the second digital code, the circuit inside the main ADC module operates according to the second digital code to generate a sampling pre-charge voltage. It should be noted that the difference between the sampling pre-charge voltage and the voltage at the output end of the main amplifier module is V fs / 2 m Within; among them, V fs is the analog signal input range of the main ADC module, and m is the number of bits of the second digital code. That is, the preset error threshold can be set to V fs / 2 m , or set it to be less than V fs / 2 m .

[0133] When the third switch is switched from an open state to a closed state, the main amplifier module begins charging the sampling capacitor in the main ADC module. The input voltage of the main ADC module has already been established as the sampling pre-charge voltage. Therefore, based on the sampling pre-charge voltage, the input voltage of the main ADC module can be set to the same voltage as the output voltage of the main amplifier module. Finally, the sampling phase of the main ADC module ends.

[0134] In the above process, before the main amplifier module is directly connected to the main ADC module, the input voltage of the main ADC module, i.e., the sampling pre-charge voltage, is already very close to the voltage at the output of the main amplifier module. Therefore, when the input voltage of the main ADC module is established to a sufficient accuracy, no large voltage step will be generated at the output of the main amplifier module, thereby preventing the internal circuit of the high-precision amplifier from being disturbed by the capacitor charging process. Moreover, even if the bandwidth of the main amplifier module is small, it does not take a long time to establish the final input voltage of the main ADC module to a sufficient accuracy.

[0135] In one embodiment of the present disclosure, the internal circuit of the main ADC module 103 and the working principle of the internal circuit can refer to the main ADC module 200 shown in FIG. 2 in the above embodiment, which will not be described in detail in this embodiment of the present disclosure.

[0136] According to an embodiment of the present disclosure, an analog signal processing circuit for a high-precision ADC is provided. The circuit includes a main amplifier module, a main ADC module, an auxiliary ADC module, and a third switch. This circuit structure forms two parallel signal chains. The third switch can be controlled to disconnect and rapidly convert the analog signal through the link between the main amplifier module and the auxiliary ADC module to obtain a digital signal. This digital signal is then transmitted to the main ADC module, enabling rapid pre-charging within the main ADC module to generate a sampled pre-charge voltage. The third switch is then controlled to conduct, accurately establishing the input voltage of the main ADC module based on the pre-charge. Thus, this circuit protects the main amplifier module from rapid charging interference when the input voltage of the main ADC module experiences large swings. Compared to conventional circuits where the amplifier acting as a pre-charge buffer requires a larger slew rate and bandwidth, the circuit provided by the embodiment of the present disclosure has a low number of auxiliary ADC bits, resulting in minimal power consumption and area overhead, thus saving circuit power consumption and area overhead.

[0137] In addition, compared with the related art, the analog signal processing circuit provided by the embodiment of the present disclosure may also have the following advantages:

[0138] (1) In the related art, a large current is generated during the process of quickly charging the ADC using a pre-charge buffer, which easily interferes with other analog signal lines on the layout routing, increasing the difficulty of layout design of the connection line between the pre-charge buffer and the ADC. However, the analog signal processing circuit provided by the embodiment of the present disclosure does not increase the complexity of the key analog signal routing in the layout because the pre-charge information of the analog signal is transmitted from the auxiliary ADC module to the main ADC module through the digital domain.

[0139] (2) The analog signal processing circuit provided by the embodiment of the present disclosure reduces the number of switches in the analog signal chain, thereby improving the impact of switch leakage current on ADC sampling accuracy under high temperature conditions.

[0140] FIG7 shows a flowchart of an analog signal processing method for a high-precision ADC provided by an embodiment of the present disclosure. The method is applied to the circuit shown in any of FIG1 to FIG5 , and the method includes the following steps S301 to S303:

[0141] In step S301, when the main ADC module in the circuit is in the sampling phase, an analog signal to be converted is obtained;

[0142] In step S302, the analog signal to be converted is conditioned by the main amplifier module and the auxiliary amplifier module in the circuit, and the analog signal to be converted after being conditioned by the auxiliary amplifier module is converted by the auxiliary ADC module in the circuit to obtain a conversion result, and the conversion result is sent to the main ADC module;

[0143] In step S303, based on the analog signal to be converted conditioned by the main amplifier module and the conversion result, the input voltage of the main ADC module is established to an input voltage that meets the target accuracy requirement, so as to achieve sampling of the analog signal at the input voltage.

[0144] In one embodiment of the present disclosure, the description of the circuit structure can refer to the detailed description in the above embodiment, and the present disclosure will not elaborate on this embodiment.

[0145] In one embodiment of the present disclosure, the conversion result can be understood as the first digital code.

[0146] In one embodiment of the present disclosure, the step of establishing the input voltage of the main ADC module to an input voltage that meets target accuracy requirements based on the analog signal to be converted conditioned by the main amplifier module and the conversion result, so as to implement sampling of the analog signal at the input voltage, includes:

[0147] When a first switch located between the main ADC module and the main amplifier module is in an off state, the logic states of M sampling capacitors in a high position in the main ADC module are adjusted to be consistent with the conversion result according to the conversion result, and then the lower plates of all the sampling capacitors in the main ADC module are short-circuited to generate a sampling pre-charge voltage; wherein the difference between the sampling pre-charge voltage and the voltage at the output end of the main amplifier module is less than or equal to a preset error threshold; and the value of M is the same as the number of bits of the conversion result, and M is a positive integer;

[0148] Switching the first switch to a closed state;

[0149] The sampling capacitor in the main ADC module is charged according to the analog signal to be converted after conditioning by the main amplifier module, so that the input voltage of the main ADC module is established from the sampling pre-charge voltage to the same voltage as the output end of the main amplifier module.

[0150] In this embodiment, during the sampling phase of the main ADC module, when the first switch between the main ADC module and the amplifier module is disconnected, the auxiliary amplifier module drives the auxiliary ADC to convert the signal at its analog signal input terminal, obtaining a conversion result. This conversion result contains information about the analog signal to be converted, and the number of bits of this conversion result is the same as that of the auxiliary ADC. This conversion result is then sent to the main ADC module. In this process, due to the low precision and high speed of the auxiliary ADC module, a rough conversion of the input analog signal to be converted is performed in a very short time to obtain the conversion result.

[0151] After that, after the main ADC module receives the conversion result, the circuit inside the main ADC module acts according to the conversion result and short-circuits the lower plates of all sampling capacitors in the main ADC module to generate a sampling pre-charge voltage. It should be noted that the difference between the sampling pre-charge voltage and the voltage at the output of the main amplifier module is V fs / 2 m Within; among them, V fs is the analog signal input range of the main ADC module, and m is the number of bits of the first digital code. That is, the preset error threshold can be set to V fs / 2 m , or less than V fs / 2 m .

[0152] When the first switch between the main ADC module and the amplifier module is switched from an open state to a closed state, the main amplifier module begins charging the sampling capacitor in the main ADC module. The input voltage of the main ADC module has already been established as the sampling pre-charge voltage. This allows the input voltage of the main ADC module to be equal to the voltage at the output of the main amplifier module based on the sampling pre-charge voltage. Finally, the sampling phase of the main ADC module ends.

[0153] In the above process, before the main amplifier module is directly connected to the main ADC module, the input voltage of the main ADC module, i.e., the sampling pre-charge voltage, is already very close to the voltage at the output of the main amplifier module. Therefore, when the input voltage of the main ADC module is established to a sufficient accuracy, no large voltage step will be generated at the output of the main amplifier module, thereby preventing the internal circuit of the high-precision amplifier from being disturbed by the capacitor charging process. Moreover, even if the bandwidth of the main amplifier module is small, it does not take a long time to establish the final input voltage of the main ADC module to an input voltage that meets the sufficient accuracy requirements.

[0154] According to the analog signal processing method for a high-precision ADC provided by the embodiments of the present disclosure, by controlling the disconnection of a switch, the analog signal is rapidly converted through a link between an amplifier module and an auxiliary ADC module to obtain a digital signal. This digital signal is then transmitted to the main ADC module, enabling rapid precharging within the main ADC module to generate a sampling precharge voltage. The switch is then controlled to conduct, accurately establishing the input voltage of the main ADC module based on the precharge. This protects the main amplifier module from rapid charging interference when the input voltage of the main ADC module experiences large swings. Furthermore, because the sampling precharge voltage is already very close to the output voltage of the main amplifier, the bandwidth requirements for the amplifier are relatively low. Furthermore, because the auxiliary ADC has a low number of bits, its own power consumption and area overhead are very low, and the load provided to the auxiliary amplifier is also relatively small. This allows the auxiliary amplifier to achieve a high-speed design while operating at a low current, thereby saving circuit power consumption and area overhead.

[0155] FIG8 shows a flowchart of another analog signal processing method for a high-precision ADC provided by an embodiment of the present disclosure. The method is applied to the circuit shown in FIG6 . The method includes the following steps S401 to S403:

[0156] In step S401, when the main ADC module in the circuit is in a sampling phase, an analog signal to be converted is obtained;

[0157] In step S402, the analog signal to be converted is conditioned by the main amplifier module in the circuit, and the conditioned analog signal to be converted is converted by the auxiliary ADC module in the circuit to obtain a conversion result, and the conversion result is sent to the main ADC module;

[0158] In step S403, the input voltage of the main ADC module is established to an input voltage that meets the target accuracy requirement according to the conditioned analog signal to be converted and the conversion result, so as to implement sampling of the analog signal at the input voltage.

[0159] In one embodiment of the present disclosure, the description of the circuit structure can refer to the detailed description in the above embodiment, and the present disclosure will not elaborate on this embodiment.

[0160] In one embodiment of the present disclosure, the conversion result can be understood as the second digital code.

[0161] In one embodiment of the present disclosure, establishing the input voltage of the main ADC module to an input voltage that meets target accuracy requirements based on the conditioned analog signal to be converted and the conversion result, so as to implement sampling of the analog signal at the input voltage, includes:

[0162] When a third switch located between the main ADC module and the main amplifier module is in an off state, the logic states of a plurality of sampling capacitors in a high position in the main ADC module are adjusted to be consistent with the conversion result according to the conversion result, and then the lower plates of all the sampling capacitors in the main ADC module are short-circuited to generate a sampling pre-charge voltage; wherein the difference between the sampling pre-charge voltage and the voltage at the output end of the main amplifier module is less than or equal to a preset error threshold, and the number of the plurality of sampling capacitors is the same as the number of bits of the conversion result;

[0163] Switching the third switch to a closed state;

[0164] The sampling capacitor in the main ADC module is charged according to the conditioned analog signal to be converted, so that the input voltage of the main ADC module is established from the sampling pre-charge voltage to the same voltage as the output end of the main amplifier module.

[0165] In this embodiment, during the sampling phase of the primary ADC module, when the third switch between the primary ADC module and the amplifier module is disconnected, the primary amplifier module drives the auxiliary ADC to convert the signal at its analog signal input terminal, obtaining a conversion result. This conversion result contains information about the analog signal to be converted, and the number of bits in this conversion result is the same as that of the auxiliary ADC. This conversion result is then transmitted to the primary ADC module. In this process, due to the low precision and high speed of the auxiliary ADC module, a rough conversion of the input analog signal to be converted is performed in a very short time to obtain the conversion result.

[0166] After that, after the main ADC module receives the conversion result, the circuit inside the main ADC module acts according to the conversion result and short-circuits the lower plates of all sampling capacitors in the main ADC module to generate a sampling pre-charge voltage. It should be noted that the difference between the sampling pre-charge voltage and the voltage at the output of the main amplifier module is V fs / 2 m Within; among them, V fs is the analog signal input range of the main ADC module, and m is the number of bits of the second digital code. That is, the preset error threshold can be set to V fs / 2 m , or set it to be less than V fs / 2 m .

[0167] When the third switch between the main ADC module and the amplifier module is switched from an open state to a closed state, the main amplifier module begins charging the sampling capacitor in the main ADC module. The input voltage of the main ADC module has already been established as the sampling pre-charge voltage. This allows the input voltage of the main ADC module to be equal to the voltage at the output of the main amplifier module based on the sampling pre-charge voltage. Finally, the sampling phase of the main ADC module ends.

[0168] In the above process, before the main amplifier module is directly connected to the main ADC module, the input voltage of the main ADC module, i.e., the sampling pre-charge voltage, is already very close to the voltage at the output of the main amplifier module. Therefore, when the input voltage of the main ADC module is established to a sufficient accuracy, no large voltage step will be generated at the output of the main amplifier module, thereby preventing the internal circuit of the high-precision amplifier from being disturbed by the capacitor charging process. Moreover, even if the bandwidth of the main amplifier module is small, it does not take a long time to establish the final input voltage of the main ADC module to a voltage that meets the sufficient accuracy requirements.

[0169] According to the analog signal processing method for a high-precision ADC provided by the embodiments of the present disclosure, by controlling the disconnection of a switch, the analog signal is rapidly converted through the link between the main amplifier module and the auxiliary ADC module to obtain a digital signal, and the digital signal is transmitted to the main ADC module, thereby achieving rapid pre-charging within the main ADC module to generate a sampled pre-charge voltage. The switch is then controlled to conduct, and the input voltage of the main ADC module is accurately established based on the pre-charge. In this way, when the input voltage of the main ADC module undergoes large swings, the main amplifier module is protected from rapid charging interference. Because the sampled pre-charge voltage is already very close to the output voltage of the main amplifier, the bandwidth requirements for the amplifier are relatively low. The auxiliary ADC has a low number of bits, and its own power consumption and area overhead are very low, thereby saving power consumption and area overhead of the circuit.

[0170] An embodiment of the present disclosure provides a chip including the analog signal processing circuit for high-precision ADC shown in any one of FIG. 1 to FIG. 6 in the above embodiment.

[0171] An embodiment of the present disclosure provides an electronic device, including a chip including an analog signal processing circuit for a high-precision ADC as described in the above embodiments.

[0172] The above description is merely a preferred embodiment of the present disclosure and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the invention herein is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the inventive concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this disclosure.

Claims

1. An analog signal processing circuit for a high-precision ADC, characterized in that, The analog signal processing circuit includes: a main amplifier module, a main ADC module, an auxiliary amplifier module, an auxiliary ADC module, and a first switch; The input end of the auxiliary amplifier module is connected to the input signal end, and the output end is connected to the analog input end of the auxiliary ADC module. The auxiliary amplifier module is used to condition the analog signal to be converted input from the input signal end and output a first conditioned analog signal to be converted through the output end; The digital output end of the auxiliary ADC module is connected to the digital input end of the main ADC module. The auxiliary ADC module is used to convert the first conditioned analog signal to be converted and output a converted first digital code through the digital output end, where the first digital code contains information of the analog signal to be converted; The input end of the main amplifier module is connected to the input signal end, and the output end is connected to the first terminal of the first switch. The main amplifier module is used to condition the analog signal to be converted input from the input signal end and output a second conditioned analog signal to be converted through the output end; The analog input end of the main ADC module is connected to the second terminal of the first switch. The main ADC module is used to establish the input voltage of the main ADC module to an input voltage meeting the target accuracy requirement according to the second conditioned analog signal received through the analog input end and the first digital code received through the digital input end, so as to sample the analog signal at the input voltage; Wherein, the number of bits of the main ADC module is greater than the number of bits of the auxiliary ADC module.

2. The circuit according to claim 1, wherein When the main ADC module is in the sampling stage and the first switch is in the off state, the main ADC module is used to act according to the information of the analog signal to be converted contained in the first digital code to generate a sampling pre-charge voltage; wherein, the difference between the sampling pre-charge voltage and the voltage at the output end of the main amplifier module is less than or equal to a preset error threshold.

3. The circuit according to claim 2, wherein When the first switch is switched from the off state to the on state, the main ADC module is used to charge based on the sampling pre-charge voltage according to the second conditioned analog signal to make the input voltage of the main ADC module the same as the voltage at the output end of the main amplifier module.

4. The circuit according to claim 1 or 2, characterized in that, The main ADC module includes: a sampling capacitor array, a sampling switch array corresponding to the sampling capacitor array, a second switch, a comparator, and a control logic module; Wherein, the upper plates of each sampling capacitor in the sampling capacitor array are connected together and connected to the first terminal of the second switch and the inverting input end of the comparator, and the lower plate of each sampling capacitor is respectively connected to the first terminal of the corresponding sampling switch; The second terminals of each sampling switch in the sampling switch array are connected together and connected to a first voltage input end, and the first voltage input end is connected to the second terminal of the first switch; The third terminals of each of the sampling switches are connected together and connected to the second voltage input terminal; wherein, the second voltage input terminal is used for inputting a first reference voltage; The fourth terminals of each of the sampling switches are connected together and connected to the third voltage input terminal; wherein, the third voltage input terminal is used for inputting a ground voltage; The second terminal of the second switch is connected to the fourth voltage input terminal; The positive input terminal of the comparator is connected to the fifth voltage input terminal, and the output terminal is connected to the first input terminal of the control logic module; wherein, both the fourth voltage input terminal and the fifth voltage input terminal are used for inputting a second reference voltage; The output terminal of the control logic module is connected to the sampling switch array, and the second input terminal is connected to the digital output terminal of the auxiliary ADC module; wherein, the connection direction between the auxiliary ADC module and the control logic module is from the output terminal of the auxiliary ADC module to the second input terminal of the control logic module.

5. The circuit according to claim 4, wherein The control logic module is configured to, when the first switch is in the open state and the second switch is in the closed state, control the connection states of the sampling switches in the sampling switch array according to the first digital code, so that the logical states of the M sampling capacitors at the high positions in the sampling capacitor array are consistent with the first digital code, and then control the connection of the first terminal and the second terminal of each sampling switch, so that the sampling capacitor array generates a sampling pre-charge voltage; wherein, the value of M is the same as the number of bits of the first digital code, and M is a positive integer.

6. The circuit according to claim 5, characterized in that, When the first switch is switched from the open state to the closed state, the sampling capacitor array is configured to charge based on the sampling pre-charge voltage according to the second conditioned analog signal to be converted, so that the voltage of the lower plate of the sampling capacitor array is established to be the same as the voltage of the output terminal of the main amplifier module.

7. The circuit according to claim 4, wherein The sampling capacitor array is any one of the following: a single-ended capacitor array, a differential capacitor array.

8. An analog signal processing circuit for a high-precision ADC, characterized in that, The analog signal processing circuit includes: a main amplifier module, a third switch, a main ADC module, and an auxiliary ADC module; The input terminal of the main amplifier module is connected to the input signal terminal, and the output terminal is connected to the first terminal of the third switch and the analog input terminal of the auxiliary ADC module. The main amplifier module is configured to condition the analog signal to be converted input from the input signal terminal and output the conditioned analog signal to be converted through the output terminal; The digital output terminal of the auxiliary ADC module is connected to the digital input terminal of the main ADC module. The auxiliary ADC module is configured to convert the conditioned analog signal to be converted and input the converted second digital code through the digital output terminal; The analog input terminal of the main ADC module is connected to the second terminal of the third switch. The main ADC module is configured to establish the input voltage of the main ADC module to an input voltage meeting the target accuracy requirement according to the conditioned analog signal to be converted received through the analog input terminal and the second digital code received through the digital input terminal, so as to realize sampling of the analog signal at the input voltage; Wherein, the number of bits of the main ADC module is greater than that of the auxiliary ADC module.

9. An analog signal processing method for a high-precision ADC, characterized in that, Applied to the circuit according to any one of claims 1 to 7, the method includes: When the main ADC module in the circuit is in the sampling stage, obtain the analog signal to be converted; Condition the analog signal to be converted through the main amplifier module and the auxiliary amplifier module in the circuit, and convert the analog signal to be converted conditioned by the auxiliary amplifier module through the auxiliary ADC module in the circuit to obtain a conversion result, and send the conversion result to the main ADC module; According to the analog signal to be converted conditioned by the main amplifier module and the conversion result, establish the input voltage of the main ADC module to an input voltage meeting the target accuracy requirement, so as to sample the analog signal at the input voltage.

10. The method according to claim 9, characterized in that, The step of establishing the input voltage of the main ADC module to an input voltage meeting the target accuracy requirement according to the analog signal to be converted conditioned by the main amplifier module and the conversion result, so as to sample the analog signal at the input voltage includes: When the first switch located between the main ADC module and the main amplifier module is in the off state, according to the conversion result, adjust the logical states of M sampling capacitors at the high bits in the main ADC module to be consistent with the conversion result, and then short-circuit the lower plates of all sampling capacitors in the main ADC module to generate a sampling pre-charging voltage; wherein, the difference between the sampling pre-charging voltage and the voltage at the output end of the main amplifier module is less than or equal to a preset error threshold; the value of M is the same as the number of bits of the conversion result, and M is a positive integer; Switch the first switch to the on state; Charge the sampling capacitors in the main ADC module according to the analog signal to be converted conditioned by the main amplifier module, so that the input voltage of the main ADC module starts from the sampling pre-charging voltage and is established to be the same as the voltage at the output end of the main amplifier module.

11. An analog signal processing method for a high-precision ADC, characterized in that, Applied to the circuit according to claim 8, the method includes: When the main ADC module in the circuit is in the sampling stage, obtain the analog signal to be converted; Condition the analog signal to be converted through the main amplifier module in the circuit, and convert the conditioned analog signal to be converted through the auxiliary ADC module in the circuit to obtain a conversion result, and send the conversion result to the main ADC module; According to the conditioned analog signal to be converted and the conversion result, establish the input voltage of the main ADC module to an input voltage meeting the target accuracy requirement, so as to sample the analog signal at the input voltage.

12. A chip, characterized in that, Including the analog signal processing circuit according to any one of claims 1 to 8.

13. An electronic device, characterized in that, Including the chip according to claim 12.

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