Semiconductor chip and semiconductor product

Abstract

Provided is a configuration for a semiconductor chip for chiplets, in which an inductor can be appropriately formed. An inductor (21) is formed in a wiring layer different from a wiring layer in which a plurality of bumps (13) are formed. The inductor (21), in a planar view, overlaps at least one of the plurality of bumps (13). This configuration makes it possible to appropriately form the inductor (21) without being restricted by the bump arrangement.

Description

Semiconductor chips and semiconductor products

[0001] The present disclosure relates to semiconductor chips for chiplets.

[0002] In recent years, a new technology called "chiplet" has been attracting attention in the field of semiconductor technology. Chiplet is a technology in which large-scale circuits that have previously been integrated onto a single semiconductor chip are individually divided into multiple small semiconductor chips, and these multiple semiconductor chips are connected via microbumps on a substrate called an "interposer," which is then mounted on a package substrate.

[0003] Furthermore, semiconductor products often have circuit configurations that include inductors, such as an LC-PLL (Phase Locked Loop) circuit that serves as a clock source.

[0004] Patent Document 1 discloses a configuration for a semiconductor integrated circuit used in a receiving device, which can reduce the area occupied by an inductor included in an equalizer that performs equalization processing.

[0005] JP 2023-45027 A

[0006] For example, in an LC-PLL circuit, high Q values ​​are required for inductors due to the demands for high speed and low jitter. Therefore, when forming an inductor on a semiconductor substrate, it is preferable to have fewer restrictions on its size and placement location. However, with regard to chiplets, prior art documents, including Patent Document 1, do not disclose any configuration for forming an inductor.

[0007] The present disclosure provides a configuration that allows appropriate formation of an inductor in a semiconductor chip for a chiplet.

[0008] A semiconductor chip for a chiplet according to a first aspect of the present disclosure comprises a semiconductor substrate, a first wiring layer provided on the semiconductor substrate and having a plurality of bumps formed thereon, and a second wiring layer provided between the semiconductor substrate and the first wiring layer and having an inductor formed thereon, wherein the inductor overlaps with at least one of the plurality of bumps in a planar view.

[0009] According to this aspect, in a semiconductor chip for chiplets, an inductor is formed in a second wiring layer separate from a first wiring layer on which a plurality of bumps are formed. The inductor overlaps at least one of the plurality of bumps in a plan view. This allows the inductor to be appropriately formed without being restricted by bump placement. For example, an inductor included in an LC-PLL circuit can be formed to have a large area and a high Q value.

[0010] According to the present disclosure, inductors can be appropriately formed for semiconductor chips for chiplets.

[0011] 1A is a cross-sectional view showing an example of the configuration of a semiconductor product according to an embodiment; 1B is a circuit function of the semiconductor product according to an embodiment; 1C is a circuit configuration example of a PLL circuit; 1D is a circuit configuration example of the dashed line portion of FIG. 3, (a) is an LCVCO, and (b) is an LCVCO having a transformer; 1E is an example of a layer structure in a semiconductor chip according to an embodiment; 1F is a plan view showing an example of the arrangement of microbumps, inductors, and capacitors in a semiconductor chip according to an embodiment; 1F is a first example of a shielding structure according to an embodiment; 1F is a second example of a shielding structure according to an embodiment; 1F is a third example of a shielding structure according to an embodiment; 1F is a fourth example of a shielding structure according to an embodiment; 1F is a fifth example of a shielding structure according to an embodiment; 1F is a sixth example of a shielding structure according to an embodiment;

[0012] Hereinafter, embodiments will be described with reference to the drawings. In this specification, the term "plan view" refers to a view of a semiconductor chip or the like from a direction perpendicular to the surface of the semiconductor chip.

[0013] 1 is a cross-sectional view showing an example of the configuration of a semiconductor product according to an embodiment. The semiconductor product shown in Fig. 1 is configured using a chiplet architecture. The semiconductor product shown in Fig. 1 includes a package substrate 1, an interposer 2 having a relay wiring structure, and semiconductor chips 11 and 12 that are semiconductor chips for chiplets.

[0014] A BGA (Ball Grid Array) 3, which is an example of an external connection terminal, is formed on the lower surface of the package substrate 1. A capacitor 4 is also formed on the same surface of the package substrate 1. An interposer 2 is disposed on the upper surface of the package substrate 1 via a plurality of microbumps 5.

[0015] The semiconductor chip 11 is connected to the upper surface of the interposer 2 in the drawing via a plurality of microbumps 13. The semiconductor chip 12 is connected to the upper surface of the interposer 2 in the drawing via a plurality of microbumps 14. The semiconductor chip 11 includes a transceiver circuit 15, and the semiconductor chip 12 includes a transceiver circuit 16. The transceiver circuits 15 and 16 transmit and receive signals via the interposer 2. The transceiver circuits 15 and 16 may be provided as IP macros.

[0016] 2 is a diagram showing an example of the circuit functions of the transmission / reception circuits 15 and 16. The circuit functions shown in Fig. 2 constitute a transmission / reception system based on the BoW (Bunch of Wires) standard. The BoW standard is a standard in which only the master chip has a clock source, and the slave chip receives the clock from the master chip.

[0017] The transmission / reception circuit 15 includes a PLL (Phase Locked Loop) circuit 17 that serves as a clock source. The transmission / reception circuit 15 transmits data and also transmits a clock using the clock generated by the PLL circuit 17. The transmission / reception circuit 16 uses the clock transmitted from the transmission / reception circuit 15 to restore the transmitted data, etc.

[0018] FIG. 3 shows a typical circuit configuration example of a PLL circuit. The PLL circuit shown in FIG. 3 is a so-called LC-PLL, and includes a phase comparator (PFD) 21, a charge pump (CP) 22, a low-pass filter (LPF) 23, a voltage-controlled oscillator (VCO) 24, and a frequency divider (DIV) 25. The phase comparator 21 outputs a pulse signal representing the phase difference between an input reference clock refclk and a clock obtained by dividing the output clock vcoclk. The charge pump 22 outputs a current corresponding to the detected phase difference. The low-pass filter 23 generates a control voltage Vtol from the output current of the charge pump 22, and the voltage-controlled oscillator 24 oscillates at a frequency corresponding to the control voltage Vtol to generate the output clock vcoclk.

[0019] 4A and 4B are diagrams showing examples of the circuit configuration of the dashed line portion A in FIG. 3, where (a) is an example of an LCVCO, and (b) is an example of an LCVCO having a transformer.

[0020] In the example of Figure 4(a), the LCVCO includes an LPF and a VCO. The LPF includes a capacitor and a resistor and generates a control voltage Vtol. The VCO has a circuit configuration in which a pair of MOM capacitors connected in series, a pair of variable capacitors connected in series whose capacitance changes according to the control voltage Vtol, an inductor, and a pair of cross-coupled inverters are connected in parallel, and generates differential output clocks (CK, CKX). The variable capacitors are formed, for example, by varactors.

[0021] In the example of Figure 4(b), the LCVCO includes an LPF and a VCO, and has a transformer. The LPF has the same circuit configuration as Figure 4(a). In addition to the circuit configuration of Figure 4(a), the VCO has a secondary inductor that forms a transformer and is paired with an inductor connected in parallel with a capacitor. The secondary inductor is configured so that it can be switched between a conductive state (on) and a non-conductive state (off) by a switch circuit, thereby allowing the transformer to be switched on and off.

[0022] Here, because LC-PLLs require high speed and low jitter, the inductors used in LCVCOs must have a high Q (Quality Factor) value, be large in size, and be formed with low-resistance wiring. For this reason, in a typical semiconductor chip, it is preferable to form the inductor on the top layer (e.g., an aluminum wiring layer) that has low resistance. However, in a chiplet architecture, multiple microbumps are formed on the top layer of the semiconductor chip. Therefore, in a semiconductor chip for chiplets, if an inductor is to be formed on the same top layer, the microbump arrangement places great restrictions on it, making it difficult to form an appropriate inductor.

[0023] That is, because microbumps are formed on the top layer of a semiconductor chip and are regularly arranged with a narrow pitch, there is little space on the top layer for freely forming inductors. Furthermore, if the inductor and microbumps are arranged closely together on the top layer, interference may occur, causing changes in inductance and noise. In this case, sufficient separation is required between the inductor and the microbumps to prevent degradation of the PLL characteristics. Furthermore, even if the inductor can be formed in the free space on the top layer, the layout of the PLL circuit is restricted by the inductor's placement. This may increase the area of ​​the PLL circuit and make implementation more difficult.

[0024] Therefore, in this embodiment, the inductor is formed in an intermediate layer (e.g., a copper wiring layer) rather than in the top layer of the semiconductor chip. The intermediate layer has a higher wiring resistance than the top layer. However, for example, in the case of a PLL circuit used in the BoW standard, there is no requirement for low long-term jitter, and the level of the requirement for low jitter is not very high, so the inductor used in the LCVCO does not need to have a very high Q value. For this reason, in a semiconductor chip for chiplets, even if the inductor is formed in the intermediate layer, the required characteristics, such as the Q value, can be obtained by appropriately selecting the intermediate layer to be formed and sizing the inductor appropriately.

[0025] FIG. 5 shows an example of the layer structure of a semiconductor chip 11 according to an embodiment. As shown in FIG. 5, in this embodiment, a microbump layer on which microbumps 13 are formed is located at the top. Below the microbump layer is an inductor layer on which an inductor included in an LC-PLL is formed. Furthermore, below the inductor layer is a MOM (Metal-Oxide-Metal) capacitor layer on which a capacitor is formed. In this embodiment, shield layers on which shield wiring is formed are provided above and below the inductor layer, and a power mesh layer on which a power mesh having mesh-shaped power wiring is formed is provided between the shield layer and the microbump layer. The power mesh is also formed in the same wiring layer as the inductor layer. Below the MOM capacitor layer, a transistor layer on which a group of transistors is formed is provided. The group of transistors is formed, for example, on a semiconductor substrate. Furthermore, in addition to the above-mentioned layers, a connection layer on which connection wiring is formed is provided. Connection wiring is also formed in each of the above-mentioned layers as needed. Note that each layer may be composed of a single wiring layer, or may be composed of multiple adjacent wiring layers.

[0026] Fig. 6 is a plan view showing an example of the arrangement of microbumps, inductors, and capacitors in a semiconductor chip 11 according to the embodiment. In the arrangement example of Fig. 6, microbumps 13 are regularly arranged in a 4 x 4 array in the microbump layer. In other words, four microbumps 13 arranged at the vertices of a substantially rectangular shape form one group, and these groups of microbumps are regularly arranged in a grid pattern.

[0027] Note that a microbump is, for example, a bump with a size of several tens of μm or less, particularly a bump with a size of several μm to several tens of μm. The bump size is, for example, the diameter of the sphere if the bump is approximately spherical, the diameter of the cylinder if the bump is approximately cylindrical, or the length of the long side, short side, or diagonal of the rectangle in plan view if the bump is approximately rectangular.

[0028] In the inductor layer, two inductors 21 are arranged. A part of the inductor 21 overlaps with the microbump 13 in a plan view.

[0029] With this arrangement, the inductor 21 can be freely and appropriately formed in terms of size and position without being restricted by the arrangement of the microbumps 13. Therefore, the required characteristics, such as the Q value, can be obtained for the inductor 21. Note that the size of the inductor refers to, for example, the outer diameter of the inductor, and in the case where the inductor is formed by spiral wiring, the outer diameter of the spiral.

[0030] The microbumps 13 each have a size Dim_B in plan view and are arranged at intervals Int_B. The inductor 21 has a size Dim_I in plan view. In this case, the relationship Dim_I < 2 × Dim_B + Int_B may be satisfied. That is, as shown in FIG. 6 , the inductor 21 may be formed to a size that fits within a space occupied by a group of four microbumps 13 arranged at the vertices of a substantially rectangular shape in plan view.

[0031] Furthermore, four capacitors 22 are arranged in the MOM capacitor layer. Part of the capacitors 22 overlaps with the microbumps 13 in plan view. Also, part of the capacitors 22 overlaps with the inductors 21 in plan view.

[0032] With this arrangement, the capacitor 22 can also be freely and appropriately formed in terms of size and position without being restricted by the arrangement of the microbumps 13 and the inductor 21. Note that the capacitor 22 does not have to overlap the microbumps 13 and the inductor 21 in plan view.

[0033] (Shielding Structure) When an inductor formed in an inductor layer has a structure that forms a current loop in the layers above and below it, or in the vicinity of it within the same layer, that inductor itself becomes an inductor, causing mutual induction between the inductor and a real inductor. This mutual inductance causes fluctuations in the characteristics of the real inductor. In order to avoid or suppress this fluctuation in characteristics, a shielding structure is formed in this embodiment. The shielding structure is composed of shielding wiring formed in shield layers provided above and below the inductor layer, shielding wiring formed in the inductor layer, etc.

[0034] In the following description, the horizontal direction of the plan view is the X direction, and the vertical direction of the plan view is the Y direction.

[0035] 7 shows a first example of a shielding structure according to an embodiment, in which (a) is a plan view showing an inductor layer and a shielding layer thereunder, (b) is a plan view showing an inductor layer and a shielding layer thereunder, and (c) is a cross-sectional view taken along line A-B in (a) and (b).

[0036] As shown in Fig. 7A, a pair of shielding wires 31 extending in the Y direction are formed in the layer below the inductor 21. The shielding wires 31 are connected to power supply wires 33 and 34 through vias 36 at two locations P1 and P2 that sandwich the inductor 21 in a plan view, and the potential is fixed. As shown in Fig. 7B, a pair of shielding wires 32 extending in the Y direction are formed in the layer above the inductor 21. The pair of shielding wires 32 are connected to power supply wires 33 and 34 through vias 37 at two locations P3 and P4 that sandwich the inductor 21 in a plan view, and the potential is fixed.

[0037] The pair of shield wirings 31 are connected at two points P1 and P2 to form a current loop. The pair of shield wirings 32 are connected at two points P3 and P4 to form a current loop. These current loops affect the characteristics of the inductor 21, so in order to suppress this effect, it is preferable that the connection points P1 to P4 be located as far away as possible from the inductor 21. For example, it is preferable that the distance between each of the connection points P1 to P4 and the inductor 21 is greater than the size Dim_I of the inductor.

[0038] 8 shows a second example of a shielding structure according to an embodiment, in which (a) is a plan view showing an inductor layer and a shielding layer thereunder, (b) is a plan view showing an inductor layer and a shielding layer thereunder, and (c) is a cross-sectional view taken along line A-B in (a) and (b).

[0039] As shown in Fig. 8(a), a pair of shielding wires 31 extending in the Y direction are formed in the layer below the inductor 21. However, each of the pair of shielding wires 31 is connected to the power supply wire 35 at only one point via a via 38, and the potential is fixed. As shown in Fig. 8(b), a pair of shielding wires 32 extending in the Y direction are formed in the layer above the inductor 21. However, each of the pair of shielding wires 32 is connected to the power supply wire 35 at only one point via a via 39, and the potential is fixed.

[0040] In the second example, unlike the first example, no current loop is formed by the shield wiring, and therefore there is no effect on the characteristics of the inductor 21.

[0041] 9 shows a third example of a shielding structure according to an embodiment, in which (a) is a plan view showing an inductor layer and a shielding layer thereunder, (b) is a plan view showing an inductor layer and a shielding layer thereunder, and (c) is a cross-sectional view taken along line A-B in (a) and (b).

[0042] As shown in Fig. 9A, a pair of shielding wires 31 extending in the Y direction is formed in the lower layer of the inductor 21. However, the potential of the pair of shielding wires 31 is not fixed and they are in a floating state. As shown in Fig. 9B, a pair of shielding wires 32 extending in the Y direction is formed in the upper layer of the inductor 21. However, the potential of the pair of shielding wires 32 is not fixed and they are in a floating state.

[0043] In the third example, unlike the first example, no current loop is formed by the shield wiring, and therefore there is no effect on the characteristics of the inductor 21.

[0044] In the first to third examples, the shield wiring is formed in both the lower and upper layers of the inductor 21, but this is not limiting, and for example, the shield wiring may be formed only in the lower layer of the inductor 21 or only in the upper layer of the inductor 21. Also, in the first to third examples, a pair of shield wiring is formed, but this is not limiting, and for example, a single shield wiring may be formed, or three or more shield wirings may be formed.

[0045] 10 shows a fourth example of a shielding structure according to an embodiment. In Fig. 10, (a) is a plan view showing an inductor layer and a shield layer thereunder, (b) is a plan view showing an inductor layer and a shield layer thereunder, (c) is a cross-sectional view taken along line A-B in (a) and (b), and (d) is a cross-sectional view taken along line C-D in (a) and (b).

[0046] 10( a) and 10(b), two shield wirings 41 and 42 are formed in the same wiring layer as the inductor 21 so as to surround both sides of the inductor 21 in the X direction and both sides of the inductor 21 in the Y direction. Both ends of the shield wirings 41 and 42 are connected via vias 46 to a shield wiring 43 formed in a lower shield layer, and both ends are connected via vias 47 to a shield wiring 44 formed in an upper shield layer. Here, the shield wirings 41 and 42 are formed, for example, by power supply wiring of a power supply mesh formed in the same inductor layer as the inductor 21. Therefore, the potentials of the shield wirings 41, 42, 43, and 44 are fixed.

[0047] 10 , a gap 61 is formed between the shield wiring 41 and the shield wiring 42. The gap 61 prevents a current loop from being formed by the portions of the shield wirings 41 and 42 that extend to surround both sides of the inductor 21 in the X direction and both sides in the Y direction.

[0048] In the fourth example, the gap 61 is formed in the shield wiring 41 and the shield wiring 42 in a portion that extends to surround both sides of the inductor 21 in the X direction, but the position where the gap 61 is formed is not limited to the form of the fourth example. The position where the gap 61 is formed may be any position that prevents the formation of a current loop, and for example, the gap 61 may be formed in the shield wiring 41 and the shield wiring 42 in a portion that extends to surround both sides of the inductor 21 in the Y direction.

[0049] Meanwhile, a current loop is formed by connecting both ends of the shield wirings 41 and 42 to the shield wirings 43 and 44. To suppress the influence of this current loop on the inductor characteristics, it is preferable that the shield wirings 43 and 44 be located as far away as possible from the inductor 21. For example, it is preferable that the distance between the shield wirings 43 and 44 and the inductor 21 in a plan view is greater than the size Dim_I of the inductor 21.

[0050] 11 shows a fifth example of a shielding structure according to an embodiment. In Fig. 11, (a) is a plan view showing an inductor layer and a shield layer thereunder, (b) is a plan view showing an inductor layer and a shield layer thereunder, (c) is a cross-sectional view taken along line A-B in (a) and (b), and (d) is a cross-sectional view taken along line C-D in (a) and (b).

[0051] 11A and 11B, a shield wiring 45 is formed in the same wiring layer as the inductor 21 so as to surround both sides in the X direction and both sides in the Y direction of the inductor 21. Both ends of the shield wiring 45 are connected via vias 48 to shield wiring 43 formed in the lower shield layer, and both ends are connected via vias 49 to shield wiring 44 formed in the upper shield layer. Here, as in the fourth example, the shield wiring 45 is formed, for example, by power supply wiring of a power supply mesh formed in the same inductor layer as the inductor 21. Therefore, the potentials of the shield wirings 43, 44, and 45 are fixed.

[0052] 11 , a gap 62 is formed in the shield wiring 45. The gap 62 prevents a current loop from being formed by a portion of the shield wiring 45 that extends to surround both sides in the X direction and both sides in the Y direction of the inductor 21. As in the fourth example, the position where the gap 62 is formed is not limited to the form of the fifth example, and may be any position that prevents the formation of a current loop.

[0053] In addition, in the fifth example, both ends of the shield wiring 45 are connected to the shield wirings 43 and 44, but unlike the fourth example, a current loop is not formed by the connection of the shield wirings, and therefore there is no effect on the characteristics of the inductor 21.

[0054] 12 shows a sixth example of a shielding structure according to an embodiment. In Fig. 12, (a) is a plan view showing an inductor layer and a shield layer thereunder, (b) is a plan view showing an inductor layer and a shield layer thereunder, (c) is a cross-sectional view taken along line A-B in (a) and (b), (d) is a cross-sectional view taken along line C-D in (a) and (b), and (e) is a cross-sectional view taken along line E-F in (a) and (b).

[0055] The sixth example actively utilizes the current loop formed by the shield wiring to form a transformer between the inductor 21, thereby changing the inductance value of the inductor 21 and making it possible to expand the oscillation range of the LC-VCO. In other words, the sixth example forms a transformer. The switching elements SW1 and SW2 are configured to be switchable between a conductive state (ON) and a non-conductive state (OFF). Here, the switching elements SW1 and SW2 are configured by transistors located below the inductor 21.

[0056] 12A, a pair of shield wirings 51 extending in the Y direction are formed in a layer below the inductor 21. Only one point of the pair of shield wirings 51 is connected to the power supply wiring 53 via a via 54, and the potential is fixed. The pair of shield wirings 51 are also connected to each other via a switching element SW1 and a connection wiring 56. The point connected to the power supply wiring 53 and the point connected via the switching element SW1 are located on either side of the inductor 21 in a plan view.

[0057] 12B, a pair of shield wirings 52 extending in the Y direction are formed on the layer above the inductor 21. Only one point of the pair of shield wirings 52 is connected to the power supply wiring 53 via a via 55, and the potential is fixed. The pair of shield wirings 52 are also connected to each other via a switching element SW2 and a connection wiring 57. The point connected to the power supply wiring 53 and the point connected via the switching element SW2 are located on either side of the inductor 21 in a plan view.

[0058] When switching element SW1 is on, the pair of shielding wires 51 are mutually conductive, forming a current loop 58 (shown as a dashed-dotted line in the figure). This forms a transformer between inductor 21 and the parasitic inductor generated by current loop 58, making it possible to change the inductance value of inductor 21. Furthermore, when switching element SW2 is on, the pair of shielding wires 52 are mutually conductive, forming a current loop 59 (shown as a dashed-dotted line in the figure). This forms a transformer between inductor 21 and the parasitic inductor generated by current loop 59, making it possible to change the inductance value of inductor 21.

[0059] The current loop 58 formed by the shield wiring 51 and the current loop 59 formed by the shield wiring 52 are different in size, and correspondingly, the inductance values ​​of the parasitic inductances generated by the current loops are also different between the current loops 58 and 59. Therefore, by changing the combination of the on and off states of the switching elements SW1 and SW2, the inductance value of the inductor 21 can be changed into multiple patterns.

[0060] The shielding structure of the sixth example may be applied to devices other than semiconductor chips for chiplets. This shielding structure can realize an inductor structure in which the inductance value of the inductor can be changed by turning on and off a switching element. For example, it can be used to realize an LCVCO with a transformer.

[0061] The present disclosure provides a configuration that allows appropriate formation of an inductor in a semiconductor chip for chiplets, and is therefore useful for, for example, miniaturizing semiconductor products.

[0062] REFERENCE SIGNS LIST 1 package substrate 2 interposer 11, 12 semiconductor chip 13, 14 microbumps 17 PLL circuit 21 inductor 22 capacitor 31, 32 shield wiring 41, 42, 43, 44, 45 shield wiring 51, 52 shield wiring SW1, SW2 switching element

Claims

1. A semiconductor chip for a chiplet, comprising: a semiconductor substrate; a first wiring layer provided on the semiconductor substrate and having a plurality of bumps formed thereon; and a second wiring layer provided between the semiconductor substrate and the first wiring layer and having an inductor formed therein, wherein the inductor overlaps at least one of the plurality of bumps in a plan view.

2. The semiconductor chip according to claim 1, wherein each of the plurality of bumps is a micro bump.

3. The semiconductor chip according to claim 1, wherein the plurality of bumps each have a size Dim_B and are arranged at an interval Int_B in a plan view, the inductor has a size Dim_I in a plan view, and the semiconductor chip satisfies the relationship Dim_I < 2 × Dim_B + Int_B.

4. The semiconductor chip according to claim 1, further comprising a third wiring layer provided between the semiconductor substrate and the second wiring layer or between the first wiring layer and the second wiring layer and having a capacitor formed therein, wherein the capacitor overlaps the inductor in a plan view.

5. The semiconductor chip according to claim 4, wherein the capacitor has a Metal-Oxide-Metal (MOM) structure.

6. The semiconductor chip according to claim 1, further comprising a first shield wiring arranged in a fourth wiring layer above or below the second wiring layer so as to overlap the inductor in a plan view.

7. The semiconductor chip according to claim 6, wherein the first shield wiring is a pair of shield wirings extending in a first direction.

8. The semiconductor chip according to claim 7, wherein the pair of shield wirings are connected to each other and fixed in potential at first and second positions in the first direction, and the first and second positions are located at positions sandwiching the inductor in a plan view.

9. The semiconductor chip according to claim 8, wherein the inductor has a size Dim_I in a plan view, and the first and second positions each have an interval from the inductor greater than Dim_I.

10. The semiconductor chip according to claim 7, wherein the pair of shield wirings are connected to each other only at one location in the first direction and are fixed in potential.

11. The semiconductor chip according to claim 7, wherein the pair of shield wirings are not connected to each other and are in a floating state.

12. The semiconductor chip according to claim 7, wherein the pair of shield wirings are connected to each other at a first location in the first direction and are fixed in potential, and at a second location in the first direction, are connected to each other via a switching element configured to be switchable between a conductive state and a non-conductive state, and the first and second locations are in positions sandwiching the inductor in a plan view.

13. The semiconductor chip according to claim 12, wherein the switching element is constituted by a transistor formed under the second wiring layer.

14. The semiconductor chip according to claim 1, comprising a second shield wiring formed in the second wiring layer so as to surround the inductor in a plan view.

15. The semiconductor chip according to claim 14, comprising a pair of shield wirings extending with the inductor sandwiched therebetween in a fourth wiring layer above or below the second wiring layer, and the second shield wiring is connected to the pair of shield wirings and is fixed in potential.

16. The semiconductor chip according to claim 15, wherein the inductor has a size Dim_I in a plan view, and each of the pair of shield wirings has a distance from the inductor greater than Dim_I in a plan view.

17. The semiconductor chip according to claim 1, comprising a PLL (Phase Locked Loop) circuit including an LC-VCO (Voltage Controlled Oscillator), and the inductor is used for the LC-VCO.

18. A semiconductor product composed of a chiplet architecture, comprising: a package substrate; an interposer having a relay wiring structure and connected to the surface of the package substrate; and a first semiconductor chip which is the semiconductor chip according to any one of claims 1 to 17, wherein the first semiconductor chip is connected to the surface of the interposer opposite to the package substrate via the plurality of bumps.

19. In the semiconductor product according to claim 18, further comprising a second semiconductor chip connected to the surface of the interposer opposite to the package substrate via a plurality of bumps, wherein the first semiconductor chip includes an LC-VCO (Voltage Controlled Oscillator) and a PLL (Phase Looked Loop) circuit for generating a clock signal, the inductor is used in the LC-VCO, and the second semiconductor chip receives the clock signal output from the first semiconductor chip.

20. A semiconductor chip, comprising: a semiconductor substrate; a first wiring layer provided on the semiconductor substrate and having an inductor formed thereon; and a pair of shield wirings provided in a second wiring layer above or below the first wiring layer, extending in a first direction and arranged to overlap the inductor in a plan view, wherein the pair of shield wirings are connected to each other at a first location in the first direction and are fixed in potential, and at a second location in the first direction, are connected to each other via a switching element configured to be switchable between a conductive state and a non-conductive state, and the first and second locations are located at positions sandwiching the inductor in a plan view.

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