Gilbert cell type multiplier

Abstract

The present invention comprises an output circuit in which a pair of load terminals are connected to a pair of output terminals in a main circuit. The output circuit comprises: a first load inductor having a first end connected to a power supply and a second end connected to one of the pair of load terminals; and a second load inductor having a first end connected to the power supply and a second end connected to the other of the pair of load terminals. The inductance of each of the first load inductor and the second load inductor is set so as to suppress the output of unnecessary waves to the outside.

Description

Gilbert cell multiplier

[0001] This application claims priority to Japanese Patent Application No. 2024-004852, filed on January 16, 2024, the contents of which are incorporated herein by reference.

[0002] Patent Document 1 discloses a Gilbert cell multiplier, which is a multiplier circuit (multiplication circuit) in the form of a circuit in which differential amplifier circuits are stacked vertically, and as shown in Figures 1 and 3, a balun is provided at the output section to suppress the output of harmonics other than those of the desired wavelength.

[0003] US Patent Application Publication No. 2023 / 0018212

[0004] However, the balun is a device that combines multiple coils and requires a relatively large mounting area, making it difficult to miniaturize the circuit in a conventional Gilbert cell multiplier.

[0005] The present invention has been made in view of the above circumstances, and has as its object to provide a Gilbert cell type multiplier that can be made smaller than conventional multipliers.

[0006] In order to achieve the above object, a first aspect of the Gilbert cell multiplier according to the present invention comprises an output circuit having a pair of load terminals connected to a pair of output terminals in a main circuit, the output circuit comprising: a first load inductor having a first end connected to a power supply and a second end connected to one of the pair of load terminals; and a second load inductor having a first end connected to the power supply and a second end connected to the other of the pair of load terminals, wherein the inductances of the first load inductor and the second load inductor are set so as to suppress the output of unwanted waves to the outside.

[0007] A second aspect of the Gilbert cell multiplier according to the present invention is the first aspect, wherein the output circuit includes a series resonant circuit between the pair of load terminals, and the resonant frequency of the series resonant circuit is set so as to suppress the output of the unwanted waves to the outside.

[0008] A third aspect of the Gilbert cell multiplier according to the present invention is the first or second aspect, wherein the first load inductor has a first auxiliary inductor, and the second load inductor has a second auxiliary inductor.

[0009] A fourth aspect of the Gilbert cell multiplier according to the present invention is the third aspect, wherein a first output resistor is connected in parallel to the first auxiliary inductor, and a second output resistor is connected in parallel to the second auxiliary inductor.

[0010] According to the present invention, it is possible to provide a Gilbert cell type multiplier that can be made smaller than conventional multipliers.

[0011] 1 is a circuit diagram showing the configuration of a Gilbert cell multiplier according to a first embodiment of the present invention; 2 is an equivalent circuit of a part of an output circuit according to the first embodiment of the present invention; 3 is a waveform diagram showing waveforms of each part of the Gilbert cell multiplier according to the first embodiment of the present invention; 4 is a characteristic diagram showing frequency characteristics of the output circuit according to the first embodiment of the present invention; and 5 is a circuit diagram showing the configuration of a Gilbert cell multiplier according to a second embodiment of the present invention.

[0012] Hereinafter, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] First, a first embodiment of the present invention will be described with reference to Figures 1 to 4. As shown in Figure 1, a Gilbert cell type multiplier A according to the first embodiment includes a main circuit B1 and an output circuit B2.

[0013] The main circuit B1 has a basic function of the Gilbert cell type multiplier A, i.e., a function of multiplying a signal frequency, and has a pair of output terminals Dp and Dn for outputting a pair of multiplied output signals to the outside. Of the pair of output terminals Dp and Dn, the output terminal Dp is a first output terminal and the output terminal Dn is a second output terminal.

[0014] This main circuit B1 receives a pair of phase-inverted signals (analog signals) input from the outside, and multiplies the pair of phase-inverted signals by a pair of phase-inverted local signals (analog signals) separately input from the outside, thereby generating a signal with an additive frequency component and a signal with a subtractive frequency component between the signal frequency of the pair of phase-inverted signals and the local frequency of the pair of phase-inverted local signals.

[0015] Here, of the signal of the addition frequency component and the signal of the subtraction frequency component, if the desired signal (desired wave) required for the Gilbert cell multiplier A is the signal of the addition frequency component, the signal of the subtraction frequency component is an unwanted signal (unwanted wave).On the other hand, if the frequency component required for the Gilbert cell multiplier A is the subtraction frequency, the signal of the addition frequency component is an unwanted signal (unwanted wave).

[0016] The output circuit B2 is provided corresponding to the pair of output terminals Dp, Dn in the main circuit B1 and includes a pair of load terminals Ep, En. Of the pair of load terminals Ep, En, the load terminal Ep is a first load terminal and is connected to the first output terminal Dp. Also, of the pair of load terminals Ep, En, the load terminal En is a second load terminal and is connected to the second output terminal Dn.

[0017] The output circuit B2 functions as a load circuit for the main circuit B1 and also has the function of suppressing the output of the unnecessary signals (unwanted waves) to the outside. The output circuit B2 also has the function of supplying power to the main circuit B1.

[0018] Explaining the details of the main circuit B1 and the output circuit B2, as shown in the figure, the main circuit B1 includes a pair of input terminals 1p, 1n, a pair of input capacitors 2p, 2n, a pair of input bias resistors 3p, 3n, an input bias terminal 4, a pair of input transistors 5p, 5n, a constant current terminal 6, a constant current transistor 7, a source resistor 8, a ground terminal 9, a pair of local terminals 10p, 10n, a pair of local capacitors 11p, 11n, a pair of local bias resistors 12p, 12n, a local bias terminal 13, two pairs of local transistors 14p1, 14n1, 14p2, 14n2, a pair of matching inductors 15p, 15n, a pair of matching capacitors 16p, 16n, a pair of circuit output terminals 17p, 17n, and the above-mentioned pair of output terminals Dp, Dn.

[0019] Of the pair of input terminals 1p, 1n, the first input terminal 1p is connected to an external signal source and also to a first end of one of the pair of input capacitors 2p, 2n (i.e., the first input capacitor 2p). The first input terminal 1p outputs one of a pair of phase-inverted signals (i.e., a first high-frequency signal) input from the signal source to the first end of the first input capacitor 2p.

[0020] Of the pair of input terminals 1p, 1n, the second input terminal 1n is connected to an external signal source and also to a first end of the other of the pair of input capacitors 2p, 2n (i.e., the second input capacitor 2n). The second input terminal 1n outputs the other of the pair of phase-inverted signals input from the signal source (i.e., the second high-frequency signal) to the first end of the second input capacitor 2n.

[0021] Of the pair of input capacitors 2p, 2n, the first input capacitor 2p has a first end connected to the first input terminal 1p and a second end connected to one of the pair of input transistors 5p, 5n (i.e., the base terminal of the first input transistor 5p) and a first end of one of the pair of input bias resistors 3p, 3n (i.e., the first input bias resistor 3p). The first input capacitor 2p is a coupling capacitor that supplies only the AC component contained in the first high-frequency signal to the first input transistor 5p.

[0022] Of the pair of input capacitors 2p, 2n, the second input capacitor 2n has a first end connected to the second input terminal 1n and a second end connected to the base terminal of the other of the pair of input transistors 5p, 5n (i.e., the second input transistor 5n) and a first end of the other of the pair of input bias resistors 3p, 3n (i.e., the second input bias resistor 3n). The second input capacitor 2n is a coupling capacitor that supplies only the AC component contained in the second high-frequency signal to the second input transistor 5n.

[0023] Of the pair of input bias resistors 3p, 3n, the first input bias resistor 3p has a first end connected to the second end of the first input capacitor 2p and the base terminal of the first input transistor 5p, and a second end connected to the input bias terminal 4 and the second end of the second input bias resistor 3n. The first input bias resistor 3p has a predetermined resistance value and sets the base DC voltage (bias voltage) of the first input transistor 5p to a predetermined value.

[0024] Of the pair of input bias resistors 3p, 3n, the second input bias resistor 3n has a first end connected to the second end of the second input capacitor 2n and the base terminal of the second input transistor 5n, and a second end connected to the input bias terminal 4 and the second end of the first input bias resistor 3p. The second input bias resistor 3n has a predetermined resistance value and sets the base DC voltage (bias voltage) of the second input transistor 5n to a predetermined value.

[0025] The input bias terminal 4 is connected to an external bias power supply and also to the second end of the first input bias resistor 3 p and the second end of the second input bias resistor 3 n, and applies a predetermined DC voltage to the second end of the first input bias resistor 3 p and the second end of the second input bias resistor 3 n.

[0026] As shown in the figure, the pair of input transistors 5p, 5n are N-type bipolar transistors. Of the pair of input transistors 5p, 5n, the base terminal of the first input transistor 5p is connected to the second end of the first input capacitor 2p and the first end of the first input bias resistor 3p. The emitter terminal of the first input transistor 5p is connected to the drain terminal of the constant current transistor 7 and the emitter terminal of the second input transistor 5n.

[0027] Furthermore, the collector terminal of the first input transistor 5p is connected to the emitter terminal of the first local transistor 14p1 and the emitter terminal of the second local transistor 14n1 of the two pairs of local transistors 14p1, 14n1, 14p2, and 14n2.

[0028] Such a first input transistor 5p differentially amplifies a first high-frequency signal input to the base terminal of the first input transistor 5p and a second high-frequency signal input to the base terminal of the second input transistor 5n, and outputs a first differential signal that is in phase with the second high-frequency signal to the emitter terminal of the first local transistor 14p1 and the emitter terminal of the second local transistor 14n1.

[0029] Of the pair of input transistors 5p, 5n, the second input transistor 5n has a base terminal connected to the second end of the second input capacitor 2n and the first end of the second input bias resistor 3n, and an emitter terminal connected to the drain terminal of the constant current transistor 7 and the emitter terminal of the first input transistor 5p.

[0030] Furthermore, the collector terminal of the second input transistor 5n is connected to the emitter terminal of the third local transistor 14p2 and the emitter terminal of the fourth local transistor 14n2 of the two pairs of local transistors 14p1, 14n1, 14p2, 14n2.

[0031] Such a second input transistor 5n differentially amplifies the second high-frequency signal input to the base terminal of the second input transistor 5n and the first high-frequency signal input to the base terminal of the first input transistor 5p, and outputs a second differential signal that is in phase with the first high-frequency signal to the emitter terminal of the third local transistor 14p2 and the emitter terminal of the fourth local transistor 14n2.

[0032] The constant current terminal 6 is connected to an external bias power supply and also to the gate terminal of the constant current transistor 7. The constant current terminal 6 applies a predetermined DC voltage supplied from the bias power supply to the gate terminal of the constant current transistor 7 as a gate bias voltage.

[0033] As shown in the figure, the constant current transistor 7 is an N-channel MOS (Metal Oxide Semiconductor) transistor. The constant current transistor 7 has a gate terminal connected to the constant current terminal 6, a source terminal connected to a first end of a source resistor 8, and a drain terminal connected to the emitter terminal of the first input transistor 5p and the emitter terminal of the second input transistor 5n. The constant current transistor 7 passes a source current corresponding to the gate bias voltage through the source resistor 8.

[0034] The source resistor 8 has a first end connected to the source terminal of the constant current transistor 7 and a second end connected to the ground terminal 9. The source resistor 8 has a predetermined resistance value, and generates a voltage across its both ends according to the source current passed from the constant current transistor 7.

[0035] The ground terminal 9 is connected to an external ground potential (GND) and also to the second end of the source resistor 8. The ground terminal 9 is used to set the operating reference potential of the Gilbert cell type multiplier A to the ground potential (GND).

[0036] Of the pair of local terminals 10p, 10n, the first local terminal 10p is connected to an external local signal source and also to a first end of one of the pair of local capacitors 11p, 11n (i.e., the first local capacitor 11p). The first local terminal 10p outputs one of a pair of phase-inverted local signals (i.e., the first local signal) input from the local signal source to the first end of the first local capacitor 11p.

[0037] Of the pair of local terminals 10p, 10n, the second local terminal 10n is connected to an external local signal source and also to a first end of the other of the pair of local capacitors 11p, 11n (i.e., the second local capacitor 11n). The second local terminal 10n outputs the other of the pair of phase-inverted local signals (i.e., the second local signal) input from the local signal source to the first end of the second local capacitor 11n.

[0038] Of the pair of local capacitors 11p, 11n, the first local capacitor 11p has a first end connected to the first local terminal 10p and a second end connected to the base terminal of the first local transistor 14p1 and the base terminal of the third local transistor 14p2 of the two pairs of local transistors 14p1, 14n1, 14p2, 14n2.

[0039] The first local capacitor 11p has a second end connected to a first end of one of the pair of local bias resistors 12p, 12n (i.e., the first local bias resistor 12p). Such a first local capacitor 11p is a coupling capacitor that supplies only the AC component contained in the first local signal to the first local transistor 14p1 and the third local transistor 14p2.

[0040] Of the pair of local capacitors 11p, 11n, the second local capacitor 11n has a first end connected to the second local terminal 10n and a second end connected to the base terminal of the second local transistor 14n1 and the base terminal of the fourth local transistor 14n2 of the two pairs of local transistors 14p1, 14n1, 14p2, 14n2.

[0041] The second local capacitor 11n has a second end connected to the first end of the other of the pair of local bias resistors 12p, 12n (i.e., the second local bias resistor 12n). This second local capacitor 11n is a coupling capacitor that supplies only the AC component contained in the second local signal to the second local transistor 14n1 and the fourth local transistor 14n2.

[0042] Of the pair of local bias resistors 12p, 12n, the first local bias resistor 12p has a first end connected to the second end of the first local capacitor 11p, the base terminal of the first local transistor 14p1, and the base terminal of the third local transistor 14p2.

[0043] The first local bias resistor 12p has a second end connected to the local bias terminal 13 and the second end of the second local bias resistor 12n. The first local bias resistor 12p has a predetermined resistance value and sets the base DC voltage (bias voltage) of each of the first local transistor 14p1 and the third local transistor 14p2 to a predetermined value.

[0044] Of the pair of local bias resistors 12p, 12n, the second local bias resistor 12n has a first end connected to the second end of the second local capacitor 11n, the base terminal of the second local transistor 14n1, and the base terminal of the fourth local transistor 14n2.

[0045] The second local bias resistor 12n has a second end connected to the local bias terminal 13 and the second end of the first local bias resistor 12p. The second local bias resistor 12n has a predetermined resistance value and sets the base DC voltage (bias voltage) of each of the second local transistor 14n1 and the fourth local transistor 14n2 to a predetermined value.

[0046] The local bias terminal 13 is connected to an external bias power supply and also to the second end of the first local bias resistor 12p and the second end of the second local bias resistor 12n, and applies a predetermined DC voltage to the second end of the first local bias resistor 12p and the second end of the second local bias resistor 12n.

[0047] As shown in the figure, the two pairs of local transistors 14p1, 14n1, 14p2, and 14n2 are all N-type bipolar transistors. Of the two pairs of local transistors 14p1, 14n1, 14p2, and 14n2, the first local transistor 14p1 and the second local transistor 14n1 form a first pair, and the third local transistor 14p2 and the fourth local transistor 14n2 form a second pair.

[0048] The first local transistor 14p1 forms a first pair with the second local transistor 14n1, and has a base terminal connected to the base terminal of the third local transistor 14p2, the second terminal of the first local capacitor 11p, and the first terminal of the first local bias resistor 12p.

[0049] The first local transistor 14p1 has an emitter terminal connected to the emitter terminal of the second local transistor 14n1 and the collector terminal of the first input transistor 5p, and a collector terminal connected to the collector terminal of the fourth local transistor 14n2, a first end of one of the pair of matching inductors 15p, 15n (i.e., the first matching inductor 15p), and the first output terminal Dp.

[0050] Such a first local transistor 14p1 differentially amplifies the first local signal and the second local signal, and multiplies the first local signal by the first differential signal input from the first input transistor 5p, thereby outputting a first multiplied signal that is in the opposite phase to the first local signal.

[0051] The second local transistor 14n1 forms a first pair with the first local transistor 14p1, and has a base terminal connected to the base terminal of the fourth local transistor 14n2, the second terminal of the second local capacitor 11n, and the first terminal of the second local bias resistor 12n.

[0052] The second local transistor 14n1 has an emitter terminal connected to the emitter terminal of the first local transistor 14p1 and the collector terminal of the first input transistor 5p, and a collector terminal connected to the collector terminal of the third local transistor 14p2, the first end of the other of the pair of matching inductors 15p, 15n (i.e., the second matching inductor 15n), and the second output terminal Dn.

[0053] Such a second local transistor 14n1 differentially amplifies the second local signal and the first local signal, and multiplies the second local signal by the first differential signal input from the first input transistor 5p, thereby outputting a second multiplied signal that is in the opposite phase to the second local signal.

[0054] The third local transistor 14p2 forms a second pair with the fourth local transistor 14n2, and has a base terminal connected to the base terminal of the first local transistor 14p1, the second terminal of the first local capacitor 11p, and the first terminal of the first local bias resistor 12p.

[0055] The third local transistor 14p2 has an emitter terminal connected to the emitter terminal of the fourth local transistor 14n2 and the collector terminal of the second input transistor 5n, and a collector terminal connected to the collector terminal of the second local transistor 14n1, the first end of the other of the pair of matching inductors 15p, 15n (i.e., the second matching inductor 15n), and the second output terminal Dn.

[0056] Such a third local transistor 14p2 differentially amplifies the first local signal and the second local signal, and multiplies the first local signal by the second differential signal input from the second input transistor 5n, thereby outputting a third multiplied signal that is in the opposite phase to the first local signal.

[0057] The fourth local transistor 14n2 forms a second pair with the third local transistor 14p2, and has a base terminal connected to the base terminal of the second local transistor 14n1, the second terminal of the second local capacitor 11n, and the first terminal of the second local bias resistor 12n.

[0058] The fourth local transistor 14n2 has an emitter terminal connected to the emitter terminal of the third local transistor 14p2 and the collector terminal of the second input transistor 5n, and a collector terminal connected to the collector terminal of the first local transistor 14p1, the first end of one of the pair of matching inductors 15p, 15n (i.e., the first matching inductor 15p), and the first output terminal Dp.

[0059] Such a fourth local transistor 14n2 differentially amplifies the second local signal and the first local signal, and multiplies the second local signal by the second differential signal input from the second input transistor 5n, thereby outputting a fourth multiplied signal that is in the opposite phase to the second local signal.

[0060] Of the pair of matching inductors 15p, 15n, the first matching inductor 15p has a predetermined inductance, and a first end is connected to the collector terminal of the first local transistor 14p1, the collector terminal of the fourth local transistor 14n2, the first output terminal Dp, and the first load terminal Ep of the output circuit B2. Also, the second end of the first matching inductor 15p is connected to the first end of one of the pair of matching capacitors 16p, 16n (i.e., the first matching capacitor 16p).

[0061] Of the pair of matching inductors 15p, 15n, the second matching inductor 15n has a predetermined inductance, and a first end thereof is connected to the collector terminal of the second local transistor 14n1, the collector terminal of the third local transistor 14p2, the second output terminal Dn, and the second load terminal En of the output circuit B2. Also, the second matching inductor 15n has a second end thereof connected to the first end of the other of the pair of matching capacitors 16p, 16n (i.e., the second matching capacitor 16n).

[0062] Of the pair of matching capacitors 16p, 16n, the first matching capacitor 16p has a predetermined capacitance, a first end connected to the second end of the first matching inductor 15p, and a second end connected to one of the circuit output terminals 17p, 17n (i.e., the first circuit output terminal 17p).

[0063] Of the pair of matching capacitors 16p, 16n, the second matching capacitor 16n has a predetermined capacitance, a first end connected to the second end of the second matching inductor 15n, and a second end connected to the other of the circuit output terminals 17p, 17n (i.e., the second circuit output terminal 17n).

[0064] The inductance and capacitance of the first matching inductor 15p and first matching capacitor 16p connected in series are set so as to achieve impedance matching with the circuit (post-stage circuit) connected in the post-stage of the Gilbert cell multiplier A. Similarly, the inductance and capacitance of the second matching inductor 15n and second matching capacitor 16n connected in series are also set so as to achieve impedance matching with the post-stage circuit.

[0065] Of the pair of circuit output terminals 17p, 17n, the first circuit output terminal 17p is connected to the second end of the first matching capacitor 16p and a first input terminal of the subsequent circuit, and the second circuit output terminal 17n is connected to the second end of the second matching capacitor 16n and a second input terminal of the subsequent circuit.

[0066] The first circuit output terminal 17p and the second circuit output terminal 17n output a desired frequency component (desired wave) from among two frequency components contained in the first to fourth multiplied signals output from the first to fourth local transistors 14p1, 14n1, 14p2, and 14n2, respectively, to a subsequent circuit. The desired frequency component is set by the circuit performance of the output circuit B2.

[0067] On the other hand, as shown in the figure, the output circuit B2 includes a power supply terminal 18, a pair of output inductors 19p, 19n, a pair of output resistors 20p, 20n, a pair of output lines 21p, 21n, and a pair of load terminals Ep, En. Of these components, the output inductor 19p and the first output line 21p form a first load inductor in the present invention. The other output inductor 19n and the second output line 21n form a second load inductor in the present invention.

[0068] The power supply terminal 18 is connected to a first end of one of the pair of output inductors 19p, 19n (i.e., the second output inductor 19n) and a first end of the other of the pair of output inductors 19p, 19n (i.e., the second output inductor 19n). The power supply terminal 18 is also connected to an external DC power supply (hereinafter simply referred to as the "power supply"). Power of a predetermined voltage (flow voltage) is supplied to the power supply terminal 18 from the DC power supply.

[0069] Of the pair of output inductors 19p, 19n, one output inductor 19p has a predetermined inductance (first inductance L1). A first end of the one output inductor 19p is connected to the power supply terminal 18 and a first end of the other output inductor 19n, and a second end of the one output inductor 19p is connected to a first end of one of the pair of output resistors 20p, 20n (i.e., the first output resistor 20p) and a first end of one of the pair of output lines 21p, 21n (i.e., the first output line 21p).

[0070] The other output inductor 19n of the pair of output inductors 19p, 19n has a predetermined inductance (second inductance L2). A first end of the other output inductor 19n is connected to the power supply terminal 18, and a second end of the other output inductor 19n is connected to a first end of the other of the pair of output resistors 20p, 20n (i.e., the second output resistor 20n) and a first end of the other of the pair of output lines 21p, 21n (i.e., the second output line 21n).

[0071] For example, the pair of output inductors 19p, 19n are CT-type inductors having a center tap (CT) connected to the power supply terminal 18, a first tap connected to a first end of a first output resistor 20p and a first end of a first output line 21p, and a second tap connected to a first end of a second output resistor 20n and a first end of a second output line 21n.

[0072] A part of such an output circuit B2 (i.e., a pair of output inductors 19p, 19n) can be represented as an equivalent circuit (T-type circuit) shown in Fig. 2. In Fig. 2, the second end of one output inductor 19p is a contact point P1, and the second end of the other output inductor 19n is a contact point P2.

[0073] That is, in the pair of output inductors 19p, 19n, the second end of the first inductance L1 is connected to the first contact P1, and the second end of the second inductance L2 is connected to the second contact P1. Also, in the pair of output inductors 19p, 19n, the first end of the first inductance L1 and the first end of the second inductance L2 are connected.

[0074] In addition, the pair of output inductors 19p, 19n has a first parasitic capacitance C1 connected between a connection point between a first end of the first inductance L1 and a first end of the second inductance L2 and ground potential (GND). Furthermore, in the pair of output inductors 19p, 19n, a first end of a second parasitic capacitance C2 is connected to the first end of the first inductance L1, and a second end of the second parasitic capacitance C2 is connected to the first end of the second inductance L2, on either side of the connection point.

[0075] The first inductance L1 and the second inductance L2 of the pair of output inductors 19p, 19n are set so that the desired wave of the two frequency component signals (desired wave and unwanted wave) contained in the first to fourth multiplied signals is output to the subsequent circuit. In other words, the pair of output inductors 19p, 19n has the function of absorbing the unwanted waves contained in the first to fourth multiplied signals.

[0076] 1, in the main circuit B1, a first resistor 20p is provided between one output inductor 19p and one of the pair of load terminals Ep, En (i.e., the first load terminal Ep), and a second resistor 20n is provided between the other output inductor 19n and the other of the pair of load terminals Ep, En (i.e., the second load terminal En).

[0077] That is, the first output resistor 20p has a first end connected to the second end of one output inductor 19p and the first end of the first output line 21p, and a second end connected to the second end of the first output line 21p and the first load terminal Ep (i.e., the first output terminal Dp in the main circuit B1). Such a first output resistor 20p is a first load resistor having a predetermined resistance value.

[0078] Of the pair of output resistors 20p, 20n, the second output resistor 20n has a first end connected to the second end of the other output inductor 19n and the first end of the second output line 21n, and a second end connected to the second end of the second output line 21n and the second load terminal En (i.e., the second output terminal Dn in the main circuit B1). Such second output resistor 20n is a second load resistor having a predetermined resistance value.

[0079] Of the pair of output lines 21p, 21n, the first output line 21p has a first end connected to the second end of one output inductor 19p and the first end of the first output resistor 20p, and a second end connected to the second end of the first output resistor 20p and the first load terminal Ep (i.e., the first output terminal Dp in the main circuit B1). Such a first output line 21p is a transmission line of a predetermined length and functions as a first auxiliary inductor that assists one output inductor 19p.

[0080] Of the pair of output lines 21p, 21n, the second output line 21n has a first end connected to the second end of the other output inductor 19n and the first end of the second output resistor 20n, and a second end connected to the second end of the second output resistor 20n and the second load terminal En (i.e., the second output terminal Dn in the main circuit B1). Such second output line 21n is a transmission line of a predetermined length and functions as a second auxiliary inductor that assists the other output inductor 19n.

[0081] That is, in the output circuit B2 in the first embodiment, the first load inductor has one output inductor 19p and a first output line 21p (first auxiliary inductor), and the second load inductor has the other output inductor 19n and a second output line 21n (second auxiliary inductor). Also, in this output circuit B2, a first output resistor 20p is connected in parallel to the first output line 21p (first auxiliary inductor), and a second output resistor 20n is connected in parallel to the second output line 21n (second auxiliary inductor).

[0082] Although the configuration of the output circuit B2 of this Gilbert cell multiplier A is different from that of a known Gilbert cell multiplier circuit, the configuration of the main circuit B1 is the same as that of a known Gilbert cell multiplier circuit. In other words, the Gilbert cell multiplier A of this embodiment is configured to function as a known Gilbert cell multiplier circuit as a whole.

[0083] Next, the operation of the Gilbert cell type multiplier A according to this embodiment will be described in detail with reference to FIGS.

[0084] In this Gilbert cell multiplier A, a pair of phase-inverted signals are input from an external signal source to a pair of input terminals 1p and 1n, and a pair of local signals are input from an external local signal source to a pair of local terminals 10p and 10n. That is, a first high-frequency signal is input to the first input terminal 1p, and a second high-frequency signal is input to the second input terminal 1n. As shown in FIG. 3 , the first high-frequency signal Sinp and the second high-frequency signal Sinn are a pair of phase-inverted signals (analog signals) that have the same frequency (i.e., the first frequency) but are 180° out of phase with each other.

[0085] A first local signal is input to first local terminal 10p, and a second local signal is input to second local terminal 10n. The first and second local signals have the same frequency (i.e., the second frequency) and are a pair of phase-inverted local signals (analog signals) that are 180° out of phase with each other.

[0086] The pair of input transistors 5p, 5n generate a pair of differential signals by differentially amplifying a pair of phase-inverted signals input from a pair of input terminals 1p, 1n via a pair of input capacitors 2p, 2n, and output the pair of differential signals to two pairs of local transistors 14p1, 14n1, 14p2, 14n2.

[0087] That is, the first input transistor 5p generates a first differential signal and outputs it to the first pair of the first local transistor 14p1 and the second local transistor 14n1, and the second input transistor 5n generates a second differential signal and outputs it to the second pair of the third local transistor 14p2 and the fourth local transistor 14n2.

[0088] The two pairs of local transistors 14p1, 14n1, 14p2, 14n2 generate first to fourth multiplied signals by multiplying a pair of differential signals input to each emitter terminal from the pair of input transistors 5p, 5n by a pair of phase-inverted local signals input to each base terminal from the pair of local terminals 10p, 10n via a pair of local capacitors 11p, 11n.

[0089] That is, the first local transistor 14p1 generates a first multiplied signal by multiplying the first differential signal input from the first input transistor 5p to its emitter terminal by the first local signal input from the first local terminal 10p to its base terminal via the first local capacitor 11p.

[0090] The second local transistor 14n1 generates a second multiplied signal by multiplying the first differential signal input from the first input transistor 5p to its emitter terminal by the second local signal input from the second local terminal 10n to its base terminal via the second local capacitor 11n.

[0091] The third local transistor 14p2 generates a third multiplied signal by multiplying the second differential signal input from the second input transistor 5n to its emitter terminal by the first local signal input from the first local terminal 10p to its base terminal via the first local capacitor 11p.

[0092] The fourth local transistor 14n2 generates a fourth multiplied signal by multiplying the second differential signal input from the second input transistor 5n to its emitter terminal by the second local signal input from the second local terminal 10n to its base terminal via the second local capacitor 11n.

[0093] Here, of the first to fourth multiplication signals, the first and fourth multiplication signals are output to the first output terminal Dp, and the second and third multiplication signals are output to the second output terminal Dn. These first to fourth multiplication signals are multi-frequency signals that include a desired wave of a desired frequency component and an unwanted wave of an unwanted frequency component.

[0094] Of the pair of load terminals Ep, En, the first load terminal Ep is connected to the first output terminal Dp, and the second load terminal En is connected to the second output terminal Dn. An output circuit B2 absorbs only the unwanted waves among the desired waves and unwanted waves contained in the first to fourth multiplied signals.

[0095] That is, the pair of output inductors 19p, 19n in this output circuit B2 are set so that the first inductance L1 and the second inductance L2 absorb the unwanted waves contained in the first to fourth multiplication signals, and therefore only the desired waves propagate from the pair of output terminals Dp, Dn to the pair of circuit output terminals 17p, 17n.

[0096] Such an output circuit B2 has, for example, attenuation characteristics as shown in Fig. 4. That is, the output circuit B2 has frequency characteristics that selectively attenuate only the unnecessary frequency components corresponding to approximately 30 GHz among the contained frequency components of the first to fourth multiplication signals output from the main circuit B1 to the first load terminal Ep and the second load terminal En.

[0097] Of the pair of circuit output terminals 17p, 17n, a first output signal Soutp is output from the first circuit output terminal 17p to a first input terminal of the subsequent circuit, and a second output signal Soutn is output from the second circuit output terminal 17n to a second input terminal of the subsequent circuit.

[0098] When the desired wave is a signal having a frequency equal to the sum of the first high-frequency signal Sinp and the second high-frequency signal Sinn and the first local signal and the second local signal, the first output signal Soutp and the second output signal Soutn have a frequency higher than the frequency of the first high-frequency signal Sinp and the second high-frequency signal Sinn, as shown in Figure 3.

[0099] According to the first embodiment, instead of the balun in the conventional Gilbert cell type multiplier circuit, a pair of output inductors 19p, 19n is provided in which the first inductance L1 and the second inductance L2 are set to absorb unwanted waves contained in the first to fourth multiplication signals, making it possible to provide a Gilbert cell type multiplier A that can be made smaller than conventional ones.

[0100] In the first embodiment, in the output circuit B2, the first output inductor 19p is connected in series to a first output line 21p (first auxiliary inductor), and the second output inductor 19n is connected in series to a second output line 21n (second auxiliary inductor). In the output circuit B2, the first output line 21p is connected in parallel to a first output resistor 20p, and the second output line 21n is connected in parallel to a second output resistor 20n.

[0101] That is, the output circuit B2 in the first embodiment includes a pair of output inductors 19p, 19n, a pair of output resistors 20p, 20n, and a pair of output lines 21p, 21n. According to the first embodiment, it is possible to easily set the inductances of the first load inductor and the second load inductor in the output circuit B2.

[0102] Second Embodiment Next, a second embodiment of the present invention will be described. As shown in Fig. 5, a Gilbert cell multiplier A1 according to the second embodiment includes a main circuit B1 and an output circuit B2'. In Fig. 5, the same components as those in the Gilbert cell multiplier A according to the first embodiment are denoted by the same reference numerals.

[0103] 5, the output circuit B2' in the second embodiment does not include the pair of output lines 21p, 21n in the first embodiment, but instead includes a pair of output resistors 20p, 20n connected in parallel to a pair of output inductors 19p, 19n, and includes a series resonant circuit 22 between a pair of load terminals Ep, En. In the second embodiment, one output inductor 19p corresponds to the first load inductor in the present invention, and the other output inductor 19n corresponds to the second load inductor in the present invention.

[0104] That is, in the second embodiment, the first output resistor 20p is connected in parallel to the first output inductor 19p, and the second output resistor 20n is connected in parallel to the second output inductor 19n. Also, as shown in the figure, the series resonant circuit 22 is a series-connected circuit consisting of two inductors and one capacitor. More specifically, the series resonant circuit 22 is a series-connected circuit in which one capacitor is provided between two inductors, and a first end is connected to the first load terminal Ep and a second end is connected to the second load terminal En.

[0105] The resonant frequency of this series resonant circuit 22 is set to the frequency of the spurious waves contained in the first to fourth multiplied signals, i.e., the series resonant circuit 22 is set to suppress the output of the spurious waves to the outside.

[0106] In the Gilbert cell multiplier A1 according to the second embodiment, the pair of output inductors 19p and 19n absorbs the unwanted waves contained in the first to fourth multiplication signals, and the series resonant circuit 22 also absorbs the unwanted waves. Therefore, according to the second embodiment, it is possible to provide a Gilbert cell multiplier A1 that can be made smaller than conventional multipliers, and it is also possible to more reliably absorb the unwanted waves.

[0107] The present invention is not limited to the above-described embodiment, and the following modifications are possible, for example: (1) In the first embodiment, the pair of output inductors 19p, 19n, the pair of output resistors 20p, 20n, and the pair of output lines 21p, 21n are provided, but the present invention is not limited to this. The pair of output resistors 20p, 20n and the pair of output lines 21p, 21n may be omitted as necessary.

[0108] (2) In the above embodiment, the pair of matching inductors 15p and 15n and the pair of matching capacitors 16p and 16n are provided, but the present invention is not limited to this. The pair of matching inductors 15p and 15n and the pair of matching capacitors 16p and 16n may be omitted as necessary.

[0109] (3) In the above embodiment, the connection point between the pair of output inductors 19p and 19n (i.e., the first end of the first output inductor 19p and the first end of the second output inductor 19n) is connected only to the power supply terminal 18 (power supply), but the present invention is not limited to this. For example, an auxiliary capacitor that supplements the first parasitic capacitance C1 in the equivalent circuit of FIG. 2 may be provided between the connection point between the pair of output inductors 19p and 19n (i.e., the power supply terminal 18) and ground potential (GND).

[0110] A, A1...Gilbert cell type multiplier, B1...main circuit, B2, B2'...output circuit, Dp, Dn...output terminal, Ep, En...load terminal, 1p, 1n...input terminal, 2p, 2n...input capacitor, 3p, 3n...input bias resistor, 4...input bias terminal, 5p, 5n...input transistor, 6...constant current terminal, 7...constant current transistor, 8...source resistor, 9...ground terminal, 10p, 10n...local terminal, 11 p, 11n...local capacitor, 12p, 12n...local bias resistor, 13...local bias terminal, 14p1, 14n1, 14p2, 14n2...local transistor, 15p, 15n...matching inductor, 16p, 16n...matching capacitor, 17p, 17n...circuit output terminal, 18...power supply terminal, 19p, 19n...output inductor, 20p, 20n...output resistor, 21p, 21n...output line

Claims

1. A Gilbert cell type frequency multiplier comprising an output circuit in which a pair of load terminals are connected to a pair of output terminals in a main circuit, the output circuit comprising: a first load inductor having a first end connected to a power supply and a second end connected to one of the pair of load terminals; and a second load inductor having a first end connected to the power supply and a second end connected to the other of the pair of load terminals, wherein inductances of the first load inductor and the second load inductor are set to suppress output of unnecessary waves to the outside.

2. The Gilbert cell type frequency multiplier according to claim 1, wherein the output circuit includes a series resonance circuit between the pair of load terminals, and a resonance frequency of the series resonance circuit is set to suppress output of the unnecessary waves to the outside.

3. The Gilbert cell type frequency multiplier according to claim 1 or 2, wherein the first load inductor has a first auxiliary inductor, and the second load inductor has a second auxiliary inductor.

4. The Gilbert cell type frequency multiplier according to claim 3, wherein a first output resistor is connected in parallel to the first auxiliary inductor, and a second output resistor is connected in parallel to the second auxiliary inductor.

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