Array substrate, display panel, and display apparatus

Abstract

An array substrate, a display panel, and a display apparatus. The array substrate comprises: a base substrate (100) provided with a display region (AA); a plurality of pixel electrodes (101) arranged in an array in the display region (AA); a plurality of data lines (102) extending between the pixel electrodes (101) in a first direction (Y); a plurality of transistors (103) located between adjacent pixel electrodes (101) arranged in the first direction (Y), first electrodes (301) of the transistors (103) being connected to the pixel electrodes (101); a plurality of connection lines (104) located between the adjacent pixel electrodes (101) arranged in the first direction (Y), at least some of the connection lines (104) being connected to the data lines (102) and second electrodes (302) of the transistors (103); and a plurality of gate lines (105) extending between the pixel electrodes (101) in a second direction (X) intersecting the first direction (Y). The gate lines (105) are connected to gate electrodes (303) of the transistors (103). Each gate line (105) comprises a recess (GV), an opening of the recess (GV) faces a pixel electrode (101) to which the gate line (105) is electrically connected by means of a transistor (103), a connection line (104) is arranged at an opening side of the recess (GV), the recess (GV) comprises a first portion (GV1) and a second portion (GV2) located on two sides of a data line (102), the first portion (GV1) is close to the connection line (104), and the area of the orthographic projection of the first portion (GV1) on the base substrate (100) is greater than the area of the orthographic projection of the second portion (GV2).

Description

Array substrate, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) feature compact size, low power consumption, high image quality, zero radiation, and portability. They have experienced rapid development in recent years, gradually replacing traditional cathode ray tube (CRT) displays and dominating the current flat-panel display market. Currently, TFT-LCDs are widely used in a variety of large, medium, and small-sized products, encompassing nearly every major electronic product in today's information society, including LCD TVs, high-definition digital TVs, computers (desktop and laptop), mobile phones, tablets, navigation systems, in-car displays, projection displays, camcorders, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0003] Summary of the Invention

[0004] The array substrate, display panel, and display device provided by the embodiments of the present disclosure are specifically described as follows:

[0005] In one aspect, an embodiment of the present disclosure provides an array substrate, comprising:

[0006] a base substrate, the base substrate comprising a display area;

[0007] A plurality of pixel electrodes are arranged in an array in the display area;

[0008] a plurality of data lines extending along a first direction between the pixel electrodes;

[0009] a plurality of transistors, located between adjacent pixel electrodes arranged along the first direction, wherein first electrodes of the transistors are connected to the pixel electrodes;

[0010] a plurality of connecting lines located between adjacent pixel electrodes arranged along the first direction, at least some of the connecting lines connecting the data line and the second electrode of the transistor;

[0011] A plurality of gate lines extend between the pixel electrodes along a second direction, the second direction intersecting the first direction, the gate lines being connected to the gates of the transistors, the gate lines comprising grooves, the openings of the grooves facing the pixel electrodes to which the gate lines are electrically connected through the transistors, the connecting lines being provided on the opening sides of the grooves, the grooves comprising a first portion located on a side of the data line facing the connecting line, and a second portion located on a side of the data line away from the connecting line, the orthographic projection area of ​​the first portion on the base substrate being greater than the orthographic projection area of ​​the second portion on the base substrate.

[0012] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the boundary of the gate line at the first portion is a step structure, and the boundary of the gate line at the second portion is an L-shaped structure.

[0013] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the minimum distance between the stepped structure and the data line in the second direction is a, the minimum distance between the stepped structure and the connecting line in the first direction is b, the distance between the L-shaped structure and the data line in the second direction is c, and the size of the L-shaped structure in the first direction is d, wherein a and c are approximately the same, b is greater than or equal to a and less than d.

[0014] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the orthographic projection of the connecting line on the base substrate is located within the orthographic projection of the first part on the base substrate.

[0015] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the second electrode of the transistor includes a connecting portion connected to the connecting line, and the angle between the connecting portion and the connecting line is an obtuse angle.

[0016] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a plurality of switching electrodes, and an insulating layer located between the layer where the pixel electrodes are located and the layer where the switching electrodes are located; the switching electrodes are coupled to the pixel electrodes and the first electrode of the transistor through via holes penetrating the insulating layer;

[0017] The via hole gradually increases in size in a direction from the layer where the pixel electrode is located to the layer where the switching electrode is located, and the via hole includes a bottom opening facing one side of the base substrate;

[0018] An overlapping area between the bottom opening and the first electrode of the transistor is 6 / 11 to 7.2 / 11 of an area of ​​the bottom opening.

[0019] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the overlapping dimension of the bottom opening and the first pole of the transistor in the first direction is e, and the overlapping dimension of the bottom opening and the first pole of the transistor in the second direction is f; the dimension of the bottom opening in the first direction is g, and the dimension of the bottom opening in the second direction is h, wherein f is equal to h and less than g, and e / g is greater than or equal to 6 / 11 and less than or equal to 7.2 / 11.

[0020] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the via hole is a step hole that gradually descends in the direction from the first electrode of the transistor to the pixel electrode.

[0021] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the first electrode of the transistor includes a overlapping portion that overlaps and is electrically connected to the pixel electrode, and a compensation portion located on a side of the overlapping portion away from the connecting line, and the orthographic projection of the compensation portion on the base substrate overlaps with the orthographic projection of the gate line on the base substrate.

[0022] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the first electrode of the transistor further includes an electrode portion located on the side of the overlapping portion facing the connecting line, and the electrode portion and the compensation portion are staggered in the first direction.

[0023] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the compensation portion is located on the side of the electrode portion facing the gate line; and on the side close to the gate line, the boundary of the compensation portion extending along the second direction and the boundary of the overlapping portion extending along the second direction are arranged roughly collinearly.

[0024] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the pixel electrode includes a connecting portion overlapping the overlapping portion, and the length of the overlapping portion in the second direction is substantially the same as the length of the connecting portion in the second direction.

[0025] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the base substrate also includes a non-display area located on at least one side of the display area, and the non-display area is provided with a common electrode signal line and a feedback signal line, and the common electrode signal line and the feedback signal line respectively include a first layer of wiring arranged on the same layer as the gate line, and a second layer of wiring arranged on the same layer as the data line and connected to the first layer of wiring.

[0026] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the layer where the gate lines are located is located between the layer where the data lines are located and the base substrate;

[0027] The first-layer wiring includes a first slit, the second-layer wiring includes a second slit, and the orthographic projection of the first slit on the base substrate in the double-layer wiring region is located within the orthographic projection of the second slit on the base substrate.

[0028] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the non-display area includes a first non-display area for binding a driving circuit, and a second non-display area and a third non-display area opposite to each other, and the second non-display area and the third non-display area are respectively connected to the first non-display area;

[0029] In the second non-display area and the third non-display area, the signal lines transmitting the same signal have substantially the same line width.

[0030] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes dummy pixel columns located on the side of the signal line facing the display area in the second non-display area and the third non-display area, and the number of dummy pixel columns in the second non-display area is different from the number of dummy pixel columns in the third non-display area.

[0031] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes an orientation film, and around the via hole: the thickness of the orientation film on the side of the pixel electrode electrically connected to the transistor in the via hole is greater than the thickness of the orientation film on other sides around the via hole.

[0032] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, within the via hole, the thickness of the alignment film increases in a direction from the first electrode of the transistor to the pixel electrode.

[0033] On the other hand, an embodiment of the present disclosure further provides a display panel, comprising the above-mentioned array substrate provided by an embodiment of the present disclosure, and an opposite substrate arranged opposite to the array substrate.

[0034] On the other hand, an embodiment of the present disclosure provides a display device, including the above-mentioned display panel provided by the embodiment of the present disclosure, and a backlight module located on the light incident side of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 is a schematic structural diagram of a transistor and its vicinity in a related array substrate;

[0036] FIG2 is an enlarged structural diagram of the Z1 region in FIG1 ;

[0037] FIG3 is a schematic structural diagram of an array substrate provided in an embodiment of the present disclosure;

[0038] FIG4 is a physical diagram of an array substrate provided in an embodiment of the present disclosure;

[0039] FIG5 is a layout diagram of an array substrate provided in an embodiment of the present disclosure;

[0040] FIG6 is an enlarged structural diagram of the Z2 area in FIG5 ;

[0041] FIG7 is an enlarged structural diagram of the Z3 region in FIG6 ;

[0042] FIG8 is a schematic diagram of a parallel structure of the structure shown in FIG6;

[0043] FIG9 is a schematic diagram of the enlarged structure of the Z4 region in FIG8 ;

[0044] FIG10 is a schematic structural diagram of the layer where the pixel electrode is located in FIG5 ;

[0045] FIG11 is a schematic structural diagram of the layer where the gate lines are located in FIG5 ;

[0046] FIG12 is a schematic structural diagram of the layer where the active layer is located in FIG5;

[0047] FIG13 is a schematic structural diagram of the layer where the data line is located in FIG5;

[0048] FIG14 is a schematic structural diagram of the insulating layer in FIG5 ;

[0049] FIG15 is a schematic structural diagram of the layer where the common electrode is located in FIG5 ;

[0050] FIG16 is an enlarged structural diagram of the Z5 region in FIG6 ;

[0051] FIG17 is a schematic diagram of the cross-sectional structure along line CC' in FIG16;

[0052] FIG18 is a schematic diagram of the cross-sectional structure along line DD' in FIG16;

[0053] FIG19 is a real shot of a half via test according to an embodiment of the present disclosure;

[0054] FIG20 is a picture of a half via provided in an embodiment of the present disclosure;

[0055] FIG21 is an enlarged picture of a half via provided in an embodiment of the present disclosure;

[0056] FIG22 is a cross-sectional view of a half via provided in an embodiment of the present disclosure;

[0057] FIG23 is a schematic diagram of the structure of the relevant 3 / 4 vias;

[0058] FIG24 is a schematic diagram of the cross-sectional structure along line AA' in FIG23;

[0059] FIG25 is a schematic diagram of the cross-sectional structure along line BB' in FIG23;

[0060] FIG26 is a real shot of a 3 / 4 via test according to an embodiment of the present disclosure;

[0061] FIG27 is a schematic diagram of PI diffusion of a related full-via solution;

[0062] FIG28 is a schematic diagram of PI diffusion of a half-via solution disclosed herein;

[0063] FIG29 is a schematic diagram of another structure of an array substrate provided in an embodiment of the present disclosure;

[0064] FIG30 is an enlarged structural diagram of the Z6 region in FIG29 ;

[0065] FIG31 is a schematic diagram of another structure of an array substrate provided in an embodiment of the present disclosure;

[0066] FIG32 is a schematic diagram of the cross-sectional structure along the II-II' direction in FIG5;

[0067] FIG33 is a schematic structural diagram of a display panel provided in an embodiment of the present disclosure;

[0068] FIG34 is a schematic diagram of another structure of a display panel provided in an embodiment of the present disclosure;

[0069] FIG35 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure;

[0070] FIG36 is another structural schematic diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0071] To further clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In this disclosure, exemplary embodiments are described with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes shown in the drawings are to be expected, for example, as a result of manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape resulting from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features; a sharp angle illustrated may be rounded, etc. Therefore, the regions shown in the drawings are schematic in nature, and their sizes and shapes are not intended to illustrate the precise shapes of the regions or reflect true scale, but are intended solely to illustrate the present disclosure. Throughout, identical or similar reference numerals denote identical or similar elements or elements having identical or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0072] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0073] In the following description, when an element or layer is referred to as being “on” or “connected to” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as being “disposed on one side of” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intermediate elements or intermediate layers. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0074] Figure 1 is a schematic diagram of the structure of a transistor and its surroundings in a related array substrate, and Figure 2 is an enlarged schematic diagram of the structure of region Z1 in Figure 1. As can be seen from Figures 1 and 2, the array substrate includes a pixel electrode 101, a data line 102, a transistor 103, a connecting line 104, and a gate line 105. A first electrode 301 of the transistor 103 is electrically connected to the pixel electrode 101, a second electrode 302 of the transistor 103 is electrically connected to the data line 102 via the connecting line 104, and a gate 303 of the transistor 103 is partially multiplexed with the gate line 105.

[0075] In some embodiments, the first electrode 301, the second electrode 302, the connecting line 104, and the data line 102 of the transistor 103 are arranged in the same layer and the same material, and a gate insulating layer (GI) is provided between the layer where the data line 102 is located and the layer where the gate line 105 is located. During the manufacturing process, there may be residual conductive particles. Once the conductive particles pierce the gate insulating layer, it is easy to cause a short circuit between the first electrode 301, the second electrode 302, or the connecting line 104 and the gate line 105 (i.e., Data Gate Short, DGS), in which case the pixel needs to be repaired. For example, the connecting line 104 can be cut with a laser along the dotted line II' in FIG. 2. Cutting will cause the material of the connecting line 104 to splash and accumulate in the repair space RS. In FIG. 2, due to insufficient repair space RS, the data line 102 and the gate line 105 will be fused together after cutting, resulting in repair failure and a new DGS, which affects the product yield and product sales level.

[0076] In order to solve the above-mentioned technical problems existing in the related art, the present disclosure provides an array substrate. Figure 3 is a structural schematic diagram of the array substrate provided in the embodiment of the present disclosure, Figure 4 is a physical diagram of the array substrate provided in the embodiment of the present disclosure, Figure 5 is a layout diagram of the array substrate provided in the embodiment of the present disclosure, Figure 6 is an enlarged structural schematic diagram of the Z2 area in Figure 5, and Figure 7 is an enlarged structural schematic diagram of the Z3 area in Figure 6. As can be seen from Figures 3 to 7, the array substrate provided in the embodiment of the present disclosure may include:

[0077] A base substrate 100 includes a display area AA, wherein the display area AA includes a plurality of sub-pixel areas (e.g., a red sub-pixel area R, a green sub-pixel area G, and a blue sub-pixel area B) arranged in an array. Optionally, the base substrate 100 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, or the like.

[0078] Multiple pixel electrodes 101 are located in sub-pixel regions (e.g., red sub-pixel region R, green sub-pixel region G, and blue sub-pixel region B) of the display area AA. The pixel electrodes 101 may be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), or gallium zinc oxide (GZO).

[0079] A plurality of data lines 102 extend along a first direction Y between the pixel electrodes 101. Optionally, the material of the data lines 102 may include a metal such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), or nickel (Ni). The data lines 102 may have a single-layer structure or a stacked-layer structure. For example, the data lines 102 may have a stacked-layer structure consisting of a titanium metal layer / an aluminum metal layer / a titanium metal layer. Optionally, every two pixel electrodes 101 arranged along the second direction X constitute a pixel electrode group PX, and the two pixel electrodes 101 of the same pixel electrode group PX are electrically connected to the same data line 102.

[0080] Multiple transistors 103 are located between adjacent pixel electrodes 101 arranged along a first direction Y. A first electrode 301 of the transistor 103 is connected to the pixel electrode 101. Optionally, two transistors 103 are provided in a space enclosed by two data lines 102 and four pixel electrodes 101. The two pixel electrodes 101 electrically connected to the two transistors 103 are located in different rows and columns. The transistor 103 may be a bottom-gate transistor, a top-gate transistor, or a dual-gate transistor. This disclosure uses the bottom-gate transistor as an example for description. In addition, the transistor 103 may be a P-type transistor or an N-type transistor, which is not limited herein.

[0081] A plurality of connecting lines 104 are located between adjacent pixel electrodes 101 arranged along the first direction Y, and at least some of the connecting lines 104 connect the data line 102 and the second electrode 302 of the transistor 103. It should be noted that, under normal circumstances, the connecting lines 104 are electrically connected to the data line 102 and the second electrode 302 of the transistor 103 (for example, the three are on the same layer and integrally arranged). However, after repairing a DGS defect, some of the connecting lines 104 may be cut and no longer electrically connected to the data line 102 and the second electrode 302 of the transistor 103. Optionally, the first electrode 301 of the transistor 103 is a source and the second electrode 302 is a drain, or the first electrode 301 is a drain and the second electrode 302 is a source.

[0082] In this disclosure, "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for producing a specific pattern, and then using the same mask through a single patterning process. That is, one patterning process corresponds to one mask (also known as a photomask). Depending on the specific pattern, one patterning process may include multiple exposure, development, or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or at different heights or have different thicknesses.

[0083] A plurality of gate lines 105 extend between the pixel electrodes 101 along a second direction X, where the second direction X intersects the first direction Y. The gate lines 105 are connected to the gates 303 of the transistors 103. For example, a portion of the gate lines 105 is multiplexed as the gates 303 of the transistors 103, or the gates 303 of the transistors 103 are integrated with the gate lines 105 and protrude relative to the gate lines 105. Optionally, the material of the gate lines 105 may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The gate lines 105 may be a single-layer structure or a stacked-layer structure, for example, a gate line 105 may be a plurality of gate lines 105. Line 105 is a single-layer structure composed of a molybdenum metal layer; in some embodiments, the gate line 105 includes a groove GV, the opening of the groove GV faces the pixel electrode 101 electrically connected to the gate line 105 through the transistor 103, and a connecting line 104 is provided on the opening side of the groove GV. The groove GV includes a first portion GV1 located on the side of the data line 102 facing the connecting line 104, and a second portion GV2 located on the side of the data line 102 away from the connecting line 104. The orthographic projection area of ​​the first portion GV1 on the base substrate 100 is larger than the orthographic projection area of ​​the second portion GV2 on the base substrate 100.

[0084] By comparing Figures 1 and 2 of the related art, it can be seen that in the present disclosure, the groove GV of the gate line 105 is set as above, which is equivalent to moving the gate line 105 at the groove GV inward to the bottom of the connecting line 104, and at the same time lifting the connecting line 104. In this way, when the pixel size of the related art is close to that of the present disclosure, the first part GV1 serving as the repair space RS in the present disclosure is larger, especially the lateral dimension H2 of the first part GV1 can be much larger than the lateral dimension H1 of the repair space RS in Figure 2, which is beneficial to ensuring the repair yield and will not affect the pixel aperture ratio.

[0085] In some embodiments, as shown in Figures 6 and 7 , the orthographic projection of the connecting line 104 on the base substrate 100 is located within the orthographic projection of the first portion GV1 on the base substrate 100 to prevent the connecting line 104 from excessively moving upward and affecting the aperture ratio. Specifically, in Figures 6 and 7 , the boundary of the connecting line 104 near the pixel electrode 101 and the boundary of the first portion GV1 near the pixel electrode 101 are arranged approximately collinearly. For example, the distance in the first direction Y between the boundary of the connecting line 104 near the pixel electrode 101 and the boundary of the first portion GV1 near the pixel electrode 101 is within an error range of 0 to 1 μm caused by factors such as manufacturing and measurement.

[0086] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 6 and 7, the boundary of the gate line 105 at the first part GV1 can be a stepped structure, and the boundary of the gate line 105 at the second part GV2 can be an L-shaped structure. In other embodiments, as shown in Figures 8 and 9, the boundaries of the gate line 105 at the first part GV1 and the second part GV2 can also be L-shaped. Compared with the groove GV shown in Figures 6 and 7, the first part GV1 as the maintenance space RS in the groove GV shown in Figures 8 and 9 is obviously larger, but at the same time, the line width of the gate line 105 below the first part GV1 is reduced, causing the resistance of the gate line 105 to increase, which is not conducive to signal transmission and affects the image quality. Therefore, after meeting the maintenance space, in order to take into account the image quality requirements within the screen, it is advisable to use the groove GV solution shown in Figures 6 and 7.

[0087] Continuing with Figures 6 and 7 , it can be seen that the minimum distance between the stepped structure and the data line 102 in the second direction X is a, the minimum distance between the stepped structure and the connecting line 104 in the first direction Y is b, the distance between the L-shaped structure and the data line 102 in the second direction X is c, and the dimension of the L-shaped structure in the first direction Y is d. a and c are primarily used to ensure that the parasitic capacitance between the gate line 105 and the data line 102 is small and does not interfere with each other. b is used, on the one hand, to ensure that the parasitic capacitance between the gate line 105 and the data line 102 is small and does not interfere with each other, and on the other hand, to ensure that the repair space RS is large and easy to repair. d is used to ensure that the repair space RS is large and prevent the gate line 105 below the repair space RS from being too thin. Therefore, in the present disclosure, a and c can be approximately the same, and b can be greater than or equal to a and less than d. Optionally, a, b, and c are greater than or equal to 5 μm. The value of d can be set based on the actual product wiring space without affecting the aperture ratio and taking into account the small resistance of the gate line 105 and the large repair space RS. This disclosure does not impose any specific restrictions. In addition, it should be understood that with the advancement of technology, the values ​​of a, b, and c may be less than 5 μm.

[0088] It should be noted that in the embodiments provided in the present disclosure, due to the limitations of process conditions or the influence of other factors such as measurement, "approximately the same" may be completely equivalent, or there may be some deviations (for example, a deviation of ±5%). Therefore, as long as the "approximately the same" relationship between related features meets the error allowance, it falls within the scope of protection of the present disclosure.

[0089] It is worth noting that in the present disclosure, the layer where the pixel electrode 101 is located, the layer where the data line 102 is located, the active layer 304 of the transistor 103, and the layer where the gate line 105 are located can be made using separate masks. As shown in Figures 10 and 11, the pixel electrode 101 and the gate line 105 can also be made using the same mask. In this case, due to the obstruction of the gate line 105, the pixel electrode material 101' overlapping with the gate line 105 exists in the layer where the pixel electrode 101 is located; as shown in Figures 12 and 13, the active layer 304 of the transistor 103 and the data line 102 can also be made using the same mask. In this case, due to the obstruction of the components in the layer where the data line 102 is located, the active layer material 304' overlapping with the components in the layer where the data line 102 is located exists in the active layer 304. The present disclosure is explained by taking the pixel electrode 101 and the gate line 105 sharing the mask, and the active layer 304 of the transistor 103 and the data line 102 sharing the mask as an example. Optionally, the material of the active layer 304 may be amorphous silicon (a-Si), polycrystalline silicon (Poly-Si), oxide (eg, indium gallium zinc oxide IGZO), etc.

[0090] In the case where the pixel electrode 101 and the gate line 105 of the present disclosure share a mask plate, and the active layer 304 of the transistor 103 and the data line 102 share a mask plate, as shown in FIG7 , the minimum distance a between the stepped structure and the data line 102 in the second direction X is a=s1+s2+s3, the maximum distance H2 between the stepped structure and the data line 102 in the second direction X is H2=s1+s4+s3, the minimum distance b between the stepped structure and the connecting line 104 in the first direction Y is b=s1+s5+s3, and the distance c between the L-shaped structure and the data line 102 in the second direction X is c=s1+s2+s3, where s1 represents the epitaxial size of the active layer material 304' compared to the pattern of the layer where the data line 102 is located. s2 represents the minimum lateral dimension between the epitaxial boundary of the active layer material 304' compared to the layer pattern where the data line 102 is located, and the epitaxial boundary of the pixel electrode material 101' relative to the gate line 105, s3 represents the epitaxial dimension of the pixel electrode material 101' relative to the gate line 105, s4 represents the maximum lateral dimension between the epitaxial boundary of the active layer material 304' compared to the layer pattern where the data line 102 is located, and the epitaxial boundary of the pixel electrode material 101' relative to the gate line 105, and s5 represents the longitudinal dimension between the epitaxial boundary of the active layer material 304' compared to the layer pattern where the data line 102 is located, and the epitaxial boundary of the pixel electrode material 101' relative to the gate line 105.

[0091] In some embodiments, as shown in Figures 6 and 7, the second pole 302 of the transistor 103 includes a connecting portion 3021 connected to the connecting line 104. To ensure that the maintenance space RS is large, the angle α between the connecting portion 3021 and the connecting line 104 can be set to be an obtuse angle greater than 90° and less than 180°, for example, α is 135°. Continuing to refer to Figures 6 and 7, it can be seen that the second pole 302 of the transistor 103 can also include a first electrode portion 3022 integrally provided with the connecting portion 3021, and the first electrode portion 3022 is U-shaped. Of course, in some embodiments, the first electrode portion 3022 can also be other structures such as I-type, which is not specifically limited in this disclosure.

[0092] In some embodiments, in the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in Figures 14 to 22, a plurality of transfer electrodes 106 may be further included. Optionally, the transfer electrodes 106 and the common electrode 107 are provided in the same layer and with the same material. Optionally, the material of the common electrode 107 may include transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), and gallium zinc oxide (GZO). An insulating layer (for example, the insulating layer includes a gate insulating layer 108 and a passivation layer 109) is provided between the layer where the pixel electrode 101 is located and the layer where the transfer electrodes 106 are located. The transfer electrodes 106 penetrate the insulating layer (for example, the gate insulating layer 108 and the passivation layer 109). 8 and the passivation layer 109) is coupled to the pixel electrode 101 and the first pole 301 of the transistor 103; the via hole v gradually increases in the direction from the layer where the pixel electrode 101 is located to the layer where the switching electrode 106 is located, and in the direction from the first pole 301 of the transistor 103 to the pixel electrode 101 (that is, from right to left in Figure 17), the via hole v is a gradually descending step hole, and the via hole v includes a bottom opening v1 facing the side of the substrate 100; the overlapping area of ​​the bottom opening v1 and the first pole 301 of the transistor 103 is 6 / 11 to 7.2 / 11 of the area of ​​the bottom opening v1. For the convenience of description, the via hole v disclosed in the present invention is referred to as a half via hole.

[0093] In some embodiments, as shown in Figures 16 to 18, the overlapping dimension of the bottom opening v1 and the first electrode 301 of the transistor 103 in the first direction Y is e, and the overlapping dimension of the bottom opening v1 and the first electrode 301 of the transistor 103 in the second direction X is f; the dimension of the bottom opening v1 in the first direction Y is g, and the dimension of the bottom opening v1 in the second direction X is h, wherein f is equal to h and less than g, and e / g is greater than or equal to 6 / 11 and less than or equal to 7.2 / 11, so that the overlapping area of ​​the bottom opening v1 and the first electrode 301 of the transistor 103 is 6 / 11 to 7.2 / 11 of the area of ​​the bottom opening v1.

[0094] Specifically, the exposure accuracy of the exposure machine, process fluctuations, and normal pixel connection and the monitoring of the actual size of the via hole during the factory production process are taken into consideration. In some embodiments, the size h of the bottom opening v1 in the second direction X needs to meet the minimum accuracy of the exposure machine (DI value ≥ 2.8μm, that is, the size of the via hole after exposure and development). According to the CD Bais (critical dimension parameter deviation) of the etching process, the actual size of the via hole can require the size h of the bottom opening v1 in the second direction X to be ≥ 6.5μm; the epitaxial size s6 of the active layer material 304' relative to the first pole 301 is ≥ 1.2μm. When the active layer 304 and the layer where the data line 102 is located are made of separate mask plates, s6 is 0, and the layer where the data line 102 is located is relatively offset by 3μm from the layer where the pixel electrode 101 is located. At the same time, considering the CD Bais (critical dimension parameter deviation) fluctuations, in order to ensure the intact connection between the pixel electrode 101 and the transfer electrode 106, it is necessary to set the bottom opening v1 in the first direction Y beyond the extension distance s6+s7=ge≥5μm of the first pole 301, and the carrying size of the bottom opening v1 and the first pole 301 e>g / 2. At this time, the via CD detection equipment can effectively capture the via size in the D-D' direction. Optionally, e≥6μm, considering the process fluctuation, g≥11μm, therefore, e / g can be between 6 / 11 and 7.2 / 11. Based on this, for the design of the via v disclosed in this disclosure, the area of ​​the bottom opening v1 is h*g≥6.5μm*11μm=71.5μm 2 The overlapping area between the bottom opening v1 and the first electrode 301 is h*e≥6.5μm*6μm=39μm 2 The area of ​​the non-overlapping first electrode 301 is h*(ge)≥6.5μm*5μm=32.5μm 2 .

[0095] Figures 23 to 26 illustrate a design scheme for a via v in the related art. In Figures 23 to 26, s8 represents the distance from the bottom opening v1 of the via v to the active layer 304 in the first direction Y, s9 represents the distance that the active layer material 304' extends beyond the first pole 301 in the first direction Y, s10 represents the dimension of the bottom opening v1 above the first pole 301 in the first direction Y, s11 represents the distance from the bottom opening v1 of the via v to the active layer 304 in the second direction X, s12 represents the distance that the active layer material 304' extends beyond the first pole 301 in the second direction X, and s13 represents the dimension of the bottom opening v1 above the first pole 301 in the second direction X.

[0096] Because the via hole v in the related art is a 3 / 4 via hole design, that is, 3 / 4 of the area of ​​the via hole v overlaps with the first electrode 301, but only 1 / 4 of the area overlaps with the pixel electrode 101. Considering the good contact between the pixel electrode 101 and the transfer electrode 106, the area of ​​the via hole v at 1 / 4 should be as large as possible, while taking into account the accuracy of the exposure machine and process fluctuations. Generally, s8+s9≥5.5μm, which will be larger than the half-via hole design disclosed in the present invention; considering the offset between the via hole v and the first electrode 301, as well as process fluctuations, it is necessary to ensure that s10≥3.5μm, Similarly, s11+s12≥5.5μm. Considering factors such as pixel opening, s13<0.5*(s11+s12+s13). Considering the monitoring of via v on the production line, s13 needs to be close to s11+s12. Therefore, generally, s13≥5μm. Therefore, for the 3 / 4 via v design, s8+s9+s10≥9μm, s11+s12+s13≥10.5μm. Generally, the area of ​​the bottom opening v1 is (s8+s9+s10)*(s11+s12+s13)≥94.5μm 2 The overlapping area between the bottom opening v1 and the first electrode 301 is s10*(s11+s12)+s13*(s8+s9+s10)≥3.5μm*5.5μm+5μm*9μm=64.25μm 2 The area on the non-overlapping first pole 301 is (s8+s9)*(s11+s12)≥5.5μm*5.5μm=30.25μm 2 .

[0097] From the above, it can be seen that the half-via area of ​​the present disclosure is 71.5 μm 2 , the 3 / 4 via area in the related art is 94.5μm 2 Therefore, the area of ​​the half via hole of the present invention is smaller than the area of ​​the corresponding 3 / 4 via hole. Under the same pixel size, the pixel aperture ratio of the present invention is larger. At the same time, the non-overlapping area between the half via hole of the present invention and the first electrode 301 (equivalent to the overlapping area between the half via hole and the pixel electrode 101) is 32.5μm. 2 The overlap area between the relevant 3 / 4 via hole and the pixel electrode 101 is 30.25 μm 2Therefore, the overlapping area between the half-via of the present invention and the pixel electrode 101 is larger than the overlapping area between the related 3 / 4 via and the pixel electrode 101, making the contact and fault tolerance of the half-via of the present invention and the pixel electrode 101 better than the related 3 / 4 via design. In addition, the layer where the first electrode 301 is located is between the layer where the pixel electrode 101 is located and the layer where the transfer electrode 106 is located. Therefore, the hole depth of the via v at the overlap with the pixel electrode 101 is greater than the hole depth at the overlap with the first electrode 301. Compared with the related 3 / 4 via, the half-via of the present invention has a larger deep hole area and a gentler via slope, which is conducive to ensuring a more uniform diffusion of the alignment liquid (such as PI) and reducing the probability of in-plane mura caused by uneven diffusion of PI at the via v.

[0098] PI solution is generally Thickness, as shown in FIG27, when the full via is designed (i.e., the overlapping holes of the transfer electrode 106 and the first pole 301 and the pixel electrode 101 are independent of each other), the PI liquid itself has a certain tension, which is easily hindered by the via during diffusion, causing uneven diffusion, making it difficult for PI to flow into the via, causing PI to accumulate around the via, and the thickness of the PI at the accumulation point may be twice that of the conventional place, or even thicker, which easily causes the formation of surface pitting defects. Combining FIG17, FIG18 and FIG28, it can be seen that p1 / p2 / p3 / p4 represents the distance that the transfer electrode 106 exceeds the via v. The present disclosure adopts a half-via design. When the PI liquid flows to p1 / p2 / p3 / p4, because the via v has a height difference, the PI liquid easily diffuses from p2 into the via v and will not accumulate outside the via v. Finally, around the via v: the thickness of the orientation film formed by PI on the side of the pixel electrode 101 electrically connected to the transistor 103 toward the via v (i.e., the thickness of the orientation film in the p2 area) is greater than the orientation film. The thickness of the film on other sides around the via v (i.e., the thickness of the orientation film in the p1 / p3 / p4 region); inside the via v, the thickness of the orientation film increases in the direction from the first pole 301 of the transistor 103 to the pixel electrode 101 (i.e., the thickness of the orientation film in the s6 region is greater than the thickness in the s7 / e region). In short, the thickness relationship of the orientation film finally formed by PI at various locations is s6>s7 / e>p2>p1 / p3 / p4. Compared with the full via solution shown in Figure 27, the difference in PI thickness at various locations is smaller, and the uniformity of the PI film is better.

[0099] Figures 19 and 26 are actual photos of the half-via and related 3 / 4-via disclosed in this disclosure on the production line, respectively. The passivation layer 109 is a transparent medium. Passivation layer 109 is mounted on a non-metallic medium, showing the background color of the glass substrate, which is difficult to identify. The via v that penetrates the passivation layer 109 is mounted on the first pole 301 of the metal material, showing the metal reflection color. Compared with the color of the glass substrate, the metal reflection is more easily distinguished by the device CCD lens. Therefore, the CD value monitoring of the via v is also to capture the part of the via v mounted on the metal. The black dot MK in Figures 19 and 26 is the point where the via v is actually captured on the production line. Therefore, the present disclosure can also realize in-factory equipment monitoring based on small-sized vias.

[0100] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in Figures 6, 7, and 16, the first electrode 301 of the transistor 103 includes an overlapping portion 3011 that overlaps and is electrically connected to the pixel electrode 101, and a compensation portion 3012 located on the side of the overlapping portion 3011 away from the connecting line 104. The orthographic projection of the compensation portion 3012 on the base substrate 100 overlaps the orthographic projection of the gate line 105 on the base substrate 100. As shown in Figure 6, the data line 102 is electrically connected to two transistors 103. If the compensation portion 3012 is not provided, the parasitic capacitance Cgs between the first electrodes 301 of the two transistors 103 and the gate line 105 will be different due to left-right alignment deviation. This will in turn cause the charging rates of the two pixel electrodes 101 electrically connected to the two transistors 103 to be different, affecting the display effect. By providing the compensation portion 3012 , the present disclosure can ensure that the parasitic capacitance Cgs between the first electrodes 301 of the two transistors 103 and the gate line 105 is the same even when there is a left-right alignment deviation, thereby improving display quality.

[0101] Continuing with reference to FIG6 , FIG7 , and FIG16 , it can be seen that the first electrode 301 of the transistor 103 in the present disclosure may further include a second electrode portion 3013 located on the side of the overlapping portion 3011 facing the connecting line 104 , with the second electrode portion 3013 and the compensation portion 3012 being staggered in the first direction Y. If the compensation portion 3012 is moved to be collinear with the second electrode portion 3013 , the gate line 105 overlapping the compensation portion 3012 must be correspondingly moved toward the pixel electrode 101 to which it is electrically connected. If the non-aperture area is insufficient, the moved gate line 105 will occupy part of the aperture area, thereby affecting the pixel aperture ratio. If the second electrode portion 3013 is moved to be arranged colinearly with the compensation portion 3012, the gate line 105 overlapping with the second electrode portion 3013 and the first electrode portion 3022 accommodating the second electrode portion 3013 need to be moved accordingly away from the pixel electrode 101 to which they are electrically connected. The line width of the first common electrode line 110 between the two gate lines 105 is correspondingly reduced and the line resistance is increased, thereby affecting the uniformity of the common voltage signal.

[0102] In order to take into account both the pixel aperture ratio and the uniformity of the common voltage signal, as shown in Figures 6, 7 and 16, the compensation portion 3012 can be disposed on the side of the second electrode portion 3013 facing the gate line 105; and on the side close to the gate line 105, the boundary of the compensation portion 3012 extending along the second direction X and the boundary of the overlapping portion 3011 extending along the second direction X are substantially collinearly disposed, that is, on the side close to the gate line 105, the distance in the first direction Y between the extension line of the boundary of the compensation portion 3012 and the overlapping portion 3011 extending along the second direction X is within the error range caused by factors such as manufacturing and measurement, for example, less than or equal to 1 μm.

[0103] In some embodiments, as shown in Figure 16, the pixel electrode 101 includes an overlapping portion 1011 that overlaps with the overlapping portion 3011. Optionally, in order to ensure the connection yield between the overlapping portion 1011 and the overlapping portion 3011, the length of the overlapping portion 1011 in the second direction Y can be set to be approximately the same as the length of the overlapping portion 3011 in the second direction X, that is, the lengths of the two are within the error range (for example, ±5%) caused by equipment, measurement, etc.

[0104] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 29 and 30, the base substrate 100 also includes a non-display area BB located on at least one side of the display area AA, and the non-display area BB is provided with multiple signal lines SL, and the multiple signal lines SL include but are not limited to common electrode signal lines CL, feedback signal lines FL, short circuit lines SRL, and ground lines GL. Optionally, an electrostatic unit ESD may also be provided in the non-display area BB, and the electrostatic unit ESD may disperse static electricity to the common electrode signal line CL and the ground line GL through the short circuit line SRL to avoid poor circuits caused by excessive static electricity.

[0105] In the present disclosure, the uniformity of the common voltage signal on the common electrode signal line CL plays a vital role in improving the afterimage, crosstalk and other defects; the feedback signal line FL can be used to monitor the fluctuation of the common voltage signal in the screen. When the feedback signal line FL monitors that the common voltage signal in the screen has fluctuated beyond the preset threshold, it will apply a reverse signal to the screen through other common voltage compensation signal lines, thereby reducing the common voltage signal fluctuation. With the upgrade of products, narrow bezels have become a trend. Generally, the common voltage signal lines CL and feedback signal lines FL on the periphery of the product are wired using the metal of the layer where the gate line 105 is located. Due to the narrow bezel design, the peripheral common voltage signal lines CL and feedback signal lines FL cannot be designed to be very wide, so that the line resistance of the common voltage signal lines CL and feedback signal lines FL is often large, which is not conducive to improving the display quality. The solution is often to increase the film thickness of the layer where the gate line 105 is located to reduce the resistance, and the increase in film thickness often leads to an increase in cost.

[0106] In order to take into account both narrow frame and low cost, as shown in FIG30, the present disclosure can set at least part of the signal line SL (for example, the common voltage signal line CL and the feedback signal line FL located outside the gate drive circuit GOA) to include a first layer wiring SL1 provided in the same layer and material as the gate line 105, and a second layer wiring SL2 provided in the same layer and material as the data line 102. The first layer wiring SL1 of the same signal line SL is connected to the second layer wiring SL2. Because there is a gate insulation layer 108 between the layer where the data line 102 is located and the layer where the gate line 105 is located, the first layer wiring SL1 and the second layer wiring SL2 of the same signal line SL in the present disclosure become parallel. According to the parallel resistance formula R 总 =R gate *R sd / (R gate +R sd ) It can be seen that the parallel resistance of the double-layer wiring is much smaller than the resistance of the single-layer wiring using the gate line 105, thereby achieving narrow line width and low resistance without increasing the film thickness, so the cost is lower.

[0107] In some embodiments, the sealant in the non-display area BB can be irradiated on the side of the array substrate where the base substrate 100 is located to achieve curing of the sealant. Accordingly, in order to transmit the irradiated light, the present disclosure can set the first layer wiring SL1 of the layer where the gate line 105 is located to include a first slit st1, and the second layer wiring SL2 of the layer where the data line 102 is located to include a second slit st2. Optionally, the layer where the gate line 105 is located is located between the layer where the data line 102 is located and the base substrate 100. To ensure that the upper second slit does not block the first slit in the case of alignment fluctuation, the present disclosure can set the orthographic projection of the first slit st1 on the base substrate 100 in the double-layer wiring area to be located within the orthographic projection of the second slit st2 on the base substrate 100. For example, the second slit st2 expands 1.5μm relative to the first slit st1. Optionally, to improve the curing effect of the sealant, the area of ​​the slit in the wiring accounts for 30% to 70%, for example, 35%.

[0108] There is a gate insulating layer 108 between the layer where the gate line 105 is located and the layer where the data line 102 is located. In some embodiments, the gate insulating layer 108 can be punched with a hole to connect the first layer wiring SL1 of the layer where the gate line 105 is located with the second layer wiring SL2 of the layer where the data line 102 is located. If a separate via mask is produced for the gate insulating layer 108, it will increase development costs, increase the factory's production process, and reduce production capacity. Therefore, a via mask can be produced for the gate insulating layer 108 and the passivation layer 109. Through a single exposure, a shallow hole penetrating to the layer where the data line 102 is located and a deep hole penetrating to the layer where the gate line 105 is located or the layer where the pixel electrode 101 is located can be formed. Based on this, as shown in Figure 30, the double-layer wiring disclosed in the present invention can use a single exposure to realize at least one deep hole V2 overlapping with the first layer wiring SL1, and at least one shallow hole V3 overlapping with the second layer wiring SL2, and use the overlapping electrode 111 of the same layer and the same material as the common electrode 107 to cover the deep hole V2 and the shallow hole V3, so as to connect the first layer wiring SL1 with the second layer wiring SL2.

[0109] In some embodiments, as shown in FIG31 , the non-display area BB includes a first non-display area BB1 for binding a driving circuit (e.g., a chip-on-film (COF) or a flexible circuit board (FPC)), and a second non-display area BB2 and a third non-display area BB3 disposed opposite to each other, and the second non-display area BB2 and the third non-display area BB3 are connected to the first non-display area BB1, respectively. The second non-display area BB2 and the third non-display area BB3 of conventional products are usually designed to be of the same size, thereby bringing visual beauty. Continuing to refer to FIG29 , it can be seen that the second non-display area BB2 and the third non-display area BB3 may include a gate drive circuit (GOA) signal line area (i.e., an area of ​​width i), a GOA area (i.e., an area of ​​width j), a common electrode-related signal line area (i.e., an area of ​​width k), a dummy pixel area (i.e., an area of ​​width l), etc., from the edge of the substrate to the display area AA. However, in some special applications, the widths of the second non-display area BB2 and the third non-display area BB3 need to be different. In this case, the design of the second non-display area BB2 and the third non-display area BB3 cannot be exactly the same.

[0110] For products with different sizes of the second non-display area BB2 and the third non-display area BB3, it is generally ensured that the number of dummy pixel columns in the second non-display area BB2 and the third non-display area BB3 is the same (that is, the width l of the dummy pixel area is the same). By adjusting the width i of the GOA signal line area, the width j of the GOA area, and the width k of the common electrode-related signal line area, the sizes of the second non-display area BB2 and the third non-display area BB3 are achieved to be inconsistent.

[0111] However, in actual design, if the width i of the GOA signal line area is adjusted to achieve inconsistent sizes between the second non-display area BB2 and the third non-display area BB3, the GOA signal lines in the left second non-display area BB2 and the third non-display area BB3 will be wider on one side and thinner on the other side, and there will be differences in resistance, etc., which can easily cause differences in left and right displays, affecting image quality and performance.

[0112] If the size inconsistency between the second non-display area BB2 and the third non-display area BB3 is achieved by adjusting the width j of the GOA area, this can be achieved by adjusting the distance between the GOA tubes while ensuring that the GOA tubes are the same size. Although the GOA tubes remain the same, the line resistance and other factors connecting the GOA tubes are inconsistent, which can easily lead to differences in the signals output by the left and right GOAs, resulting in poor display.

[0113] If the width k of the common electrode-related signal line area is adjusted to achieve inconsistent sizes between the second non-display area BB2 and the third non-display area BB3, the line widths of the common electrode-related signal lines in the second non-display area BB2 and the third non-display area BB3 will be inconsistent, resulting in inconsistent line resistance, which will cause differences in the signals of the common electrode-related signal lines in the left and right areas, causing abnormal display quality.

[0114] From the above, it can be seen that for products with inconsistent size requirements for the second non-display area BB2 and the third non-display area BB3, adjusting the width i of the GOA signal line area, the width j of the GOA area, and the width k of the common electrode related signal line area will affect the screen display.

[0115] For products in which the second non-display area BB2 and the third non-display area BB3 have different sizes, the present disclosure proposes a new one. Specifically, in the present disclosure, the width i of the GOA signal line area, the width j of the GOA area, and the width k of the common electrode-related signal line area in the second non-display area BB2 and the third non-display area BB3 adopt the same design, so that the line widths of the signal lines SL transmitting the same signal in the second non-display area BB2 and the third non-display area BB3 are roughly the same, and by adjusting the number of virtual pixel columns in the second non-display area BB2 and the third non-display area BB3, the different sizes of the second non-display area BB2 and the third non-display area BB3 are achieved.

[0116] Specifically, assuming that the width of the second non-display area BB2 is m, the width of the third non-display area BB3 is n, m≠n, and the non-display area here is only the frame of the bare panel, not the frame of the assembled backlight module. In the present disclosure, the GOA signal line area, the GOA area, and the common electrode related signal line area adopt the same design in the second non-display area BB2 and the third non-display area BB3, and are i, j, and k respectively. 3.3 Assuming that the pixel size is H*V, the size of a sub-pixel (i.e., 1 dot) is 1 / 3H*V (for conventional products, H=V, and for some special products, H is not equal to V), the number of virtual pixel columns in the second non-display area BB2 is (mijk) / (1 / 3H), and the number of virtual pixel columns in the third non-display area BB3 is (nijk) / (1 / 3H). By fine-tuning the size of i, j, and k, the number of virtual pixel columns in the second non-display area BB2 and the third non-display area BB3 can be made an integer, which is convenient for layout drawing and confirmation and drawing of subsequent process drawings. Because dummy pixels are designed in the non-display area, they are covered by black matrix (for three-sided narrow-border products) or ink (for four-sided narrow-border products), without affecting the display area AA. Furthermore, a single row of dummy pixels can typically effectively protect the display pixels in the display area AA during development and etching processes.

[0117] It should be noted that the only difference between the dummy pixel disclosed in the present invention and the conventional pixel is that the pixel electrode 101 of the dummy pixel and the first electrode 301 of the transistor 103 are insulated from each other, that is, no via v for connecting the pixel electrode 101 and the first electrode 301 is provided in the dummy pixel. This not only prevents the dummy pixel from being accidentally lit, but also helps to ensure more uniform PI diffusion.

[0118] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in Figures 5, 10, and 11, two gate lines 105 are included between two adjacent rows of pixel electrodes 101 arranged along the first direction Y, wherein one gate line 105 is connected to a portion of the pixel electrodes 101 in the adjacent row of pixel electrodes 101, and the other gate line 105 is connected to a portion of the pixel electrodes 101 in the adjacent row of pixel electrodes 101, and the pixel electrodes 101 connected by the two gate lines 105 are staggered in the second direction X. That is, the present disclosure adopts a dual-gate pixel structure, which can effectively reduce the number of data lines 102, and accordingly reduce the number of source driver chips, thereby reducing costs.

[0119] In some embodiments, as shown in Figures 5, 10, 11 and 13, a first common electrode line 110 is provided in the layer where the gate line 105 is located, and a second common electrode line 112 is provided in the layer where the data line 102 is located, wherein the first common electrode line 110 is located between the two gate lines 105, and the second common electrode line 112 and the data line 102 are alternately arranged in the gap where the pixel electrode 101 extends along the first direction Y, and the second common electrode line 112 is connected to the first common electrode line 110, which is beneficial to improving the uniformity of the common voltage signal.

[0120] In some embodiments, as shown in Figures 5, 11, and 13 to 15, the first common electrode line 110 includes an oblique portion 1101 intersecting the first direction Y, and a straight portion 1102 extending along the second direction X and integrally provided with the oblique portion 1101; the second common electrode line 112 includes a main body 1121 extending along the first direction Y, and a branch portion 1122 located on one side of the main body 1121; wherein the orthographic projection of the main body 1121 on the base substrate 100 intersects the orthographic projection of the oblique portion 1101 on the base substrate 100, and the branch portion 1122 is perpendicular to the base substrate 100 and the oblique portion 1101 and the straight portion 1102. The branches 1122 overlap with each other in the direction of the straight portion 1102, and the branch portion 1122 is connected to the straight portion 1102. Optionally, the branch portion 1122 can be connected to the straight portion 1102 through the common electrode 107. Specifically, the branch portion 1122 and the straight portion 1102 are connected to the common electrode 107 using a through hole PTH. The through hole PTH penetrates the passivation layer 109 at the branch portion 1122 and penetrates the passivation layer 109 and the gate insulation layer 108 at the straight portion 1102. By providing the second common electrode line 112 with a branch portion 1122 and connecting it to the straight portion 1102, the process difficulty can be reduced and the connection yield can be improved compared to using the oblique portion 1101 to connect it to the main body 1121. In addition, the branch portion 1122 can be connected to the straight portion 1102 through the common electrode 107, which can further improve the uniformity of the common voltage signal.

[0121] 5 , 11 , 13 and 15 , it can be seen that in order to ensure that the common electrode 107 is continuously arranged in both the first direction Y and the second direction X, the orthographic projection of the common electrode 107 on the base substrate 100 can be arranged to cover the orthographic projection of the second common electrode line 112 on the base substrate 100 , the orthographic projection of the common electrode 107 on the base substrate 100 covers the orthographic projection of the data line 102 between the row gaps on the base substrate 100 , and the orthographic projection of the common electrode 107 on the base substrate 100 does not overlap with the orthographic projection of the gate line 105 between the main body 1121 on the base substrate 100. 5 , 11 and 13 , the data line 102 has a smaller line width than the gate line 105. Therefore, the orthographic projection of the common electrode 107 on the base substrate 100 and the orthographic projection of the gate line 105 between the trunk portion 1121 on the base substrate 100 do not overlap, which can effectively reduce the load on the gate line 105. At the same time, given that the data line 102 has a smaller line width, even if the orthographic projection of the common electrode 107 on the base substrate 100 covers the orthographic projection of the data line 102 on the base substrate 100 between the row gaps, the increase in the load on the data line 102 is limited.

[0122] In some embodiments, as shown in Figures 5, 10, 15, and 32, the common electrode 107 includes a plurality of slit electrode portions 1071. The orthographic projections of the slit electrode portions 1071 on the base substrate 100 overlap with the orthographic projections of the pixel electrodes 101 on the base substrate 100, so that the electric field between the slit electrode portions 1071 and the pixel electrodes 101 controls liquid crystal deflection to achieve image display. In some embodiments, the slit electrode portions 1071 can be a dual-domain electrode as shown in Figure 15, or a cross-shaped electrode, etc., which is not limited in this disclosure.

[0123] Based on the same inventive concept, embodiments of the present disclosure provide a display panel, as shown in Figures 33 and 34 , comprising the array substrate 001 described above, and an opposing substrate 002 disposed opposite the array substrate 001. In some embodiments, the opposing substrate 002 may include a substrate 200 and a black matrix 201. The black matrix 201 has a grid-like structure. Optionally, the data lines 102, transistors 103, and gate lines 105 are located within the black matrix region. Color resists may be disposed within the grid of the black matrix 201. Optionally, the color resists include a red color resist corresponding to the red sub-pixel region R, a blue color resist corresponding to the blue sub-pixel region B, and a green color resist corresponding to the green sub-pixel region G.

[0124] In some embodiments, as shown in Figures 33 and 34 , the display panel provided by the embodiments of the present disclosure may further include a liquid crystal layer 003 between an array substrate 001 and an opposing substrate 002. In some embodiments, a first polarizer 004 may be provided on a side of the array substrate 001 away from the opposing substrate 002, and a second polarizer 005 may be provided on a side of the opposing substrate 002 away from the array substrate 001. The polarization directions of the first polarizer 004 and the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are readily understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure.

[0125] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, as shown in Figures 35 and 36, including the above-mentioned display panel PNL provided in the embodiment of the present disclosure, and a backlight module BLU located on the light incident side of the display panel PNL. The backlight module BLU can be a direct-type backlight module or an edge-type backlight module. Optionally, the edge-type backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser and a brightening film stacked on the light-emitting side of the matrix light source, etc., and the reflective sheet includes an opening arranged opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source can be light-emitting devices (LEDs), such as quantum dot light-emitting devices.

[0126] In some embodiments, the lamp beads can also be micro light-emitting devices (such as Mini LED, Micro LED), etc. Submillimeter or even micron-scale micro light-emitting devices are self-luminous devices like organic light-emitting devices (OLED). Like organic light-emitting devices, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angle. And because the light emission of inorganic light-emitting devices is based on metal semiconductors with more stable properties and lower resistance, compared with organic light-emitting devices based on organic matter, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life. And when the micro light-emitting device is used as a backlight source, it can achieve a more precise dynamic backlight effect. While effectively improving the brightness and contrast of the screen, it can also solve the glare phenomenon caused by traditional dynamic backlight between the bright and dark areas of the screen, thereby optimizing the visual experience.

[0127] In some embodiments, the above-mentioned display device provided in the embodiments of the present disclosure may be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function. Optionally, the display device provided in the present disclosure includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip is a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may further include a memory, a power module, etc., and realize power supply and signal input and output functions through additionally provided wires, signal lines, etc. For example, the control chip may further include hardware circuits and computer executable code, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc. In addition, those skilled in the art will understand that the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure. In other words, the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

[0128] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0129] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: a base substrate, the base substrate comprising a display area; A plurality of pixel electrodes are arranged in an array in the display area; a plurality of data lines extending along a first direction between the pixel electrodes; a plurality of transistors, located between adjacent pixel electrodes arranged along the first direction, wherein first electrodes of the transistors are connected to the pixel electrodes; a plurality of connecting lines located between adjacent pixel electrodes arranged along the first direction, at least some of the connecting lines connecting the data line and the second electrode of the transistor; A plurality of gate lines extend between the pixel electrodes along a second direction, the second direction intersecting the first direction, the gate lines being connected to the gates of the transistors, the gate lines comprising grooves, the openings of the grooves facing the pixel electrodes to which the gate lines are electrically connected through the transistors, the connecting lines being provided on the opening sides of the grooves, the grooves comprising a first portion located on a side of the data line facing the connecting line, and a second portion located on a side of the data line away from the connecting line, the orthographic projection area of the first portion on the base substrate being greater than the orthographic projection area of the second portion on the base substrate.

2. The array substrate according to claim 1, wherein: The boundary of the gate line at the first portion is a step structure, and the boundary of the gate line at the second portion is an L-shaped structure.

3. The array substrate according to claim 2, wherein: The minimum distance between the stepped structure and the data line in the second direction is a, the minimum distance between the stepped structure and the connecting line in the first direction is b, the distance between the L-shaped structure and the data line in the second direction is c, and the size of the L-shaped structure in the first direction is d, wherein a and c are approximately the same, and b is greater than or equal to a and less than d.

4. The array substrate according to any one of claims 1 to 3, wherein: The orthographic projection of the connecting line on the base substrate is located within the orthographic projection of the first part on the base substrate.

5. The array substrate according to any one of claims 1 to 3, wherein: The second electrode of the transistor includes a connecting portion connected to the connecting line, and an angle between the connecting portion and the connecting line is an obtuse angle.

6. The array substrate according to any one of claims 1 to 5, wherein: It also includes a plurality of switching electrodes, and an insulating layer located between the layer where the pixel electrodes are located and the layer where the switching electrodes are located; The switching electrode is coupled to the pixel electrode and the first electrode of the transistor through a via hole penetrating the insulating layer; The via hole gradually increases in size in a direction from the layer where the pixel electrode is located to the layer where the switching electrode is located, and the via hole includes a bottom opening facing one side of the base substrate; An overlapping area between the bottom opening and the first electrode of the transistor is 6 / 11 to 7.2 / 11 of an area of the bottom opening.

7. The array substrate according to claim 6, wherein: The overlapping dimension of the bottom opening and the first electrode of the transistor in the first direction is e, and the overlapping dimension of the bottom opening and the first electrode of the transistor in the second direction is f; the dimension of the bottom opening in the first direction is g, and the dimension of the bottom opening in the second direction is h, wherein f is equal to h and less than g, and e / g is greater than or equal to 6 / 11 and less than or equal to 7.2 / 11.

8. The array substrate according to claim 6 or 7, wherein: In the direction from the first electrode of the transistor to the pixel electrode, the via hole is a step hole that gradually descends.

9. The array substrate according to any one of claims 1 to 8, wherein: The first electrode of the transistor includes a lap portion overlapping and electrically connected to the pixel electrode, and a compensation portion located on a side of the lap portion away from the connecting line, and the orthographic projection of the compensation portion on the base substrate overlaps with the orthographic projection of the gate line on the base substrate.

10. The array substrate according to claim 9, wherein: The first electrode of the transistor further includes an electrode portion located on a side of the overlapping portion facing the connecting line, and the electrode portion and the compensation portion are staggered in the first direction.

11. The array substrate according to claim 10, wherein: The compensation portion is located on a side of the electrode portion facing the gate line; and on a side close to the gate line, a boundary of the compensation portion extending along the second direction and a boundary of the overlapping portion extending along the second direction are substantially collinearly arranged.

12. The array substrate according to any one of claims 9 to 11, wherein: The pixel electrode includes a connecting portion overlapping the overlapping portion, and a length of the overlapping portion in the second direction is substantially the same as a length of the connecting portion in the second direction.

13. The array substrate according to any one of claims 1 to 12, wherein: The base substrate also includes a non-display area located on at least one side of the display area, and the non-display area is provided with a common electrode signal line and a feedback signal line. The common electrode signal line and the feedback signal line respectively include a first layer of wiring arranged on the same layer as the gate line, and a second layer of wiring arranged on the same layer as the data line and connected to the first layer of wiring.

14. The array substrate according to claim 13, wherein: The layer where the gate lines are located is located between the layer where the data lines are located and the base substrate; The first-layer wiring includes a first slit, the second-layer wiring includes a second slit, and the orthographic projection of the first slit on the base substrate in the double-layer wiring region is located within the orthographic projection of the second slit on the base substrate.

15. The array substrate according to claim 13 or 14, wherein: The non-display area includes a first non-display area for binding a driving circuit, and a second non-display area and a third non-display area opposite to each other, and the second non-display area and the third non-display area are respectively connected to the first non-display area; In the second non-display area and the third non-display area, the signal lines transmitting the same signal have substantially the same line width.

16. The array substrate according to claim 15, wherein: It also includes dummy pixel columns located on the side of the signal line facing the display area in the second non-display area and the third non-display area, and the number of dummy pixel columns in the second non-display area is different from the number of dummy pixel columns in the third non-display area.

17. The array substrate according to claim 8, wherein: An orientation film is also included, and around the via hole, the thickness of the orientation film on the side of the via hole facing the pixel electrode electrically connected to the transistor is greater than the thickness of the orientation film on other sides around the via hole.

18. The array substrate according to claim 17, wherein: In the via hole, the thickness of the alignment film increases in a direction from the first electrode of the transistor to the pixel electrode.

19. A display panel, wherein: The invention comprises the array substrate according to any one of claims 1 to 18, and an opposite substrate arranged opposite to the array substrate.

20. A display device comprising the display panel according to claim 19, and a backlight module located on a light incident side of the display panel.

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