Thin film forming method

Abstract

The present invention relates to a thin film forming method and, more specifically, to a thin film forming method for forming a group III-V thin film on a substrate. A thin film forming method according to an embodiment of the present invention is directed to a method for forming a group III-V thin film on a substrate including a structure layer, wherein the method comprises the steps of: supplying a source gas containing a group III element to the structure layer; and supplying a reactant gas containing a group V element to the structure layer.

Description

Thin film formation method

[0001] The present invention relates to a method for forming a thin film, and more particularly, to a method for forming a group 3-5 thin film on a substrate.

[0002] Transistors are used to drive semiconductor devices such as logic devices and memory devices.

[0003] Meanwhile, with the advancement of semiconductor technology, the speed and integration of semiconductor devices are rapidly progressing, and accordingly, the demand for pattern miniaturization and high-precision pattern dimensions is increasing.

[0004] Traditionally, amorphous or crystalline silicon has been used as the channel layer of transistors. However, using silicon as the channel layer has the disadvantages of relatively slow reaction times and relatively high power loss. Therefore, active research is being conducted to utilize Group III-V thin films, which enable rapid signal switching and low energy loss, as the channel layer of transistors.

[0005] (Prior art literature)

[0006] Korean Patent Publication No. 10-2019-0074774

[0007] The present invention provides a method for forming a thin film capable of forming a group 3-5 thin film used as a channel layer of a transistor at low temperature.

[0008] A method for forming a thin film according to an embodiment of the present invention is a method for forming a group 3-5 thin film on a substrate including a structural layer having an interlayer insulating layer, a conductive via penetrating all or part of the interlayer insulating layer, a conductive line connected to the conductive via, and source and drain electrodes formed on an upper portion of the interlayer insulating layer, the method comprising: a source gas supply step of supplying a source gas containing a group 3 element to the structural layer to adsorb the source gas on the source and drain electrodes; a reactant gas supply step of supplying a reactant gas containing a group 5 element to the structural layer to react the source gas adsorbed on the source and drain electrodes with the reactant gas; and a repeating step of repeating the source gas supply step and the reactant gas supply step a plurality of times.

[0009] In addition, a method for forming a thin film according to an embodiment of the present invention may include a method for forming a group 3-5 thin film on a substrate including a structural layer having an interlayer insulating layer, a conductive via penetrating all or part of the interlayer insulating layer, a conductive line connected to the conductive via, a gate electrode formed on an upper portion of the interlayer insulating layer, and a gate insulating film formed on the gate electrode, the method comprising: a source gas supply step of supplying a source gas containing a group 3 element to the structural layer to adsorb the source gas on the gate insulating film; a reactant gas supply step of supplying a reactant gas containing a group 5 element to the structural layer to react the source gas adsorbed on the gate insulating film with the reactant gas; and a repeating step of repeating the source gas supply step and the reactant gas supply step a plurality of times.

[0010] Between the source gas supply step and the reactant gas supply step, a step of forming hydrogen plasma in a reaction space in which the substrate is provided may be further included.

[0011] After the above reactant gas supply step, the method may further include a step of forming hydrogen plasma in a reaction space where the substrate is provided.

[0012] The method may further include a step of forming hydrogen plasma in a reaction space where the substrate is provided while supplying the reactant gas.

[0013] Between the source gas supply step and the reactant gas supply step, a step of supplying a purge gas to a reaction space in which the substrate is provided may be further included.

[0014] Between the source gas supply step and the reactant gas supply step, a step of pumping the source gas supplied to the reaction space in which the substrate is provided may be further included.

[0015] Between the above source gas supply step and the above reactant gas supply step, a purge gas may not be supplied to the reaction space in which the substrate is provided.

[0016] The above group 3 elements may include one or more of gallium (Ga), indium (In), and aluminum (Al).

[0017] The above group 5 element may include one or more of nitrogen (N), arsenide (As), and phosphorus (P).

[0018] The above 3-5 group thin film may include a channel layer of a transistor.

[0019] According to an embodiment of the present invention, a group 3-5 thin film used as a channel layer of a transistor can be formed at a low temperature of 500°C or less.

[0020] That is, by forming a group 3-5 thin film used as a channel layer of a transistor through an atomic layer deposition process, a semiconductor layer including a group 3-5 thin film crystallized at low temperature can be formed.

[0021] In addition, by using the semiconductor layer formed in this way as a channel layer, a transistor capable of fast signal switching and having a low energy loss rate can be manufactured.

[0022] FIG. 1 is a drawing exemplarily showing a semiconductor device according to an embodiment of the present invention.

[0023] FIG. 2 is a drawing showing a semiconductor device formed according to an embodiment of the present invention.

[0024] FIG. 3 is a schematic drawing showing a substrate processing device according to an embodiment of the present invention.

[0025] Figure 4 is a drawing schematically showing a thin film forming method according to an embodiment of the present invention.

[0026] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. These embodiments of the present invention are provided solely to ensure complete disclosure of the present invention and to fully inform those skilled in the art of the scope of the invention.

[0027] When a component, such as a film, region, or substrate, is referred to as being "on" another component throughout the specification, it can be interpreted that the component is either directly "on" the other component, or there may be other components intervening therebetween.

[0028] Additionally, relative terms such as "upper" or "lower" may be used herein to describe the relative relationship of certain elements to other elements as depicted in the drawings. It should be understood that relative terms are intended to encompass other orientations of the elements in addition to the orientation depicted in the drawings. The drawings may be exaggerated for the purpose of illustrating the invention in detail, and like reference numerals throughout the drawings designate like elements.

[0029]

[0030] FIG. 1 is a drawing exemplarily showing a semiconductor device according to an embodiment of the present invention.

[0031] Referring to FIG. 1, a method for forming a thin film according to an embodiment of the present invention forms a group 3-5 thin film used as a channel layer of a transistor (T), and such a transistor (T) can be included in a memory device such as a DRAM (Dynamic Random Access Memory). DRAM is a type of volatile semiconductor memory device commonly used in electronic devices such as computers and portable terminals.

[0032] A DRAM may include multiple memory cells arranged in multiple rows and columns, each of which may include, for example, one transistor (T) and one capacitor (C).

[0033] As such, a DRAM may include a word line and a bit line. Here, the word line may be connected to or included in the gate line of a transistor (T), and determines whether a memory cell is used. Meanwhile, the bit line may be connected to or included in the source electrode or drain electrode of the transistor (T), and serves to confirm the value (0 or 1) of the stored memory.

[0034] Meanwhile, Group 3-5 thin films refer to thin films made by combining Group 3 elements and Group 5 elements on the periodic table. Such Group 3-5 thin films may include, but are not limited to, gallium nitride (GaN) thin films or gallium arsenide (GaAs) thin films, and may of course include various thin films made by combining Group 3 elements and Group 5 elements.

[0035] Hereinafter, a case in which a thin film formation method according to an embodiment of the present invention is used to form a channel layer of a transistor (T) included in a DRAM is exemplarily described. However, it is obvious that the thin film formation method according to an embodiment of the present invention can be used not only for DRAM but also for manufacturing various circuits for independently driving each cell or pixel in semiconductor devices, liquid crystal displays, etc.

[0036]

[0037] FIG. 2 is a drawing showing a semiconductor device formed according to an embodiment of the present invention.

[0038] As illustrated in FIG. 2, a semiconductor device according to an embodiment of the present invention includes a substrate (100), a front end of line structure (200) formed on the substrate (100) by a front end of line (FEOL) process, and a back end of line structure (300) formed on the front end of line structure (200) by a back end of line (BEOL) process.

[0039] Here, the front-end-of-line process means a process of forming an active component of a semiconductor device during the manufacture of the semiconductor device, and the front-end-of-line structure (200) means a structure formed by such a front-end-of-line process.

[0040] In addition, the back-end-of-line process refers to a process of forming conductive vias, conductive lines, interlayer insulating layers, etc. for electrically connecting various components in the front-end-of-line process, and the back-end-of-line structure (300) refers to a structure formed by such a back-end-of-line process.

[0041] The back-end of the line structure (300) may include a plurality of interlayer insulating layers. Conductive vias may be formed to vertically penetrate all or part of at least one interlayer insulating layer, and conductive lines may be formed on the interlayer insulating layer by being electrically connected to the conductive vias. In this way, the back-end of the line structure (300) formed by stacking a plurality of interlayer insulating layers may include a plurality of conductive lines stacked with the interlayer insulating layers interposed therebetween, and a transistor (T) connected to a capacitor of a DRAM may be formed between the conductive lines. At this time, when a high voltage is applied to the gate electrode of the transistor (T), the capacitor (C) is charged, so that the memory may have a value of 1, and when a low voltage is applied to the gate electrode of the transistor (T), the capacitor (C) is discharged, so that the memory may have a value of 0.

[0042] The present invention relates to a method for forming a group 3-5 thin film of a transistor (T) included in at least one of a front end of line structure (200) and a back end of line structure (300), and more particularly, to a method for forming a channel layer of a transistor (T) included in at least one of a front end of line structure (200) and a back end of line structure (300) as a group 3-5 thin film at low temperature. Hereinafter, a substrate processing apparatus used in an embodiment of the present invention and a thin film forming method using the same will be described in detail.

[0043]

[0044] FIG. 3 is a schematic drawing showing a substrate processing device according to an embodiment of the present invention.

[0045] Referring to FIG. 3, a substrate processing device according to an embodiment of the present invention is a device for forming a thin film, for example, a group 3-5 thin film, and includes a chamber (10), a substrate support unit (20) provided within the chamber (10) to support a substrate (100) provided within the chamber (10), a gas injection unit (30) provided within the chamber (10) to face the substrate support unit (20) and to inject a process gas toward the substrate support unit (20), and an RF power source (50) for supplying power to generate plasma within the chamber (10). In addition, the substrate processing device may include a gas supply unit (40) for supplying a process gas, and may further include a control unit (not shown) for controlling the RF power source (50).

[0046] The chamber (10) provides a predetermined reaction space and maintains it airtight. The chamber (10) may include a body (12) having a predetermined reaction space, including a flat surface of approximately circular or rectangular shape and a side wall extending upward from the flat surface, and a cover (14) positioned on the body (12) in an approximately circular or rectangular shape to maintain the chamber (10) airtight. However, the chamber (10) is not limited thereto and may be manufactured in various shapes corresponding to the shape of the substrate (100).

[0047] An exhaust port (not shown) may be formed in a predetermined area on the lower surface of the chamber (10), and an exhaust pipe (not shown) connected to the exhaust port may be provided on the outside of the chamber (10). In addition, the exhaust pipe may be connected to an exhaust device (not shown). A vacuum pump such as a turbo molecular pump may be used as the exhaust device. Therefore, the inside of the chamber (10) may be vacuum-sucked to a predetermined reduced pressure atmosphere, for example, a predetermined pressure of 0.1 mTorr or less, by the exhaust device. The exhaust pipe may be installed on the side of the chamber (10) below the substrate support member (20) described later in addition to the lower surface of the chamber (10). In addition, it goes without saying that a plurality of exhaust pipes and corresponding exhaust devices may be further installed in order to reduce the exhaust time.

[0048] Meanwhile, a substrate (100) provided into a chamber (10) for a thin film formation process may be mounted on the substrate support member (20). Here, the substrate (100) may be a substrate whose structural layer is exposed in the process of forming a front end of line structure (200) or a back end of line structure (300). Hereinafter, a thin film formation process is described as an example of performing a thin film formation process on a substrate whose structural layer is exposed in the process of forming a back end of line structure (300), but this can of course be equally applied to performing a thin film formation process on a substrate whose structural layer is exposed in the process of forming a front end of line structure (200).

[0049] In this case, the substrate (100) may be a substrate (100) on which a front end-of-line structure (200) is formed, and on which at least one interlayer insulating layer included in a back end line structure (300) is formed on the front end-of-line structure (200). As described above, the back end-of-line structure (300) may include a plurality of interlayer insulating layers, and at this time, a conductive via may be formed to vertically penetrate all or part of at least one interlayer insulating layer, and a conductive line may be formed on the interlayer insulating layer by being electrically connected to the conductive via. During the back end-of-line process, such a conductive via and a conductive line may be formed on the interlayer insulating layer, and a thin film transistor (T) may be formed on the interlayer insulating layer on which the conductive via and the conductive line are formed.

[0050] Meanwhile, as described above, the group 3-5 thin film is used as a channel layer of the transistor (T). Accordingly, a predetermined process may be performed to form a group 3-5 thin film used as a channel layer of the transistor (T) on the interlayer insulating layer on which the conductive via and the conductive line are formed. The transistor (T) includes a top gate type in which source and drain electrodes, a channel layer, a gate insulating film, and a gate electrode are sequentially laminated from the bottom, and a bottom gate type in which a gate electrode, a gate insulating film, a channel layer, and source and drain electrodes are sequentially laminated. At this time, before forming the channel layer of the transistor (T), in the case of the top gate type, the source and drain electrodes need to be formed in advance on the interlayer insulating layer, and in the case of the bottom gate type, the gate electrode and the gate insulating film need to be formed in advance on the interlayer insulating layer. Accordingly, on the interlayer insulating layer where the conductive via and conductive line are formed, source and drain electrodes or gate electrodes and gate insulating films may be formed, and the layer where the source and drain electrodes or gate electrodes and gate insulating films are formed on the interlayer insulating layer to form the channel layer of the transistor (T) is defined as a structural layer.

[0051] Accordingly, a substrate (100) with such a structural layer exposed can be mounted on the substrate support member (20) to form a 3-5 group thin film. Meanwhile, the substrate support member (20) can be equipped with, for example, an electrostatic chuck to hold the substrate (100) by electrostatic force so that the substrate (100) can be mounted and supported, or the substrate (100) can be supported by vacuum suction or mechanical force.

[0052] The substrate support (20) may be provided in a shape corresponding to the shape of the substrate (100), for example, a circle or a square. The substrate support (20) may include a substrate support (22) on which the substrate (100) is mounted, and an elevator (24) disposed below the substrate support (22) to move the substrate support (22) up and down. Here, the substrate support (22) may be manufactured to be larger than the substrate (100), and the elevator (24) is provided to support at least one area of ​​the substrate support (22), for example, the center, and when the substrate (100) is mounted on the substrate support (22), the substrate support (22) may be moved closer to the gas injection unit (20). In addition, a heater (not shown) may be installed inside the substrate support. The heater generates heat to a predetermined temperature to heat the substrate support (22) and the substrate (100) mounted on the substrate support (22), thereby allowing a thin film to be uniformly deposited on the substrate (100).

[0053] The gas supply unit (40) may be installed at least partially outside the chamber (10) and supplies gas to the gas injection unit (30). The gas supply unit (40) may include a source gas supply unit for supplying a source gas and a reactant gas supply unit for supplying a reactant gas. In addition, the gas supply unit (40) may further include a purge gas supply unit for supplying an inert gas such as argon (Ar) gas or a gas with low reactivity such as nitrogen (N2) gas. In addition, the gas supply unit (40) may further include a process gas supply unit for supplying hydrogen (H2) gas.

[0054] Meanwhile, the gas supply unit (40) does not necessarily supply one gas to the gas injection unit (30), but may be configured to supply multiple gases simultaneously or supply a gas selected from among multiple gases.

[0055] The source gas supply unit may be configured to supply a gas containing a Group 3 element as a source gas, and the reactant gas supply unit may supply a gas containing a Group 5 element as a reactant gas. Here, the Group 3 element may include one or more of gallium (Ga), indium (In), and aluminum (Al). In addition, the Group 5 element may include one or more of nitrogen (N), arsenide (As), and phosphorus (P). For example, when forming a gallium nitride (GaN) thin film as a Group 3-5 thin film, the source gas may include trimethylgallium (TMGa) gas or triethylgallium (TMGa) gas, and the reactant gas may include ammonia (NH3) gas.

[0056] A gas injection unit (30) is provided at the upper side inside the chamber (10) and injects a process gas toward the substrate (100). The gas injection unit (30) is connected at the upper side to a gas supply unit (40), and a plurality of injection holes (not shown) for injecting the process gas onto the substrate (100) are formed at the lower side. In this way, a source gas supply path for injecting and supplying a source gas onto the substrate and a reactant gas supply path for injecting and supplying a reactant gas onto the substrate are formed inside the gas injection unit (30). The source gas supply path and the reactant gas supply path are formed to be independent and separate from each other, so that the source gas and the reactant gas can be supplied onto the substrate separately without being mixed within the gas injection unit (30).

[0057] The gas injection unit (30) can be manufactured in a shape corresponding to the shape of the substrate (100), and can be manufactured in an approximately circular or rectangular shape. Here, the gas injection unit (30) can be provided at a predetermined distance from the side wall and the cover (14) of the chamber (10). In addition, when forming plasma in the reaction space within the chamber (10), the gas injection unit (30) can receive power from an RF power source (50) and act as an upper electrode.

[0058] The RF power source (50) supplies power to form plasma. That is, the RF power source (50) supplies power to generate plasma in the reaction space within the chamber (10). For example, the RF power source (50) supplies power to either the substrate support (20) or the gas injection unit (30), and the other of the substrate support (20) or the gas injection unit (30) is grounded, so that plasma can be formed in the space between the substrate support (20) and the gas injection unit (30).

[0059]

[0060] Figure 4 is a drawing schematically showing a thin film forming method according to an embodiment of the present invention.

[0061] Referring to FIG. 4, a method for forming a thin film according to an embodiment of the present invention is a method for forming a group 3-5 thin film on a substrate (100), including a step (S210) of supplying a source gas containing a group 3 element to a reaction space and a step (S220) of supplying a reactant gas containing a group 5 element to the reaction space. In addition, the method for forming a thin film according to an embodiment of the present invention may further include a step (S100) of providing a substrate in a reaction space before the step (S210) of supplying the source gas, and the step (S210) of supplying the source gas and the step (S220) of supplying the reactant gas may be repeatedly performed until a group 3-5 thin film having a desired thickness is formed.

[0062] That is, a method for forming a thin film according to an embodiment of the present invention is a method for forming a group 3-5 thin film on a substrate (100) including a structural layer having an interlayer insulating layer, a conductive via penetrating all or part of the interlayer insulating layer, a conductive line connected to the conductive via, and source and drain electrodes formed on the interlayer insulating layer, in order to form a top gate type transistor, the method may include a source gas supply step (S210) of supplying a source gas containing a group 3 element to the structural layer to adsorb the source gas on the source and drain electrodes, a reactant gas supply step (S220) of supplying a reactant gas containing a group 5 element to the structural layer to react the source gas adsorbed on the source and drain electrodes with the reactant gas, and a repeating step of repeating the source gas supply step and the reactant gas supply step multiple times.

[0063] In addition, a method for forming a thin film according to an embodiment of the present invention is a method for forming a group 3-5 thin film on a substrate (100) including a structural layer having an interlayer insulating layer, a conductive via penetrating all or part of the interlayer insulating layer, a conductive line connected to the conductive via, a gate electrode formed on an upper portion of the interlayer insulating layer, and a gate insulating film formed on the gate electrode, in order to form a bottom gate type transistor, the method may include a source gas supply step (S210) of supplying a source gas containing a group 3 element to the structural layer to adsorb the source gas on the gate insulating film, a reactant gas supply step (S220) of supplying a reactant gas containing a group 5 element to the structural layer to react the source gas adsorbed on the gate insulating film with the reactant gas, and a repeating step of repeating the source gas supply step and the reactant gas supply step multiple times.

[0064] The step of preparing a substrate (S100) prepares a substrate (100) in which a structural layer is exposed in the process of forming a front-end-of-line structure (200) or a back-end-of-line structure (300). Here, the structural layer may include an interlayer insulating layer, a conductive via penetrating all or part of the interlayer insulating layer, a conductive line connected to the conductive via, and source and drain electrodes formed on the interlayer insulating layer in order to form a top-gate transistor. Alternatively, the structural layer may include an interlayer insulating layer, a conductive via penetrating all or part of the interlayer insulating layer, a conductive line connected to the conductive via, a gate electrode formed on the interlayer insulating layer, and a gate insulating film formed on the gate electrode in order to form a bottom-gate transistor. Here, the substrate support (20) may be provided with, for example, an electrostatic chuck or the like so that such a substrate can be seated and supported, and the substrate may be held by electrostatic force, or the substrate may be supported by vacuum suction or mechanical force.

[0065] A method for forming a thin film according to an embodiment of the present invention can form a channel layer including a Group 3-5 compound on a metal layer on an interlayer insulating layer by an atomic layer deposition (ALD) process. To this end, the method for forming a thin film according to an embodiment of the present invention can include a step (S210) of supplying a source gas containing a Group 3 element to a reaction space and a step (S220) of supplying a reactant gas containing a Group 5 element to the reaction space. In this way, in an embodiment of the present invention, a Group 3-5 thin film can be formed on a metal layer in a low-temperature process of 500°C or less by using an atomic layer deposition process.

[0066] The step of supplying a source gas (S210) supplies a source gas containing a Group III element onto the substrate. Here, the step of supplying the source gas supplies a source gas containing gallium onto the substrate through the source gas supply path of the substrate processing device described above. At this time, the Group III element may include one or more of gallium (Ga), indium (In), and aluminum (Al), and in the case of forming a gallium nitride (GaN) thin film, the source gas may include trimethyl gallium (TMGa) gas or triethyl gallium (TEGa) gas containing gallium as a main component. In the step of supplying the source gas, the source gas containing the Group III element is sprayed onto the substrate and adsorbed. That is, in order to form a top gate type transistor, the step of supplying the source gas (S210) may supply a source gas containing a Group III element to the structural layer and adsorb the source gas onto the source and drain electrodes. Meanwhile, in order to form a bottom gate type transistor, the step of supplying a source gas (S210) may supply a source gas containing a group 3 element to the structural layer and adsorb the source gas on the gate insulating film.

[0067] After the step of supplying the source gas (S210), a step of purging the reaction space to which the source gas has been supplied may be performed. In the step of purging the reaction space to which the source gas has been supplied, the source gas remaining in the reaction space of the chamber (10) can be removed. This can be achieved by supplying a purge gas, such as an inert gas, for example, argon (Ar) gas, to the reaction space, or alternatively, by performing only a step of pumping the reaction space without supplying the purge gas. That is, the method for forming a thin film according to an embodiment of the present invention may further include a step of supplying a purge gas to the reaction space between the step of supplying the source gas (S210) and the step of supplying the reactant gas (S220), so that the reaction space can be purged by supplying the purge gas. Alternatively, the method may further include a step of pumping the source gas supplied to the reaction space between the step of supplying the source gas (S210) and the step of supplying the reactant gas (S220), so that the reaction space can be purged without supplying the purge gas.

[0068] After the step of purging the reaction space to which the source gas is supplied, a step of supplying a reactant gas (S220) is performed. The step of supplying the reactant gas (S220) supplies a reactant gas containing a Group 5 element onto the substrate. Here, the step of supplying the reactant gas (S220) supplies a reactant gas containing nitrogen onto the substrate through the reactant gas supply path of the substrate processing device described above. At this time, the Group 5 element may include one or more of nitrogen (N), arsenide (As), and phosphorus (P), and in the case of forming a gallium nitride (GaN) thin film, the reactant gas may include ammonia (NH3) gas containing nitrogen as a main component. When the reactant gas is supplied onto the substrate to which the raw material is adsorbed, the raw material reacts with the reactant contained in the reactant gas. That is, in order to form a top gate type transistor, the step of supplying a reactant gas (S220) can cause the source gas adsorbed on the source and drain electrodes in the step of supplying a source gas (S210) to react with the reactant gas. Meanwhile, in order to form a bottom gate type transistor, the step of supplying a reactant gas (S220) can cause the source gas adsorbed on the gate insulating film in the step of supplying a source gas (S210) to react with the reactant gas.

[0069] At this time, in the step of supplying the reactant gas (S220), RF power (50) may be applied to the reaction space to activate the reactant gas and generate plasma in order to effectively react the Group 5 element component with the Group 3 element component. That is, the thin film forming method according to an embodiment of the present invention may further include a step of applying power for forming plasma to the reaction space, and at this time, at least a part of the step of supplying the reactant gas (S220) may be performed while the power for forming plasma is applied to the reaction space. That is, at least a part of the section in which the step of supplying the reactant gas is performed may overlap with the section in which the power for forming plasma is applied to the reaction space. Here, the step of applying RF power (50) to the reaction space includes all cases in which RF power (50) is applied while the step of supplying the reactant gas is performed. It goes without saying that the RF power (50) may be applied before starting to supply the reactant gas to the reaction space, or after ending the supply of the reactant gas to the reaction space, or the RF power (50) may be applied intermittently, i.e., in a pulse form, while the reactant gas is supplied.

[0070] In this way, in the step of supplying a reactant gas (S220), by activating and supplying the reactant gas, the supplied gas containing a group 5 element is activated into radicals to react with a group 3 element component, thereby forming a semiconductor layer containing a group 3-5 compound on the substrate at a lower process temperature. That is, when the reactant gas is activated and supplied onto the substrate, the process space of the chamber (10) can be controlled to a low temperature of 200°C or more and 500°C or less to form a group 3-5 thin film.

[0071] After the step of supplying the reactant gas (S220), a step of purging the reaction space to which the reactant gas has been supplied may be performed. In the step of purging the reaction space to which the reactant gas has been supplied, the reactant gas remaining in the reaction space of the chamber (10) may be removed. This step of purging the reactant gas may be performed by supplying an inert gas, for example, argon (Ar) gas, to the reaction space, similar to the step of purging the source gas, and as described above, the argon (Ar) gas may be supplied through at least one of the source gas supply path and the reactant gas supply path.

[0072] Meanwhile, the thin film forming method according to an embodiment of the present invention may further include a step of forming hydrogen plasma in the reaction space between the step of supplying the source gas (S210) and the step of supplying the reactant gas (S220). That is, in the thin film forming method according to an embodiment of the present invention, the step of supplying the source gas (S210), the step of forming hydrogen plasma in the reaction space, and the step of supplying the reactant gas (S220) may be performed sequentially. In this way, if the hydrogen plasma is formed in the reaction space after the step of supplying the source gas (S210), impurities included in the thin film can be effectively removed.

[0073] In addition, the method for forming a thin film according to an embodiment of the present invention may further include a step of forming hydrogen plasma in the reaction space after the step of supplying the reactant gas (S220). That is, the method for forming a thin film according to an embodiment of the present invention may sequentially perform the step of supplying a source gas (S210), the step of supplying the reactant gas (S220), and the step of forming hydrogen plasma in the reaction space. In this way, when hydrogen plasma is formed in the reaction space after the step of supplying the reactant gas (S220), not only can the formation of oxygen vacancies in the thin film be suppressed, but also the stress of the thin film can be controlled and the film quality can be improved.

[0074] Here, the thin film forming method according to an embodiment of the present invention can be performed by repeating the step of supplying a source gas (S210) and the step of supplying a reactant gas (S220) multiple times. For example, the thin film forming method according to an embodiment of the present invention can perform a process cycle including the step of supplying a source gas (S210), the step of purging the source gas, the step of supplying a reactant gas (S220), and the step of purging the reactant gas multiple times. That is, in the thin film forming method according to an embodiment of the present invention, the step of supplying a source gas, the step of purging the source gas, the step of supplying a reactant gas, and the step of purging the reactant gas form one process cycle, and the process cycle can be repeatedly performed until a Group 3-5 thin film having a desired thickness, i.e., a channel layer, is formed on a substrate.

[0075]

[0076] While the preferred embodiments of the present invention have been described and illustrated using specific terms above, such terms are solely for the purpose of clearly describing the present invention, and it is to be understood that various modifications and variations may be made to the embodiments and terms described herein without departing from the spirit and scope of the appended claims. Such modified embodiments should not be construed individually from the spirit and scope of the present invention, but should be considered to fall within the scope of the claims.

Claims

1. A method for forming a 3-5 group thin film on a substrate including a structural layer having an interlayer insulating layer, a conductive via penetrating all or part of the interlayer insulating layer, a conductive line connected to the conductive via, and source and drain electrodes formed on top of the interlayer insulating layer, A source gas supply step of supplying a source gas containing a group 3 element to the above structural layer and adsorbing the source gas on the source and drain electrodes; A reactant gas supply step for supplying a reactant gas containing a group 5 element to the above structural layer to react the source gas adsorbed on the source and drain electrodes with the reactant gas; and A method for forming a thin film, comprising a repeating step of repeating the source gas supply step and the reactant gas supply step multiple times.

2. A method for forming a 3-5 group thin film on a substrate including a structural layer having an interlayer insulating layer, a conductive via penetrating all or part of the interlayer insulating layer, a conductive line connected to the conductive via, a gate electrode formed on top of the interlayer insulating layer, and a gate insulating film formed on the gate electrode, A source gas supply step of supplying a source gas containing a group 3 element to the above structural layer and adsorbing the source gas on the gate insulating film; A reactant gas supply step for supplying a reactant gas containing a group 5 element to the structural layer to react the reactant gas with a source gas adsorbed on the gate insulating film; and A method for forming a thin film, comprising a repeating step of repeating the source gas supply step and the reactant gas supply step multiple times.

3. In claim 1 or 2, A method for forming a thin film further comprising: a step of forming hydrogen plasma in a reaction space in which the substrate is provided between the source gas supply step and the reactant gas supply step.

4. In claim 1 or 2, A method for forming a thin film further comprising, after the above reactant gas supply step, a step of forming hydrogen plasma in a reaction space in which the substrate is provided.

5. In claim 1 or 2, A method for forming a thin film further comprising: a step of forming hydrogen plasma in a reaction space in which the substrate is provided while supplying the reactant gas.

6. In claim 1 or 2, A method for forming a thin film further comprising a step of supplying a purge gas to a reaction space in which the substrate is provided between the source gas supply step and the reactant gas supply step.

7. In claim 1 or 2, A method for forming a thin film further comprising a step of pumping the source gas supplied to a reaction space in which the substrate is provided between the source gas supply step and the reactant gas supply step.

8. In claim 1 or 2, A thin film forming method in which a purge gas is not supplied to a reaction space in which the substrate is provided between the source gas supply step and the reactant gas supply step.

9. In claim 1 or 2, A method for forming a thin film, wherein the above group 3 element includes one or more of gallium (Ga), indium (In), and aluminum (Al).

10. In claim 1 or 2, A method for forming a thin film, wherein the above group 5 element includes one or more of nitrogen (N), arsenide (As), and phosphorus (P).

11. In claim 1 or 2, The above 3-5 group thin film is a method for forming a thin film including a channel layer of a transistor.

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