Electrical characteristic prediction system and electrical characteristic prediction method

Abstract

Provided is an electrical characteristic prediction system for a semiconductor element. The electrical characteristic prediction system includes: a reception unit; a processing unit; and a presentation unit. The reception unit has the function of receiving layout data of the semiconductor element. The processing unit is configured to execute: a process for performing a first inference in which a concentration distribution is predicted from the layout data on the basis of a first model; and a process for performing a second inference in which electrical characteristics of the semiconductor element are predicted from the concentration distribution on the basis of a second model. The presentation unit has the function of presenting results of the second inference. The concentration distribution is the concentration distribution of at least one selected from among a donor, oxygen, oxygen vacancies, or impurity atoms, and the electrical characteristics of the semiconductor element are at least one selected from among threshold voltage, shift voltage, S value, and DIBL.

Description

Electrical characteristic prediction system and electrical characteristic prediction method

[0001] 1. Field of the Invention The present invention relates to a system for predicting electrical characteristics of a semiconductor device. 2. Field of the Invention The present invention relates to a method for predicting electrical characteristics of a semiconductor device. 3. Field of the Invention The present invention relates to a method for creating a dataset for training a model used in predicting electrical characteristics of a semiconductor device.

[0002] In this specification and elsewhere, a semiconductor element refers to an element that can function by utilizing semiconductor characteristics. Examples include semiconductor elements such as transistors, diodes, light-emitting elements, and light-receiving elements. Another example of a semiconductor element is a passive element such as a capacitor, resistor, or inductor that is formed by a conductive film or an insulating film. Another example of a semiconductor element is a semiconductor device that includes a circuit having a semiconductor element or a passive element.

[0003] In recent years, in fields using artificial intelligence (AI), robotics, and energy fields that handle high power such as power ICs, the development of new semiconductor elements has been progressing to solve issues such as increasing computational loads and increasing power consumption. While the integrated circuits and semiconductor elements used in integrated circuits required by the market are becoming increasingly complex, there is a demand for the early launch of integrated circuits with new functions. However, the process design, device design, and circuit design in the development of semiconductor elements require the knowledge, know-how, and experience of skilled engineers.

[0004] In the development of transistors, when control of threshold voltage (Vth) is required, process development is carried out to control Vth. However, Vth varies not only depending on the process but also on the layout. For example, Non-Patent Document 1 reports that Vth depends on the layout in transistors using silicon in the channel formation region (also called Si transistors).

[0005] In recent years, oxide semiconductors have attracted attention as a semiconductor material that can be used to form transistors that are resistant to short-channel effects and have extremely low leakage current in the off state. Transistors using oxide semiconductors can be fabricated at low temperatures, and are therefore attracting attention as a technology that allows for easy stacking. Furthermore, because thin-film scaling is possible, oxide semiconductors are expected to be used in a variety of applications, including memory, logic, and displays.

[0006] N. Karmokar et al. , “Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead,” 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, Taiwan, 2022, pp. 114-121

[0007] For example, the threshold voltage (Vth) of a transistor can be obtained by actually fabricating the transistor and measuring its electrical characteristics, but fabricating the transistor and obtaining the actual measured value of Vth requires a lot of time and money. Furthermore, because a mask needs to be modified when the layout of the transistor is changed, evaluating the layout dependency of the Vth of the transistor requires even more time and money.

[0008] Therefore, a system that uses AI to predict the electrical characteristics of a transistor from its layout is effective. The AI ​​training requires a data set of layout and actual measured values ​​of the electrical characteristics, which requires the preparation of many actual measured values. Furthermore, because the electrical characteristics of a transistor change depending on the carrier concentration distribution in the channel, it is difficult to predict the electrical characteristics from the layout alone.

[0009] In view of the above, an object of one embodiment of the present invention is to provide a system for predicting electrical characteristics of a semiconductor element.An object of one embodiment of the present invention is to provide a method for predicting electrical characteristics of a semiconductor element.An object of one embodiment of the present invention is to provide a method for creating a dataset for training a model used in predicting electrical characteristics of a semiconductor element.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc.

[0011] One aspect of the present invention is an electrical characteristic prediction system including a receiving unit, a processing unit, and a presentation unit. The receiving unit has a function of receiving layout data of a semiconductor element. The processing unit is configured to perform a first inference process of predicting a concentration distribution from the layout data based on a first model, and a second inference process of predicting electrical characteristics of the semiconductor element from the concentration distribution based on a second model. The presentation unit has a function of presenting the results of the second inference. The concentration distribution is a concentration distribution of at least one selected from donors, oxygen, oxygen vacancies, and impurity atoms. The electrical characteristic of the semiconductor element is at least one selected from threshold voltage, shift voltage, subthreshold swing value (S value), and drain-induced barrier lowering (DIBL).

[0012] In the above-mentioned electrical characteristic prediction system, it is preferable that the first model has learned a first data set, the first data set has a plurality of first data, each of the plurality of first data has layout data and a concentration distribution, and at least one of the plurality of first data has the layout data and a concentration distribution created by calculation using the layout data and a physical model.

[0013] In the above-described electrical characteristic prediction system, it is preferable that the second model has learned a second data set, the second data set has a plurality of second data, each of the plurality of second data has a concentration distribution and electrical characteristics, and at least one of the plurality of second data has the electrical characteristics and a concentration distribution created by calculation using layout data from which the electrical characteristics were obtained.

[0014] In the electrical characteristic prediction system, the processing unit is preferably configured to execute a process of converting layout data into numerical data.

[0015] In the above-mentioned electrical characteristic prediction system, it is preferable that the layout data includes two or more layers, and the processing unit is configured to perform the following processes: assigning a bit pattern to a mask area of ​​each layer; dividing the semiconductor element and its periphery into partial areas in each layer; and adding, for each divided partial area, the bit patterns assigned to the mask areas included in the partial area.

[0016] In the electrical characteristic prediction system, the processing unit is preferably configured to execute a process of converting layout data into image data.

[0017] In the above-mentioned electrical characteristic prediction system, it is preferable that the layout data includes two or more layers, and the processing unit is configured to perform the following processes: assigning colors to mask areas of each layer; dividing the semiconductor element and its surroundings into partial areas in each layer; and, for each divided partial area, synthesizing the colors assigned to the mask areas included in the partial area.

[0018] One aspect of the present invention is a method for predicting electrical characteristics of a semiconductor device, comprising first to fourth steps. In the first step, an information processing device accepts layout data of the semiconductor device. In the second step, the information processing device performs a first inference to predict a concentration distribution from the layout data based on a first model. The concentration distribution is a concentration distribution of at least one selected from donors, oxygen, oxygen vacancies, and impurity atoms. In the third step, the information processing device performs a second inference to predict electrical characteristics of the semiconductor device from the concentration distribution based on a second model. The electrical characteristic of the semiconductor device is at least one selected from threshold voltage, shift voltage, S value, and DIBL. In the fourth step, the information processing device presents a result of the second inference.

[0019] In the above-mentioned electrical characteristic prediction method, it is preferable that the first model has learned a first data set, the first data set has a plurality of first data, each of the plurality of first data has layout data and a concentration distribution, and at least one of the plurality of first data has the layout data and a concentration distribution created by calculation using the layout data and a physical model.

[0020] In the above-described electrical characteristic prediction method, it is preferable that the second model has learned a second data set, the second data set has a plurality of second data, each of the plurality of second data has a concentration distribution and electrical characteristics, and at least one of the plurality of second data has the electrical characteristics and a concentration distribution created by calculation using layout data from which the electrical characteristics were obtained.

[0021] In the above-mentioned electrical characteristic prediction method, it is preferable that a fifth step is provided between the first step and the second step, the layout data includes two or more layers, and in the fifth step, the information processing device assigns a bit pattern to a mask area of ​​each layer, divides the semiconductor element and its periphery into partial areas in each layer, and for each divided partial area, adds up the bit patterns assigned to the mask areas included in the partial area, thereby converting the layout data into numerical data.

[0022] In the above-mentioned electrical characteristic prediction method, it is preferable that a fifth step is provided between the first step and the second step, the layout data includes two or more layers, and in the fifth step, the information processing device assigns colors to mask areas of each layer, divides the semiconductor element and its periphery into partial areas in each layer, and for each divided partial area, synthesizes the colors assigned to the mask areas included in the partial area, thereby converting the layout data into image data.

[0023] According to one aspect of the present invention, a system for predicting electrical characteristics of a semiconductor device can be provided. According to one aspect of the present invention, a method for predicting electrical characteristics of a semiconductor device can be provided. According to one aspect of the present invention, a method for creating a dataset for training a model used in predicting electrical characteristics of a semiconductor device can be provided.

[0024] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Note that the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification, drawings, etc., and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the effects listed above and / or other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

[0025] FIG. 1A is a block diagram of an electrical characteristic prediction system. FIGS. 1B and 1C are block diagrams showing an example of a processing unit. FIGS. 2A and 2B are examples of layout configurations of semiconductor elements. FIGS. 3A to 3D are diagrams explaining layout data processing. FIGS. 4A to 4F are diagrams explaining layout data processing. FIG. 5 is a flow diagram of an electrical characteristic prediction method. FIG. 6 is a flow diagram of an electrical characteristic prediction method. FIG. 7A is a cross-sectional view of a semiconductor element, and FIG. 7B is a diagram explaining concentration distribution. FIGS. 8A to 8C are diagrams comparing measured electrical characteristics with calculated electrical characteristics. FIG. 9A is a cross-sectional view of a semiconductor element, and FIG. 9B is a diagram explaining concentration distribution. FIGS. 10A to 10C are diagrams comparing measured electrical characteristics with calculated electrical characteristics. FIGS. 11A to 11D are diagrams explaining a diffusion model, and FIGS. 11E and 11F are diagrams explaining application of the diffusion model to a semiconductor element. 12A to 12D show the calculation results of the concentration distribution, and Fig. 13 is a diagram comparing the actual measured values ​​of the shift voltage with the calculated values ​​of the shift voltage.

[0026] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0027] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0028] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0029] In this specification, the ordinal numbers such as "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, an ordinal number assigned to a component in one part of this specification may not match an ordinal number assigned to the same component in another part of this specification or in the claims.

[0030] 1A to 13 , a system for predicting electrical characteristics of a semiconductor element, a method for predicting electrical characteristics of a semiconductor element, and a method for creating a dataset for training a model used for predicting the electrical characteristics of a semiconductor element, according to one embodiment of the present invention, will be described. Note that in this embodiment, a transistor including an oxide semiconductor in a channel formation region (also referred to as an OS transistor) may be used as the semiconductor element.

[0031] According to one aspect of the present invention, there is provided a system for predicting electrical characteristics of a semiconductor device, the system including a processing unit configured to perform a first inference process and a second inference process.

[0032] In the first inference, the concentration distribution is predicted from layout data of a semiconductor element based on the first model. As described above, the electrical characteristics of a transistor change depending on the concentration distribution of carriers in the channel. Note that carriers in a p-channel transistor are acceptors, and carriers in an n-channel transistor are donors. For example, oxygen vacancies and hydrogen atoms (H) trapped in oxygen vacancies are used as donor sources for an n-channel OS transistor. Ｏ , or V Ｏ Examples of the donor source for a Si transistor include impurity atoms, which are also referred to as H. Note that oxygen vacancies are formed due to an insufficient supply of oxygen, and therefore oxygen indirectly contributes to the donor. For example, impurity atoms can be used as donor sources for Si transistors. Specifically, boron (B) and aluminum (Al) can be used as acceptor sources for p-channel Si transistors. For example, phosphorus (P) and arsenic (As) can be used as donor sources for n-channel Si transistors.

[0033] Therefore, the concentration distribution predicted by the first inference is preferably a concentration distribution of one or both of the donor and the donor source. In particular, when the semiconductor element whose electrical characteristics are to be predicted is an OS transistor, the concentration distribution predicted by the first inference is preferably a concentration distribution of at least one selected from the group consisting of the donor, oxygen, oxygen vacancy, and impurity atoms.

[0034] In the second inference, electrical characteristics of the semiconductor element are predicted from the concentration distribution based on the second model, where the concentration distribution is the concentration distribution output from the first model, and the semiconductor element whose electrical characteristics are predicted is the semiconductor element corresponding to the layout data input to the first model.

[0035] When the semiconductor element is a transistor, the electrical characteristic of the semiconductor element predicted by the second inference is at least one selected from a threshold voltage (Vth), a shift voltage (Vsh), an S value, and a DIBL.

[0036] Here, the threshold voltage (Vth) can be calculated by the root Id method. The root Id method is a method in which the gate voltage (Vg) [V] is plotted on the horizontal axis and the square root of the drain current (Id) is plotted on the horizontal axis. １／２ In the Id-Vg characteristics plotted with Id as the vertical axis, the tangent at the point where the slope of the curve is maximum and Id １／２ This method defines the gate voltage at the intersection with the line at V = 0 (i.e., the Vg axis) as the threshold voltage.

[0037] The shift voltage (Vsh) is determined by plotting the Id-Vg characteristic with the gate voltage (Vg) [V] on the horizontal axis and the drain current (Id) [A] on the vertical axis, and the tangent to the point where the slope of the curve is maximum is Id = 1 pA (1 × 10 −１２ The S value is the gate voltage (Vg) at which the drain current (Id) changes by one order of magnitude at a constant drain voltage (Vd) in the subthreshold region. DIBL is the amount of change in the shift voltage (Vsh) when the drain voltage (Vd) is changed by 1 V.

[0038] By performing the first inference process and the second inference process, it is possible to predict the electrical characteristics of a semiconductor element from the layout of the semiconductor element.

[0039] The first model has been trained on a first data set, the first data set including a plurality of first data, each of which includes layout data and a concentration distribution of a semiconductor element.

[0040] A semiconductor device is fabricated using one or more masks, i.e., the layout data of the semiconductor device includes data of at least one mask, i.e., at least one layer including a mask region.

[0041] At least one of the plurality of first data sets preferably includes layout data of a semiconductor device and a concentration distribution created by calculation using the layout data and a physical model. Creating the concentration distribution by calculation using a physical model can shorten the time required to prepare the first data set, thereby increasing the development speed. Furthermore, the number of times semiconductor devices need to be fabricated to prepare the first data set can be reduced, thereby reducing costs.

[0042] The second model has been trained on a second data set, the second data set including a plurality of second data, each of which includes a concentration distribution and electrical characteristics of a semiconductor element.

[0043] At least one of the plurality of second data sets preferably includes electrical characteristics of the semiconductor device and a concentration distribution created by calculation using layout data from which the electrical characteristics are obtained. By creating the concentration distribution by calculation, the time required to prepare the second data set can be shortened, thereby increasing the development speed. Furthermore, the number of times that semiconductor devices need to be fabricated to prepare the second data set can be reduced, thereby reducing costs.

[0044] By using the first model and the second model, it is possible to predict the electrical characteristics of a semiconductor element from the layout of the semiconductor element.

[0045] The processing unit is preferably configured to execute a process for processing the layout data, thereby reducing the amount of data input to the first model and shortening the time required for the first inference while maintaining the accuracy of the first inference.

[0046] According to one aspect of the present invention, a system for predicting electrical characteristics of a semiconductor device includes a receiving unit and a presenting unit. The receiving unit receives layout data of the semiconductor device. The received layout data of the semiconductor device is supplied to a processing unit and used in a first inference. The presenting unit presents the results of a second inference supplied from the processing unit.

[0047] The electrical characteristic prediction system can also be said to be a system capable of executing processing using the electrical characteristic prediction method of one aspect of the present invention. Specifically, another aspect of the present invention is an electrical characteristic prediction method that receives layout data of a semiconductor element, performs a first inference to predict a concentration distribution from the layout data based on a first model, performs a second inference to predict the electrical characteristics of the semiconductor element from the concentration distribution output by the first inference based on a second model, and presents a result of the second inference.

[0048] <Electrical Property Prediction System> The electrical property prediction system of this embodiment will be described with reference to FIGS. 1A to 4F.

[0049] 1A shows a block diagram of an electrical characteristic prediction system according to the present embodiment. The electrical characteristic prediction system 100 includes a receiving unit 110, a processing unit 120, and a presentation unit .

[0050] The receiving unit 110 can receive data from outside the electrical characteristic prediction system 100. For example, the receiving unit 110 receives layout data of a semiconductor device.

[0051] The format of the layout data received by the receiving unit 110 is preferably a format that can be input to the first model. For example, it is preferably numerical data or image data. If the processing unit 120 has a function for processing the layout data, the format of the layout data received by the receiving unit 110 may be a format that is difficult to input to the first model. Details of the first model and the function for processing the layout data will be described later.

[0052] The processing unit 120 has a function of performing processes such as calculation, analysis, and inference using the data supplied from the receiving unit 110. The processing unit 120 can supply the created data (e.g., calculation results, analysis results, and inference results) to the presentation unit 130.

[0053] The processing unit 120 has a function of performing a first inference and a function of performing a second inference.

[0054] In the first inference, a concentration distribution is predicted from layout data of a semiconductor element based on a first model. That is, the processing unit 120 is configured to execute a process of predicting a concentration distribution from layout data of a semiconductor element based on the first model. Note that the first inference uses layout data of the semiconductor element supplied from the receiving unit 110. Alternatively, layout data processed by the processing unit 120 is used. The predicted concentration distribution is a concentration distribution of at least one selected from donors, oxygen, oxygen vacancies, and impurity atoms.

[0055] In the second inference, the electrical characteristics of the semiconductor element are predicted from the concentration distribution based on the second model. That is, the processing unit 120 is configured to execute a process of predicting the electrical characteristics of the semiconductor element from the concentration distribution based on the second model. The concentration distribution used in the second inference is the concentration distribution output in the first inference. The predicted electrical characteristics of the semiconductor element are at least one selected from the threshold voltage, the shift voltage, the S value, and the DIBL.

[0056] It is preferable to use a neural network (particularly, deep learning) for each of the first model and the second model. As the deep learning, it is preferable to use, for example, a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder (AE), a variational autoencoder (VAE), a random forest, a support vector machine, gradient boosting, a generative adversarial network (GAN), a diffusion model, a transformer, or the like.

[0057] The first model predicts the concentration distribution from the layout data of the semiconductor element, and can be called a concentration distribution generation AI. The second model predicts the electrical characteristics of the semiconductor element from the concentration distribution, and can be called an electrical characteristics estimation AI.

[0058] The first model is preferably trained on a first data set, and the second model is preferably trained on a second data set, as will be described later in detail.

[0059] 1B is a diagram showing the configuration of the processing unit 120. As shown in FIG. 1B, the processing unit 120 may include a first processing unit 121 and a second processing unit 122.

[0060] The first processing unit 121 has a function of performing a first inference, and the second processing unit 122 has a function of performing a second inference.

[0061] 1B, the functions of the processing unit 120 are classified and independent of each other, but some or all of the functions of the processing unit 120 may not be independent. Furthermore, the configuration of the processing unit according to one aspect of the present invention is not limited to the configuration of the processing unit 120 shown in FIG. 1B.

[0062] The processing unit 120 preferably has a function of processing the layout data. Furthermore, the processing unit 120 is preferably configured to execute a process of processing the layout data. Even if the layout data received by the receiving unit 110 is in a format that is difficult to input into the first model, the processing can be executed to use the data for the first inference. Furthermore, by executing the processing, the amount of data input into the first model can be reduced, and the time required for the first inference can be shortened while maintaining the accuracy of the first inference.

[0063] Regarding the process of processing the layout data, the processing unit 120 is preferably configured to execute at least one of a first process and a second process, for example. The first process is a process of converting the layout data into numerical data, and the second process is a process of converting the layout data into image data.

[0064] An example of layout data before being converted into numerical data or image data will now be described with reference to FIGS. 2A and 2B. FIG.

[0065] The layout data for the semiconductor element includes first to nth layers (n is an integer of 2 or greater). Each of the first to nth layers includes a mask region. The effective range of the layout data is not particularly limited, but can be, for example, a 10 μm square region including the semiconductor element whose electrical characteristics are to be predicted and its surroundings.

[0066] 2A and 2B show layout data 200L. The layout data 200L includes a layer 201L having a mask region 201, a layer 202L having a mask region 202, a layer 203L having a mask region 203, a layer 204L having a mask region 204, and a layer 205L having a mask region 205. As shown in FIG. 2B, the layout data 200L has a configuration in which the layer 204L is arranged on the layer 205L, the layer 203L is arranged on the layer 204L, the layer 202L is arranged on the layer 203L, and the layer 201L is arranged on the layer 202L.

[0067] The first processing will be described with reference to FIGS. 3A to 3D.

[0068] The first process includes, for example, a first step, a second step, and a third step.

[0069] In the first step included in the first process, a bit pattern is assigned to the mask region of each layer. Since the layout data 200L shown in FIG. 2A includes five layers, each layer can be represented by, for example, 5 bits. As an example, as shown in FIG. 3A, the bit pattern "00001" is assigned to the mask region 201, the bit pattern "00010" is assigned to the mask region 202, the bit pattern "00100" is assigned to the mask region 203, the bit pattern "01000" is assigned to the mask region 204, and the bit pattern "10000" is assigned to the mask region 205.

[0070] In the second step included in the first process, the effective range of the layout data in each layer is divided into partial regions. That is, in the second step included in the first process, the semiconductor element and its periphery are divided into partial regions in each layer. The division method is not particularly limited, but for example, mesh division can be used. In this case, the area of ​​the partial region is typically 1 nm square or 10 nm square.

[0071] Fig. 3B shows an enlarged view of the area P surrounded by the dashed line in Fig. 2A. Fig. 3B also shows an example in which the area P is divided into 5 x 5 partial areas. Note that in Fig. 3B, for ease of understanding, the areas of the partial areas are made larger than the sizes described above.

[0072] In FIG. 3B, partial region 201p is an area that overlaps with mask region 201, partial region 204p is an area that overlaps with mask region 204, partial region 211p is an area that overlaps with mask region 201 and mask region 204, and partial region 299p is an area that does not overlap with any of mask regions 201 to 205.

[0073] Although not shown in FIG. 3B , partial region 203p is an area that overlaps with mask region 203, partial region 205p is an area that overlaps with mask region 205, partial region 212p is an area that overlaps with mask region 201, mask region 202, and mask region 204, and partial region 213p is an area that overlaps with mask region 204 and mask region 205.

[0074] In the third step included in the first process, for each divided partial region, the bit patterns assigned to the mask regions included in the partial region are added. For example, the bit pattern "00001" assigned to mask region 201 and the bit pattern "01000" assigned to mask region 204 are added to partial region 211p. As a result, the bit pattern of partial region 211p becomes "01001" (FIG. 3C). Furthermore, the bit pattern "00001" assigned to mask region 201, the bit pattern "00010" assigned to mask region 202, and the bit pattern "01000" assigned to mask region 204 are added to partial region 212p. As a result, the bit pattern of partial region 211p becomes "01011" (FIG. 3C). Furthermore, the bit pattern "01000" assigned to mask region 204 and the bit pattern "10000" assigned to mask region 205 are added to partial region 213p. As a result, the bit pattern of the partial area 213p becomes "11000" (FIG. 3C).

[0075] Since partial region 201p overlaps with mask region 201, the bit pattern of partial region 201p is "00001". Furthermore, the bit pattern of partial region 204p is "01000". Furthermore, since partial region 299p does not overlap with any of mask regions 201 to 205, the bit pattern of partial region 299p is "00000".

[0076] As described above, each partial area can be represented by a bit pattern. Note that in Fig. 3D, the bit pattern of each partial area is represented by a hatched pattern.

[0077] By performing the first process, the layout data can be converted into numerical data. By converting the layout data into numerical data, the amount of data input to the first model can be reduced, and the time required for the first inference can be shortened while maintaining the accuracy of the first inference.

[0078] The second process will be described with reference to FIGS. 4A to 4F.

[0079] The second process includes, for example, a first step, a second step, and a third step.

[0080] In the first step included in the second process, colors are assigned to the mask regions of each layer. Since the layout data 200L shown in FIG. 2A includes five layers, each layer can be represented by five colors, for example. For example, color Col01 is assigned to mask region 201, color Col02 is assigned to mask region 202, color Col03 is assigned to mask region 203, color Col04 is assigned to mask region 204, and color Col05 is assigned to mask region 205. Note that in FIGS. 4A to 4E, the colors assigned to each mask region are represented by hatching patterns.

[0081] In the second step included in the second process, the effective range of the layout data is divided into partial regions in each layer. That is, in the second step included in the first process, the semiconductor element and its periphery are divided into partial regions in each layer. Note that the second step included in the second process is the same as the second step included in the first process, and therefore the content described with reference to FIG. 3B can be referred to.

[0082] In the third step included in the second process, for each divided partial region, the colors assigned to the mask regions included in the partial region are combined. For example, for partial region 211p, color Col01 assigned to mask region 201 and color Col04 assigned to mask region 204 are added together. In this case, color Col11 assigned to partial region 211p can be calculated using, for example, the following formula:

[0083]

[0084] In the above formula, α is transparency. In other words, transparency is taken into account when combining colors using the above formula. Note that in order to combine colors, α must be a value greater than 0 and less than 1.

[0085] The color of the partial region 201p is the same as the color Col01 assigned to the mask region 201. Similarly, the color of the partial region 204p is the same as the color Col04 assigned to the mask region 204.

[0086] As described above, each partial region can be represented by a color. Note that in Fig. 4F, the color of each partial region is represented by a hatching pattern or an overlap of hatching patterns.

[0087] By performing the second process, the layout data can be converted into image data. By converting the layout data into image data, the amount of data input to the first model can be reduced, and the time required for the first inference can be shortened while maintaining the accuracy of the first inference.

[0088] The color synthesis in the third step included in the second process is not limited to the above method, and may be, for example, additive color mixing or subtractive color mixing.

[0089] 1C is a diagram showing the configuration of the processing unit 120. As shown in FIG. 1C, the processing unit 120 may include a third processing unit 123 in addition to the first processing unit 121 and second processing unit 122 described above.

[0090] The third processing unit 123 has a function of processing the layout data, and also has a function of performing at least one of the first processing and the second processing described above.

[0091] 1C, the processing unit 120 is classified into functions that the processing unit 120 has and is independent of each other, but some or all of the functions of the processing unit 120 may not be independent. Furthermore, the configuration of the processing unit according to one aspect of the present invention is not limited to the configuration of the processing unit 120 shown in FIG.

[0092] The processing unit 120 may include, for example, an arithmetic circuit. The processing unit 120 may include, for example, a central processing unit (CPU). The processing unit 120 may also include, for example, a graphics processing unit (GPU). The processing unit 120 may also include, for example, a tensor processing unit (TPU) or a neural processing unit (NPU).

[0093] The processing unit 120 may have a microprocessor such as a DSP (Digital Signal Processor). The microprocessor may be configured to be implemented by a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array) or an FPAA (Field Programmable Analog Array). The processing unit 120 may also have a quantum processor. The processing unit 120 can perform various data processing and program control by interpreting and executing instructions from various programs using the processor. Programs that can be executed by the processor are stored in at least one of a memory area and a storage unit of the processor.

[0094] The processing unit 120 may have a main memory. The main memory may include at least one of a volatile memory such as a random access memory (RAM) and a non-volatile memory such as a read only memory (ROM). The main memory may also include at least one of NOSRAM (registered trademark) and DOSRAM (registered trademark), which will be described later.

[0095] The RAM may be, for example, a dynamic random access memory (DRAM) or a static random access memory (SRAM), and a virtual memory space is allocated to it and used as a working space for the processing unit 120. The operating system, application programs, program modules, program data, lookup tables, and the like stored in the storage unit are loaded into the RAM for execution. The data, programs, and program modules loaded into the RAM are each directly accessed and operated by the processing unit 120.

[0096] The ROM can store a BIOS (Basic Input / Output System), firmware, etc., which do not require rewriting. Examples of ROM include mask ROM, OTPROM (One Time Programmable Read Only Memory), and EPROM (Erasable Programmable Read Only Memory). Examples of EPROMs include UV-EPROMs (Ultra-Violet Erasable Programmable Read Only Memories), which allow stored data to be erased by exposure to ultraviolet light, EEPROMs (Electrically Erasable Programmable Read Only Memories), and flash memories.

[0097] The processing section 120 can include one or both of an OS transistor and a Si transistor.

[0098] The processing unit 120 preferably includes an OS transistor. Because an OS transistor has an extremely small off-state current, using the OS transistor as a switch for retaining charge (data) flowing into a capacitor functioning as a memory element can ensure a long data retention period. By using this characteristic in at least one of the register and cache memory of the processing unit, the processing unit can be operated only when necessary, and can be turned off in other cases by saving information from the previous processing in the memory element. In other words, normally-off computing is possible, and the power consumption of the information processing system can be reduced.

[0099] As shown in FIG. 1B, when the processing unit 120 has a first processing unit 121 and a second processing unit 122, the first processing unit 121 and the second processing unit 122 may be provided in a single information processing device or in separate information processing devices.

[0100] Also, as shown in FIG. 1C, when the processing unit 120 has a first processing unit 121, a second processing unit 122, and a third processing unit 123, the first processing unit 121, the second processing unit 122, and the third processing unit 123 may be provided in a single information processing device or in separate information processing devices.

[0101] The first processing unit 121 and the second processing unit 122 have the function of performing the first inference and the second inference, respectively. Therefore, it is preferable that the first processing unit 121 and the second processing unit 122 have higher processing capabilities than the third processing unit 123. For example, it is preferable that an information processing device including the first processing unit 121 and the second processing unit 122 has the function of a parallel computer. By using the information processing device as a parallel computer, it is possible to perform large-scale calculations required for learning and inferring the first model and the second model.

[0102] The presentation unit 130 outputs data based on the processing results of the processing unit 120. The presentation unit 130 can supply at least one of the calculation results, analysis results, and inference results of the processing unit 120 to an external device of the electrical characteristic prediction system 100.

[0103] The presentation unit 130 can present, for example, the result of the second inference. The presentation unit 130 may also present the result of the first inference. The presentation unit 130 may also present the layout data of the semiconductor element received by the reception unit 110.

[0104] The presentation unit 130 has a function of displaying data. As the presentation unit 130, for example, a display device can be used.

[0105] Alternatively, the presenting unit 130 may output a file in a format such as txt, docx, xml, pdf, or csv.

[0106] The electrical characteristic prediction system 100 may include a storage unit. The storage unit has a function of storing a program executed by the processing unit 120. The storage unit may also have a function of storing data created by the processing unit 120 (e.g., calculation results, analysis results, inference results), data input to the receiving unit 110, etc.

[0107] The storage unit may also have a function of storing layout data of semiconductor elements. In this case, a user can specify layout data stored in the storage unit, and the specified layout data can be accepted by the accepting unit 110. In other words, the accepting unit 110 can accept data from within the electrical characteristic prediction system 100.

[0108] The storage unit may have a database. Furthermore, the electrical characteristic prediction system 100 may have a database separate from the storage unit. The electrical characteristic prediction system 100 may have a function of retrieving data from a database that exists outside the storage unit or outside the electrical characteristic prediction system 100. Furthermore, the electrical characteristic prediction system 100 may have a function of retrieving data from both its own database and an external database.

[0109] A file server may be used instead of the database. For example, when using files stored in a file server, it is preferable that the database has paths to files stored in the file server.

[0110] The storage unit includes at least one of a volatile memory and a non-volatile memory. Examples of the volatile memory include DRAM and SRAM. Examples of the non-volatile memory include ReRAM (Resistive Random Access Memory, also called resistance change memory), PRAM (Phase change Random Access Memory), FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetoresistive Random Access Memory, also called magnetoresistive memory), and flash memory. The storage unit may also include at least one of NOSRAM and DOSRAM. The storage unit may also include a recording media drive. Examples of recording media drives include hard disk drives (HDDs) and solid state drives (SSDs).

[0111] NOSRAM is an abbreviation for "Nonvolatile Oxide Semiconductor Random Access Memory (RAM)." NOSRAM refers to a memory in which memory cells are two-transistor (2T) or three-transistor (3T) gain cells and transistors (also called OS transistors) that use metal oxide in their channel formation regions. OS transistors have an extremely small leakage current, i.e., a current that flows between the source and drain in an off state. NOSRAM can be used as a nonvolatile memory by retaining a charge corresponding to data in the memory cell using its extremely small leakage current characteristic. In particular, NOSRAM can read stored data without destroying it (nondestructive readout), making it suitable for arithmetic processing in which only data read operations are repeated a large number of times. NOSRAM can increase its data capacity by stacking layers, and therefore can be used as a large-scale cache memory, main memory, or storage memory to improve the performance of semiconductor devices.

[0112] DOSRAM is an abbreviation for "Dynamic Oxide Semiconductor RAM" and refers to a RAM having 1T (transistor) 1C (capacitor) type memory cells. DOSRAM is a DRAM formed using OS transistors, and is a memory that temporarily stores information sent from an external device. DOSRAM is a memory that takes advantage of the low off-state current of OS transistors.

[0113] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor.

[0114] The metal oxide included in the channel formation region preferably contains indium (In). When the metal oxide included in the channel formation region contains indium, the carrier mobility (electron mobility) of the OS transistor is increased. Furthermore, the metal oxide included in the channel formation region is preferably an oxide semiconductor containing element M. The element M is preferably at least one of aluminum (Al), gallium (Ga), and tin (Sn). Other elements applicable to element M include boron (B), silicon (Si), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), yttrium (Y), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), and tungsten (W). However, a combination of two or more of the above elements may be used as element M. The element M is, for example, an element having a high bond energy with oxygen. For example, it is an element having a higher bond energy with oxygen than indium. The metal oxide contained in the channel formation region is preferably a metal oxide containing zinc (Zn), since zinc-containing metal oxides may be easily crystallized.

[0115] The metal oxide contained in the channel formation region is not limited to a metal oxide containing indium, but may be, for example, a metal oxide containing zinc but not indium, such as zinc tin oxide or gallium tin oxide, a metal oxide containing gallium, or a metal oxide containing tin.

[0116] The processing unit 120 has a function of acquiring data from the storage unit, and may also have a function of recording or registering data in the storage unit.

[0117] The electrical characteristic prediction system 100 preferably uses AI for at least part of the processing.

[0118] In particular, it is preferable that an artificial neural network (ANN, hereinafter also simply referred to as a neural network) be used in the electrical characteristic prediction system 100. The neural network is realized by a circuit (hardware) or a program (software).

[0119] In this specification, a neural network refers to a general model that mimics the neural circuit network of a living organism, determines the connection strength between neurons through learning, and has problem-solving capabilities. A neural network has an input layer, an intermediate layer (hidden layer), and an output layer.

[0120] In this specification and the like, when discussing neural networks, determining the connection strengths (also called weighting coefficients) between neurons from existing information may be referred to as "learning."

[0121] In this specification and the like, the act of constructing a neural network using connection strengths obtained by learning and deriving a new conclusion from it may be referred to as "inference."

[0122] This concludes the explanation of the electrical characteristics prediction system.

[0123] <Electrical Characteristics Prediction Method> The electrical characteristics prediction method of this embodiment will be described with reference to FIGS. 5 and 6. FIG.

[0124] The electrical characteristic prediction method of this embodiment includes processes in steps S01 to S04 shown in FIG. 5. Note that the electrical characteristic prediction method of this embodiment preferably uses the electrical characteristic prediction system of one embodiment of the present invention. In this case, the electrical characteristic prediction system can be said to be a system that can perform processing using the electrical characteristic prediction method of this embodiment.

[0125] The electrical characteristic prediction system preferably includes an information processing device, which includes a receiving unit 110, a processing unit 120, and a presentation unit 130.

[0126] In step S01, the information processing device receives layout data for a semiconductor device. Note that in step S01, the information processing device can be read as the receiving unit 110.

[0127] For example, a user may input layout data of a semiconductor element into the information processing device. Alternatively, for example, a user may specify layout data of a semiconductor element stored in a storage unit of the information processing device. The layout data of the semiconductor element may be presented to the presentation unit 130. Furthermore, when the layout data of a semiconductor element is input into the information processing device by a user, the layout data of the semiconductor element may be stored in a storage unit of the information processing device.

[0128] In step S02, the information processing device performs a first inference. For example, in step S02, the information processing device performs a first inference to predict a concentration distribution from layout data of a semiconductor element based on a first model. Note that, for details of the first inference, the contents of the above-mentioned <Electrical Characteristic Prediction System> can be referred to. Also, in step S02, the information processing device can be read as the processing unit 120.

[0129] The result of the first inference may be presented on the presentation unit 130. The result of the first inference may also be stored in a storage unit included in the information processing device.

[0130] In step S03, the information processing device performs a second inference. For example, in step S03, the information processing device performs a second inference to predict electrical characteristics of a semiconductor element from a concentration distribution based on a second model. For details of the second inference, see the above-mentioned <Contents of the Electrical Characteristics Prediction System>. In step S03, the information processing device can be read as the processing unit 120.

[0131] In step S04, the information processing device presents the result of the second inference. Note that in step S04, the information processing device can be read as the presentation unit 130.

[0132] From the above, it is possible to predict the electrical characteristics of a semiconductor element from the layout data of the semiconductor element.

[0133] If the layout data of the semiconductor element received in step S01 is in a format that makes it difficult to input into the first model, it is preferable to include processing in step S05 between steps S01 and S02, as shown in FIG. 6.

[0134] In step S05, the information processing device processes the layout data of the semiconductor element. For details of the layout data processing, please refer to the contents of the above-mentioned "Electrical Characteristics Prediction System." In step S05, the information processing device can be read as the processing unit 120.

[0135] This concludes the description of the electrical characteristic prediction method.

[0136] <First Data Set and Second Data Set> As described above, the first model has been trained on the first data set, and the second model has been trained on the second data set.

[0137] The first data set includes a plurality of first data, each of which includes layout data and a concentration distribution of a semiconductor element. The greater the number of first data included in the first data set, the higher the accuracy of the first inference. Note that the first data can be referred to as first training data because it is used to train the first model.

[0138] The second data set includes a plurality of second data, each of which includes a concentration distribution and electrical characteristics of a semiconductor element. The greater the number of second data included in the second data set, the higher the accuracy of the second inference. Note that the second data can be referred to as second training data because it is used to train the second model.

[0139] Hereinafter, a method for creating the first data set and the second data set, and a method for training the first model and the second model will be described.

[0140] [Creation Method and Learning Method 1] In this section, an example of a method for creating a first dataset and a second dataset, and a method for learning a second model from a first model will be described with reference to FIGS. 7A to 10C.

[0141] First, the layout data used in the actual process and the measured values ​​of the electrical characteristics of the semiconductor element are prepared.

[0142] Next, a label of the first learning data is specified based on the electrical characteristics of the semiconductor element. Hereinafter, the label of the first learning data may be referred to as the first label. For example, a threshold voltage is specified as the first label. Note that the first label does not need to be limited to the threshold voltage, and can be selected from a shift voltage, an S value, a DIBL, or the like. Furthermore, the first label does not need to be limited to one type, and two or more types selected from the electrical characteristics described above can be used.

[0143] Next, the actual measured value of the electrical characteristic designated as the first label is acquired.

[0144] Next, a concentration distribution that reproduces the actual measured values ​​of the acquired electrical characteristics is calculated. For example, by changing the concentration distribution of carriers in the channel, the actual measured values ​​of the electrical characteristics of the semiconductor element can be reproduced. For example, TCAD (Technology Computer Aided Design) can be used for the calculation.

[0145] 7A is a cross-sectional view of an example of a semiconductor element. The semiconductor element shown in FIG. 7A is an n-channel OS transistor, and carriers are donors.

[0146] 7A is a double-gate transistor having a trench gate self-aligned (TGSA) structure. The conductive layer TGE functions as a top gate electrode, the insulating layer TGI functions as a top gate insulating layer, the conductive layer BGE functions as a back gate electrode, the insulating layer BGI functions as a back gate insulating layer, one of the conductive layers SD1 and SD2 functions as a source electrode, and the other of the conductive layers SD1 and SD2 functions as a drain electrode, forming a channel in the oxide semiconductor layer OS. The conductive layers VIA1 and VIA2 function as plugs or wirings, and the insulating layer OST functions as an interlayer film.

[0147] In addition, in FIG. 7A, the layout is such that the semiconductor element is 1 μm ２ In other words, the density of the semiconductor elements is 19.2 / μm. ２ The layout is designed so that

[0148] The dashed line in FIG. 7A indicates a portion located at the center in the film thickness direction of the oxide semiconductor layer OS.

[0149] 7B is a diagram illustrating an example of a donor concentration distribution created by calculation. FIG. 7B shows the donor concentration distribution in the portion indicated by the dashed line in FIG. 7A. In FIG. 7B, the vertical axis represents the donor concentration [cm −３ 7B ], and the horizontal axis represents the position [nm] in the L-length direction. The position overlapping with the center of the conductive layer TGE is set to 0 nm on the horizontal axis. The dotted line in FIG. 7B represents the donor concentration distribution before heat treatment, the dashed line in FIG. 7B represents the donor concentration distribution after heat treatment at 400° C. for 4 hours, and the solid line in FIG. 7B represents the donor concentration distribution after heat treatment at 400° C. for 8 hours.

[0150] 7A shows the concentration distribution of donors before and after the heat treatment in the oxide semiconductor layer OS. Note that in the oxide semiconductor layer OS in FIG. 7A, a lower donor concentration is indicated by a darker color, and a higher donor concentration is indicated by a lighter color.

[0151] 8A to 8C show Id-Vg characteristics. In FIGS. 8A to 8C, the horizontal axis represents gate voltage (Vg) [V], and the vertical axis represents drain current (Id) [A]. The solid lines represent the measured Id-Vg characteristics, and the dotted lines represent the Id-Vg characteristics calculated using the donor concentration distribution shown in FIG. 7B. FIG. 8A shows the results before heat treatment, FIG. 8B shows the results after heat treatment at 400° C. for four hours, and FIG. 8C shows the results after heat treatment at 400° C. for eight hours.

[0152] 8A to 8C, it can be seen that the actually measured electrical characteristics can be reproduced by taking into consideration the donor concentration distribution.

[0153] 9A is a cross-sectional view of another example of a semiconductor element. The semiconductor element shown in FIG. 9A is an n-channel OS transistor, and the carriers are donors.

[0154] The semiconductor element shown in Fig. 9A is a double-gate transistor having a TGSA structure. The components of the semiconductor element shown in Fig. 9A are the same as those of the semiconductor element shown in Fig. 7A, so the contents described with reference to Fig. 7A can be referred to.

[0155] In addition, in FIG. 9A, the layout is such that the semiconductor element is 1 μm ２ In other words, the density of the semiconductor elements is designed to be 1.0 element / μm ２ The layout is designed so that

[0156] The dashed line in FIG. 9A indicates a portion located at the center in the film thickness direction of the oxide semiconductor layer OS.

[0157] 9B is a diagram illustrating an example of a donor concentration distribution created by calculation. FIG. 9B shows the donor concentration distribution in the portion indicated by the dashed line in FIG. 9A. In FIG. 9B, the vertical axis represents the donor concentration [cm −３], and the horizontal axis represents the position [nm] in the L-length direction. The position overlapping with the center of the conductive layer TGE is set to 0 nm on the horizontal axis. The dotted line in FIG. 9B represents the donor concentration distribution before heat treatment, the dashed line in FIG. 9B represents the donor concentration distribution after heat treatment at 400° C. for 4 hours, and the solid line in FIG. 9B represents the donor concentration distribution after heat treatment at 400° C. for 8 hours. The dotted line and dashed line in FIG. 9B almost overlap.

[0158] 10A to 10C show Id-Vg characteristics. In FIGS. 10A to 10C, the horizontal axis represents gate voltage (Vg) [V], and the vertical axis represents drain current (Id) [A]. The solid lines represent the measured Id-Vg characteristics, and the dotted lines represent the Id-Vg characteristics calculated using the donor concentration distribution shown in FIG. 9B. FIG. 10A shows the results before heat treatment, FIG. 10B shows the results after heat treatment at 400° C. for 4 hours, and FIG. 10C shows the results after heat treatment at 400° C. for 8 hours.

[0159] 10A to 10C, it can be seen that the actually measured electrical characteristics can be reproduced by taking into consideration the donor concentration distribution.

[0160] From the above, it can be seen that by taking the donor concentration distribution into consideration, it is possible to reproduce the actually measured electrical characteristics even when the layout is different.

[0161] The simulation software does not need to be limited to TCAD. The target of the concentration distribution is not limited to the donor. The concentration distribution in the W direction of the semiconductor element may be taken into account in addition to the L direction of the semiconductor element.

[0162] Next, data augmentation (sometimes called data padding) is performed. Data augmentation is a technique for increasing the number of training data (expanding the amount of training data) by generating variant training data based on already prepared training data.

[0163] As an example, the number of density distributions is increased using the actual measured values ​​of the acquired electrical characteristics. For example, it is advisable to increase the number of density distributions by taking into account the variation in the actual measured values ​​of the electrical characteristics. Specifically, it is assumed that the labels of the first learning data have a variation according to a normal distribution. In this case, the following electrical characteristics are prepared, centered around one of the actual measured values ​​of the acquired electrical characteristics: 34 points within a range of ±1σ, 7 points within a range of −2σ to −1σ, 7 points within a range of +1σ to +2σ, 1 point within a range of −3σ to −2σ, and 1 point within a range of +2σ to +3σ. Then, the number of density distributions can be increased by calculating density distributions corresponding to these electrical characteristics. In other words, density distributions can be padded.

[0164] Based on the above, a plurality of second training data are created using the calculated concentration distribution as input and actual measured values ​​of the electrical characteristics of the semiconductor element as correct labels, and a plurality of second training data are created using the calculated and inflated concentration distribution as input and electrical characteristics prepared on the assumption that they follow a normal distribution as correct labels. A second data set including the created plurality of second training data is used to train a second model. In other words, at least one of the plurality of second training data included in the second data set has electrical characteristics and a concentration distribution created by calculation using layout data from which the electrical characteristics were obtained.

[0165] Furthermore, a plurality of first training data are created using layout data as input, with density distributions created by calculation or density distributions inflated by calculation as correct labels. A first model is trained using a first dataset including the created plurality of first training data.

[0166] As described above, the first learning data and the second learning data are padded from the actual measured values ​​of the electrical characteristics, and the electrical characteristics of the semiconductor element in any layout data can be estimated.

[0167] [Creation Method and Learning Method 2] In the above-described [Creation Method and Learning Method 1], a concentration distribution is created by calculation so as to reproduce the actual measured values ​​of the electrical characteristics of a semiconductor element, but the present invention is not limited to this. In this section, a learning method different from the above-described [Creation Method and Learning Method 1] will be described using Figures 11A to 13.

[0168] For example, it is possible to create a concentration distribution by calculation using layout data and a physical model of a semiconductor device. Specifically, a diffusion model is prepared, and the diffusion model is reflected in the bulk of the components and the interfaces between the components, and a concentration distribution can be created by performing calculations.

[0169] In this section, an OS transistor is used as a semiconductor element, and a concentration distribution of oxygen and oxygen vacancies is used as a concentration distribution, and a manufacturing method and a learning method will be described.

[0170] In order to calculate the change in the concentration of oxygen and oxygen vacancies in the channel formation region of an OS transistor, oxygen (exO) and oxygen vacancies (V Ｏ The behavior of ions is classified into four types: the first is diffusion, the second is generation, the third is recombination, and the fourth is desorption.

[0171] The first behavior will be described with reference to FIG. 11A.

[0172] In the first behavior, oxygen and oxygen vacancies diffuse through the bulk of the constituent element according to the unsteady diffusion equation, which is Fick's second law. The unsteady diffusion equation is shown in the following equations (1) and (2).

[0173]

[0174] where D is the diffusion coefficient, c is the concentration of oxygen or oxygen vacancies, t is time, and k Ｂ is the Boltzmann constant, T is the absolute temperature, and E ａ is the activation energy.

[0175] 11A shows the diffusion of the element OA from top to bottom in the oxide layer OI, where the concentration of the element OA decreases from top to bottom. In other words, the diffusion of the element OA in the direction of the arrow is shown. The element OA is oxygen or oxygen vacancy.

[0176] The second behavior will be described with reference to Fig. 11B. In Fig. 11B, OS represents an oxide semiconductor layer, ME represents a metal layer, OX represents an oxide film, and VO represents oxygen vacancies.

[0177] In the second behavior, oxygen vacancies VO are formed in the oxide semiconductor layer OS at the interface between the oxide semiconductor layer OS and the metal layer ME due to oxidation of the metal layer ME. At this time, an oxide film OX grows in the metal layer ME near the interface. It is assumed that the formation of oxygen vacancies VO becomes less likely as the oxide film OX becomes thicker. Note that it is assumed that the second behavior ceases to react when the reducing power on the metal layer ME side is lost due to the growth of the oxide film OX, or when the oxygen vacancy concentration in the oxide semiconductor layer OS reaches an upper limit.

[0178] Based on the above assumptions, the following equations (3) and (4) are derived.

[0179]

[0180] where n is the outward normal vector at the interface between structural elements (arrow shown in FIG. 11B), J is the vector field, G is the oxygen vacancy formation coefficient, and c ｍａｘ is the upper limit of the oxygen vacancy concentration, and c Ｖｏ is the oxygen vacancy concentration, and G ０ is the probability of oxygen vacancy formation, and E ｇ is the activation energy.

[0181] The third behavior will be described with reference to Fig. 11C. In Fig. 11C, OS represents an oxide semiconductor layer, OI represents an oxide layer, VO represents oxygen vacancies, and O represents oxygen.

[0182] In the third behavior, when oxygen vacancies VO and oxygen O exist near the interface between the oxide semiconductor layer OS and the oxide layer OI, the oxygen vacancies VO are reduced by recombination of the oxygen vacancies VO and oxygen O. The reduction of the oxygen vacancies VO due to recombination is called curing. The curing occurs when the oxygen concentration (c ｅｘＯ ) and oxygen deficiency concentration (c Ｖｏ ) is assumed to be proportional to

[0183] Based on the above assumptions, the following equations (5) and (6) are derived.

[0184]

[0185] where R is the recombination coefficient of oxygen vacancies and oxygen, and R ０ is the recombination reaction rate, and E ｒ is the activation energy.

[0186] The fourth behavior will be described with reference to Fig. 11D, in which OI denotes an oxide layer, ME denotes a conductive layer, OX denotes an oxide film, and O denotes oxygen.

[0187] In the fourth behavior, when oxygen O is present near the interface between the metal layer ME and the oxide layer OI, desorption of oxygen O occurs due to oxidation of the metal layer ME, similar to the first behavior. It is assumed that desorption of oxygen O also becomes less likely as the oxide film OX grows.

[0188] Based on the above assumptions, the following equations (7) and (8) are derived.

[0189]

[0190] where Des is the oxygen desorption coefficient, Des ０ is the oxygen desorption probability, and E ｄｅｓ is the activation energy.

[0191] In this way, the concentration distribution of oxygen and oxygen vacancies in a semiconductor element based on any layout data can be created.

[0192] An example of a semiconductor device to which the above diffusion model can be applied is shown in FIGS. 11E and 11F.

[0193] The semiconductor element shown in FIG. 11E includes a conductive layer TGE, a conductive layer SD1, a conductive layer SD2, a conductive layer BGE, a conductive layer VIA1, a conductive layer VIA2, an oxide semiconductor layer OS, an insulating layer TGI, an insulating layer BGI, and an insulating layer OST.

[0194] 11E is a transistor having two gates, a so-called dual-gate transistor, and has a TGSA structure. The conductive layer TGE functions as a top gate electrode, the insulating layer TGI functions as a top gate insulating layer, the conductive layer BGE functions as a back gate electrode, the insulating layer BGI functions as a back gate insulating layer, the conductive layers SD1 and SD2 function as source and drain electrodes, and a channel is formed in the oxide semiconductor layer OS. The conductive layers VIA1 and VIA2 function as plugs or wirings.

[0195] 11F is an enlarged view of the region surrounded by the dashed line in FIG. 11E. The region Q surrounded by the dotted line in FIG. 11F is the region to which the second behavior is applied, the region R surrounded by the dashed line in FIG. 11F is the region to which the third behavior is applied, and the region S surrounded by the dashed line in FIG. 11F is the region to which the fourth behavior is applied. Furthermore, the first behavior is applied to the bulk of each component.

[0196] An example of software that can be used to calculate the concentration distribution is the finite element method-based general-purpose simulation software "COMSOL Multiphysics."

[0197] 12A to 12D show the results of calculating the concentration distributions of oxygen and oxygen vacancies using "COMSOL Multiphysics" for the three-dimensional model of the semiconductor element shown in FIGS. 11E and 11F. FIG. 12A is a cross-sectional view of the semiconductor element in the channel length direction, and FIG. 12B is an enlarged view of the channel formation region and its vicinity in FIG. 12A. FIG. 12C is a cross-sectional view of the semiconductor element in the channel width direction, and FIG. 12D is an enlarged view of the channel formation region and its vicinity in FIG. 12C. In the oxide semiconductor layer OS in FIGS. 12A to 12D, a lower concentration of oxygen vacancies is indicated by a darker color, and a higher concentration of oxygen vacancies is indicated by a lighter color.

[0198] As shown in FIGS. 12A to 12D, the concentration distribution of oxygen vacancies in the channel formation region of an OS transistor can be calculated using layout data and a diffusion model.

[0199] The software that can be used to calculate the concentration distribution is not limited to the above.

[0200] In addition to the donor concentration distribution, introducing a negative fixed charge makes it easier to reproduce the measured electrical characteristics. Therefore, by regarding oxygen as a negative fixed charge and oxygen vacancies as a donor source, the actual measurements can be reproduced from the concentration distribution of oxygen and oxygen vacancies in the semiconductor device.

[0201] FIG. 13 shows a comparison between the shift voltage calculated by introducing the concentration distribution created by the method described with reference to FIGS. 11A to 12D into a device simulation (TCAD (Synopsys)) and the actually measured value of the shift voltage. In FIG. 13, the vertical axis represents the calculated shift voltage, and the horizontal axis represents the actually measured value of the shift voltage. The black circles in FIG. 13 represent the shift voltage when the drain voltage (Vd) is 0.1 V, and the squares in FIG. 13 represent the shift voltage when the drain voltage (Vd) is 1.2 V.

[0202] It can be seen from FIG. 13 that there is a correlation between the measured values ​​of the electrical characteristics and the electrical characteristics calculated by the calculation using the concentration distribution created by the above method.

[0203] Next, data augmentation is performed.

[0204] For example, it is advisable to increase the number of concentration distributions in consideration of layout variations during the process, such as pattern misalignment and film thickness variations.

[0205] As described above, a plurality of first training data are created using layout data as input, with density distributions created by calculation or density distributions inflated by calculation as correct labels. A first model is trained using a first dataset including the created plurality of first training data. That is, at least one of the plurality of first training data included in the first dataset has layout data and a density distribution created by calculation using the layout data and a physical model.

[0206] Furthermore, a second training data set is created in which the calculated concentration distribution or the calculated inflated concentration distribution is used as an input and the measured values ​​of the electrical characteristics are used as correct labels. A second model is trained using the second data set including the created second training data.

[0207] As described above, the first learning data and the second learning data are padded from the layout data, and the electrical characteristics of the semiconductor element in any layout data can be estimated.

[0208] This concludes the description of the methods for creating the first and second data sets, and the methods for training the first and second models.

[0209] Although an OS transistor is used as a semiconductor element in this embodiment, the semiconductor element is not limited to an OS transistor. A transistor using a semiconductor material other than an oxide semiconductor for a channel formation region may be used as a diode, a light-emitting element, a light-receiving element, or the like.

[0210] According to one aspect of the present invention, a system for predicting electrical characteristics of a semiconductor device can be provided. According to one aspect of the present invention, a method for predicting electrical characteristics of a semiconductor device can be provided. According to one aspect of the present invention, a method for creating a dataset for training a model used in predicting electrical characteristics of a semiconductor device can be provided.

[0211] A plurality of configuration examples shown in this embodiment mode can be combined as appropriate.

[0212] BGE: conductive layer, BGI: insulating layer, ME: metal layer, O: oxygen, OA: element, OI: oxide layer, OS: oxide semiconductor layer, OST: insulating layer, OX: oxide film, P: region, Q: region, R: region, S: region, SD1: conductive layer, SD2: conductive layer, TGE: conductive layer, TGI: insulating layer, VIA1: conductive layer, VIA2: conductive layer, VO: oxygen vacancy, 100: electrical characteristic prediction system, 110: reception unit, 120: processing unit, 121: first processing unit, 122: second processing unit , 123: third processing unit, 130: presentation unit, 200L: layout data, 201: mask area, 201L: layer, 201p: partial area, 202: mask area, 202L: layer, 203: mask area, 203L: layer, 203p: partial area, 204: mask area, 204L: layer, 204p: partial area, 205: mask area, 205L: layer, 205p: partial area, 211p: partial area, 212p: partial area, 213p: partial area, 299p: partial area

Claims

The device includes a reception unit, a processing unit, and a presentation unit, the receiving unit has a function of receiving layout data of a semiconductor element, the processing unit is configured to perform a first inference process for predicting a concentration distribution from the layout data based on a first model, and a second inference process for predicting an electrical characteristic of the semiconductor element from the concentration distribution based on a second model; the presentation unit has a function of presenting a result of the second inference, the concentration distribution is a concentration distribution of at least one selected from donors, oxygen, oxygen vacancies, and impurity atoms, The electrical characteristic prediction system, wherein the electrical characteristic of the semiconductor element is at least one selected from a threshold voltage, a shift voltage, a subthreshold swing value (S value), and a drain-induced barrier lowering (DIBL). 　 In claim 1, the first model has been trained on a first dataset; the first data set includes a plurality of first data; each of the plurality of first data includes layout data and a density distribution; At least one of the plurality of first data includes layout data and a concentration distribution created by calculation using the layout data and a physical model. 　 In claim 1, the second model has been trained on a second dataset; the second data set comprises a plurality of second data; each of the plurality of second data has a concentration distribution and an electrical characteristic; At least one of the plurality of second data includes an electrical characteristic and a concentration distribution created by calculation using layout data from which the electrical characteristic is obtained. 　 In claim 1, The processing unit is configured to convert the layout data into numerical data. 　 In claim 4, the layout data includes two or more layers; The processing unit is configured to perform the following processes: assigning a bit pattern to a mask area of ​​each layer; dividing the semiconductor element and its periphery into partial areas in each layer; and adding, for each divided partial area, the bit pattern assigned to the mask area included in the partial area. 　 In claim 1, The electrical characteristic prediction system is configured so that the processing unit executes a process of converting the layout data into image data. 　 In claim 6, the layout data includes two or more layers; The processing unit is configured to perform the following processes: assigning colors to mask areas of each layer; dividing the semiconductor element and its periphery into partial areas in each layer; and synthesizing the colors assigned to the mask areas included in each partial area for each divided partial area. 　 A method for predicting electrical characteristics of a semiconductor device, comprising first to fourth steps, In the first step, the information processing device receives layout data of a semiconductor device; In the second step, the information processing device performs a first inference to predict a density distribution from the layout data based on a first model; the concentration distribution is a concentration distribution of at least one selected from donors, oxygen, oxygen vacancies, and impurity atoms, In the third step, the information processing device performs a second inference to predict electrical characteristics of the semiconductor element from the concentration distribution based on a second model; the electrical characteristic of the semiconductor element is at least one selected from a threshold voltage, a shift voltage, a subthreshold swing value (S value), and a drain-induced barrier lowering (DIBL); In the fourth step, the information processing device presents a result of the second inference. 　 In claim 8, the first model has been trained on a first dataset; the first data set includes a plurality of first data; each of the plurality of first data includes layout data and a density distribution; At least one of the plurality of first data includes layout data and a concentration distribution created by calculation using the layout data and a physical model. In claim 8, the second model has been trained on a second dataset; the second data set comprises a plurality of second data; each of the plurality of second data has a concentration distribution and an electrical characteristic; At least one of the plurality of second data includes an electrical characteristic and a concentration distribution created by calculation using layout data from which the electrical characteristic is obtained. 　 In claim 8, A fifth step is provided between the first step and the second step, the layout data includes two or more layers; In the fifth step, the information processing device assigns a bit pattern to a mask area of ​​each layer, divides the semiconductor element and its periphery into partial areas in each layer, and adds up the bit patterns assigned to the mask areas included in each partial area, thereby converting the layout data into numerical data. 　 In claim 8, A fifth step is provided between the first step and the second step, the layout data includes two or more layers; In the fifth step, the information processing device assigns colors to mask areas of each layer, divides the semiconductor element and its periphery into partial areas in each layer, and for each divided partial area, combines the colors assigned to the mask areas included in the partial area, thereby converting the layout data into image data.

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