Semiconductor device

Abstract

In the present invention, oscillation caused by switching of a rectifying element is suppressed by reducing the influence of a time constant caused by the parasitic capacitance, etc., of the rectifying element. This semiconductor device is configured to comprise: a rectifying element; a determination circuit that determines ON / OFF of the rectifying element on the basis of the voltage between a pair of output terminals of the rectifying element; an amplification circuit that controls ON / OFF of the rectifying element on the basis of the determination result of the determination circuit; and a voltage division circuit connected between an output terminal of the amplification circuit or an input terminal of the rectifying element and one of the output terminals of the rectifying element. The determination circuit sets a divided voltage of a node of the voltage division circuit as a positive input or a negative input.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] One technology related to semiconductor devices is disclosed in the following Patent Document 1. Patent Document 1 discloses a technology of "a rectifier circuit including a rectifier element that performs synchronous rectification, a determination circuit that determines whether the rectifier element is on or off based on the voltage between a pair of main terminals of the rectifier element, and a gate drive circuit that turns the rectifier element on or off based on the determination result." This rectifier circuit is a voltage-determining synchronous rectifier circuit.

[0003] Japanese Patent Application Laid-Open No. 2015-116077

[0004] In a voltage-determining synchronous rectifier circuit, especially an autonomous synchronous rectifier circuit, the rectification signal from the determination circuit is fed back via a rectifier element, forming a closed-loop operation. In this closed-loop operation, when the rectifier element is turned on, the resistance value is reduced, causing a drop in the voltage between the output terminals (source terminal - drain terminal) of the rectifier element, and the determination circuit is turned off. This repetition of operation is subject to delays due to the influence of a time constant caused by the parasitic capacitance of the rectifier element, which can easily cause oscillations due to the switching of the rectifier element.

[0005] The present invention has been made in view of the above circumstances, and aims to reduce the influence of the time constant caused by the parasitic capacitance of the rectifying element and to suppress oscillation caused by switching of the rectifying element.

[0006] In order to solve the above problems, for example, the configuration described in the claims is adopted. The present application includes a plurality of means for solving the above problems, and one example thereof is a semiconductor device including a rectifying element, a determination circuit that determines whether the rectifying element is on or off based on a voltage between a pair of output terminals of the rectifying element, an amplifier circuit that controls the rectifying element on or off based on the determination result of the determination circuit, and a voltage divider circuit connected between the output terminal of the amplifier circuit or the input terminal of the rectifying element and one of the output terminals of the rectifying element, wherein the determination circuit receives the divided voltage of the voltage divider circuit as a positive input or a negative input.

[0007] According to the present invention, it is possible to reduce the influence of the time constant caused by the parasitic capacitance of the rectifying element and to suppress oscillation caused by switching of the rectifying element.

[0008] Problems, configurations, and effects other than those described above will become apparent from the following description of the mode for carrying out the invention (hereinafter referred to as the embodiment).

[0009] FIG. 1 is a circuit diagram showing an example of the configuration of a synchronous rectifier circuit according to a first embodiment of the present invention. FIG. 2 is a waveform diagram showing waveforms when half-wave rectification is performed in a synchronous rectifier circuit according to a reference example. FIG. 3 is an operational waveform diagram during rectification in a synchronous rectifier circuit according to a reference example. FIG. 4 is a waveform diagram explaining how delays occur due to the gate capacitance of a rectifier element in a synchronous rectifier circuit according to a reference example. FIG. 5 is a waveform diagram explaining conditions under which the synchronous rectifier circuit according to a reference example does not oscillate. FIG. 6 is a waveform diagram showing waveforms when half-wave rectification is performed in the synchronous rectifier circuit according to the first embodiment of the present invention. FIG. 7 is a circuit diagram showing an example of the configuration of an autonomous synchronous rectifier circuit according to a second embodiment of the present invention. FIG. 8 is a circuit diagram showing an example of a configuration suitable for use as an amplifier circuit according to a third embodiment of the present invention. FIG. 9 is a waveform diagram showing the operating voltages of an N-channel MOSFET and a P-channel MOSFET in an inverter with a common-source configuration, the current when they are connected in series, and the through current. FIG. 10 is a circuit diagram showing an example of the configuration of an output stage of an amplifier circuit according to a fourth embodiment of the present invention. FIG. 11 is a waveform diagram showing the operating voltages of an N-channel MOSFET and a P-channel MOSFET in an amplifier circuit with a common-drain configuration, the current when they are connected in series, and the current at an intermediate voltage. FIG. 12 is a circuit diagram showing an example of the configuration of an amplifier circuit according to a fifth embodiment of the present invention.

[0010] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functions or configurations are designated by the same reference numerals, and redundant description will be omitted.

[0011] First Embodiment [Configuration Example of Synchronous Rectifier Circuit] In a first embodiment of the present invention, a synchronous rectifier circuit is exemplified as a semiconductor device. Fig. 1 is a circuit diagram showing a configuration example of a synchronous rectifier circuit according to the first embodiment of the present invention.

[0012] As shown in FIG. 1, the synchronous rectifier circuit 10 according to the first embodiment is a voltage determination type synchronous rectifier circuit including a rectifier element 11, a determination circuit 12, an amplifier circuit 13, and a voltage divider circuit .

[0013] Here, a synchronous rectifier circuit 20 is shown as an example, which uses a MOSFET with an SJ (super junction) structure as the rectifier element 11. The rectifier element 11 is connected between a pair of output terminals 15 and 16. That is, one output terminal (e.g., drain terminal) of the rectifier element 11 is connected to the output terminal 15, and the other output terminal (e.g., source terminal) of the rectifier element 11 is connected to the output terminal 16. A power supply voltage VIN is applied to the determination circuit 12 and the amplifier circuit 13 through an input terminal 17.

[0014] The judgment circuit 12 performs a judgment process of whether the rectifying element 11 is on (forward direction) or off (reverse direction) by, for example, using the voltage on the source terminal side of the rectifying element 11 as a positive input and the voltage at node n1 of the voltage divider circuit 14, i.e., the divided voltage of the voltage divider circuit 14, as a negative input.

[0015] Here, it is assumed that the amplifier circuit 13 is of non-inverting logic, and the divided voltage of the voltage divider circuit 14 is used as a negative input. However, it is also possible for the amplifier circuit 13 to be of inverting logic, and in this case, the judgment circuit 12 will use the divided voltage of the voltage divider circuit 14 as a positive input.

[0016] The amplifier circuit 13 controls the on (forward direction) / off (reverse direction) of the rectifier element 11 based on the determination result of the determination circuit 12. In other words, the amplifier circuit 13 is a gate driver that drives the input terminal (gate terminal) of the rectifier element 11.

[0017] The voltage divider circuit 14 is connected between the output terminal of the amplifier circuit 13 and one output terminal (e.g., drain terminal) of the rectifier element 11. Specifically, the voltage divider circuit 14 is composed of a resistor element 141 having one end connected to one output terminal (e.g., drain terminal) of the rectifier element 11, and a resistor element 142 connected between the other end of the resistor element 141 and the output terminal of the amplifier circuit 13, and the common connection node of the resistor elements 141 and 142 is a node n1 from which a divided voltage is derived.

[0018] It should be noted that, here, it is assumed that the circuit configuration is such that the output terminal of the amplifier circuit 13 and the input terminal (gate terminal) of the rectifier element 11 are directly connected, and based on this assumption, the voltage divider circuit 14 is connected between the output terminal of the amplifier circuit 13 and one of the output terminals of the rectifier element 11. However, this connection configuration is not limited to this. For example, if some kind of circuit (e.g., a resistor element) is interposed between the output terminal of the amplifier circuit 13 and the input terminal of the rectifier element 11, the voltage divider circuit 14 can also be connected between the input terminal and one of the output terminals of the rectifier element 11.

[0019] [Regarding Oscillation Caused by Switching of Rectifier Element] Here, as a reference example, a synchronous rectifier circuit having a circuit configuration that only feedbacks the drain terminal-source terminal voltage (drain-source voltage) of the rectifier element 11 will be described, in contrast to the synchronous rectifier circuit 10 according to the first embodiment having the above configuration. In the synchronous rectifier circuit according to the reference example that only feedbacks the drain-source voltage of the rectifier element 11, a time constant occurs due to the parasitic capacitance of the rectifier element 11, and a delay occurs due to the influence of this time constant. Furthermore, when the forward current when the rectifier element 11 is on is small, the on / off control of the rectifier element 11 is not constant, and oscillation occurs due to the switching of the rectifier element 11 (see FIG. 2).

[0020] FIG. 2 shows waveforms obtained when half-wave rectification is performed in a synchronous rectifier circuit according to a reference example having a circuit configuration in which only the drain-source voltage of the rectifier element 11 is fed back. FIG. 3 shows operational waveforms during rectification in the synchronous rectifier circuit according to the reference example. The operational waveforms in FIG. 3 show waveforms of the drain-source voltage Vds of the rectifier element 11, the output voltage Vcmp_out of the determination circuit 12, the output voltage Vamp_out of the amplifier circuit 13, the on-resistance Rds of the rectifier element 11, and the current -Ids flowing through the rectifier element 11. The drain-source voltage Vds of the rectifier element 11 is fed back to the determination circuit 12.

[0021] 4 shows a waveform diagram illustrating how a delay occurs due to the gate capacitance Cg of the rectifier element 11 in a synchronous rectifier circuit according to a reference example of a circuit configuration that only feedbacks the drain-source voltage of the rectifier element 11. The waveform diagram in FIG. 4 shows the waveforms of the drain-source voltage Vds of the rectifier element 11, the output voltage Vcmp_out of the determination circuit 12, and the output voltage Vamp_out of the amplifier circuit 13.

[0022] When the drain-source voltage Vds of the rectifying element 11 reaches the determination voltage Vcmp of the determination circuit 12, the output voltage Vcmp_out of the determination circuit 12 is inverted from low level (L) to high level (H). In response to this, the output voltage Vamp_out of the amplifier circuit 13 gradually rises from low level toward the on-voltage of the rectifying element 11. At this time, a delay occurs due to the gate capacitance Cg of the rectifying element 11 until the output voltage Vamp_out of the amplifier circuit 13 reaches the on-voltage of the rectifying element 11 from low level.

[0023] Here, the conditions under which oscillation does not occur in a synchronous rectifier circuit according to a reference example of a circuit configuration that only feedbacks the drain-source voltage of the rectifier element 11 will be described using the waveform diagram of Fig. 5. The waveform diagram of Fig. 5 shows the waveforms of the drain-source voltage Vds of the rectifier element 11, the output voltage Vcmp_out of the determination circuit 12, the output voltage Vamp_out of the amplifier circuit 13, the on-resistance Rds of the rectifier element 11, and the current -Ids flowing through the rectifier element 11.

[0024] Although binary control of the rectifying element 11 (on / off) can reduce delay time, if the input and output do not match due to feedback operation, the control becomes unstable, and oscillation cannot be avoided with binary control as is. If continuous analog control were used, it would be possible to operate at a point where the input and output match, making it possible to suppress oscillation. Specifically, an intermediate voltage between high level (H) and low level (L) is effective in preventing oscillation. However, even with analog control, oscillation cannot be suppressed if the delay due to the gate capacitance Cg is large.

[0025] [Regarding the Function and Effect of the Synchronous Rectifier Circuit of the First Embodiment] In contrast to the synchronous rectifier circuit of the reference example, which has a circuit configuration that only feedbacks the drain-source voltage of the rectifier element 11 described above, the synchronous rectifier circuit 10 of the first embodiment has a circuit configuration in which a voltage divider circuit 14 is provided between the output terminal of the amplifier circuit 13 and one output terminal (e.g., the drain terminal) of the rectifier element 11. The input to the determination circuit 12 is not the drain-source voltage of the rectifier element 11, but the voltage between node n1 of the voltage divider circuit 14 and the source terminal of the rectifier element 11. This reduces the influence of the time constant due to the parasitic capacitance of the rectifier element 11 and suppresses oscillation due to switching of the rectifier element 11. More specifically, this makes it easier to control the switching of the rectifier element 11 at a voltage intermediate between on and off, thereby making it easier to suppress oscillation.

[0026] 6 shows a waveform diagram when half-wave rectification is performed in the synchronous rectifier circuit 10 according to the first embodiment, which is provided with a feedback circuit that feeds back the output of the amplifier circuit 13 to the determination circuit 12. The resistor element 142 of the voltage divider circuit 14 forms the feedback circuit that feeds back the output of the amplifier circuit 13 to the determination circuit 12.

[0027] Furthermore, in the synchronous rectifier circuit 10 according to the first embodiment, when the resistance value of the resistor element 141 in the voltage divider circuit 14 is R1 and the resistance value of the resistor element 142 is R2, the gain G of the synchronous rectifier circuit 10 is G = R1 / (R1 + R2). That is, the gain G of the synchronous rectifier circuit 10 is lower than the gain (=1) when the voltage divider circuit 14 is not provided. In this way, the reduction in the gain G of the synchronous rectifier circuit 10 facilitates convergence to a state in which the control input of the rectifier element 11 and the determination output of the determination circuit 12 match. This also effectively suppresses oscillation caused by the switching of the rectifier element 11.

[0028] Second Embodiment [Configuration Example of an Autonomous Synchronous Rectifier Circuit] In a first embodiment of the present invention, an autonomous synchronous rectifier circuit is exemplified as a semiconductor device. Fig. 7 is a circuit diagram showing a configuration example of an autonomous synchronous rectifier circuit according to a second embodiment of the present invention.

[0029] As shown in Figure 7, the autonomous synchronous rectifier circuit 20 of the second embodiment has a circuit configuration that includes a rectifier element 11, a judgment circuit 12, an amplifier circuit 13, and a voltage divider circuit 14, as well as a step-down circuit 21, a diode 22, and a capacitance element 23.

[0030] The step-down circuit 21 is composed of N-channel depletion-type MOSFETs 211 and 212 and resistors 213 and 214. The MOSFET 211 is connected between one output terminal (e.g., drain terminal) of the rectifier 11 and one end of the resistor 141 of the voltage divider circuit 14. The drain terminal of the MOSFET 212 is connected to one output terminal (e.g., drain terminal) of the rectifier 11, and the source terminal is connected to the gate terminal of the MOSFET 211. The resistors 213 and 214 are connected in series between the gate terminal of the MOSFET 211 and the other output terminal (e.g., source terminal) of the rectifier 11. The gate terminal of the MOSFET 212 is connected to a common connection node N of the resistors 213 and 214.

[0031] [Example of Operation of Autonomous Synchronous Rectifier Circuit] The step-down circuit 21 configured as described above steps down a relatively high AC voltage applied to one output terminal (e.g., drain terminal) of the rectifier element 11. The voltage stepped down by the step-down circuit 21 is supplied to the capacitor element 23 via the diode 22. This charges the capacitor element 23. This charging operation is performed during a positive period of the AC voltage. Then, during a negative period of the AC voltage, a voltage based on the charge stored in the capacitor element 23 is supplied to the determination circuit 12 and the amplifier circuit 13 as a power supply voltage.

[0032] As described above, the autonomous synchronous rectifier circuit 20 according to the second embodiment is configured such that the negative input terminal of the determination circuit 12 and one of the output terminals (for example, the drain terminal) of the rectifier element 11 are not directly connected to each other, but rather the step-down circuit 21 is interposed between the two terminals. In the autonomous synchronous rectifier circuit 20 having this circuit configuration, when a large current flows from the source terminal (terminal A) to the drain terminal (terminal B) of the rectifier element 11, high resistance is present between the negative input terminal (terminal A') and the positive input terminal (terminal B') of the determination circuit 12, and therefore the same voltage is applied between terminals A and B.

[0033] [Regarding the Function and Effect of the Amplifier Circuit According to the Second Embodiment] As described above, in the autonomous synchronous rectifier circuit 20 according to the second embodiment, although the negative input terminal of the determination circuit 12 and one output terminal (e.g., the drain terminal) of the rectifier element 11 are not directly connected, during operation in which a large current flows from terminal B to terminal A, the (A-B) voltage = (A'-B') voltage. Therefore, the autonomous synchronous rectifier circuit 20 according to the second embodiment can also achieve the same functions and effects as the synchronous rectifier circuit 10 according to the first embodiment. That is, by providing the voltage divider circuit 14 and setting the input of the determination circuit 12 to the voltage between node n1 of the voltage divider circuit 14 and the source terminal of the rectifier element 11, the function and effect of suppressing oscillation caused by switching of the rectifier element 11 can be achieved.

[0034] Third Embodiment In a second embodiment of the present invention, a configuration example suitable for use as the amplifier circuit 13 in the synchronous rectifier circuit 10 according to the first embodiment or the autonomous synchronous rectifier circuit 20 according to the second embodiment will be described. Fig. 8 is a circuit diagram showing a configuration example suitable for use as the amplifier circuit 13 according to the third embodiment of the present invention.

[0035] (Regarding a gate driver with a common-source configuration) The amplifier circuit 13 is a gate driver that drives the input terminal (gate terminal) of the rectifier element 11. A typical gate driver often uses a circuit (inverter) with a common-source configuration in which a P-channel MOSFET and an N-channel MOSFET are connected in series. This common-source gate driver has very high drivability (driving capability) and gain (amplification factor), and is suitable for high-speed driving of loads such as gate capacitance (for example, driving the gate of a MOSFET).

[0036] However, in the case of a common-source inverter, if an intermediate voltage that has not been binarized is applied, the P-channel MOSFET and the N-channel MOSFET will be turned on simultaneously, causing conduction (short circuit) between the power supply line and the ground line, and a through current will flow between the power supply line and the ground line, increasing the power consumption of the gate driver and, ultimately, increasing the power consumption of the synchronous rectifier circuit that uses the gate driver as the amplifier circuit 13.

[0037] Figure 9 shows waveforms of the operating voltages of an N-channel MOSFET and a P-channel MOSFET in a source-grounded inverter, the current when they are connected in series, and the through current. In the waveform diagram in Figure 9, the vertical axis represents the gate-source voltage Vgs of the rectifier element, the horizontal axis represents the drain current Id and source current Is, VC represents the maximum power supply voltage, and Vth represents the threshold voltage of the rectifier element. The current capacity of the P-channel MOSFET alone is shown by the dotted waveform, and the current capacity of the N-channel MOSFET alone is shown by the dashed-dotted line.

[0038] [Configuration Example of Amplifier Circuit According to Third Embodiment] In contrast to a general gate driver (amplifier circuit) with a common-source configuration, the amplifier circuit 13 according to the third embodiment has a circuit configuration in which unit circuits (stages) with a common-drain configuration are connected in multiple stages. Fig. 8 illustrates a circuit configuration in which n stages of unit circuits 13_1 to 13_n with a common-drain configuration are cascade-connected.

[0039] Focusing on the first stage, the first-stage unit circuit 13_1 has a drain-grounded configuration in which a high-side N-channel MOSFET nm_1 and a low-side P-channel MOSFET pm_1 are connected in series between a positive power supply V+ and a negative power supply V-. Specifically, the drain terminal of the high-side N-channel MOSFET nm_1 is connected to the positive power supply V+, and the drain terminal of the low-side P-channel MOSFET pm_1 is connected to the negative power supply V-, with the source terminals and gate terminals of both MOSFETs nm_1 and pm_1 connected in common. The gate common connection node serves as an input terminal, and the source common connection node serves as an output terminal.

[0040] [Regarding the effects of the amplifier circuit according to the third embodiment] The unit circuits of the above configuration are connected in multiple stages, and the output terminal of the previous stage is connected to the input terminal of the next stage between the unit circuits 13_1 to 13_n of each stage, thereby forming an amplifier circuit 13 with a drain-grounded configuration.

[0041] In the case of the amplifier circuit 13 with a common-drain configuration, the gain (amplification factor) is slightly lower than 1, and the drivability (driving capability) is also inferior on average to that of a common-source configuration. However, even if an intermediate voltage that has not been binarized is input, the positive power supply V+ and the negative power supply V− are not electrically connected (short-circuited). This prevents a through current from flowing between the positive power supply V+ and the negative power supply V−, thereby reducing the power consumption of the amplifier circuit 13. Therefore, the amplifier circuit 13 of the third embodiment with a common-drain configuration is suitable for use as the amplifier circuit 13 in the synchronous rectifier circuit 10 of the first embodiment or the autonomous synchronous rectifier circuit 20 of the second embodiment, which perform a feedback operation in which an intermediate voltage (see FIG. 5 ) frequently appears. This allows the power consumption of the synchronous rectifier circuit 10 or the autonomous synchronous rectifier circuit 20 to be reduced.

[0042] Fourth Embodiment [Configuration Example of Amplifier Circuit According to Fourth Embodiment] The fourth embodiment is a first improvement of the third embodiment. Fig. 10 is a circuit diagram showing a configuration example of an output stage of an amplifier circuit according to a fourth embodiment of the present invention.

[0043] 10 illustrates the output stage of the amplifier circuit 13 according to the fourth embodiment, i.e., the final-stage unit circuit 13_n consisting of an N-channel MOSFET nm_n and a P-channel MOSFET pm_n. The amplifier circuit 13 according to the fourth embodiment has a circuit configuration in which an N-channel depletion-type MOSFET nmd for pull-down purposes is provided in the final-stage unit circuit 13_n.

[0044] The N-channel depletion-type MOSFET nmd has a drain terminal connected to the gate terminal of the P-channel MOSFET pm_n, and has a gate terminal and a source terminal connected to the negative power supply V-. This depletion-type MOSFET nmd is an element through which a drain current Id flows even when the gate-source voltage Vgs is a negative voltage.

[0045] [Regarding the Function and Effect of the Amplifier Circuit According to the Fourth Embodiment] As described above, in the amplifier circuit 13 according to the fourth embodiment, the final-stage unit circuit 13_n is provided with an N-channel depletion-type MOSFET nmd for pull-down purposes. As a result, even when the gate voltage Vg is equal to the source voltage Vs in the rectifier element 11, the depletion-type MOSFET nmd does not cause the rectifier element 11 to float, thereby stabilizing the operation of the amplifier circuit 13.

[0046] 11 shows waveform diagrams of the operating voltages of the N-channel MOSFET and the P-channel MOSFET in the amplifier circuit 13 with a common-drain configuration, the current when they are connected in series, and the current at an intermediate voltage. In the waveform diagram in Fig. 11, the current capacity of the P-channel MOSFET alone is shown by a dotted waveform, the current capacity of the N-channel MOSFET alone is shown by a dashed-dotted line, and the current capacity of the N-channel depletion-type MOSFET alone is shown by a broken line.

[0047] Fifth Embodiment [Configuration Example of Amplifier Circuit According to Fifth Embodiment] The fifth embodiment is a second improvement of the third embodiment. Fig. 12 is a circuit diagram showing a configuration example of an amplifier circuit according to a fifth embodiment of the present invention.

[0048] The amplifier circuit according to the fifth embodiment has a configuration in which a small-scale driver 30 with a common-source configuration is connected in parallel to an amplifier circuit 13 made up of unit circuits with a common-drain configuration connected in multiple stages. Here, "small-scale" means that the transistor size is smaller than that of the amplifier circuit 13 with a common-drain configuration.

[0049] Here, the amplifier circuit 13 has a circuit configuration in which two-stage cascade-connected unit circuits each having a drain-grounded configuration are illustrated. Specifically, the amplifier circuit 13 is configured to include a first-stage unit circuit 13_1 in which an N-channel MOSFET nm_1 and a P-channel MOSFET pm_1 are connected in series in this order between a positive power supply and a negative power supply, and a second-stage unit circuit 13_2 in which an N-channel MOSFET nm_2 and a P-channel MOSFET pm_2 are connected in series in this order between a positive power supply and a negative power supply.

[0050] In contrast to the amplifier circuit 13 with a common-drain configuration, the driver 30 with a common-source configuration has a circuit configuration in which three circuits (inverters) with a common-source configuration are cascaded. Specifically, the driver 30 with a common-source configuration is configured, between a positive power supply and a negative power supply, with a first-stage inverter 31 in which a P-channel MOSFET pm_11 and an N-channel MOSFET nm_11 are connected in series in this order, a second-stage inverter 32 in which a P-channel MOSFET pm_12 and an N-channel MOSFET nm_12 are connected in series in this order, and a third-stage inverter 33 in which a P-channel MOSFET pm_13 and an N-channel MOSFET nm_13 are connected in series in this order.

[0051] [Operational Effects of the Amplifier Circuit of the Fifth Embodiment] In the amplifier circuit 13 with a common-drain configuration, a dead zone where the output does not change with respect to the input may occur. Therefore, in the amplifier circuit of the fifth embodiment, as described above, a small-scale driver 30 with a common-source configuration is connected in parallel to the amplifier circuit 13 with a common-drain configuration, and input nodes and output nodes of the amplifier circuit 13 with a common-drain configuration and the driver 30 with a common-source configuration are connected to each other with the same logic. By connecting nodes of the same logic in this manner, it is possible to prevent the occurrence of a dead zone where the output does not change with respect to the input.

[0052] <<Modifications>> The present invention is not limited to the above-described embodiments, and various other applications and modifications are possible without departing from the spirit of the present invention as defined in the claims. The above-described embodiments have described the configuration of the semiconductor device in detail and specifically in order to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. For example, in the above-described embodiments, a case where an SJ-structure MOSFET is used as the rectifying element is illustrated, but the rectifying element is not limited to an SJ-MOSFET, and may be a power semiconductor element such as a SiC-MOSFET or an IGBT (Insulated Gate Bipolar Transistor).

[0053] 10...Synchronous rectification circuit according to the first embodiment, 11...Rectification element, 12...Determination circuit, 13...Amplification circuit, 14...Voltage dividing circuit, 15, 16...Output terminal, 17...Input terminal, 20...Autonomous synchronous rectification circuit according to the second embodiment, 21...Step-down circuit, 22...Diode, 23...Capacitance element, 30...Driver with source grounding configuration, 31, 32, 33...Inverter

Claims

1. A semiconductor device comprising: a rectifier element; a judgment circuit that judges whether the rectifier element is on or off based on the voltage between a pair of output terminals of the rectifier element; an amplifier circuit that controls the on / off of the rectifier element based on the judgment result of the judgment circuit; and a voltage divider circuit connected between the output terminal of the amplifier circuit or the input terminal of the rectifier element and one of the output terminals of the rectifier element, wherein the judgment circuit uses the divided voltage of the voltage divider circuit as a positive input or a negative input.

2. The semiconductor device according to claim 1, wherein the amplifier circuit is made up of multiple stages of unit circuits, each of which has an output terminal of a preceding circuit connected to an input terminal of a succeeding circuit, and each of the multiple stages of unit circuits is a drain-grounded circuit made up of an N-channel MOSFET and a P-channel MOSFET connected in series between a positive power supply and a negative power supply.

3. The semiconductor device according to claim 2, wherein the final stage unit circuit of the amplifier circuit has an N-channel depletion type MOSFET.

4. The semiconductor device according to claim 2, further comprising a driver with a common source connected in parallel to said amplifier circuit.

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