Temperature sensor comprising stack structure

Abstract

The present invention relates to a temperature sensor comprising a stack structure and, more specifically, comprises: a first MOS transistor of which one end is connected to a power source; and a second MOS transistor of which one end is connected to the other end of the first MOS transistor and the other end is connected to a ground, wherein the first and second MOS transistors are N-MOS transistors or P-MOS transistors and are the same type, when the first and second MOS transistors are N-MOS transistors, the gate of the first MOS transistor is connected to the source thereof, and when the first and second MOS transistors are P-MOS transistors, the gate of the second MOS transistor is connected to the source thereof.

Description

Temperature sensor including stack structure

[0001] The present invention relates to a temperature sensor, and more particularly, to a temperature sensor including a stack structure.

[0002]

[0003] Figures 1 and 2 are temperature sensors utilizing conventionally turned-off transistors.

[0004] As illustrated in Fig. 1, in the case of a temperature sensor utilizing a conventional NMOS, the gate voltage is connected to ground. Furthermore, as illustrated in Fig. 2, in the case of a temperature sensor utilizing a conventional PMOS, the gate voltage is connected to the power supply.

[0005] At this time, the leakage current generated by the temperature sensor illustrated in FIGS. 1 and 2 may be as shown in the following mathematical expression 1.

[0006]

[0007] At this time, in the case of NMOS, if we rewrite it as an equation for the output voltage, it is as follows: Mathematical Expression 2.

[0008]

[0009] Here, if the leakage current relationship is applied to PMOS, it is as follows: Mathematical Expression 3.

[0010]

[0011] At this time, class It can be seen that the larger the value, the more sensitive the output voltage is to temperature.

[0012] [Prior Art Literature]

[0013] [Patent Document]

[0014] Korean Patent Publication No. 10-1046455 (“Amplifier circuit and voltage compensation method thereof”, published on July 4, 2011)

[0015]

[0016] The present invention has been devised to solve the above-mentioned problems, and the purpose of a temperature sensor including a stack structure according to the present invention is to provide a more stable temperature sensor including an improved stack structure.

[0017]

[0018] A temperature sensor including a stack structure according to various embodiments of the present invention for solving the above-described problems comprises a first MOS transistor having one end connected to a power source and a second MOS transistor having one end connected to the other end of the first MOS transistor and the other end connected to ground, wherein the first and second MOS transistors are N-MOS transistors or P-MOS transistors and are of the same type, and when the first MOS transistor and the second MOS transistor are N-MOS transistors, the gate of the first MOS transistor is connected to the source, and when the first MOS transistor and the second MOS transistor are P-MOS transistors, the gate of the second MOS transistor is connected to the source.

[0019] In addition, it is characterized by further including a temperature detection unit that provides temperature information based on the voltage of a node connected to the other end of the first MOS transistor and one end of the second MOS transistor.

[0020] Additionally, the channel width of the first MOS transistor is characterized by being larger than the channel width of the second MOS transistor.

[0021] In addition, it is characterized in that it includes a first MOS transistor connected to a power source and second to n-th MOS transistors connected between the other terminal of the first MOS transistor and the ground and connected in series to each other, wherein the first and second MOS transistors are N-MOS transistors or P-MOS transistors and are of the same type, and when the first and second to n-th MOS transistors are N-MOS transistors, the gates of the first to n-1-th MOS transistors are respectively connected to the sources, and when the first and second to n-th MOS transistors are P-MOS transistors, the gates of the second to n-th MOS transistors are respectively connected to the sources (n is a natural number greater than or equal to 3).

[0022] In addition, when the first and second to nth MOS transistors are N-MOS transistors, the temperature detection unit is further characterized by providing temperature information based on the voltage of the node to which the other end of the n-1th MOS transistor and one end of the nth MOS transistor are connected, and when the first and second to nth MOS transistors are P-MOS transistors, the temperature detection unit is characterized by further including the voltage of the node to which the other end of the first MOS transistor and one end of the second MOS transistor are connected.

[0023] In addition, the temperature detection unit is characterized by including an amplifier that amplifies a voltage output from the node to which a plurality of transistors are connected, an ADC that converts the voltage output from the amplifier into a digital signal and outputs it, and a digital correction circuit that linearizes and outputs the digital signal.

[0024] In addition, the temperature detection unit is characterized in that it provides temperature information based on the digital signal.

[0025] In addition, the present invention includes a temperature detection unit that provides temperature information based on a voltage difference between a voltage of a node to which the other terminal of the first MOS transistor and the one terminal of the second MOS transistor are connected and a power supply, a second MOS transistor to which the other terminal of the first MOS transistor is connected and a ground, a third MOS transistor to which the one terminal of the third MOS transistor is connected and a fourth MOS transistor to which the other terminal of the third MOS transistor is connected and a voltage of a node to which the other terminal of the third MOS transistor and the one terminal of the fourth MOS transistor are connected, wherein the first and second MOS transistors are N-MOS transistors, the third and fourth MOS transistors are P-MOS transistors, and the gate of the first MOS transistor and the fourth MOS transistor are each connected to a source.

[0026] In addition, the channel width of the first MOS transistor is larger than the channel width of the second MOS transistor, and the channel width of the third MOS transistor is larger than the channel width of the fourth MOS transistor.

[0027] In addition, the temperature detection unit is characterized by including a differential amplifier that amplifies and outputs the difference between the voltage of a node connected to the other end of the first MOS transistor and one end of the second MOS transistor and the voltage of a node connected to the other end of the third MOS transistor and one end of the fourth MOS transistor, an ADC that converts the voltage output from the amplifier into a digital signal and outputs it, and a digital correction circuit that linearizes and outputs the digital signal.

[0028] In addition, the present invention includes a temperature detection unit that provides temperature information based on a voltage difference between a voltage of a node to which the other terminal of the first P-MOS transistor and the one terminal of the n-th N-MOS transistor are connected and connected between the other terminal of the first P-MOS transistor and the ground and the second to n-th N-MOS transistors are connected in series with each other, a first P-MOS transistor having one terminal connected to the power supply and the other terminal of the first P-MOS transistor and the one terminal of the n-th N-MOS transistor, and a voltage of a node to which the other terminal of the first P-MOS transistor and the one terminal of the second P-MOS transistor are connected, wherein the gates of the first to n-1-th N-MOS transistors and the second to n-th P-MOS transistors are each connected to a source.

[0029] In addition, the temperature detection unit is characterized by including a differential amplifier that amplifies and outputs the difference between the voltage of a node connected to the other end of the n-1th N-MOS transistor and one end of the nth N-MOS transistor and the voltage of a node connected to the other end of the first P-MOS transistor and one end of the second P-MOS transistor, an ADC that converts the voltage output from the differential amplifier into a digital signal and outputs it, and a digital correction circuit that linearizes and outputs the digital signal.

[0030] In addition, the temperature detection unit is characterized in that it provides temperature information based on the digital signal.

[0031]

[0032] According to a temperature sensor including a stack structure according to various embodiments of the present invention as described above, there is an effect of alleviating the design complexity of a temperature sensor readout circuit through a wide swing.

[0033] Additionally, it has the effect of complementing and strengthening the PUF system through the operation of a cryogentic side-attack prevention circuit.

[0034] In addition, it has the effect of compensating for the temperature adaptive performance of temperature-sensitive electronic circuit systems.

[0035]

[0036] Figures 1 and 2 are circuit diagrams of a temperature sensor utilizing a conventionally turned-off transistor.

[0037] FIG. 3 is a circuit diagram of a temperature sensor utilizing a turned-off NMOS transistor of a two-stage stack structure according to an embodiment of the present invention.

[0038] FIG. 4 is a circuit diagram of a temperature sensor utilizing a turned-off PMOS transistor of a two-stage stack structure according to an embodiment of the present invention.

[0039] FIG. 5 is a circuit diagram of a temperature sensor utilizing a turned-off NMOS transistor of a three-stage stack structure according to an embodiment of the present invention.

[0040] FIG. 6 is a circuit diagram of a temperature sensor utilizing a turned-off PMOS transistor of a three-stage stack structure according to an embodiment of the present invention.

[0041] Figure 7 is a circuit diagram of a temperature sensor utilizing a turned-off NMOS transistor of an n-stage stack structure according to an embodiment of the present invention.

[0042] Figure 8 is a circuit diagram of a temperature sensor utilizing a turned-off PMOS transistor of an n-stage stack structure according to an embodiment of the present invention.

[0043] FIG. 9 is a circuit diagram of a temperature sensor utilizing a turned-off CMOS transistor of a two-stage stack structure according to an embodiment of the present invention.

[0044] FIG. 10 is a circuit diagram of a temperature sensor utilizing a turned-off CMOS transistor of a three-stage stack structure according to an embodiment of the present invention.

[0045]

[0046] In order to explain the present invention, its operational advantages, and the purpose achieved by the practice of the present invention, preferred embodiments of the present invention are exemplified and examined with reference thereto below.

[0047] First, the terms used in this application are only used to describe specific embodiments and are not intended to limit the present invention, and the singular expression may include plural expressions unless the context clearly indicates otherwise. In addition, it should be understood that the terms "comprise" or "have" in this application are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, and do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0048] In describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description will be omitted.

[0049] Before describing a temperature sensor including a stack structure according to an embodiment of the present invention, the parameters indicated below are referred to in Table 1 below.

[0050]

[0051] FIG. 3 is a circuit diagram of a temperature sensor utilizing a turned-off NMOS transistor (101, 102) of a two-stage stack structure according to an embodiment of the present invention.

[0052] A temperature sensor having a two-stage stack structure according to an embodiment of the present invention may include a first MOS transistor (M1) and a second MOS transistor (M2). According to an embodiment of the present invention, the first MOS transistor (M1) and the second MOS transistor (M2) are configured as either an N-MOS transistor or a P-MOS transistor, and are configured as the same type. First, referring to FIG. 3, a case where the first MOS transistor (M1) and the second MOS transistor (M2) are N-MOS transistors (101, 102) will be described.

[0053] The N-MOS transistor (hereinafter, the first N-MOS transistor) (101) corresponding to the first MOS transistor (M1) is first connected to a power supply (V DD ) can be connected. One end of the first N-MOS transistor (101) may be the drain end of the first N-MOS transistor (101).

[0054] An N-MOS transistor (hereinafter, referred to as a second N-MOS transistor) (102) corresponding to the second MOS transistor (M2) may have one end connected to the other end of the first N-MOS transistor (101). One end of the second N-MOS transistor (102) may be a drain end of the second N-MOS transistor (102), and the other end of the first N-MOS transistor (101) may be a source end of the first N-MOS transistor (101).

[0055] The other terminal of the second N-MOS transistor (102) is connected to ground, and the other terminal of the second N-MOS transistor (102) may be a source terminal.

[0056] Here, unlike in the prior art, the gate of the first N-MOS transistor (101) and the second N-MOS transistor (102) are not connected to the ground in common with the second N-MOS transistor (102), but rather, it is preferable that the gate of the first N-MOS transistor (101) is connected to the source, and the gate of the second N-MOS transistor (102) is connected to the ground.

[0057] The first N-MOS transistor (101) and the second N-MOS transistor (102) having this stack structure have a transistor channel width (transistor width, W eff ) can be set differently. Specifically, the channel width (transistor width, W) of the first N-MOS transistor (101) eff ) can be set to be larger than the channel width of the second N-MOS transistor (102).

[0058] As described above, the output voltage of the temperature sensor according to the structure of Fig. 3 ( ) can be defined as in the following mathematical expression 4.

[0059]

[0060]

[0061]

[0062] Looking at mathematical expression 6, the aspect ratio ( ) while maintaining the DIBL (Drain Induced Barrier Lowering) phenomenon is alleviated by designing the first N-MOS transistor (101) to be long. can be established. Therefore, the temperature-voltage gain (Mathematical Formula 5) can be further improved.

[0063] Here, the DIBL phenomenon refers to a phenomenon in which the leakage current due to the drain voltage increases as the channel length shortens.

[0064] Meanwhile, the supply noise transfer function in the frequency domain based on the circuit of Fig. 3 can be derived as shown in the following mathematical expression 7.

[0065]

[0066] Therefore, the poles and zeros of the supply noise transfer function can be expressed as in the following mathematical expression 8.

[0067]

[0068] Accordingly, the structure according to the embodiment of the present invention can have a larger load capacity than the conventional structure, thereby reducing noise power.

[0069] In addition, the temperature sensor according to the present invention may further include a temperature detection unit (110). The temperature detection unit (110) detects the voltage (V) of the node to which the other end of the first N-MOS transistor (101) and one end of the second N-MOS transistor (102) are connected. OUT1 ) can provide temperature information.

[0070] In addition, the temperature detection unit (110) detects the voltage (V) output from the node where the other end of the first N-MOS transistor (101) and one end of the second N-MOS transistor (102) are connected. OUT1 ) may include an amplifier (111) that amplifies the voltage output from the amplifier (111), an ADC (112) that converts the voltage output from the amplifier (111) into a digital signal and outputs it, and a digital correction circuit (113) that linearizes the digital signal and outputs it. The temperature detection unit (110) may provide temperature information based on the digital signal output from the digital correction circuit (113).

[0071]

[0072] FIG. 4 is a circuit diagram of a temperature sensor utilizing a turned-off PMOS transistor (103, 104) of a two-stage stack structure according to an embodiment of the present invention.

[0073] According to an embodiment of the present invention, the first MOS transistor (M1) and the second MOS transistor (M2) are configured as either an N-MOS transistor or a P-MOS transistor, and are configured as the same type. In Fig. 4, a case where the first MOS transistor (M1) and the second MOS transistor (M2) are P-MOS transistors (201, 202) is described.

[0074] The P-MOS transistor (hereinafter, the first P-MOS transistor) (201) corresponding to the first MOS transistor (M1) is first connected to a power supply (V DD ) can be connected. One end of the first P-MOS transistor (201) may be the source end of the first P-MOS transistor (201).

[0075] A P-MOS transistor (hereinafter, referred to as a second P-MOS transistor) (202) corresponding to the second MOS transistor (M2) may have one end connected to the other end of the first P-MOS transistor (201). One end of the second P-MOS transistor (202) may be the source end of the second P-MOS transistor (202), and the other end of the first P-MOS transistor (201) may be the drain end of the first P-MOS transistor (201).

[0076] The other terminal of the second P-MOS transistor (202) is connected to ground, and the other terminal of the second P-MOS transistor (202) may be a drain terminal.

[0077] Here, unlike in the prior art, the gate of the first P-MOS transistor (201) and the second P-MOS transistor (202) are not connected to a power source in common with the second P-MOS transistor (202), but rather, it is preferable that the gate of the first P-MOS transistor (201) is connected to a power source, and the gate of the second P-MOS transistor (202) is connected to a source.

[0078] In addition, the temperature sensor according to the present invention may further include a temperature detection unit (110). The temperature detection unit (110) detects the voltage (V) of a node to which the other end of the first P-MOS transistor (201) and one end of the second P-MOS transistor (202) are connected. OUT2 ) can provide temperature information.

[0079] In addition, the temperature detection unit (110) detects the voltage (V) output from the node where the other end of the first P-MOS transistor (201) and one end of the second P-MOS transistor (202) are connected. OUT2 ) may include an amplifier (111) that amplifies the voltage output from the amplifier (111), an ADC (112) that converts the voltage output from the amplifier (111) into a digital signal and outputs it, and a digital correction circuit (113) that linearizes the digital signal and outputs it. The temperature detection unit (110) may provide temperature information based on the digital signal output from the digital correction circuit (113).

[0080] FIG. 5 is a circuit diagram of a temperature sensor utilizing a turned-off NMOS transistor of a three-stage stack structure according to an embodiment of the present invention.

[0081] A temperature sensor having a three-stage stack structure according to an embodiment of the present invention may include a first MOS transistor (M1) and second to n-th MOS transistors (M2 to Mn). Here, n means a natural number greater than or equal to 3.

[0082] According to an embodiment of the present invention, the first MOS transistor (M1) and the second to nth MOS transistors (M2 to Mn) are configured as either N-MOS transistors or P-MOS transistors, and are configured as the same type. First, referring to FIG. 5, a case where the first MOS transistor (M1) and the second to nth MOS transistors (M2 to Mn) are N-MOS transistors (101, 102, 103) and configured in three stages will be described.

[0083] The N-MOS transistor (hereinafter, the first N-MOS transistor) (101) corresponding to the first MOS transistor (M1) is first connected to a power supply (V DD ) can be connected. One end of the first N-MOS transistor (101) may be the drain end of the first N-MOS transistor (101).

[0084] An N-MOS transistor (hereinafter, referred to as a second N-MOS transistor) (102) corresponding to the second MOS transistor (M2) may have one end connected to the other end of the first N-MOS transistor (101). One end of the second N-MOS transistor (102) may be a drain end of the second N-MOS transistor (102), and the other end of the first N-MOS transistor (101) may be a source end of the first N-MOS transistor (101).

[0085] An N-MOS transistor (hereinafter, referred to as a third N-MOS transistor) (103) corresponding to the third MOS transistor (M3) may have one end connected to the other end of the second N-MOS transistor (102). One end of the third N-MOS transistor (103) may be a drain end of the third N-MOS transistor (103), and the other end of the second N-MOS transistor (102) may be a source end of the second N-MOS transistor (102). In addition, the other end of the third N-MOS transistor (103) may be connected to ground, and the other end of the third N-MOS transistor (103) may be a source end.

[0086] Here, the gates of the first and second N-MOS transistors (101, 102) are preferably connected to the source, respectively, and the gate of the third N-MOS transistor (103) is preferably connected to the ground.

[0087] As illustrated in Fig. 5, the structure including a three-stage stack structure and in which the gate voltage and source voltage of each transistor are connected generates a minute leakage current, and this tendency may become more severe as the process becomes finer.

[0088] Here, the output voltage of the temperature sensor according to the structure of Fig. 5 ( ) can be defined as in the following mathematical expression 9.

[0089]

[0090] In addition, the temperature sensor according to the present invention may further include a temperature detection unit, although not shown in Fig. 5. The temperature detection unit may provide temperature information based on the voltage of a node connected to the other end of the second N-MOS transistor (102) and one end of the third N-MOS transistor (103).

[0091] In addition, the temperature detection unit detects the voltage (V) output from the node where the other end of the second N-MOS transistor (102) and one end of the third N-MOS transistor (103) are connected. OUT1 ) may include an amplifier that amplifies the voltage output from the amplifier, an ADC that converts the voltage output from the amplifier into a digital signal and outputs it, and a digital compensation circuit that linearizes the digital signal and outputs it. The temperature detection unit may provide temperature information based on the digital signal output from the digital compensation circuit.

[0092]

[0093] FIG. 6 is a circuit diagram of a temperature sensor utilizing a turned-off PMOS transistor of a three-stage stack structure according to an embodiment of the present invention.

[0094] A temperature sensor having a three-stage stack structure according to an embodiment of the present invention may include a first MOS transistor (M1) and second to n-th MOS transistors (M2 to Mn). Here, n means a natural number greater than or equal to 3.

[0095]

[0096] *According to an embodiment of the present invention, the first MOS transistor (M1) and the second to nth MOS transistors (M2 to Mn) are configured as either N-MOS transistors or P-MOS transistors, and are configured as the same type. In Fig. 6, a case is described where the first MOS transistor (M1), the second MOS transistor (M2), and the third MOS transistor (M3) are P-MOS transistors (201, 202, 203) and configured in three stages.

[0097] The P-MOS transistor (hereinafter, the first P-MOS transistor) (201) corresponding to the first MOS transistor (M1) is first connected to a power supply (V DD ) can be connected. One end of the first P-MOS transistor (201) may be the source end of the first P-MOS transistor (201).

[0098] A P-MOS transistor (hereinafter, referred to as a second P-MOS transistor) (202) corresponding to the second MOS transistor (M2) may have one end connected to the other end of the first P-MOS transistor (201). One end of the second P-MOS transistor (202) may be a source end of the second N-MOS transistor (102), and the other end of the first P-MOS transistor (201) may be a drain end of the first P-MOS transistor (201).

[0099] A P-MOS transistor (hereinafter, referred to as a third P-MOS transistor) (203) corresponding to the third MOS transistor (M3) may have one end connected to the other end of the second P-MOS transistor (202). One end of the third P-MOS transistor (203) may be a source end of the third P-MOS transistor (203), and the other end of the second P-MOS transistor (202) may be a drain end of the second P-MOS transistor (202). In addition, the other end of the third P-MOS transistor (203) may be connected to ground, and the other end of the third P-MOS transistor (203) may be a drain end.

[0100] Here, the gates of the second to third P-MOS transistors (202, 203) are preferably connected to the source, respectively, and the gate of the first P-MOS transistor (201) is preferably connected to the power supply.

[0101] Meanwhile, if the concepts utilizing the N-MOS transistor described above are applied to the P-MOS as shown in Fig. 6, the results can be as follows.

[0102] As shown in Fig. 6, in a structure including a three-stage stack structure and in which the gate voltage and source voltage of each transistor are connected, when the leakage current relationship equation in the N-MOS transistor structure of Fig. 5 is applied to the P-MOS, it can be seen that the temperature sensor utilizing the turned-off P-MOS transistor of the stack structure moves complementarily in voltage with respect to temperature compared to the structure utilizing the N-MOS transistor.

[0103] In addition, the temperature sensor according to the present invention may further include a temperature detection unit, although not shown in Fig. 6. The temperature detection unit detects the voltage (V) of the node to which the other end of the first P-MOS transistor (201) and one end of the second P-MOS transistor (202) are connected. OUT1 ) can provide temperature information.

[0104] In addition, the temperature detection unit detects the voltage (V) output from the node where the other end of the first P-MOS transistor (201) and one end of the second P-MOS transistor (202) are connected. OUT2 ) may include an amplifier that amplifies the voltage output from the amplifier, an ADC that converts the voltage output from the amplifier into a digital signal and outputs it, and a digital compensation circuit that linearizes the digital signal and outputs it. The temperature detection unit may provide temperature information based on the digital signal output from the digital compensation circuit.

[0105]

[0106] FIG. 7 is a circuit diagram of a temperature sensor utilizing a turned-off NMOS transistor of an n-stage stack structure according to an embodiment of the present invention.

[0107] FIG. 8 is a circuit diagram of a temperature sensor utilizing a turned-off PMOS transistor of an n-stage stack structure according to an embodiment of the present invention.

[0108] The three-stage structure described above in FIGS. 5 and 6 can be applied to n stages, as shown in FIGS. 7 and 8.

[0109] In addition, when the stack structure of the transistor is configured in 2 stages, 3 stages, or even n stages (n is a natural number greater than or equal to 2, n = j+1, j is a natural number greater than or equal to 1), the equation for the output voltage can be defined as in the following mathematical equation 10.

[0110]

[0111] In addition, as the number of stages increases, multiple RC filters are formed from the supply voltage to the output voltage terminal in the case of serially connected transistors, which can exhibit a stronger filtering effect.

[0112]

[0113] FIG. 9 is a circuit diagram of a temperature sensor utilizing a turned-off CMOS transistor of a two-stage stack structure according to an embodiment of the present invention.

[0114] It may include a first MOS transistor (M1) and a second MOS transistor (M2) which are N-MOS transistors, a third MOS transistor (M3) and a fourth MOS transistor (M4) which are P-MOS transistors, and a temperature detection unit (210).

[0115] The structure of the N-MOS transistor (101, 102) is the same as that described with reference to FIG. 3, and the structure of the P-MOS transistor (201, 202) is the same as that described with reference to FIG. 4.

[0116] The temperature detection unit (210) detects the voltage of the node where the other end of the first MOS transistor (M1) and one end of the second MOS transistor (M2) are connected (hereinafter referred to as the first output voltage (V OUT1 )) and the voltage of the node connected to the other end of the third MOS transistor (M3) and one end of the fourth MOS transistor (M4) (hereinafter referred to as the second output voltage (V OUT2 )) can provide temperature information based on the voltage difference between the first output voltage (V OUT1 ) is linearly proportional to the temperature (T) and the second output voltage (V OUT2 ) are complementary to each other because they are linearly inversely proportional to the temperature (T). Therefore, the temperature detection unit (210) outputs the first output voltage (V OUT1 ) and the second output voltage (V OUT2 ) can be used to expand the range of output voltage according to temperature (T).

[0117] Additionally, the temperature detection unit (210) may include a differential amplifier (211), an ADC (212), and a digital compensation circuit (213). The differential amplifier (211) may output a first output voltage (V OUT1 ) and the second output voltage (V OUT2) can calculate the difference between them and amplify and output the difference. The ADC (212) can convert the voltage output from the differential amplifier (211) into a digital signal and output it. The digital compensation circuit (213) can linearize and output the digital signal output from the ADC (212). The temperature detection unit (210) can provide temperature information based on the digital signal output from the digital compensation circuit (213).

[0118]

[0119] Fig. 10 is a circuit diagram of a temperature sensor utilizing a turned-off CMOS transistor of a three-stage stack structure according to an embodiment of the present invention.

[0120] It may include a first N-MOS transistor (MN1), a second N-MOS transistor (MN2), and a third N-MOS transistor (MN3) which are N-MOS transistors, a first P-MOS transistor (MP1), a second P-MOS transistor (MP2), and a second P-MOS transistor (MP3) which are P-MOS transistors, and a temperature detection unit (210).

[0121] The structure of the N-MOS transistors (101, 102, 103) is the same as that described with reference to FIG. 5, and the structure of the P-MOS transistors (201, 202, 203) is the same as that described with reference to FIG. 6.

[0122] The temperature detection unit (210) detects the voltage of the node (hereinafter referred to as the first output voltage (V)) connected to the other end of the second N-MOS transistor (MN2) and one end of the third N-MOS transistor (MN3). OUT1 )) and the voltage of the node connected to the other end of the first P-MOS transistor (MP1) and one end of the second P-MOS transistor (MP2) (hereinafter referred to as the second output voltage (V OUT2 )) can provide temperature information based on the voltage difference between the first output voltage (V OUT1 ) is linearly proportional to the temperature (T) and the second output voltage (V OUT2) are complementary to each other because they are inversely linearly proportional to the temperature (T). Therefore, the temperature detection unit () outputs the first output voltage (V OUT1 ) and the second output voltage (V OUT2 ) can be used to expand the range of output voltage according to temperature (T).

[0123] Additionally, the temperature detection unit (210) may include a differential amplifier (211), an ADC (212), and a digital compensation circuit (213). The differential amplifier (211) may output a first output voltage (V OUT1 ) and the second output voltage (V OUT2 ) can calculate the difference between them and amplify and output the difference. The ADC (212) can convert the voltage output from the differential amplifier (211) into a digital signal and output it. The digital compensation circuit (213) can linearize and output the digital signal output from the ADC (212). The temperature detection unit (210) can provide temperature information based on the digital signal output from the digital compensation circuit (213).

[0124] In addition, although a temperature sensor utilizing a turned-off CMOS transistor of a three-stage stack structure is described in FIG. 10, it is not limited thereto, and a temperature sensor utilizing a CMOS transistor including an n-stage stack structure including the structures of FIGS. 7 and 8 may also be included.

[0125]

[0126] While preferred embodiments of the present invention have been described above, the present invention is not limited to the specific embodiments described above. That is, those skilled in the art to which the present invention pertains may make numerous changes and modifications to the present invention without departing from the spirit and scope of the appended claims, and all such appropriate changes and modifications should be considered equivalents and fall within the scope of the present invention.

[0127]

[0128] [Explanation of symbols]

[0129] 101 ~ 10n: nth N-MOS transistor

[0130] 201 ~ 20n: nth P-MOS transistor

[0131] 110, 210: Temperature detection unit

[0132] 111: Amplifier

[0133] 112, 212: ADC

[0134] 113, 213: Digital compensation circuit

[0135] 211: Differential Amplifier

Claims

1. First MOS transistor connected to the power supply; and A second MOS transistor having one end connected to the other end of the first MOS transistor and the other end connected to ground; The above first and second MOS transistors are N-MOS transistors or P-MOS transistors and are of the same type, When the first MOS transistor and the second MOS transistor are N-MOS transistors, the gate of the first MOS transistor is connected to the source, If the first MOS transistor and the second MOS transistor are P-MOS transistors, the gate of the second MOS transistor is connected to the source. A temperature sensor comprising a stack structure characterized by:

2. In paragraph 1, Further comprising a temperature detection unit that provides temperature information based on the voltage of a node connected to the other end of the first MOS transistor and one end of the second MOS transistor; A temperature sensor comprising a stack structure characterized by:

3. In paragraph 1, The channel width of the first MOS transistor is greater than the channel width of the second MOS transistor. A temperature sensor comprising a stack structure characterized by:

4. First MOS transistor connected to the power supply; and Second to n-th MOS transistors connected between the other terminal of the first MOS transistor and the ground and connected in series with each other; The above first and second MOS transistors are N-MOS transistors or P-MOS transistors and are of the same type, When the first and second to n-th MOS transistors are N-MOS transistors, the gates of the first to n-1-th MOS transistors are each connected to the source, When the first and second to nth MOS transistors are P-MOS transistors, the gates of the second to nth MOS transistors are each connected to the source (n is a natural number greater than or equal to 3). A temperature sensor comprising a stack structure characterized by:

5. In paragraph 4, When the first and second to nth MOS transistors are N-MOS transistors, temperature information is provided based on the voltage of the node connected to the other end of the n-1th MOS transistor and one end of the nth MOS transistor, In case the first and second to nth MOS transistors are P-MOS transistors, a temperature detection unit that provides temperature information based on the voltage of a node connected to the other end of the first MOS transistor and one end of the second MOS transistor is further included. A temperature sensor comprising a stack structure characterized by:

6. In either paragraph 2 or paragraph 5, The above temperature detection unit, An amplifier that amplifies the voltage output from the node to which a plurality of transistors are connected; An ADC that converts the voltage output from the amplifier into a digital signal and outputs it; and A digital correction circuit that linearizes and outputs the digital signal; A temperature sensor comprising a stack structure characterized by:

7. In paragraph 6, The above temperature detection unit, Providing temperature information based on the above digital signal A temperature sensor comprising a stack structure characterized by:

8. First MOS transistor connected to the power supply; A second MOS transistor having one end connected to the other end of the first MOS transistor and the other end connected to ground; First, a third MOS transistor connected to the power supply; A fourth MOS transistor having one end connected to the other end of the third MOS transistor and the other end connected to the ground; and A temperature detection unit that provides temperature information based on a voltage difference between a voltage of a node connected to the other end of the first MOS transistor and one end of the second MOS transistor and a voltage of a node connected to the other end of the third MOS transistor and one end of the fourth MOS transistor; The above first and second MOS transistors are N-MOS transistors, The above third and fourth MOS transistors are P-MOS transistors, The gate of the first MOS transistor and the fourth MOS transistor are each connected to a source. A temperature sensor comprising a stack structure characterized by:

9. In paragraph 8, The channel width of the first MOS transistor is larger than the channel width of the second MOS transistor, The channel width of the third MOS transistor is greater than the channel width of the fourth MOS transistor. A temperature sensor comprising a stack structure characterized by:

10. In paragraph 8, The above temperature detection unit, A differential amplifier that amplifies and outputs the difference between the voltage of a node connected to the other end of the first MOS transistor and one end of the second MOS transistor and the voltage of a node connected to the other end of the third MOS transistor and one end of the fourth MOS transistor; An ADC that converts the voltage output from the amplifier into a digital signal and outputs it; and A digital correction circuit that linearizes and outputs the digital signal; A temperature sensor comprising a stack structure characterized by:

11. First N-MOS transistor connected to the power supply; Second to nth N-MOS transistors connected between the other terminal of the first N-MOS transistor and the ground and connected in series with each other; First, a first P-MOS transistor connected to the power supply; Second to nth P-MOS transistors connected in series with each other, one terminal being connected between the other terminal of the first P-MOS transistor and the ground; and A temperature detection unit that provides temperature information based on a voltage difference between the other terminal of the n-1 N-MOS transistor and the voltage of a node connected to one terminal of the n-th N-MOS transistor and the voltage of a node connected to the other terminal of the first P-MOS transistor and one terminal of the second P-MOS transistor; The gates of the first to n-1th N-MOS transistors and the second to nth P-MOS transistors are each connected to the source. A temperature sensor comprising a stack structure characterized by:

12. In paragraph 11, The above temperature detection unit, A differential amplifier that amplifies and outputs the difference between the voltage of a node connected to the other end of the n-1th N-MOS transistor and one end of the nth N-MOS transistor and the voltage of a node connected to the other end of the first P-MOS transistor and one end of the second P-MOS transistor; An ADC that converts the voltage output from the differential amplifier into a digital signal and outputs it; and A digital correction circuit that linearizes and outputs the digital signal; A temperature sensor comprising a stack structure characterized by:

13. In either of paragraphs 10 or 12, The above temperature detection unit, Providing temperature information based on the above digital signal A temperature sensor comprising a stack structure characterized by:

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