Equipment and method for post-exposure bake and dry development of extreme ultraviolet photoresists

Abstract

Systems and techniques for enhancing wafer-to-wafer and in-wafer uniformity in the context of extreme ultraviolet (EUV) lithography are disclosed. By performing post-exposure bake operations and dry-development operations on an EUV-exposed wafer without breaking vacuum, wafer-to-wafer uniformity and in-wafer uniformity are improved. Performing a cooling and treatment operation in between the post-exposure bake and the dry-development process and in which the wafer is exposed to a controlled pseudo-atmospheric environment may recover dose-to-size that may be lost by performing the post-exposure bake operations and dry-development operations on the EUV-exposed wafer without breaking vacuum.

Description

EQUIPMENT AND METHOD FOR POST-EXPOSURE BAKE AND DRY DEVELOPMENT OF EXTREME ULTRAVIOLET PHOTORESISTSRELATED APPLICATION(S)

[0000] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in its entirety and for all purposes.BACKGROUND

[0001] The fabrication of semiconductor devices, such as integrated circuits, is a multi-step process involving photolithography. In general, the process includes the deposition of material on a wafer and patterning the material through lithographic techniques to form structural features (e.g., transistors and circuitry) of the semiconductor device. The steps of a typical photolithography process known in the art include: preparing the substrate; applying a photoresist, such as by spin coating; exposing the photoresist to light in a desired pattern, causing the exposed areas of the photoresist to become more or less soluble in a developer solution; developing by applying the developer solution to remove either the exposed or the unexposed areas of the photoresist; and subsequent processing to create features on the areas of the substrate from which the photoresist has been removed, such as by etching or material deposition.

[0002] The evolution of semiconductor design has created the need, and has been driven by the ability, to create ever smaller features on semiconductor substrate materials. This progression of technology has been characterized in "Moore's Law" as a doubling of the density of transistors in dense integrated circuits every two years. Indeed, chip design and manufacturing has progressed such that modern microprocessors may contain billions of transistors and other circuit features on a single chip. Individual features on such chips may be on the order of 22 nanometers (nm) or smaller, in some cases less than lOnm.

[0003] One challenge in manufacturing devices having such small features is the ability to reliably and reproducibly create photolithographic masks having sufficient resolution. Current photolithography processes typically use 193nm ultraviolet (UV) light to expose a photoresist.The fact that the light has a wavelength significantly greater than the desired size of the features to be produced on the semiconductor substrate creates inherent issues. Achieving feature sizes smaller than the wavelength of the light requires use of complex resolution enhancement techniques, such as multi-patterning. Thus, there is significant interest and research effort in developing photolithographic techniques using shorter wavelength light, such as extreme ultraviolet radiation (EUV), having a wavelength of from lOnm to 15nm, e.g., 13.5nm.

[0004] EUV photolithographic processes can present challenges, however, including low power output and loss of light during patterning. Organic chemically amplified resists (CAR) similar to those used in 193nm UV lithography have potential drawbacks when used in EUV lithography, particularly as they have low absorption coefficients in the EUV spectrum and the diffusion of photo-activated chemical species can result in pattern blur or line edge roughness. Furthermore, in order to provide the etch resistance required to pattern underlying device layers, increased thicknesses of CARs may need to be used, making small features patterned in conventional CAR materials have high aspect ratios that are at risk of pattern collapse. Accordingly, there remains a need for improved EUV photoresist materials having such properties as decreased thickness, greater EUV absorbance, and greater etch resistance.

[0005] The background description provided herein is for the purpose of generally presenting the context of the present technology. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present technology.SUMMARY

[0006] Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings, and the claims.

[0007] In some implementations, an apparatus is provided that may include a temperature- controllable wafer support. The wafer support may have a body having a first side and a second side facing in an opposite direction from the first side, a first plenum located within the body and extending radially outward from one or more inlet ports located near a centerline ofthe body, bounded on one side by a first surface, and bounded on another side by a second surface that faces towards the first surface. The wafer support may also have a second plenum located within the body and extending radially outward from one or more outlet ports located near the centerline of the body. The second plenum may be bounded on one side by a third surface and bounded on another side by a fourth surface that faces towards the third surface. The wafer support may further include a plurality of inter-plenum passages distributed along an outer perimeter of the first plenum, each inter-plenum passage located within the body and spanning between the first plenum and the second plenum. The wafer support may also include an inlet fluidical ly connected with the one or more inlet ports via one or more inlet passages located at least partially within the body and an outlet fluid ica lly connected with the one or more outlet ports via one or more outlet passages located at least partially within the body. The first plenum, the plurality of inter-plenum passages, and the second plenum may all be f luidica I ly interposed between the inlet and the outlet.

[0008] In some implementations, the apparatus may include a temperature-controllable wafer support that may have a body having a first side and a second side facing in an opposite direction from the first side. The body may have a plurality of layer parts that are positioned in a stacked arrangement, each layer part joined to the adjacent layer part or the adjacent layer parts via a corresponding diffusion bond or corresponding diffusion bonds. The plurality of layer parts may include at least a first layer part, a second layer part, and a third layer part. The temperature-controlled wafer support may also have a first plenum located within the body, extending radially outward from one or more inlet ports located near a centerline of the body, bounded on one side by a first surface, and bounded on another side by a second surface that faces towards the first surface. The first surface may be provided by the first layer part and the second surface may be provided by the second layer part. The temperature-controlled wafer support may also have a second plenum located within the body, extending radially outward from one or more outlet ports located near the centerline of the body, bounded on one side by a third surface and bounded on another side by a fourth surface that faces towards the third surface. The third surface may be provided by the second layer part and the fourth surface may be provided by the third layer part. The temperature-controlled wafer support may also have a plurality of inter-plenum passages distributed along an outer perimeter of the first plenum, each inter-plenum passage located within the body and spanning between the first plenum and the second plenum. The temperature-controlled wafer support may also have an inlet f luidica I ly connected with the one or more inlet ports via one or more inlet passages located atleast partially within the body and an outlet fluidically connected with the one or more outlet ports via one or more outlet passages located at least partially within the body. The one or more inlet passages may be at least partially defined by one or more surfaces of the second layer part and one or more surfaces of the third layer part, the first plenum, the plurality of inter-plenum passages, and the second plenum may all be fluidically interposed between the inlet and the outlet, and the one or more outlet passages may be at least partially defined by one or more surfaces of the second layer part and one or more surfaces of the third layer part.

[0009] In some implementations, the one or more outlet ports may include a plurality of outlet ports. In some further such implementations, the one or more inlet passages may include a first inlet passage having a first portion that extends along the centerline of the body, and the one or more outlet passages may include a first outlet passage having a first portion that extends at least partially around the first portion of the first inlet passage.

[0010] In some additional implementations, the apparatus may further include a radial support structure connected with the body. The radial support structure may extend outward from the body relative to the centerline of the body. The inlet and the outlet may both be located in the radial support structure, a second portion of the first inlet passage may extend from the body into the radial support structure, and a second portion of the first outlet passage may extend from the body into the radial support structure.

[0011] In some implementations, the body may include a center portion that contains the first portion of the first inlet passage and the first portion of the first outlet passage. The body may further include a first radial portion that extends from the center portion to an outermost surface of the second plenum. The first radial portion may span between the third surface and the fourth surface and may prevent the second plenum from extending a full 360° about the centerline, and the second portions of the first inlet passage and the first outlet passage may extend from the center portion and through the first radial portion before reaching the radial support structure.

[0012] In some implementations, the body may further include a second radial portion that extends from an outermost surface of the first plenum radially inward towards the centerline of the body, a temperature sensor bore may extend from the radial support structure and into the second radial portion, and a temperature sensor may be positioned within the temperature sensor bore.

[0013] In some implementations of the apparatus the one or more inlet passages may also be at least partially defined by one or more surfaces of the first layer part and one or more surfaces of the second layer part, and the one or more outlet passages may also be at least partially defined by one or more surfaces of the first layer part and one or more surfaces of the second layer part.

[0014] In some such implementations, the second layer part may include a first through-hole that defines part of the one or more inlet passages and a second through-hole that defines part of the one or more outlet passages.

[0015] In some further such implementations, the first through-hole and the second through- hole may extend along corresponding centerlines that form respective acute angles with respect to the first surface.

[0016] In some implementations, the inlet and the outlet may be located at positions offset from, and in a direction perpendicular to, a reference plane that is parallel to the first side and that intersects either the first plenum or the second plenum.

[0017] In some implementations, the apparatus may further include a ring of baffle wall segments and a ring of inlet baffle ports encircling the one or more inlet ports, each baffle wall segment extending from the first surface to the second surface and each inlet baffle port interposed between at least portions of two adjacent ones of the baffle wall segments.

[0018] In some implementations, the first portion of the first outlet passage may encircle the first portion of the first inlet passage

[0019] In some implementations, the wafer support may further include an axial support structure connected with the body and extending downward from the body along the centerline of the body. The inlet and the outlet may both be located in the axial support structure, a second portion of the first inlet passage may extend from the body into the axial support structure, and a second portion of the first outlet passage may extend from the body into the axial support structure.

[0020] In some implementations, the body may include a center portion that contains the first portion of the first inlet passage and the first portion of the first outlet passage, and the second portions of the first inlet passage and the first outlet passage may extend from the center portion and through the axial support structure.

[0021] In some implementations, the body may further include a temperature sensor bore that extends from the axial support structure, through the second plenum, and into the first plenum. The temperature sensor bore may be fluidical ly isolated from the first plenum and the second plenum within the body, and a temperature sensor may be positioned within the temperature sensor bore.

[0022] In some implementations, the first side of the body may be planar, and at least one of the first surface and the second surface may be axially symmetric and non-parallel with the first side.

[0023] In some implementations, the first plenum may have a plenum thickness closest to the centerline of the body that is greater than the plenum thickness of the first plenum closest to the inter-plenum passages.

[0024] In some implementations, the first surface may be interposed between the first side and the second surface, and the first surface may define a conical frustum. In some such implementations, the conical frustum may define a cone angle of 175° to 179°.

[0025] In some implementations, the body may further include a plurality of first flowpartitioning structures distributed throughout the first plenum. In some such implementations, each first flow-partitioning structure may span between the first surface and the second surface. In some further such implementations, the first flow-partitioning structures may have obround cross-sections in a plane perpendicular to the centerline of the body.

[0026] In some implementations, the first flow-partitioning structures may include multiple first sets of first flow-partitioning structures, the first flow-partitioning structures in each first set of first flow-partitioning structures may each have a respective long axis that is colinear with the long axes of the other first flow-partitioning structures in that first set of first flowpartitioning structures, and the first sets of first flow-partitioning structures may be arranged in a circular array about the centerline of the body.

[0027] In some such implementations, lengths of the first flow-partitioning structures in each first set of first flow-partitioning structures along the respective long axes of those first flowpartitioning structures may not increase with increasing distance from the centerline of the body, and the lengths of the first flow-partitioning structures in the first sets of first flowpartitioning structures that are closest to the centerline may be longer than the lengths of thefirst flow-partitioning structures in the first sets of first flow-partitioning structures that are furthest from the centerline.

[0028] In some implementations, the first flow-partitioning structures may include multiple second sets of first flow-partitioning structures, the first flow-partitioning structures in each second set of first flow-partitioning structures may each have a respective long axis that is colinear with the long axes of the other first flow-partitioning structures in that second set of first flow-partitioning structures, the second sets of first flow-partitioning structures may be arranged in a circular array about the centerline of the body, the first sets and second sets of first flow-partitioning structures may be arranged in alternating fashion about the centerline of the body, and the first flow-partitioning structures in the first set of first flow-partitioning structures that are closest to the centerline may be closer to the centerline than the first flowpartitioning structures in the second set of first flow-partitioning structures that are closest to the centerline.

[0029] In some implementations, the first flow-partitioning structures may be distributed throughout the first plenum with each first flow-partitioning structure being within a first distance of any directly neighboring first flow-partitioning structures. In some such implementations, the first distance may be 10mm.

[0030] In some implementations, the first flow-partitioning structures may each have a long axis that is at an oblique angle relative to a radial line drawn from, and perpendicular to, the centerline of the body to the center of the respective first flow-partitioning structure.

[0031] In some implementations, the oblique angle may increase with increasing distance from the centerline of the body.

[0032] In some implementations, the body may further include a plurality of second flowpartitioning structures distributed throughout the first plenum. In some such implementations, each second flow-partitioning structure may span between the third surface and the fourth surface. In some further implementations, the second flow-partitioning structures may have obround cross-sections in a plane perpendicular to the centerline of the body.

[0033] In some implementations, the second flow-partitioning structures may include multiple first sets of second flow-partitioning structures, the second flow-partitioning structures in each first set of second flow-partitioning structures may each have a respective long axis that is colinear with the long axes of the other second flow-partitioning structures inthat first set of second flow-partitioning structures, and the first sets of second flowpartitioning structures may be arranged in a circular array about the centerline of the body.

[0034] In some implementations, lengths of the second flow-partitioning structures in each first set of second flow-partitioning structures along the respective long axes of those second flow-partitioning structures may not increase with increasing distance from the centerline of the body, and the lengths of the second flow-partitioning structures in the first sets of second flow-partitioning structures that are closest to the centerline may be longer than the lengths of the second flow-partitioning structures in the first sets of second flow-partitioning structures that are furthest from the centerline.

[0035] In some implementations, the second flow-partitioning structures may include multiple second sets of second flow-partitioning structures, the second flow-partitioning structures in each second set of second flow-partitioning structures may each have a respective long axis that is colinear with the long axes of the other second flow-partitioning structures in that second set of second flow-partitioning structures, the second sets of second flowpartitioning structures may be arranged in a circular array about the centerline of the body, the first sets and second sets of second flow-partitioning structures may be arranged in alternating fashion about the centerline of the body, and the second flow-partitioning structures in the first set of second flow-partitioning structures that are closest to the centerline may be closer to the centerline than the second flow-partitioning structures in the second set of second flowpartitioning structures that are closest to the centerline.

[0036] In some implementations, the first plenum may be positioned in between the second plenum and the first side, the second plenum may be positioned in between the first plenum and the second side, the body may have a plurality of through-holes extending from the first side to the second side, and each through-hole may be fluidically isolated from the first plenum and the second plenum within the body.

[0037] In some implementations, the first side may have a plurality of raised regions distributed thereacross.

[0038] In some implementations, the body may have a solid volume that is less than 6 times a combined volume of the first plenum, the inter-plenum passages, and the second plenum. In some such implementations, the solid volume of the body may be less than 5 times the combined volume of the first plenum, the inter-plenum passages, and the second plenum and,in some further such implementations, the solid volume of the body may be less than 4.5 times the combined volume of the first plenum, the inter-plenum passages, and the second plenum.

[0039] In some implementations, the apparatus may further include a plurality of reservoirs, each reservoir associated with a corresponding temperature control system configured to maintain a heat transfer fluid, when present in that reservoir, within a corresponding temperature range. The plurality of reservoirs may include at least a first reservoir associated with a first temperature control system configured to maintain the heat transfer fluid, when present in the first reservoir, within a first temperature range and a second reservoir associated with a second temperature control system configured to maintain the heat transfer fluid, when present in the second reservoir, within a second temperature range. The apparatus may also include one or more coolant control valves, one or more fluid transfer lines, and one or more pumps, wherein the one or more coolant control valves and the one or more pumps are configured to be controllable so as to cause the heat transfer fluid contained within each reservoir, when present in that reservoir, to selectively flow into the heat transfer fluid inlet of the wafer support. The apparatus may also include a controller configured to control the first temperature control system and the second temperature control system such that the first temperature range is higher than the second temperature range, and control the one or more coolant control valves and the one or more pumps to cause the heat transfer fluid, when present in the first reservoir and the second reservoir, to flow from the first reservoir to the heat transfer inlet during a first time period and to flow from the second reservoir to the heat transfer inlet during a second time period.

[0040] In some implementations, the apparatus may further include a cooling-and-treatment chamber. The body of the temperature-controllable wafer support may be positioned within the cooling-and-treatment chamber. The apparatus may also include a showerhead having a plurality of gas distribution ports located above the temperature-controllable wafer support.

[0041] In some implementations, the apparatus may further include a transfer chamber housing a wafer-handling robot, a dry-development chamber connected with the transfer chamber and accessible to the wafer-handling robot, and a post-exposure bake chamber connected with the transfer chamber and accessible to the wafer-handling robot, wherein the cooling-and-treatment chamber is also connected with the transfer chamber and accessible to the wafer-handling robot.

[0042] In some implementations, the apparatus may further include a source of non-reactive carrier gas, a source of oxygen gas, a source of water vapor, and one or more showerhead control valves. The one or more showerhead control valves may be configured to selectively flow the non-reactive carrier gas, the oxygen gas, and the water vapor through the showerhead and towards the temperature-controllable wafer support via the gas distribution ports responsive to receipt of one or more control signals.

[0043] In some implementations, the apparatus may further include a load-lock connected to the transfer chamber and accessible to the wafer-handling robot. The cooling-and-treatment chamber may be positioned above the load-lock.

[0044] In some implementations, a semiconductor processing system is provided that may include one or more transfer chambers housing one or more wafer-handling robots, a drydevelopment chamber connected with the one or more transfer chambers, accessible to at least one of the one or more wafer-handling robots, and configured to facilitate performance of one or more dry-development processes on a substrate having a photopatterned extreme ultraviolet photoresist layer, a post-exposure bake chamber connected with the one or more transfer chambers, accessible to at least one of the one or more wafer-handling robots, and configured to facilitate performance of a post-exposure bake process on the substrate having the photopatterned extreme ultraviolet photoresist layer, and a cooling-and-treatment chamber connected with the one or more transfer chambers, accessible to at least one of the one or more wafer-handling robots, and configured to facilitate performance of a cooling-and- treatment process on the substrate having the photopatterned extreme ultraviolet photoresist layer. The cooling-and-treatment process may include cooling the substrate having the photopatterned extreme ultraviolet photoresist layer to a temperature in a first temperature range, flowing one or more of oxygen gas, carbon dioxide gas, and water vapor-containing gas into contact with the substrate having the photopatterned extreme ultraviolet photoresist layer, and then cooling the substrate having the photopatterned extreme ultraviolet photoresist layer to a temperature in a second temperature range. The first temperature range may be between 50°C to 200°C, and the second temperature range may be 40°C or lower.

[0045] In some implementations, at least one of the one or more dry-development processes may include flowing one or more process gases across the substrate having the photopatterned extreme ultraviolet photoresist layer to remove portions of the photopatterned extreme ultraviolet photoresist layer.

[0046] In some such implementations, the at least one of the dry-development processes may be performed with the substrate having the photopatterned extreme ultraviolet photoresist layer held at a temperature of 40°C or lower.

[0047] In some further such implementations, the at least one of the dry-development processes may be performed with the substrate having the photopatterned extreme ultraviolet photoresist layer held at a temperature of 20°C or lower.

[0048] In some implementations, the post-exposure bake process may include heating the substrate having the photopatterned extreme ultraviolet photoresist layer to a temperature greater than or equal to a third temperature of at least 130°C for a first time period.

[0049] In some such implementations, the third temperature may be at least 200°C.

[0050] In some further such implementations, the third temperature may be at least 250°C.

[0051] In some of the above implementations, the semiconductor processing system may further include a controller configured to control the one or more wafer-handling robots and the cooling-and-treatment chamber and to cause a) one of the one or more wafer-handling robots to place a first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer in the post-exposure bake chamber, b) the post-exposure bake chamber to perform the post-exposure bake process on the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer after (a), c) one of the one or more waferhandling robots to move, after (b), the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer from the post-exposure bake chamber to the cooling-and-treatment chamber, d) the cooling-and-treatment chamber to perform, after (c), a cooling-and-treatment process on the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer, and e) one of the one or more waferhandling robots to move, after (d), the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer from the cooling-and-treatment chamber to the dry-development chamber.

[0052] In some such implementations, the semiconductor processing system may further include a loadlock connected with the one or more transfer chambers and accessible to one of the one or more wafer-handling robots. The loadlock may be configured to facilitate transfer of the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer between the one or more transfer chambers and an atmospheric pressure environment,and the controller may be configured to perform (a) through (e) without placing the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer in the loadlock.

[0053] In some implementations, the semiconductor processing system may further include an oxygen source connected with the cooling-and-treatment chamber, wherein the controller is further configured to cause oxygen from the oxygen source to flow into the cooling-and- treatment chamber during at least part of (d).

[0054] In some such implementations, the semiconductor processing system may further include a vaporizer and a water source, and the controller may be further configured to cause water vapor generated by the vaporizer using water from the water source to flow into the cooling-and-treatment chamber during at least part of (d).

[0055] In some such implementations, the semiconductor processing system may further include a carbon dioxide source, wherein the controller is further configured to cause carbon dioxide from the carbon dioxide source to flow into the cooling-and-treatment chamber during at least part of (d).

[0056] In some such implementations, the cooling-and-treatment chamber may include a temperature-controlled wafer support configured to receive the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer when the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer is moved into the cooling-and-treatment chamber by one of the one or more wafer-handling robots, and the controller may be configured to cause the temperature-controlled wafer support to, while the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer is supported by the temperature-controlled wafer support: i) maintain a temperature in the first temperature range during at least part of (d), and ii) maintain a temperature in the second temperature range during at least part of (d) and after (i).

[0057] In some such implementations, the first temperature range may be between 75°C and 200°C.

[0058] In some such implementations, the first temperature range may be between 95°C and 200°C.

[0059] In some implementations, the second temperature range may be between -10°C and25°C.

[0060] In some such implementations, the second temperature range may be between -10°C and 20°C.

[0061] In some such implementations, the semiconductor processing system may further include a plurality of reservoirs, each reservoir associated with a corresponding temperature control system configured to maintain a heat transfer fluid, when present in that reservoir, within a corresponding temperature range. The plurality of reservoirs may include at least a first reservoir associated with a first temperature control system configured to maintain the heat transfer fluid, when present in the first reservoir, within the first temperature range, and a second reservoir associated with a second temperature control system configured to maintain the heat transfer fluid, when present in the second reservoir, within the second temperature range. The semiconductor processing system may also further include one or more coolant control valves, one or more fluid transfer lines, and one or more pumps. The one or more coolant control valves and the one or more pumps may be configured to be controllable so as to cause the heat transfer fluid contained within each reservoir, when present in that reservoir, to selectively flow into an inlet of the wafer support. The semiconductor processing system may also further include a controller configured to control the one or more coolant control valves and the one or more pumps to cause the heat transfer fluid, when present in the first reservoir and the second reservoir, to flow from the first reservoir to the inlet during at least part of (i) and to flow from the second reservoir to the inlet during at least part of (ii).

[0062] In some implementations, a method may be provided that includes (a) introducing a substrate having a photopatterned extreme ultraviolet photoresist layer into one or more transfer chambers housing one or more wafer-handling robots, (b) causing one of the one or more wafer-handling robots to transfer the substrate having the photopatterned extreme ultraviolet photoresist layer into a post-exposure bake chamber connected with the one or more transfer chambers, (c) causing the substrate having the photopatterned extreme ultraviolet photoresist layer to undergo a post-exposure bake process in the post-exposure bake chamber, (d) causing one of the one or more wafer-handling robots to transfer the substrate having the photopatterned extreme ultraviolet photoresist layer from the postexposure bake chamber to a cooling-and-treatment chamber connected with the one or more transfer chambers, (e) causing the substrate having the photopatterned extreme ultraviolet photoresist layer to undergo a cooling and treatment process in the cooling-and-treatment chamber, (f) causing one of the one or more wafer-handling robots to transfer the substratehaving the photopatterned extreme ultraviolet photoresist layer from the cooling-and- treatment chamber to a dry-development chamber connected with the one or more transfer chambers, and (g) causing the substrate having the photopatterned extreme ultraviolet photoresist layer to undergo one or more dry-development processes in the dry-development chamber. In such a method, the cooling-and-treatment process may include cooling the substrate having the photopatterned extreme ultraviolet photoresist layer to a temperature in a first temperature range, flowing one or more of oxygen gas, carbon dioxide gas, and water vapor-containing gas into contact with the substrate having the photopatterned extreme ultraviolet photoresist layer, and then cooling the substrate having the photopatterned extreme ultraviolet photoresist layer to a temperature in a second temperature range. Moreover, the first temperature range may be between 50°C to 200°C, and the second temperature range may be 40°C or lower.

[0063] In some implementations of the method, at least one of the one or more drydevelopment processes may include flowing one or more process gases across the substrate having the photopatterned extreme ultraviolet photoresist layer to remove portions of the photopatterned extreme ultraviolet photoresist layer.

[0064] In some implementations of the method, the at least one of the dry-development processes may be performed with the substrate having the photopatterned extreme ultraviolet photoresist layer held at a temperature of 40°C or lower.

[0065] In some implementations of the method, the at least one of the dry-development processes may be performed with the substrate having the photopatterned extreme ultraviolet photoresist layer held at a temperature of 20°C or lower.

[0066] In some implementations of the method, the post-exposure bake process may include heating the substrate having the photopatterned extreme ultraviolet photoresist layer to a temperature greater than or equal to a third temperature of at least 130°C for a first time period.

[0067] In some implementations of the method, the third temperature may be at least 200°C.

[0068] In some implementations of the method, the third temperature may be at least 250°C.

[0069] In some implementations of the method, the method may further include (h) causing the substrate having the photopatterned extreme ultraviolet photoresist layer to be removed from the dry-development chamber after (g), and (i) causing the substrate having thephotopatterned extreme ultraviolet photoresist layer to be removed from the one or more transfer chambers after (h).

[0070] In some implementations of the method, a loadlock may be connected with the one or more transfer chambers and may be accessible to one of the one or more wafer-handling robots. In such an implementation, the loadlock may be configured to facilitate removal of the substrate having the photopatterned extreme ultraviolet photoresist layer from the one or more transfer chambers and into an atmospheric pressure environment, and the method may include performing (a) through (h) without placing the substrate having the photopatterned extreme ultraviolet photoresist layer in the loadlock.

[0071] In some implementations of the method, the method may further include causing oxygen to flow into the cooling-and-treatment chamber during at least part of (e).

[0072] In some implementations of the method, the method may further include causing water vapor to flow into the cooling-and-treatment chamber during at least part of (e).

[0073] In some implementations of the method, the method may further include causing carbon dioxide to flow into the cooling-and-treatment chamber during at least part of (e).

[0074] In some implementations of the method, the cooling-and-treatment chamber may include a temperature-controlled wafer support, and the method may further include causing the substrate having the photopatterned extreme ultraviolet photoresist layer to be placed on the temperature-controlled wafer support and causing the temperature-controlled wafer support to, while the substrate having the photopatterned extreme ultraviolet photoresist layer is supported by the temperature-controlled wafer support, 1) maintain a temperature in the first temperature range during at least part of (e), and 2) maintain a temperature in the second temperature range during at least part of (e) and after (1).

[0075] In some implementations of the method, the first temperature range may be between 75°C and 200°C.

[0076] In some implementations of the method, the first temperature range may be between 95°C and 200°C.

[0077] In some implementations of the method, the second temperature range may be between -10°C and 25°C.

[0078] In some implementations of the method, the second temperature range may be between -10°C and 20°C.

[0079] In some implementations of the method, the method may further include causing a heat transfer fluid to flow from a first reservoir to an inlet of the temperature-controlled wafer support during at least part of (1) and causing a heat transfer fluid to flow from a second reservoir to the inlet of the temperature-controlled wafer support during at least part of (2). Moreover, the first reservoir may be associated with a first temperature control system configured to maintain the heat transfer fluid present in the first reservoir within the first temperature range, and the second reservoir may be associated with a second temperature control system configured to maintain the heat transfer fluid present in the second reservoir within the second temperature range.

[0080] In some implementations, a semiconductor processing system is provided that includes an equipment front-end module (EFEM), a post-exposure bake chamber configured to facilitate performance of a post-exposure bake process on a substrate having a photopatterned extreme ultraviolet photoresist layer, a dry-development chamber configured to facilitate performance of one or more dry-development processes on the substrate having the photopatterned extreme ultraviolet photoresist layer, and a cooling station positioned in the EFEM. The post-exposure bake chamber may be configured to be at a sub-atmospheric pressure while the post-exposure bake process is being performed, while the dry-development chamber may be configured to be at a sub-atmospheric pressure while the one or more dry development processes are being performed. The EFEM may be configured to receive a frontopening unified pod (FOUR) containing a stack of substrates. The semiconductor processing system may be configured to cause each substrate in the stack of substates to be removed from the FOUR and introduced into the post-exposure bake chamber, cause the post-exposure bake process to be performed on each substrate, cause each substrate to be returned to the EFEM after the post-exposure bake process is performed on that substrate, cause each substrate to remain in the EFEM for a determined period of time to cool to a lower temperature, cause each substrate to be introduced into the dry development chamber, cause the one or more dry development processes to be performed on each substrate after that substrate has cooled to the lower temperature in the EFEM and has been introduced into the dry development chamber, and cause each substrate to be removed from the dry development chamber after the one or more dry development processes have been performed on that substrate.BRIEF DESCRIPTION OF THE FIGURES

[0081] Reference to the following Figures is made in the discussion below; the Figures are not intended to be limiting in scope and are simply provided to facilitate the discussion below.

[0082] FIG. 1 depicts a plan view of a semiconductor processing tool that includes a transfer chamber, a dry-development chamber, and a post-exposure bake chamber.

[0083] FIG. 2 depicts a side view schematic of a portion of a semiconductor processing tool similar to that shown in FIG. 1.

[0084] FIG. 3 depicts a schematic of a semiconductor processing tool similar to that shown in FIG. 2.

[0085] FIG. 4 depicts an isometric view of an example temperature-controlled wafer support.

[0086] FIGS. 5 and 6 depict cross-sectional views of the temperature-controlled wafer support of FIG. 4 through sectioning planes depicted in FIGS. 7 and 8.

[0087] FIGS. 7 and 8 depict cross-sectional views through parallel sectioning planes that are depicted in FIGS. 5 and 6.

[0088] FIGS. 9 and 10 depict section views of a different example temperature-controlled wafer support along section lines 9 and 10 in FIG. 11.

[0089] FIG. 11 depicts a section view of the temperature-controlled wafer support of FIGS. 9 and 10 along section line 11 in FIGS. 9 and 10.

[0090] FIG. 12 depicts a section view of another example temperature-controlled wafer support.

[0091] FIG. 13 depicts another section view of the example temperature-controlled wafer support of FIG. 12.

[0092] FIG. 14 depicts a section view of another example temperature-controlled wafer support.

[0093] FIG. 15 depicts another section view of the example temperature-controlled wafer support of FIG. 14.

[0094] FIG. 16 depicts a section view of another example temperature-controlled wafer support.

[0095] FIG. 17 depicts another section view of the example temperature-controlled wafer support of FIG. 16.

[0096] FIGS. 18 and 19 depict top and bottom perspective views, respectively, of three discrete layer parts that may be separately machined from respective plates of material and then joined together to provide a temperature-controlled wafer support.

[0097] FIG. 20 depicts the layer parts of FIGS. 18 and 19 after being joined together.

[0098] FIGS. 22 and 21 show top and bottom views, respectively, of the middle layer part shown in FIGS. 18 and 19.

[0099] FIGS. 23 and 24 depict top and bottom perspective views of the temperature- controlled wafer support of FIG. 20 after post-joining machining operations.

[0100] FIGS. 25 and 26 depict section views of the temperature-controlled wafer support depicted in FIGS. 23 and 24.DETAILED DESCRIPTION

[0101] Reference is made herein in detail to specific embodiments of the disclosure.Examples of the specific embodiments are illustrated in the accompanying drawings. While the disclosure will be described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the disclosure to such specific embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The present disclosure may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail so as to not unnecessarily obscure the present disclosure.

[0102] This disclosure relates generally to the field of semiconductor processing. In particular aspects, the disclosure is directed to processes and apparatuses for facilitating EUV processing of semiconductor wafers in a more cost-effective manner by reducing the amount of EUV exposure time needed to produce a given feature pattern in an EUV-sensitive photoresist to form a patterning mask in the context of EUV patterning. Such photoresists may, for example, be provided using either dry or wet deposition or coating techniques. The techniques andapparatuses disclosed herein may be used for appropriate photoresists that are dry deposited or, for example, applied through a wet process such as spin coating.

[0103] Patterning of thin films in semiconductor processing is often an important step in the fabrication of semiconductors. Patterning involves lithography. In 193nm photolithography, patterns are printed on a substrate having a photoresist layer by emitting photons from a photon source through a mask, thereby exposing a region in the shape and form of the pattern on the photosensitive photoresist. This causes a chemical reaction in the photoresist that, after development, allows certain portions of the photoresist to be removed to form the pattern. The substrate having the pattern may then be subjected to further processing operations to etch away the material that is exposed via the removed portions of the photoresist, thereby creating features defined by the pattern. The remaining photoresist may then be removed and the process repeated to create additional feature layers.

[0104] Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include nodes 22nm, 16nm, and beyond. In the 16nm node, for example, the width of a typical via or line in a Damascene structure is typically no greater than about 30nm. Scaling of features on advanced semiconductor integrated circuits (ICs) and other devices is driving lithography to improve resolution.

[0105] Extreme ultraviolet (EUV) lithography can extend lithography technology by moving to smaller imaging source wavelengths than would be achievable with non-EUV photolithography methods. EUV light sources at approximately 10-20nm, or ll-14nm wavelength, for example 13.5nm wavelength, can be used for leading-edge lithography tools, also referred to as scanners. The EUV radiation is strongly absorbed in a wide range of solid and fluid materials including quartz and water vapor, and so operates in a vacuum.

[0106] EUV lithography makes use of EUV photoresists (or just "resists") that are patterned to form masks for use in etching underlying layers. EUV resists may be polymer-based, chemically amplified resists (CARs) produced by liquid-based spin-on techniques. An alternative to CARs is directly photopatternable metal oxide-containing films, such as those available from Inpria, Corvallis, OR, and described, for example, in US Patent Publications US 2017 / 0102612, US 2016 / 021660 and US 2016 / 0116839, incorporated by reference herein at least for their disclosure of photopatternable metal oxide-containing films. Such films may be produced by spin-on techniques or dry vapor-deposited. The metal oxide-containing film can be patterned directly (i.e., without the use of a separate photoresist) by EUV exposure in a vacuum ambientproviding sub-30nm patterning resolution, for example as described in US Patent 9,996,004, issued June 12, 2018 and titled EUV PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDECONTAINING HARDMASKS, and / or in Application PCT / US19 / 31618, filed May 9, 2019, and titled METHODS FOR MAKING EUV PATTERNABLE HARD MASKS, the disclosures of which at least relating to the composition, deposition, and patterning of directly photopatternable metal oxide films to form EUV resist masks is incorporated by reference herein. Generally, the patterning involves exposure of the EUV resist with EUV radiation to form a photo pattern in the resist, followed by development to remove a portion of the resist according to the photo pattern to form the mask.

[0107] It should also be understood that the while present disclosure relates to lithographic patterning techniques and materials exemplified by EUV lithography, it is also applicable to other next generation lithographic techniques. In addition to EUV, which includes the standard 13.5nm EUV wavelength currently in use and development, the radiation sources most relevant to such lithography are DUV (deep-UV), which generally refers to use of 248nm or 193nm excimer laser sources, X-ray, which formally includes EUV at the lower energy range of the X- ray range, as well as e-beam, which can cover a wide energy range. The specific methods may depend on the particular materials and applications used in the semiconductor substrate and ultimate semiconducting device. Thus, the methods described in this application are merely exemplary of the methods and materials that may be used in present technology.

[0108] Directly photopatternable EUV resists may be composed of or contain metals and / or metal oxides mixed within organic components. The metals / metal oxides are highly promising in that they can enhance the EUV photon absorption and generate secondary electrons and / or show increased etch selectivity to an underlying film stack and device layers. Such photoresists have traditionally been developed using a wet (solvent) approach, which requires the wafer to be immersed in a developer solvent and then dried and baked. Wet development does not only limit productivity but can also lead to line collapse due to surface tension effects and / or delamination.

[0109] Dry development techniques have been proposed to overcome these issues by eliminating substrate delamination and interface failures. Dry development can improve performance (e.g., prevent line collapse due to surface tension and delamination effects encountered in wet development) and enhance throughput (e.g., by avoiding having to move the wafer through a wet development track). Other advantages may include eliminating theuse of organic solvent developers, reduced sensitivity to adhesion issues, increased EUV absorption for improved dose efficiency, and a lack of solubility-based limitations. Dry development can also provide more tunability and give further critical dimension (CD) control and better scum free defect window.

[0110] An example photopatterned metal-containing photoresist may be developed by exposure to halide-containing chemistries. An EUV-sensitive metal or metal oxide-containing film, e.g., an organotin oxide, is disposed on a semiconductor substrate. Various potential metal-containing photoresists may, for example, include photoresists that include tin, tellurium, hafnium with an organic ligand attached thereto that is an alkyl group with from 1 to 12 carbon atoms in it. The EUV-sensitive metal or metal oxide-containing film is patterned directly by EUV exposure in vacuum ambient. A pattern is then developed to form a resist mask using a development chemistry. In some embodiments, the development chemistry is a drydevelopment chemistry. In some embodiments, the dry-development chemistry may include hydrogen chloride (HCI), hydrogen bromide (HBr), or organohalides (or mixtures of two or more thereof), usually mixed with an inert carrier gas such as argon (Ar), helium (He), krypton (Kr), xenon (Xe), or nitrogen (N2) (or mixtures of two or more thereof) and, in some instances, less than 5% of oxygen and / or hydrogen. Such a dry-development chemistry, e.g., containing halogen-donating gases such as those, for example, listed above, may be flowed across or over a wafer with a latent image (a photopatterned metal-containing photoresist) with the wafer being held to a temperature in the -10°C to 40°C range after the wafer has been exposed to an EUV patterning operation. The dry-development chamber, for example, may include a wafer support that is equipped with internal coolant flow channels through which a coolant may be circulated. The coolant, for example, may be a coolant that has a freezing point below 0°C, such as ethylene or propylene glycol, and which may be stored in a refrigerated or chilled reservoir in order to lower the temperature of the coolant to levels such as -10°C (or lower) before circulating the coolant through the wafer support. Such dry-development techniques may be done in chamber pressure environments in approximately the 0.1 mTorr to 760 Torr range, e.g., in the 0.1 mTorr to 1 Torr range, while using either a gentle plasma or a thermal process while flowing a dry-development chemistry, e.g., a hydrogen and halide drydevelopment chemistry.

[0111] Once the metal-containing photoresist has been exposed to the desired lithographic pattern, e.g., in an EUV scanner or similar patterning equipment, the exposed wafer may bemoved to a dry-development chamber for performance of a dry-development process in order to remove either the exposed areas thereof (referred to as the latent image produced by the scanner) or the unexposed areas thereof. In some implementations, the exposed wafer may be subjected to a post-exposure bake (PEB)— a thermal process that may cause cleaved metal bonds, e.g., tin bonds in a tin-based alkoxy resist, to convert to metal-oxygen, e.g., tin-oxygen, bonds to form a material that is stoichiometrically close to a metal-oxide, e.g., tin-oxide, in the exposed areas. The unexposed areas during such a PEB may retain an alkyl ligand in one of the exposed valences of the metal, e.g., in one of the four valences of tin. The PEB may be performed after the wafer has been exposed to EUV but prior to performance of the drydevelopment process. Typical PEBs may include, for example, PEBs in which the wafer is heated to a temperature or temperatures between 130°C to 300°C, e.g., 130°C to 250°C, for a period of time, e.g., between 30 seconds to 240 seconds. In some instances, a PEB process may include the performance of multiple PEBs, e.g., an initial PEB such as that discussed above (although perhaps at a lower temperature range, such as 130°C to 250°C), followed by a second PEB in which the wafer may be heated to a temperature or temperatures between 200°C to 300°C in a controlled ambient environment for a period of time between 30 seconds and 240 seconds. In some instances, an initial PEB may be performed in a post-exposure bake chamber that is integrated into the same tool as the EUV scanner, thereby allowing the initial postexposure bake to be performed on the wafer without breaking vacuum (i.e., without removing the wafer from the vacuum environment that the EUV exposure occurs within or one or more different vacuum environments that may be located within the EUV scanner tool). In such implementations, a second PEB may be performed in a tool separate from the EUV scanner tool; the wafer and exposed photoresist located thereon may be moved from the EUV scanner tool and into a front-opening unified pod (FOUP) for transport, e.g., via an overhead conveyance system, to a separate tool that is equipped to perform the second PEB.

[0112] Post-exposure bake operations may be performed by placing the substrate that is to be baked onto a wafer support, e.g., pedestal, that may incorporate one or more heating systems, e.g., heat transfer channels through which high-temperature heat transfer fluid may be circulated, resistive heating elements, etc. The wafer support may be caused to increase in temperature by activating such heating systems in order to achieve a desired PEB target temperature in the wafer support (and thus the wafer supported thereby).

[0113] Subsequent to a PEB process (e.g., the initial PEB if only one PEB is performed, or after the second or further PEBs that may be performed if multiple PEBs are performed), the wafer may be transferred to a dry-development process chamber after being allowed to cool to a temperature that is suitable for performing dry-development processes, e.g., near room temperature, for example 20°C to 40°C, or at a temperature lower than room temperature, e.g., as low as -10°C.

[0114] During the dry-development process, a set of one or more dry-development gases may be flowed across the exposed surface of the wafer. The dry-development gases may be selected so as to selectively attack / etch either the exposed areas or the unexposed areas of the wafer. For example, a halide-containing chemistry, e.g., hydrogen bromide, may be used to selectively remove the unexposed areas of a photoresist, e.g., an organotin resist, as described above. Such a halide-containing chemistry may attack alkyl groups that are still connected to the metal, e.g., alkyl groups that are still connected to tin, in the unexposed areas. In contrast, the alkyl groups that may have existed in the exposed areas may have been previously driven out of those exposed regions during the exposure process and the halide-containing chemistry may therefore generally not attack (or minimally attack) the exposed regions. For example, in a tin-based alkoxy resist, the development chemistry may cause the tin alkyl that may remain in the unexposed areas to be etched away, while the tin oxide that may remain, e.g., via the PEB, may remain generally intact.

[0115] Disclosed herein is a treatment chamber that may be able to be used to facilitate and / or enhance workflows for EUV patterning. Such treatment chambers may be temperature- controlled in that they may have a temperature-controllable wafer support to allow wafers placed thereupon to be heated and / or cooled to particular temperatures. Such treatment chambers may also be configured to controllably flow one or more gases including at least oxygen, carbon dioxide, water vapor-containing gas, oxygen plus carbon dioxide, oxygen plus water vapor-containing gas, carbon dioxide plus water vapor-containing gas, or oxygen plus carbon dioxide plus water vapor-containing gas (when the water vapor-containing gas is flowed with oxygen and / or carbon dioxide, the gas that contains the water vapor may be the oxygen and / or carbon dioxide, or may be a separate carrier gas, such as a non-reactive gas like argon) across the wafer while the wafer is held at a particular temperature or temperatures. In some implementations, such a treatment chamber may be further configured to not be able to flow dry deposition gases or chemistries and / or dry development gases or chemistries. For example,in some such implementations, the treatment chamber may be further configured to not be able to flow gases such as hydrogen chloride (HCI), hydrogen bromide (HBr), organohalides, halogens, or other gases that may act to etch away the EUV photoresist (and thereby develop the lithographic pattern in the EUV-exposed photoresist).

[0116] Such treatment chambers may see potential use in a variety of contexts. For example, in some instances, such treatment chambers may be connected with a transfer chamber that may allow wafers to be transferred into or out of the treatment chamber while maintaining the wafers in a vacuum environment. This may allow for wafers to be subjected to one or more temperature-controlled processes that may provide various effects in different contexts while maintaining the wafer in a vacuum environment before and / or after transfer of the wafer to the treatment chamber. In some instances, such a treatment chamber may be connected with a transfer chamber that is connected with another chamber, e.g., a process chamber that may perform one or more processes on a wafer that may deposit a material or film on the wafer, etch or remove (including selectively etching or removing) a material or film on the wafer, cause a chemical or physical change in a material layer of the wafer (such as, for example, an EUV scanner that may expose regions of the wafer to EUV radiation in order to produce a lithographic pattern), and so forth. In yet further instances, the temperature-controlled treatment chambers discussed herein may be connected with a transfer chamber that is connected with multiple other chambers, e.g., process chambers. For example, a treatment chamber as described herein may be connected with a transfer chamber that is connected with a first process chamber and a second process chamber, thereby allowing a wafer that is resident within the tool to be transferred between the treatment chamber, the first process chamber, and the second process chamber without requiring that the wafer leave a vacuum environment. In such instances, the first process chamber and the second process chamber may each be configured to perform different processes or different types of processes. It will also be understood that the temperature-controlled treatment chambers discussed herein may also be implementable as stand-alone chambers, e.g., that are not necessarily connected with a transfer chamber. For example, a temperature-controlled treatment chamber may, in some cases, be available as a separate component or system that may be connected with existing semiconductor processing tools, or potentially as a chamber that is not connected with a transfer chamber during normal operation.

[0117] Temperature-controlled treatment chambers, as discussed herein, may provide significant benefits when implemented in certain contexts. For example, the temperature- controlled treatment chambers discussed herein may, in some cases, enable or facilitate certain EUV patterning workflows. For example, it was found that performing the dry-development process and the post-exposure bake operations in separate tools, e.g., requiring that the wafers being processed be removed from the controlled pressure and temperature environment of the post-exposure bake chamber, placed into a front-opening unified pod (FOUR) for transport to another tool having a dry-development process chamber, and then transferred from the FOUR to the dry-development process chamber, resulted in the wafers subjected to such treatment developing wafer-to-wafer and in-wafer uniformity issues. Such issues were believed to arise due to several factors— the relatively uneven flow of gas (and thus uneven cooling of the wafer and exposure to atmospheric gases) to which wafers were exposed to in the loadlock in preparation for removal from the tool that performed the post-exposure bake, the often unpredictable transit time required to move the wafer between the two tools (due to varying distances between tools, delays due to multiple FOUPs needing to transit the same portion of the overhead transit system, etc.), and varying local atmospheric conditions (e.g., due to localized changes in humidity, temperature, etc.). To eliminate these potential sources of wafer-to-wafer nonuniformity and in-wafer nonuniformity, the EUV-patterning workflow can include a post-exposure bake process and dry-development process for a given EUV-exposed wafer that are both performed within a single tool, i.e., without needing to bring the wafer out of a vacuum environment, e.g., from the vacuum environment of the post-exposure bake process, into the atmospheric environment (or near-atmospheric environment) of a FOUP, and then into the vacuum environment of the dry-development process. Such a tool may include a transfer chamber, e.g., a vacuum transfer chamber, that is connected with both a postexposure bake chamber and a dry-development chamber. While the post-exposure bake chamber and the dry-development chamber may both be sealed off from the transfer chamber, e.g., via corresponding slit valves, the environments within these various chambers are, due to the fact that all three chambers can be hermetically sealed off from ambient atmosphere, able to be kept under vacuum conditions from when the wafer is first introduced into such a tool following EUV exposure for post-exposure bake all the way until after the wafer is subjected to a dry-development process.

[0118] In EUV processing, the amount of EUV energy per unit area that must be delivered to a photoresist in order to allow that photoresist to then be developed and used to producefeatures of a desired size is referred to as the "dose to size" (DtS). Generally speaking, the DtS needed for a given photoresist directly correlates to the cost of EUV processing— the higher the DtS, the more exposure to EUV is required in order to achieve the necessary DtS. Wafers with photoresists requiring higher DtS may thus require longer EUV exposure intervals, thereby reducing the throughput that EUV scanners . EUV scanners typically have the highest operating costs of all of the various tools used in the EUV processing pipeline— both in terms of initial tool cost (e.g., $100 million dollars or more per scanner, although newer scanners may be as much as three or four times as expensive) as well as significant ongoing operational costs (such as replacing limited-life components, energy costs, repair and maintenance, etc.). Since any increase in the EUV exposure time needed for a given mask pattern will correspondingly decrease the rate at which wafers can be subjected to EUV lithographic exposure using that mask pattern, an increase in DtS will result in lower wafer throughput through the EUV scanner, thereby increasing the cost-per-wafer for EUV lithography processing.

[0119] While the approach described above (post-exposure bake chamber and drydevelopment chamber both implemented in the framework of a common tool) was found to work and resulted in drastically reduced wafer-to-wafer and in-wafer non-uniformity in wafers processed in such a tool, it was discovered that such an approach also incurred a previously unappreciated penalty— it resulted in an accompanying increase in the DtS and thereby significantly increased the per-wafer EUV patterning cost for wafers. The DtS increase, for example, was observed in some instances to be on the order of 20% (e.g., on the order of 15mJ / sq cm).

[0120] For example, in wafers on which a negative-tone photoresist film has been deposited, exposure of regions of the photoresist film to EUV radiation may cause the exposed regions of the photoresist to undergo crosslinking and / or polymerization that make the exposed regions of the photoresist more resistant to removal during the dry-development process. The degree to which the exposed regions may resist the dry-development process may be determined by the amount of EUV exposure that such regions receive, but other post-exposure factors may amplify or attenuate the degree to which the resistance to removal in the exposed regions imparted by the EUV exposure is effective. In the case of a negative-tone photoresist film, it was found that keeping the EUV-exposed wafer within the pressure-controlled environment of the post-exposure bake chamber / dry-development chamber tool to avoid or mitigate wafer-to- wafer and in-wafer non-uniformities also acted to attenuate the resistance of the EUV-exposedphotoresist to the dry-development process, thereby making the EUV-exposed areas of the photoresist more susceptible to removal during the dry-development process and limiting the minimum feature size that could be created using such photoresist films. The attenuation effect could be offset by increasing the DtS during the EUV exposure process, but at a significant increase in EUV patterning cost-per-wafer.

[0121] Somewhat surprisingly, it was discovered that exposure of such exposed photoresist films to atmospheric air (or at least some constituent elements of atmospheric air), elevated temperatures, and / or pressure environments (that are in between the pressure environment of the post-exposure bake and / or dry-development chamber process pressures and atmospheric pressure) had a restorative effect on the DtS of such photoresist films. In particular, it was found that exposure of such photoresist films to one or more of oxygen gas, carbon dioxide gas, and water vapor while at temperatures in the range of ~50°C to 100°C, e.g., ~75°C to 100°C, resulted in a significant recovery of DtS. It is believed that the DtS recovery may improve further with exposure to such gas(es) at temperatures higher than 100°C as well. For example, the ranges above may extend to 125°C, 150°C, 175°C, or 200°C.

[0122] Generally speaking, it was found that exposure to oxygen gas in combination with one or both of carbon dioxide and water vapor and / or in combination with elevated temperatures resulted in increasing levels of DtS recovery. For example, an experiment was performed in which different combinations of gases and water vapor were flowed across an EUV-exposed photoresist layer on a wafer held at different temperatures after the wafer with the EUV- exposed photoresist layer had been subjected to a post-exposure bake operation and before the wafer with the EUV-exposed photoresist layer was subjected to a dry development process. The post-exposure bake operation, in this example, was a "dry" post-exposure bake operation in which the wafer was not exposed or subjected to moisture-containing gases during the bake process. The techniques discussed herein may potentially also provide DtS recovery when performed in between "wet" post-exposure bake operations (in which the wafer may be subjected to a bake operation in the presence of some moisture-containing gas or gases) and dry-development processes, although the effect may not be as pronounced. In the experiment, oxygen gas was flowed onto the EUV-photoresist film of the wafer at the rate of ~30 standard liters per minute (slm) for various five-minute periods in the accompaniment of carbon dioxide at a flow rate of 2 slm and / or water vapor at the rate of 0.6 grams per minute or, for wafer temperatures above 55°C, at 2 grams per minute. Such gas flows were performed at differentwafer temperatures and an inert carrier gas, e.g., argon, was added to the gas flow(s), if needed, to allow the pressure in the test chamber to be maintained at ~170-180 Torr. Such gas flows may also be performed at other pressures as well, such as at pressures between 0.1 mTorr to 600 Torr or even as high as 760 Torr, if desired. It will be understood, however, that other levels / rates of gas flow and water vapor provisioning / flow may be used as well, and that the rates provided above are not limiting.

[0123] It is important to note that the exposure of the photoresist film to one or more of oxygen gas, carbon dioxide gas, and water-vapor-containing gas is understood to occur under controlled circumstances, e.g., in which the flow of such gases across the photoresist film is managed so as to occur in a particular manner, e.g., using a showerhead or other gas distribution device that is designed to flow such gas(es) towards the photoresist film in a controlled fashion and / or using valves, mass flow controllers, and / or other flow-control devices to precisely meter and regulate the flow rates, compositions, and timing of gas flows (as opposed to the uncontrolled exposure to such gases that may occur when, for example, the substrate having such a film is placed into a load lock and the load lock then equalized with the surrounding ambient environment). Moreover, such post-PEB, pre-dry development treatment processes are performed without flowing gases that may etch away the photoresist, e.g., a dry development chemistry. For example, the gases flowed across the wafer during such treatment processes may omit gases such as hydrogen chloride (HCI), hydrogen bromide (HBr), organohalides, halogens, or other gases that may act to etch away the EUV photoresist.However, the gases that are flowed during such treatment processes may, in some implementations, include other gases that are commonly found in atmospheric air, e.g., nitrogen or carbon monoxide.

[0124] A very slight amount of DtS recovery (e.g., on the order of ~1 mJ / sq cm) occurred when flowing an oxygen-carbon dioxide gas mix with no water vapor present at room temperature (~20°C) across the wafer, whereas the same gas flow at 65°C resulted in a somewhat higher amount of DtS recovery, e.g., ~3 mJ / sq cm. Flowing an oxygen-water vapor mixture across the wafer at room temperature resulted in a marginally higher amount of DtS recovery, e.g., ~4 mJ / sq cm, than was observed with the oxygen-carbon dioxide gas mix flow at 65°C; adding carbon dioxide to that same gas flow with the wafer at room temperature nearly doubled the DtS recovery, e.g., to ~7 mJ / sq cm, from what was observed with the oxygen-water vapor gas flow under the same conditions. Further oxygen-water vapor and oxygen-watervapor-carbon dioxide gas flows with the wafer held at 75°C and 100°C resulted in increasingly larger amounts of DtS recovery, with the additional presence of carbon dioxide at each temperature level generally resulting in a somewhat higher amount of DtS recovery as compared with the DtS recovery observed for oxygen-water vapor exposure without accompanying carbon dioxide flow. For example, for oxygen-water vapor and oxygen-water vapor-carbon dioxide flows at 75°C, the DtS recovery was on the order of ~10-13 mJ / sq cm and ~12.5 mJ / sq cm, respectively, while for the same flows at 100°C, the DtS recovery was on the order of ~16 mJ / sq cm and ~17 mJ / sq cm, respectively. Thus, at a wafer temperature of 100°C, the amount of DtS recovery was three or four times that observed for gas flows performed while the wafer was at 20°C.

[0125] It was determined based on these experiments that exposure of the EUV-exposed wafer and photoresist to oxygen gas, potentially in combination with water vapor and / or carbon dioxide gas, at elevated wafer temperatures, such as at temperatures of 50°C and higher, e.g., 70°C and higher, e.g., such as between 70°C and 100°C or between 75°C and 100°C (or, as noted above, to temperatures higher than 100°C), could result in significant DtS recovery in the wafer as compared to scenarios where such exposure did not occur. In fact, it was found that flowing oxygen-water vapor-carbon dioxide (and optional inert carrier gas) gas mixture, or an oxygen-water vapor gas mixture (and optional inert carrier gas), across the wafer at a 100°C wafer temperature caused all or nearly all of the DtS increase that would otherwise occur in such a wafer absent such post-PEB and pre-development treatment to be avoided, thereby allowing the wafer-to-wafer uniformity and in-wafer uniformity improvements that are achievable through use of a combined PEB / dry-development tool to be obtained without the attendant cost of requiring an increased in DtS (and the attendant EUV exposure cost increase).

[0126] While the experiment exposed wafers to such gas flows for a period of five minutes, such an exposure interval may be reduced, for example, to a duration of tens of seconds, e.g., 30 seconds, 40 seconds, or longer, although it may be desirable to keep the duration of such gas flow periods relatively short, e.g., sufficiently long enough to ensure that the desired effect is obtained but short enough to avoid creating a throughput bottleneck, e.g., in the range of 1 to 9 minutes or 1 to 5 minutes.

[0127] The present inventors also determined that performing the above DtS recovery process in a dedicated chamber, such as within a temperature-controlled treatment chamber as described above and again, in more detail, below, would be beneficial. In the context of thefollowing discussion, such a temperature-controlled treatment chamber is also referred to as a cooling and treatment chamber or the like. Such a chamber would permit the exposure to the oxygen and water vapor and / or carbon dioxide during the DtS recovery process to be performed in a sealed environment to prevent the potential migration of such gases and water vapor into the transfer chamber and to ensure that the desired atmospheric environment around the wafer is maintained during the DtS recovery process. Such a dedicated chamber may also be equipped with a wafer support that is configured to rapidly cool the wafer from the temperature it is in after the PEB, e.g., ~130°C to ~300°C (or higher), to a first temperature, e.g., ~50°C to ~100°C (or higher), at which the DtS recovery process will be performed, and then, after the DtS recovery process is complete (or while it is completing), to a second temperature of ~20°C to ~50°C (or cooler) in preparation for transfer into the dry-development chamber. Such large changes in temperatures are difficult to achieve in a rapid manner using conventional cooling wafer supports, e.g., that have a length of tubing that has been bent into a particular shape, such as a serpentine or spiral shape, and that is embedded within a correspondingly shaped groove in the wafer support. Such conventional cooling wafer supports have a relatively large amount of solid mass as compared to the amount of coolant that may be present within the cooling wafer support at any given time, thereby significantly limiting the rate at which heat may be removed from the cooling wafer support. For example, it may take between 250 and 280 seconds, e.g., almost five minutes, or more for such a conventional pedestal to be able to cool a wafer that is held at a temperature used in the DtS recovery process, e.g., 80°C, to the ultimate target temperature, e.g., room temperature or near room temperature, e.g., 25°C. In some instances, it may be desirable to shorten this cooling period to as little as 10 or 20 seconds (or less) in order to avoid creating a potential throughput bottleneck.

[0128] To address this issue, a new temperature-controlled wafer support was designed to cool wafers placed thereupon in a relatively uniform, but still rapid, manner. To achieve this, such temperature-controlled wafer supports may feature a body having a first side that is sized to accommodate and support a wafer (e.g., a first side that is larger in area than a wafer), a second side that faces in an opposite direction from the first side, and a relatively large, generally contiguous plenum that is located in between the first side and the second side. This plenum, which is referred to herein as a first plenum, may encompass a generally circular region that has a diameter slightly smaller than, equal to, or largerthan the diameter of the wafer that is to be supported by the temperature-controlled wafer support, e.g., 90% or moreof a 300mm diameter when a 300mm wafer is to be supported by the temperature-controlled wafer support. This generally circular region may be punctuated by various smaller structures, e.g., tubular columns that provide passageways for lift pins to pass through the body, structure / cooling columns that may be distributed throughout the first plenum, and various regions where solid material is provided within the first plenum in order to enclose gas flow paths and / or sensor bores that extend into the first plenum and thus fluidically isolate such gas flow paths and / or sensor bores from the first plenum.

[0129] Having the first plenum be relatively open allows the minimum distance that heat from the wafer being cooled must flow through to before reaching the coolant to be kept relatively low, thereby greatly increasing the heat transfer rate between the wafer and the coolant that is circulated through the first plenum. For example, for most of the first plenum, the distance that heat must travel to flow from the wafer to the coolant may be defined by the distance between, and in a direction perpendicular to, the first side of the temperature- controlled wafer support and a first surface that is internal to the body and that defines the boundary of the first plenum that is closest to the first side.

[0130] The portion of the first surface that lies within a circle that is sized to be the same diameter as the wafer being supported defines, in effect, the locations that have the shortest heat conduction flow paths to the wafer. In some instances, the portion of the first surface that lies within such a circular perimeter may have a wetted surface area (when coolant is present within the first plenum) that is 70%, 75%, 80%, 85%, 90%, or more of the area of the area of that circle. This percentage represents the percentage of the wafer where the minimum heat conduction path length from the wafer to the coolant is determined solely by the distance between the first surface and the first side at the relevant location— such distances are also generally the shortest heat conduction flow path lengths that the temperature-controlled wafer support provides. Thus, in such configurations, 70%, 75%, 80%, 85%, 90%, or more of the wafer, depending on the amount of wafer's bottom surface that overlaps with the first surface, may conduct heat to the coolant in the temperature-controlled wafer support via the shortest heat conduction flow paths available in the temperature-controlled wafer support, thereby drastically accelerating the rate at which the wafer can be cooled by a coolant that is introduced at a particular temperature.

[0131] The heat conduction flow paths from the wafer underside to the coolant in other areas where there is no overlap between the first surface and the wafer underside may, inmany cases, be only slightly longer than the heat conduction flow paths from the wafer underside to the first surface in the immediate vicinity thereof and may thus also provide for relatively rapid cooling.

[0132] Such a temperature-controlled showerhead may be connected with a cooling system that is connected with a plurality of different reservoirs, each reservoir configured to contain a heat-transfer liquid, e.g., coolant such as glycol or other suitable liquid, at a particular temperature. In such an implementation, different temperature coolant from different reservoirs may be selectively flowed through the first plenum during different time intervals in order to cause the temperature-controlled wafer support to rapidly increase or decrease temperature in order to arrive at a desired setpoint.

[0133] The following discussion reviews various details of the implementations discussed above. While this discussion is intended to provide further understanding of the concepts discussed earlier, it will be understood that other implementations may be evident from this disclosure, and such alternative implementations are to be understood to also fall within the scope of this disclosure. The disclosure is not limited to the specific implementations discussed below.

[0134] FIG. 1 depicts a plan view of a semiconductor processing tool that includes a transfer chamber 102, a dry-development chamber 104, and a post-exposure bake chamber 106. The semiconductor processing tool, in this example, is connected with an equipment front-end module (EFEM) 108 by two loadlocks 107 that act as airlocks and allow wafers to be passed into and out of the transfer chamberl02, which may be held at a vacuum, from and to the EFEM 108, which may be held at ambient or near-ambient atmospheric pressure, without needing to bring the transfer chamber 102 out of vacuum.

[0135] The transfer chamber 102 may contain a wafer-handling robot 110a that may be configured to remove wafers from, and deliver wafers to, the dry-development chamber 104, the post-exposure bake chamber 106, and the loadlocks 107a and 107b. The EFEM 108 may also be equipped with a separate wafer-handling robot 110b that may similarly be configured to remove wafers from, and deliver wafers to, the loadlocks 107a and 107b and to also deliver wafers to, and remove wafers from, one or more front-opening unified pods (FOUPs) that may be docked at the EFEM 108.

[0136] The depicted semiconductor processing tool may also include one or more cooling and treatment chambers 100 that may be configured to be used in the manner discussed above,e.g., to cool the wafer after the wafer experiences a PEB process in the post-exposure bake chamber 106 and before the wafer is transferred to the dry-development chamber 104. In FIG. 1, two instances of the cooling and treatment chamber 100 are depicted to show alternate configurations of such a chamber. For example, the cooling and treatment chamber 100 that is position above the loadlock 107b represents a configuration in which the cooling and treatment chamber 100 and the loadlock 107b are both connected with a common side of the transfer chamber 102 in a stacked configuration, thereby freeing up another side of the transfer chamber 102 for use with a different chamber. For example, the transfer chamber 102 in FIG. 1 may have three post-exposure bake chambers 106 and three dry-development chambers 104 each respectively connected with one of the six sides of the transfer chamber 102 not occupied by the loadlocks 107a and 107b. In an alternate configuration, the cooling and treatment chamber 100 may be connected with one of the sides of the transfer chamber 102 that is not occupied by a loadlock 107b, such as is indicated by the other cooling and treatment chamber 100 depicted in FIG. 1.

[0137] FIG. 2 depicts a side view schematic of a portion of a semiconductor processing tool similar to that shown in FIG. 1. As can be seen in FIG. 2, the tool may include a transfer chamber 202 that is connected with a cooling and treatment chamber 200 and a drydevelopment chamber 206 via slit valves 226 that may be selectively opened or closed in order to connect or seal off the cooling and treatment chamber 200 and / or the dry-development chamber 204 from the transfer chamber 202. The transfer chamber 202 may include a waferhandling robot 210 that may be controllably actuated so as to be able to extend an end effector thereof into, or withdraw the end effector from, the cooling and treatment chamber 200 and / or the dry-development chamber BB06.

[0138] The cooling and treatment chamber 200 may include a showerhead 220a (shown as a chandelier-type showerhead here, but which may also be a flush-mount or other type of showerhead) that may be fluid ically connected, via one or more showerhead control valves 234a-234e, with a plurality of gas and / or vapor sources. In FIG. 2, for example, the showerhead 220a is connected via the one or more showerhead control valves 234a-234e to a non-reactive carrier gas source 228, an oxygen gas source 230, a carbon dioxide source 231, and a water vapor source 232. It will be appreciated that, in some implementations, not all of the gas sources shown may be used. For example, the carbon dioxide source 231 may be omitted in some instances. While not shown, the gas lines that convey the gas(es) and / orwater vapor may also, in some instances, be equipped with flow metering / flow rate control devices, e.g., mass flow controllers, pressure regulators, etc., to allow for more precise control of the gas and / or water vapor flow rate to the showerhead 220a.

[0139] The cooling and treatment chamber 200 in this example is attached to an otherwise unoccupied side of the transfer chamber 202. Accordingly, the space underneath the cooling and treatment chamber 200 is generally available for use by systems that may support operations within the cooling and treatment chamber 200. Thus, in this example, the cooling and treatment chamber 200 includes a wafer support 211a that is a temperature-controllable wafer support 236. The temperature-controllable wafer support 236 may have a plurality of through-holes in it that allow lift pins 224a to extend therethrough in order to lift a wafer 201a off of the temperature-controllable wafer support 236 so that the end effector of the waferhandling robot BB10 can be inserted beneath the wafer 201 to allow the wafer 201 to then be lowered onto the wafer-handling robot 210 end effector (or to perform such actions in reverse in order to transfer the wafer 201a from the end effector of the wafer-handling robot 210 onto the temperature-controllable wafer support 236).

[0140] The temperature-controllable wafer support 236 in this example has a stem that extends downward through the floor of the cooling and treatment chamber 200. A plurality of reservoirs 212, e.g., 212a, 212b, and so forth, may be connected to an inlet and outlet on the stem via fluid supply conduits, e.g., tubing, and a plurality of coolant control valves 216, e.g., coolant control valves 216a and 216b. Pumps 235a and 235b may be provided to allow coolant from the reservoirs 212a and 212b to be selectively flowed through the temperature-controlled wafer support 236. Each reservoir 212, e.g., 212a, 212b, may be equipped or interfaced with a corresponding temperature control system 214, e.g., temperature control systems 214a, 214b, that may be controlled so as to maintain the coolant within each reservoir 212 at a temperature within a preset range. Such a system allows the coolant that is flowed through the temperature-controlled wafer support 236 to be rapidly switched between coolant sources that provide coolant at different temperatures, thereby allowing the temperature-controlled wafer support to be caused to change temperature to match such pre-set temperatures relatively rapidly.

[0141] The dry-development chamber 204 of FIG. 2 is similarly equipped with a wafer support 211b (although the wafer support 211b may be of a different design from that of temperature- controlled wafer support 236) and also includes lift pins 224b that may be caused to extendthrough openings in the wafer support 211b in order to lift wafer 201b off of (or place wafer 201b onto) the wafer support 211b. One or more process gases used during dry-development processes may be flowed into a showerhead 220b that is positioned over the wafer support 211b and wafer 201b; such process gas(es) may be flowed from one or more process gas sources 237 and through one or more valves to the showerhead 220b. As shown in FIG. 2 but not labeled, the showerheads 220a and 220b each have a plurality of gas distribution ports distributed across their undersides to allow gas that is provided to each showerhead 220 to be distributed across the wafers 201 positioned therebeneath.

[0142] FIG. 3 depicts a schematic of a semiconductor processing tool similar to that shown in FIG. 2 with respect to the wafer-handling robot 310 and the components to the right of the wafer-handling robot 310. However, the configuration shown in FIG. 3 features a cooling and treatment chamber 300 that is positioned above a loadlock 307. The cooling and treatment chamber 300 and the loadlock 307 are thus positioned on a common side of the transfer chamber 302 in a stacked configuration. As discussed, this may permit additional other process chambers to be connected with the transfer chamber 302. However, the use of a stem- equipped temperature-controlled wafer support may not be feasible in such a configuration since the space beneath the cooling-and-treatment chamber may be occupied by the loadlock 307.

[0143] In view of this, the temperature-controllable wafer support 336 in FIG. 3 is equipped with a "panhandle," e.g., a radial support structure that extends through or to a sidewall of the cooling and treatment chamber 300, thereby allowing the temperature-controllable wafer support 336 to be supported within the cooling and treatment chamber 300 without requiring structures that may interfere with the loadlock 307 positioned beneath the cooling and treatment chamber 300. The lift pins 324 that are used may also be somewhat differently configured, with the actuator that drives them positioned to the side of the cooling and treatment chamber 300 instead of beneath the cooling and treatment chamber.

[0144] The loadlock 307 and the cooling and treatment chamber 300 may each be connected with the transfer chamber 302 via slit valves 326 that may be controllably operated so as to allow the wafers 301a and 301b to be moved into and out of such chambers. The loadlock 307 may also have an additional slit valve 326 that may connect it with another chamber or enclosure, such as the EFEM 108 discussed earlier (not shown here). The loadlock 307 may also include features such as wafer support pins or other structures that may support the waferwithin the loadlock 307 such that the end effectors of the wafer handling robots (such as the wafer-handling robot 310) of the tool are able to be inserted below the wafers 301a and 301b in order to then retrieve such wafers (or deliver such wafers).

[0145] It will be understood that while the depicted examples feature a single transfer chamber, the concepts discussed above and below may also be implemented in semiconductor processing tools that include multiple transfer chambers that may be connected together, either directly or via intermediate components, such that wafers may be transported between such transfer chambers and / or between processing chambers or other chambers attached to such transfer chambers, without requiring that the wafers be exposed to atmosphere or atmospheric conditions. In other words, such wafers may be able to be kept in a vacuum environment when transported between such transfer chambers or other chambers attached thereto. Moreover, while a single wafer-handling robot is shown in the above examples, it will be understood that a transfer chamber may have multiple wafer-handling robots and, if there are multiple transfer chambers used, each may have its own wafer-handling robot or waferhandling robots. In some such implementations, a given chamber may be accessible to multiple different wafer-handling robots, and while one wafer-handling robot in such an implementation may deliver a wafer to a given chamber, another wafer-handling robot in such an implementation could potentially retrieve that wafer from that chamber.

[0146] FIG. 4 depicts an isometric view of an example temperature-controlled wafer support. As shown in FIG. 4, the temperature-controlled wafer support 436 is similar to that depicted in FIG. 3 and includes a body 438 that is configured to be supported within a cooling and treatment chamber via a radial support structure 478. The body 438 is generally disk-like in shape and has a first side 440 that is configured to support a wafer (not shown) that may be placed thereupon or thereabove, and a second side 442 that faces in an opposite direction from the first side 440. The body 438 may include through-holes 496 that may extend from the first side 440 to the second side 442 and that may be sized large enough that lift pins, such as the lift pins 424a, may be passed therethrough in order to facilitate wafer transfer to / from the temperature-controlled wafer support 410. In some implementations, the first side 440 may also have a plurality of raised regions 498. The raised regions 498 may, for example, serve as minimum-contact area features that serve to support wafers placed upon the first side 440 of the temperature-controllable wafer support 436 while at the same time offering a relatively small contact area with the wafers. Such raised regions 498 may, if provided, be sized so as toprotrude from the first side 440 by a relatively small amount, e.g., less than 0.1mm, 0.2mm, 0.3mm, etc. such that the gap between the underside of the wafer and the first side 440 causes the thin layer of gas that is resident between the first side 440 and the wafer to act so as to conductively transport heat from the wafer into the first side 440.

[0147] The radial support structure 478, as shown in this example, is generally cylindrical in shape and extends radially outward (with respect to a centerline 444 of the body 438) from an outer edge of the body 438. The radial support structure 478 may not only serve to support the body 438 within the cooling and treatment chamber, but may also serve as a conduit through which, for example, coolant that is to be flowed through the body 438 is introduced via inlet 470 and received from the body 438 via outlet 466. The radial support structure 478 may also include a temperature sensor bore 486 that may be sized to receive a temperature sensor that may be used to monitor the temperature within the body 438.

[0148] FIGS. 5 through 8 depict various cutaway views of the temperature-controlled wafer support 436. FIGS. 5 and 6, for example, depict cross-sectional views through sectioning planes that are parallel to the first side 440; these section planes are depicted in FIGS. 7 and 8. FIGS. 7 and 8, meanwhile, depict cross-sectional views through parallel sectioning planes that are perpendicular to the first side 440 and parallel to the radial axis along which the radial support structure 478 extends, as indicated by the section planes depicted in FIGS. 5 and 6.

[0149] As can be seen in FIG. 5, the body 438 may have a first plenum 446 that spans across most of the body 438 and is bounded above by a first surface 450 and bounded below by a second surface 452; the first surface 450 and the second surface 452 are visible in FIGS. 7 and 8. The first plenum 446, in this example, is generally circular in shape and has one or more inlet ports 460 located near or at the center thereof and a plurality of openings, each leading to a corresponding inter-plenum passage 462, positioned along the outer periphery thereof.Coolant may be flowed into the first plenum 446 via the inlet port(s) 460 and may then flow radially outward towards the outer perimeter of the first plenum 446 before flowing into the inter-plenum passages 462.

[0150] Similarly, the body 438 may have a second plenum 448 that also spans across most of the body 438 and is bounded above by a third surface 454 and bounded below by a fourth surface 456; the third surface 454 and the fourth surface 456 are visible in FIGS. 7 and 8. The second plenum 448, in this example, is generally circular in shape and has one or more outlet ports 458 located near or at the center thereof and a plurality of openings, each leading to acorresponding one of the inter-plenum passages 462, positioned along the outer periphery thereof.

[0151] The inter-plenum passages 462 may span between the first plenum 446 and the second plenum 448 such that coolant from the first plenum 446 that flows into the interplenum passages 462 may flow through the inter-plenum passages 462 and into the second plenum 448 along the outer perimeter thereof and may then flow radially inward towards the one or more outlet ports 458 before being flowed out of the body 438. The first plenum 446, the plurality of inter-plenum passages 462, and the second plenum 448 may all be fluidically interposed between the inlet 470 and the outlet 466.

[0152] In the depicted implementation, the first plenum 446 and the second plenum 448 are both generally circular in shape but are both punctuated by radial portions of the body 438 that divide, or nearly divide, the circular shapes of the first plenum 446 and the second plenum 448 such that each does not extend a full 360° about the centerline (or extends a full 360° about the centerline only for a portion of the radial depth of the respective plenum). For example, the second plenum 448 includes a first radial portion 482 that extends radially outward from a center portion 480 encircling the centerline 444. The first radial portion 482 may, for example, provide solid material that is contiguous with the body 438 and which may house within it one or more outlet passages 468 and one or more inlet passages 472. The one or more inlet passages 472 may, for example, fluidically connect the inlet 470 with the one or more inlet ports 460 within the body 438, and the one or more outlet passages 468 may similarly fluidically connect the outlet 466 with the one or more outlet ports 458 within the body 438. In some implementations, the first plenum 446 may include a second radial portion 484 that extends radially inward from the outer perimeter of the first plenum 446. The second radial portion 484 may, for example, provide material that may house the temperature sensor bore 486 and a temperature sensor 488, e.g., a thermocouple, that may be housed within the temperature sensor bore 486. In some implementations, the second radial portion 484 may extend inward to, or almost to, the one or more inlet ports 460, although in other implementations, such as is shown in FIG. 5, the second radial portion 484 may only extend radially inward from the outer perimeter, e.g., from the outermost surface, of the first plenum 446 by about 50% to 75% of the radial depth of the first plenum 446.

[0153] As shown in FIGS. 6 and 7, the inlet passage 472 may have a first portion 474a that extends along the centerline 444 of the body 438. The inlet passage 472 may also have asecond portion 476a that extends from the inlet port 460, through the first radial portion 482 of the body 438, and into the radial support structure 478 in order to fluidically connect with the inlet 470. The outlet passage 468 may similarly have a first portion 474b and a second portion 476b. While the second portion 476b of the outlet passage 468 may similarly extend through the first radial portion 482 of the body 438 and into the radial support structure 478 in order to fluidically connect with the outlet 466, the first portion 474b of the outlet passage 468 may, in contrast to the first portion 474a of the inlet passage 472, instead extend at least partially around the first portion 474a of the inlet passage 472.

[0154] As can be seen in the depicted implementation, multiple outlet ports 458 may be provided in the center portion 480, each outlet port 458 fluidically connecting, and fluidically interposed between, the first portion 474b of the outlet passage 468 and the second plenum 448. In other implementations, only a single, larger outlet port 458 may be used, or a lesser or greater number of outlet ports 458.

[0155] It will be understood that in a similar implementation, the configuration of the first portions 474a / b of the inlet passage 472 and the outlet passage 468 may be swapped, e.g., with there being an annular or C-shaped first portion 474a of the inlet passage 472 having inlet ports 460 distributed along the outer perimeter of the center portion 480 and with the second plenum 448 having an outlet port 458 that is located proximate the centerline 444 of the body 438.

[0156] In some such implementations, a plurality of first flow-partitioning structures 492 may be distributed throughout the first plenum 446, as shown in FIG. 5. Such first flow-partitioning structures 492 may serve multiple purposes. For example, the first flow-partitioning structures 492 may serve to help shape or direct the coolant flow from the center of the first plenum 446 so that it flows outward towards the inter-plenum passages 462 in a generally uniform manner. In instances in which the first flow-partitioning structures 492 span between the first surface 450 and the second surface 452, such first flow-partitioning structures 492 may also serve to provide structural support to the first side 440 of the body 438, thereby reducing the potential of sagging or other deformation. Such potential deformations may, in practice, be relatively slight, but given that the first side 440 is intended to support semiconductor wafers, which are typically quite flat, even small deformations may interfere with such wafer support and compromise heat transfer from the wafer to the body 438. Accordingly, the additional structural support provided to the first side 440 by the first flow-partitioning structures 492may structurally reinforce the first side 440 so as to reduce or eliminate such potential minor deflections, thereby allowing for improved heat conduction from the wafer into the body 438.

[0157] In the depicted example, the first flow-partitioning structures 492 each have an obround cross-section in the sectioning plane of FIG. 5, e.g., in a sectioning plane perpendicular to the centerline 444. However, it will be understood that such structures may, in other implementations, have other cross-sections, such as circular cross-sections, curved crosssections, etc.

[0158] In some implementations, the first flow-partitioning structures 492 may, as depicted in FIG. 5, be grouped in one or more sets of first flow-partitioning structures 492. For example, there may be a plurality of first sets 492a of first flow-partitioning structures 492, with the first flow-partitioning structures 492 in each first set 492a of first flow-partitioning structures 492 each having a respective long axis that is colinear with the long axes of the other first flowpartitioning structures 492 in that first set 492a of first flow-partitioning structures 492. In such implementations, the first sets 492a of first flow-partitioning structures 492 may be arranged in a circular array about the centerline 444 of the body 438, although it will be understood that the circular array may, in some instances, omit the first set 492a of first flow-partitioning structures 492 in one or more array positions. For example, in FIG. 5, the first set 492a of first flow-partitioning structures 492 that would be positioned in the 6 o'clock position (with respect to the Figure orientation) is omitted. The space where the omitted first set 492a of first flowpartitioning structures 492 would be positioned is instead occupied by the second radial portion 484, although one first flow-partitioning structure 492 of the omitted first set 492a of first flow-partitioning structures 492 is nonetheless still present.

[0159] In some implementations, such as that depicted in FIG. 5, the lengths of the first flowpartitioning structures 492 in each first set 492a of first flow-partitioning structures 492 along the respective long axes of those first flow-partitioning structures 492 may be defined so as to not increase with increasing distance from the centerline 444 of the body 438 and such that the lengths of the first flow-partitioning structures 492 in the first sets 492a of first flowpartitioning structures 492 that are closest to the centerline 444 are longer than the lengths of the first flow-partitioning structures 492 in the first sets 492a of first flow-partitioning structures 492 that are furthest from the centerline 444. Put another way, for each first set 492a of first flow-partitioning structures 492, the each first flow-partitioning structure 492 (other than the first flow-partitioning structure 492 of that first set 492a closest to thecenterline 444) may be shorter than, or the same size as, the closest first flow-partitioning structure 492 of that first set 492a in the radially inward direction, e.g., towards the centerline 444, and the outermost first flow-partitioning structure 492 of that first set 492a may be shorter than the innermost first flow-partitioning structure 492 of that first set 492a.

[0160] It will be understood that in some implementations, such as that depicted in FIG. 5, there may also be additional sets, such as a plurality of second sets 492b, of first flowpartitioning structures 492. The second sets 492b of first flow-partitioning structures 492 may, in some instances, have lengths that, similar to the first flow-partitioning structures 492 in the first sets 492a, get, on average, smaller with increasing distance from the centerline 444. The second sets 492b of first flow-partitioning structures 492 may also, in some instances, be arranged in a circular array (with potentially one or more instances of the second set 492b of first flow-partitioning structures 492 being omitted). In some instances, the innermost first flow-partitioning structures 492 of the first sets 492a of the first flow-partitioning structures 492 may be closer to the centerline 444 than the innermost first flow-partitioning structure 492 of the second sets 492b of first flow-partitioning structures 492.

[0161] It will also be appreciated that, in some implementations, a plurality of second flowpartitioning structures 494 may be similarly distributed throughout the second plenum 448, as shown in FIG. 6. Such second flow-partitioning structures 494 may also serve multiple purposes, similar to the purposes served by the first flow-partitioning structures 492.

[0162] In the depicted example, the second flow-partitioning structures 494 also each have an obround cross-section in the sectioning plane of FIG. 6, e.g., in a sectioning plane perpendicular to the centerline 444. However, it will be understood that such structures may, in other implementations, have other cross-sections, such as circular cross-sections, curved cross-sections, etc.

[0163] In some implementations, the second flow-partitioning structures 494 may, as depicted in FIG. 6, be grouped in one or more sets of second flow-partitioning structures 494. For example, there may be a plurality of first sets 494a of second flow-partitioning structures 494, with the second flow-partitioning structures 494 in each first set 494a of second flowpartitioning structures 494 each having a respective long axis that is colinear with the long axes of the other second flow-partitioning structures 494 in that first set 494a of second flowpartitioning structures 494. In such implementations, the first sets 494a of second flowpartitioning structures 494 may be arranged in a circular array about the centerline 444 of thebody 438, although it will be understood that the circular array may, in some instances, omit the first set 494a of second flow-partitioning structures 494 in one or more array positions. For example, in FIG. 6, the first set 494a of second flow-partitioning structures 494 that would be positioned in the 6 o'clock position (with respect to the Figure orientation) is omitted. The space where the omitted first set 494a of second flow-partitioning structures 494 would be positioned is instead occupied by the first radial portion 482.

[0164] In some implementations, such as that depicted in FIG. 6, the lengths of the second flow-partitioning structures 494 in each first set 494a of second flow-partitioning structures 494 along the respective long axes of those second flow-partitioning structures 494 may be defined so as to not increase with increasing distance from the centerline 444 of the body 438 and such that the lengths of the second flow-partitioning structures 494 in the first sets 494a of second flow-partitioning structures 494 that are closest to the centerline 444 are longer than the lengths of the second flow-partitioning structures 494 in the first sets 494a of second flowpartitioning structures 494 that are furthest from the centerline 444. Put another way, for each first set 494a of second flow-partitioning structures 494, the each second flow-partitioning structure 494 (other than the second flow-partitioning structure 494 of that first set 494a closest to the centerline 444) may be shorter than, or the same size as, the closest second flowpartitioning structure 494 of that first set 494a in the radially inward direction, e.g., towards the centerline 444, and the outermost second flow-partitioning structure 494 of that first set 494a may be shorter than the innermost second flow-partitioning structure 494 of that first set 494a.

[0165] It will be understood that in some implementations, such as that depicted in FIG. 6, there may also be additional sets, such as a plurality of second sets 494b, of second flowpartitioning structures 494. The second sets 494b of second flow-partitioning structures 494 may, in some instances, have lengths that, similar to the second flow-partitioning structures 494 in the first sets 494a, get, on average, smaller with increasing distance from the centerline 444. The second sets 494b of second flow-partitioning structures 494 may also, in some instances, be arranged in a circular array (with potentially one or more instances of the second set 494b of second flow-partitioning structures 494 being omitted). In some instances, the innermost second flow-partitioning structures 494 of the first sets 494a of the second flowpartitioning structures 494 may be closer to the centerline 444 than the innermost second flowpartitioning structure 494 of the second sets 494b of second flow-partitioning structures 494.

[0166] As discussed earlier, the temperature-controlled wafer supports discussed herein may be designed to contain a relatively large amount of coolant volume within the body 438 relative to the solid volume of the body 438. The solid volume, it will be understood, refers to the volume of the body 438 that is occupied by solid material, e.g., metal, whereas the coolant volume refers to the total amount of liquid that can be held within the first plenum 446, the second plenum 448, and the inter-plenum passages 462. In some implementations, the ratio of the solid volume of the body 438 to the coolant volume may be less than six, less than five, or less than 4.5. Having such a relatively low ratio of solid volume to coolant volume allows for much more rapid cooling of the temperature-controlled wafer support 436 by the coolant circulated through it.

[0167] Generally speaking, the first side 440 of the body 438 may be generally planar (although in some instances, the first side 440 may be non-planar, e.g., contoured to match a curvature that may be present in a wafer due to manufacturing operations performed on the wafer). The raised regions 498, if present, may protrude upward from such a planar surface, and there may also be other features that may protrude upward from the first side 440.

[0168] In some instances, one or more of the first surface 450, second surface 452, third surface 454, and fourth surface 456 may be non-parallel to the first side 440 but also axially symmetric about the centerline 444 (aside from areas where various features, e.g., flowpartitioning structures, radial portions, etc., may intersect with the various surfaces). In some such implementations, such a surface or surfaces may define a conical surface or conical frustum surface. Such a conical surface or conical frustum surface may, for example, define a cone angle of 175° to 179° in some cases.

[0169] In the depicted example, the first surface 450 is shown as being parallel to the first side 440, but the second surface 452 is shown as being conical in shape, e.g., with a cone angle of approximately 178°. This results in the plenum thickness (the distance between the first surface 450 and the second surface 452 at a particular radial distance from the centerline 444) of the first plenum 446 closest to the centerline 444 of the body 438 being greater than the plenum thickness of the first plenum 446 closest to the inter-plenum passages 462.

[0170] As coolant flows radially outward in the first plenum 446, the circumferential cross- sectional area through which the coolant flows will increase linearly with distance from the centerline 444. As the coolant is generally an incompressible fluid, the radial velocity of the coolant as it moves radially outward will slow down as the circumferential cross-sectional areathrough which the coolant flows increases. This may lead to a less even temperature distribution across the first side. However, if one or both of the first surface 450 and the second surface 452 are shaped as discussed above, e.g., to form a conical surface, this may allow the circumferential cross-sectional area to be decreased with increasing radial distance from the centerline 444, thereby helping offset the increase in circumferential cross-sectional area discussed above. This may allow the coolant flow rate to be kept more uniform across the underside of the first side 440 and may thus help keep the cooling rate of the temperature- controlled wafer support 436 more uniform.

[0171] It will be noted that the distance between the first side 440 and the first surface 450 in this example remains generally constant across the underside of the first side 440, thereby providing a generally uniform-thickness heat conduction path. This may further promote more uniform cooling behavior by the temperature-controlled wafer support 436.

[0172] The second plenum 448, in this example, has a third surface 454 that is also conical and matches, in effect, the cone angle of the second surface 452 such that the thickness of the portion of the body 438 between the first plenum 446 and the second plenum 448 remains generally the same across the body 438.

[0173] FIGS. 9 through 11 depict views of an alternate temperature-controlled wafer support design, e.g., that has a center-located, vertically oriented stem. FIGS. 9 and 10 depict section views of the temperature-controlled wafer support 936 along section lines 9 and 10 in FIG. 11, whereas FIG. 11 depicts a section view of the temperature-controlled wafer support 936 along section line 11 in FIGS. 9 and 10.

[0174] The callouts used for various features in FIGS. 9 through 11 share the same last two digits with equivalent structures in FIGS. 4 through 8, and it can be assumed, unless indicated otherwise from the discussion below or from the Figures, that the earlier description of such equivalent structures set forth with respect to FIGS. 4 through 8 is equally applicable to the structures in FIGS. 9 through 11 that have callouts with the same last two digits as a structure in FIGS. 4 through 8. In the interest of avoiding repetition, such discussion is not set forth again herein, and the reader is instead referred to the earlier discussion of equivalent structures provided above.

[0175] As noted above, the temperature-controlled wafer support 936 of FIGS. 9 through 11 differs from the temperature-controlled wafer support 436 of FIGS. 4 through 8 in one major respect— the radial support structure 478 of the implementation of FIGS. 4 through 8 has beenreplaced by an axial support structure 990, e.g., a stem that extends vertically downward from the second side #942 of the body 938. Such an arrangement allows for the first plenum 946 and the second plenum 948 to be more axial ly / radia lly symmetric since the first radial portion 482 and the second radial portion 484 that partitioned the second plenum 448 and the first plenum 446, respectively, of the temperature-controlled wafer support 436 may be omitted. However, such an arrangement may also require addition clearance below the cooling and treatment chamber, which may make it difficult to implement such a support system in tools in which the treatment and cooling chamber is to be mounted above, for example, the loadlock.

[0176] As can be seen, the axial support structure 990 may extend generally along the centerline 944 and may have within it a vertically oriented inlet passage 972 that extends along the centerline 944 from an inlet 970 and a similarly vertically oriented outlet passage 968 that extends from an outlet 966.

[0177] In the implementation shown in FIGS. 9 through 11, the outlet passage 968 has a first portion 974b that extends around a first portion 974a of the inlet passage 972. In this instance, the outlet passage 968 extends along the axial support structure 990 and also extends completely around the first portion 974a of the inlet passage.

[0178] The temperature-controlled wafer support 936 may offer generally similar, or potentially even more uniform, cooling of a wafer placed thereupon as compared with the temperature-controlled wafer support 436 discussed earlier.

[0179] FIG. 12 depicts a section view of another example temperature-controlled wafer support. FIG. 13 depicts another section view of the example temperature-controlled wafer support of FIG. 12.

[0180] FIGS. 12 and 13 depict a temperature-controlled wafer support 1236 that is similar to the temperature-controlled wafer support 936, e.g., with an axial support structure. The callouts used for various features in FIGS. 12 and 13 share the same last two digits with equivalent structures in FIGS. 4 through 11, and it can be assumed, unless indicated otherwise from the discussion below or from the Figures, that the earlier description of such equivalent structures set forth with respect to FIGS. 4 through 11 is equally applicable to the structures in FIGS. 12 and 13 that have callouts with the same last two digits as a structure in FIGS. 4 through 11. In the interest of avoiding repetition, such discussion is not set forth again herein, and the reader is instead referred to the earlier discussion of equivalent structures provided above.

[0181] The temperature-controlled wafer support 1236 has a first plenum 1246 and a second plenum 1248, similar to the temperature-controlled wafer supports discussed in the above examples. However, the first flow-partitioning structures 1292 and the second flowpartitioning structures 1294 are different from the ones discussed in connection with earlier examples discussed herein. For example, the first flow-partitioning structures 1292 include two different types of first flow-partitioning structures 1292— first flow-partitioning structures 1292a and first flow-partitioning structures 1292b. The first flow-partitioning structures 1292a (and the second flow-partitioning structures 1294, for that matter), are simple round columns that provide support to the body 1238 and but also serve to break up flow of the coolant within the first plenum 1246 and the second plenum 1248 and induce turbulence in the coolant that may accelerate heat transfer between the first side of the temperature-controlled wafer support 1236 and the coolant, thereby increasing the cooling effectiveness of the temperature- controlled wafer support 1236 (the flow-partitioning structures of the other examples discussed earlier may provide a similar effect). The first flow-partitioning structures 1292b, however, are arcuate wall structures that may induce a swirling or gyre flow in the coolant as it moves radially outward, thereby potentially smoothing out or averaging potential radial nonuniformities in coolant temperature and cooling capability. Such structures may also serve to lengthen the flow path length of the coolant flowing from the inlet port 1260 to the interplenum passages 1262, thereby providing additional opportunity for heat transfer into the coolant from the first side of the temperature-controlled wafer support 1236 and increased cooling effectiveness.

[0182] FIGS. 14 and 15 depict a temperature-controlled wafer support 1436 that is similar to the temperature-controlled wafer support 436, e.g., with a radial support structure. The callouts used for various features in FIGS. 14 and 15 share the same last two digits with equivalent structures in FIGS. 4 through 13, and it can be assumed, unless indicated otherwise from the discussion below or from the Figures, that the earlier description of such equivalent structures set forth with respect to FIGS. 4 through 13 is equally applicable to the structures in FIGS. 14 and 15 that have callouts with the same last two digits as a structure in FIGS. 4 through 13. In the interest of avoiding repetition, such discussion is not set forth again herein, and the reader is instead referred to the earlier discussion of equivalent structures provided above.

[0183] The temperature-controlled wafer support 1436 is similar to that shown in FIG. 4, e.g., with first flow-partitioning structures 1492 and second flow-partitioning structures 1494 thatare each elongate in nature and that have long axes that extend radially outward towards the outer perimeter of the first plenum 1446 and the second plenum 1448, respectively. However, it will be observed that while the first flow-partitioning structures 1492 and second flowpartitioning structures 1494 are generally arranged in what can be termed to be a plurality of nominally circular, concentric patterns, the first flow-partitioning structures 1492 and second flow-partitioning structures 1494 are actually not arranged in true circular patterns. Instead, they are arranged in a circular fill pattern, e.g., instances of the first flow-partitioning structures 1492 are replicated and distributed throughout the first plenum 1446 at varying angular positions relative to the coordinate frame of FIG. NN and / or at different radial distances from the center of the inlet port 1460, although each first flow-partitioning structure 1492 is also rotated about its center point so as to retain the same orientation of the long axes of the first flow-partitioning structures 1492 relative to the center of the inlet port 1460. The angular positions and / or radial distances used for each first flow-partitioning structure 1492 may, in some implementations, be selected such that the maximum horizontal distance between directly adjacent or directly neighboring first flow-partitioning structures 1492 is 10mm or less. Similarly, the thicknesses or widths of the first flow-partitioning structures 1492 in a direction perpendicular to the long axes thereof and parallel to the first side of the temperature- controlled wafer support 1436 may, in some instances, be 0.13mm or larger.

[0184] The second flow-partitioning structures 1494 may be similarly arranged within the second plenum 1448, if desired. It will also be noted that the flow-partitioning structures 1492 and 1494 in the above example all have equal lengths and widths, in contrast to the flowpartitioning structures of earlier examples. However, the flow-partitioning structures 1492 and 1494 of this example may also have lengths that generally increase as one moves radially outward from the inlet port 1460, similar to earlier examples.

[0185] Temperature-controlled wafer supports such as the temperature-controlled wafer support of FIGS. 14 and 15, especially if the distances between adjacent flow-partitioning structures and the widths thereof are controlled as discussed above, may be particularly well- suited to being manufactured using additive manufacturing techniques, as discussed below. For example, such dimensional constraints may limit the extent to which the "ceilings" of the plenums 1446 and 1448 are unsupported by one of the flow-partitioning structures 1492 or 1494. Using an increased number of, and shorter or smaller instances of, the flow-partitioning structures as compared with earlier examples may also, in some instances, provide foradditional turbulent flow initiation points that may induce turbulence that further aids in heat transfer between the first side of the temperature-controlled wafer support 1436 and the coolant flowed therethrough.

[0186] FIGS. 16 and 17 depict a temperature-controlled wafer support 1636 that is similar to the temperature-controlled wafer support 1436, e.g., with a radial support structure. The callouts used for various features in FIGS. 16 and 17 share the same last two digits with equivalent structures in FIGS. 4 through 15, and it can be assumed, unless indicated otherwise from the discussion below or from the Figures, that the earlier description of such equivalent structures set forth with respect to FIGS. 4 through 15 is equally applicable to the structures in FIGS. 16 and 17 that have callouts with the same last two digits as a structure in FIGS. 4 through 15. In the interest of avoiding repetition, such discussion is not set forth again herein, and the reader is instead referred to the earlier discussion of equivalent structures provided above.

[0187] It will be noted that the temperature-controlled wafer support 1636 is identical to the temperature-controlled wafer support 1436 except that the first flow-partitioning structures 1692 and the second flow-partitioning structures 1694 each have a long axis that is at an oblique angle relative to a radial vector extending out from the center of the inlet port 1660 and passing through the center of that flow-partitioning structure (as opposed to being parallel to such a vector, as in the temperature-controlled wafer support 1436 of FIGS. 14 and 15). The oblique angle may, for example, be the same for each such flow-partitioning structure within a common plenum or may, in some instances, vary for at least some of the flow-partitioning structures. For example, in some instances, the oblique angle may increase for at least some flow-partitioning structures within a common plenum as a function of increasing distance from the inlet port 1660.

[0188] Arrangements of flow-partitioning structures such as are depicted in the example of the temperature-controlled wafer support 1636 may, similar to the example of FIG. 13, direct coolant flow such that the coolant not only flows radially outward from the inlet port 1660, but also develops a tangential component so that the coolant simultaneously also flows clockwise or counterclockwise about the inlet port 1660. It will be understood that the first plenum 1646 and the second plenum 1648 may have respective flow-partitioning structures that may generate a tangential flow component that, in some implementations, results in opposite chirality, e.g., clockwise coolant flow in the first plenum 1646 and counter-clockwise coolant flow in the second plenum 1648 (or vice-versa). In some implementations, only one plenum,e.g., the first plenum 1646, may have respective flow-partitioning structures that induce chirality in the coolant flow, and the other plenum, e.g., the second plenum 1648, may have flow-partitioning structures that are not configured to induce chirality in the coolant flow. The average flow path lengths of coolant molecules within a plenum having such an arrangement of flow-partitioning structures may be increased as compared with the example of FIGS. 14 and 15, thereby providing for more opportunity for such coolant molecules to receive heat (and remove heat) from the first side of the temperature-controlled wafer support 1636. This, as discussed earlier, further increases the cooling capability and performance of the temperature- controlled wafer support 1636.

[0189] It will also be noted that the size of the flow-partitioning structures 1692 and 1694 appears to increase with increasing radial distance from the inlet port 1660. While this is certainly a potential implementations, in this case, it is caused by the fact that the intersections between the flow-partitioning structures 1692 and 1694 and the upper / lower surfaces of the plenums 1646 and 1648 that respectively contain them are filleted or rounded such that there is a smooth transition between the "vertical" sides of the flow-partitioning structures 1692 and 1694 and the horizontal or near-horizontal tops and bottoms of the plenums. The sectioning plane, in this example, passes through the flow-partitioning structures 1694, for example, at a point where the sectioning plane cuts through the "rounded" regions of the flow-partitioning structures 1694 near the outer perimeter but the "unrounded" regions of the flow-partitioning structures 1694 closer to the inlet port 1660 (for example, due to the fact that the plenums 1646 and 1648 each have a conical lower or upper surface). As a result, the cross-sectional area of the flow-partitioning structures 1694 appears to increase as one moves closer to the outer perimeter of the second plenum 1648. Such rounded interfaces may also further facilitate manufacture of the temperature-controlled wafer support 1636 through additive manufacturing techniques.

[0190] While additive manufacturing techniques may be used to manufacture the temperature-controlled wafer supports discussed herein, in some instances, such temperature- controlled wafer supports may be manufactured using subtractive manufacturing techniques in combination with various bonding or joining techniques. For example, multiple discrete plates, one or more of which may have various features machined into the mating surface(s) thereof in order to provide the internal features that may define the various plenums and flow partitioning structures that may be internal to the temperature-controlled wafer support maybe bonded or joined together to provide a temperature-controlled wafer support. For example, a temperature-controlled wafer support manufactured according to such a technique may include, in some instances, three separate layers that are arranged in a stacked formation and then bonded or otherwise joined or fused together to form a single, monolithic structure. In such an example three-layer temperature-controlled wafer support, the middle layer may, for example, have features machined into the opposing sides thereof that each face one of the othertwo layers. Such features may include, for example, channels that define all or part of the inlet passage and / or outlet passage for the temperature-controlled wafer support, the plenums of the temperature-controlled wafer support, the flow-partitioning structures that may be distributed throughout each plenum, and the inter-plenum passages that may link the two plenums through the material of the middle layer. The two adjoining layers may also have various features machines therein, if desired, but may primarily serve to act as "caps" that seal the features that are machined into the opposing sides of the middle layer. The use of three layers in such an arrangement may be the minimum that is required for a temperature- controlled wafer support with stacked, dual internal cooling plenums, but it will be understood that more than three such layers may be used to provide the same end result (or to provide for temperature-controlled wafer supports that have more than two stacked internal plenums). It will also be understood that the features that are machined into opposing sides of the middle layer may instead be machined into the mating side(s) of one or both of the layers positioned adjacent to the middle layer (or machined into the mating faces of each of two adjacent layers, although this would seemingly increase the machining cost.

[0191] In some instances, the support structure that extends from the body of the temperature-controlled wafer support in order to support it, e.g., a radial support structure (such as a "panhandle" feature) or an axial support structure (such as a "stem") may be manufactured separately from the body and may then be joined to the body in a subsequent manufacturing step. If the temperature-controlled wafer support is interfaced with an axial support structure, then it may be relatively straightforward to include seal elements, e.g., firings, at the axial support structure / temperatu re-controlled wafer support interface to individually seal the liquid-carrying passages at the interface. For example, the diameter of the axial support structure at the interface may be increased to provide sufficient clearance to allow corresponding O-ring grooves to be provided around the apertures leading to the inlet passage and the outlet passage, thereby allowing the inlet passage and the outlet passage toeach be sealed against potential leakage as they transition across the interface between the axial support structure and the body of the temperature-controlled wafer support.

[0192] However, in the case of temperature-controlled wafer supports with radial support structures, it may be more difficult to implement such arrangements. For example, there may be more stringent requirements on the size of the radial support structure, which may limit the ability to include seals (and other components, e.g., fasteners for connecting the radial support structure to the body, temperature sensors, etc.) in the interface around the inlet and outlet passages. Such limitations may, for example, result from a desire to reduce the potential for or the magnitude of azimuthal non-uniformity of radial gas flow across the edge of the wafer / body of the temperature-controlled wafer support that might arise due to the "blocking" effect of the radial support structure on such gas flow..

[0193] In such instances, one approach might be to weld the radial support structure to the body of the temperature-controlled wafer support using a weld that extends around the entire perimeter of the interface region between the temperature-controlled wafer support and the radial support structure. However, while this might prevent liquid from the inlet passage and / or outlet passage from leaking out of the body / radial support structure, it would generally be impossible to provide a separate welded perimeters that each extend entirely around the inlet passage opening orthe outlet passage opening at the interface. In other words, such an approach may prevent liquid from exiting the temperature-controlled wafer support but would not prevent coolant from leaking from the inlet passage into the outlet passage (or vice-versa) in the region where the radial support structure is welded to the body of the temperature- controlled wafer support or into other passages or bores that cross the same interface, such as the temperature sensor bore (or similar passage). Such leakage may, for example, present a corrosion issue, e.g., to components that are housed within such other passages, like a temperature sensor.

[0194] An approach for avoiding such issues is to manufacture the radial support structure and the body of the temperature-controlled wafer support at the same time such that the radial support structure is never separate from the body and, therefore, does not need to be joined thereto using a separate process. Both additive manufacturing and the above-discussed approach of bonding or joining separately machined, discrete layers may be used to implement such a strategy. The following Figures provide an example of one such approach.

[0195] FIGS. 18 and 19 depict top and bottom perspective views, respectively, of three discrete layer parts that may be separately machined from respective plates of material, e.g., aluminum, and then joined together, as shown in FIG. 20. FIGS. 22 and 21 show top and bottom views, respectively, of the middle layer part shown in FIGS. 18 and 19.

[0196] The callouts used for various features in FIGS. 18 through 21 share the same last two digits with equivalent structures in FIGS. 4 through 8, and it can be assumed, unless indicated otherwise from the discussion below or from the Figures, that the earlier description of such equivalent structures set forth with respect to FIGS. 4 through 8 is equally applicable to the structures in FIGS. 18 through 21 that have callouts with the same last two digits as a structure in FIGS. 4 through 8. In the interest of avoiding repetition, such discussion is not set forth again herein, and the reader is instead referred to the earlier discussion of equivalent structures provided above.

[0197] As can be seen in FIGS. 18 and 19, the temperature-controlled wafer support 1836 includes discrete first, second, and third layer parts 1836a, 1836b, and 1836c. The various layer parts 1836a, 1836b, and 1836c may each have topmost and bottommost surfaces that are parallel to one another such that when the layer parts 1836a, 1836b, and 1836c are stacked atop one another, the uppermost and bottommost surfaces of the stacked layer parts are parallel. In some instances, each location on the uppermost surface of the stack may have solid material between it and a corresponding location on the bottommost surface of the stack except in regions where there are passages, plenums, or other interface cavities of the temperature-controlled wafer support 1836. Such an approach may make the stacked layer parts 1836a through 1836c more suitable for bonding via diffusion bonding.

[0198] The middle layer part 1836b, in this example, has been machined to create the first plenum 1846 (see FIG. 18) and the second plenum (see FIG. 19), as well as to create the first flow partitioning structures 1892, the second flow partitioning structures 1894, the first radial portion 1882, the second radial portion 1884, and various other elements, such as the interplenum passages 1862. It can be observed that the inlet passage 1872 and the outlet passage 1868 do not, in this case, extend all the way to the outermost end of the radial support structure 1878. It can also be observed that the inlet passage 1872 and the outlet passage 1868 each include portions that are machined into both the (middle) second layer part 1836b and the (top) first layer part 1836a. For example, the portions of the inlet passage 1872 and the outlet passage 1868 that are machined into the first layer part 1836a may take the form ofparallel channels, while the portions of the inlet passage 1872 and the outlet passage 1868 that are machined into the second layer part 1836b may include channels machined into one side of the second layer part 1836b as well as through-holes (visible in FIG. 22) leading from such channels to the opposite side of the second layer part 1836b. Such an arrangement allows the inlet passage 1872 and the outlet passage 1868 to change elevation within the radial support structure 1878 of the temperature-controlled wafer support 1836. Such a configuration may be useful in situations, for example, where the processing chamber in which the temperature- controlled wafer support 1836 is used has fluidic ports for providing and receiving fluid to and from the inlet 1870 and outlet 1866 (visible in later Figures), respectively, that are positioned at an elevation such that the bulk of the inlet passage 1872 and the outlet passage 1868 may need to be offset vertically downward from such fluidic ports in order to position the wafer supported by the temperature-controlled wafer support at the desired process elevation.

[0199] In other implementations in which such an offset in elevation between the inlet 1870 and the outlet 1866 and the opposing ends of the inlet passage 1872 and the outlet passage 1868 is unnecessary, the inlet passage 1872 and the outlet passage 1868 may be provided by channels machined into (or otherwise formed in) one or more of the layer parts 1836a through 1836c, but through-hole portions of the inlet passage 1872 and the outlet passage 1868 passing through one or more of the layer parts 1836a through 1836c may be omitted.

[0200] It will be noted that the implementation shown in FIGS. 18 through 21 is missing various features, such as the inlet 1870 and the outlet 1866 discussed above. Such features, it will be noted, may all be added via external machining operations after the various layer parts 1836a through 1836c are joined together. By machining such features after the layer parts 1836a through 1836c are joined together, any potential deformation that may occur in the various layer parts 1836a through 1836c during the joining process may not cause corresponding deformation in such features. It also will be noted that, in some implementations, additional stock material may be added around the radial support structure 1878 where the radial support structure 1878 connects with the body of the temperature- controlled wafer support 1836 to help ensure successful joining of the layer parts 1836a, 1836b, and 1836c; such additional stock material may then be removed after the layer parts 1836a, 1836b, and 1836c are joined together.

[0201] The layer parts 1836a through 1836c may be joined using any appropriate process, e.g., brazing, soldering, or diffusion bonding. Diffusion bonding, in particular, may be especiallywell-suited for joining the various layer parts 1836a through 1836c together. In diffusion bonding (also referred to as diffusion welding), the various components to be bonded, e.g., the layer parts 1836a through 1836c, are placed into contact with one another and then compressed at high pressure while being held at a high temperature. The temperature that is used may be on the order of 50% to 75% of the absolute melting temperature of the materials being bonded. The components being diffusion bonded may be subjected to pressures of between 3 and 10 MPa during the bonding process, and the components being diffusion bonded may be subjected to such elevated pressures and temperatures for an extended period of time, e.g., several minutes to several hours, depending on the nature of the materials and components. By having the layer parts 1836a through 1836c have parallel top and bottom surfaces, the resulting stack of layer parts 1836a through 1836c may be easily compressed in a uniform manner during the diffusion bonding process. Moreover, smaller features, such as potential minimum contact area features, that may be present on the surfaces of the stacked layer parts 1836a through 1836c may potentially be damaged or altered due to the elevated temperatures and high pressure used during the diffusion bonding process. Such features, as well as other features that may render regions of the layer parts 1836a through 1836c possibly more susceptible to undesired deformation, such as overhangs, chamfers, or other features where there may be an air gap between surfaces that apply the compressive force to the stacked layer parts 1836a through 1836c, may be minimized to the extent possible in order to reduce the potential for gross deflection or deformation of the compressed, stacked layer parts 1836a through 1836c during the diffusion bonding process.

[0202] Diffusion bonding provides a high-strength bond that does not require the use of a separate bonding material, such as solder or brazing filler element. Moreover, diffusion bonds have the same resistance to temperature as the materials that are bonded together (since the bond is formed by the materials of the parts being bonded diffusing into each other). In contrast, the solder or filler metal used in soldering or brazing will necessarily melt at a much lower temperature than the material of the parts being joined. Finally, the high pressure that the parts being bonded are subjected to may generally act to press the parts into full contact with one another. This may ensure, for example, that the various flow partitioning structures and radial portions that may be present may be fully bonded to the facing surface of an adjacent layer part, thereby ensuring that the such elements are in good thermal contact within one another and provide uniform heat flow paths within the temperature-controlled wafer support 1836. This may avoid situations in which the temperature-controlled wafer support1836 may exhibit non-uniform cooling or heating of a wafer placed thereupon. This also ensures that the bond extends across all mating surfaces, thereby preventing potential leak paths through poorly bonded regions or regions where, if brazing or soldering were to be used, there may be gaps in filler metal or solder.

[0203] It will be noted that in a diffusion-bonded part, the seam lines between the bonded parts may be invisible or nearly invisible after the bonding process due to the absence of a filler metal in the bond area and / or the compression of the bonded parts during the bonding process. As a result, parts that are diffusion-bonded together may appear to be a seamless, monolithic structure. In the accompanying Figures, however, such seam lines are depicted as still being visible in the diffusion bonded part to make clear where the various layer parts 1836a through 1836c start and stop.

[0204] Once the layer parts 1836a through 1836c are bonded together, e.g., via diffusion bonding, the resulting structure, which may, for example, be similar to that depicted in FIG. 20, may be subjected to one or more post-bonding machining operations. For example, as seen in FIGS. 23 and 24, the top surface of the temperature-controlled wafer support 1836, corresponding to the exposed planar surface of the layer part 1836a, may be machined down to a lower height, with portions of the machined-off area being machined to a lesser extent in order to produce mesas or other raised regions that may act as minimum-contact areas for supporting a wafer that may be placed upon the temperature-controlled wafer support 1836. Additionally, through-holes 1896 may be bored or drilled through the temperature-controlled wafer support 1836 in order to allow lift pins, for example, to be extended through the temperature-controlled wafer support 1836 in order to lift the wafer off of or lower the wafer onto the temperature-controlled wafer support 1836. The through-holes 1896 may, for example, be drilled or bored through the temperature-controlled wafer support 1836 in locations where there is a continuous expanse of material between the first side 1840 and the second side 1842 of the temperature-controlled wafer support 1836. Other post-bonding machining may include, for example, shaping operations, e.g., to machine off material from bottom outer edge of the body of the temperature-controlled wafer support 1836 in order to chamfer it, or to remove material from the radial support structure 1878 in order to give it a desired cross-section, e.g., a cylindrical cross-section, or to round sharp edges. Further postbonding machining may also be used to add features such as the inlet 1870 and the outlet 1866, O-ring grooves extending around the inlet 1870 and the outlet 1866.

[0205] FIGS. 25 and 26 depict section views of the finished temperature-controlled wafer support 1836 depicted in FIGS. 23 and 24. The two section views are taken along parallel planes— FIG. 25 along the midplane of the temperature-controlled wafer support 1836 and FIG. 26 along a plane that intersects with the outlet passage 1868. As can be seen in FIG. 26, the outlet passage 1868 may include a first portion 1868a, a second portion 1868b, and a third portion 1868c. The third portion 1868c, in this example, is machined into the layer part 1836a, while the first portion 1868a and the second portion 1868b are both machined into the layer part 1836b. As can be seen, the first portion 1868a is positioned at a completely different elevation from the third portion 1868c; the second portion 1868b acts to bridge this elevation change and connect the first portion 1868a with the third portion 1868c. The second portion 1868b may, for example, be a through-hole that is drilled or bored through the second layer part 1836b. In some implementations, the through-hole may extend along an axis that is at an acute angle relative to the first surface 1850. The inlet passage 1872 may have a similar construction.

[0206] As is evident from FIGS. 25 and 26, the first layer part 1836a may provide the first surface 1850, while the second layer part 1836b may provide the second surface 1852 and the third surface 1854 and the third layer part 1836c may provide the fourth surface 1856. Moreover, it will be apparent that the inlet passage 1872 and the outlet passage 1868 may each be at least partially defined by surfaces of the second layer part 1836b and the third layer part 1836c. In the example depicted, the inlet passage 1872 and the outlet passage 1868 may also each be at least partially defined by surfaces of the first layer part 1836a and the second layer part 1836b.

[0207] It will be noted that the configurations of the first plenum 1846 and the second plenum 1848 of the above example are very similar to the configurations of the first plenum 446 and the second plenum 4V48 of FIGS. 4 through 8 in terms of the placement of features within each respective plenum. However, the first plenum 1846 does include a further feature that is not present in the other example temperature-controlled wafer supports discussed herein, e.g., a baffle provided by an annular ring of baffle wall segments 1859 that is centered on the inlet port 1860. Adjacent instances of the baffle wall segments 1859 may be separated from one another a corresponding inlet baffle port 1861, thus forming, in effect, a circular wall with a circular array of inlet baffle ports 1861 passing therethrough. The baffle wall segments 1859 may be positioned at radial locations in between the inlet port 1860 and the innermostfirst flow partitioning structures 1892, and may extend through the entire height of the first plenum at the locations where they are located, e.g., spanning between the first surface 1850 and the second surface 1852 of temperature-controlled wafer support 1836. Inclusion of the baffle feature in a similarly configured temperature-controlled wafer support design resulted in a decrease in the static pressure percent non-uniformity within the first plenum from 3.4% to 2.5% as compared with the static pressure prevent non-uniformity when the baffle feature is omitted from the first plenum (based on finite element fluid flow analysis performed under otherwise identical analysis conditions). Such baffle features may also be included in any of the other temperature-controlled wafer support designs discussed herein.

[0208] It will be understood that the various flow-partitioning structures discussed above in the various examples provided above may, in various additional implementations, be combined in different permutations, e.g., the first flow-partitioning structures from one example may be implemented in a temperature-controlled wafer support in combination with the second flowpartitioning structures from another example.

[0209] The temperature-controlled wafer supports discussed above may be made, for example, from aluminum or other metal or material having a relatively high thermal conductivity, e.g., on the order of 200 W / m / K or higher at room temperature. Any suitable manufacturing technique may be used to manufacture such temperature-controlled wafer supports. For example, the temperature-controlled wafer supports discussed above may be made using additive manufacturing techniques such as selective laser melting (SLM) (which may be used to produce ceramic or silicon versions of such wafer supports) or direct metal laser melting (DMLM) (which may be used to produce metal versions thereof). In particular, the wafer support designs discussed herein may be particularly suitable for being manufactured using laser powder-bed fusion (LPBF) additive manufacturing techniques, which may include manufacturing processes such as SLM, DMLM, SLS (selective laser sintering), and DMLS (direct metal laser sintering), all of which may be used to create metal-based components (and some of which, like SLS and SLM, may be used to create ceramic-based components).

[0210] Generally speaking, horizontal, downward-facing surfaces that are larger than 10mm in width may be at risk of sagging during additive manufacturing processing. Rounded transitions between the flow-partitioning structures and the upper surfaces of the plenums that house them may help "extend" the spacing between flow-partitioning structures that can be used without negatively impacting the manufacturability of the wafer support through additivemanufacturing techniques. For example, the 10mm or less spacing discussed above may be evaluated between the locations where the rounded transition to the upper surface of a plenum ends, which may be a distance equal to the rounded transition radius further away from the side of the flow-partitioning structure.

[0211] To further reduce or eliminate the chance of such horizontal-surface sag, some wafer supports such as are discussed herein may be designed such that the rounded transitions between the above-mentioned sides of the flow-partitioning structures and the upper interior surfaces of the plenums in which those flow-partitioning structures are disposed have radii that are large enough that the rounded transitions for between sides of the flow-partitioning structures and the upper interior surface(s) of the wafer support may touch for at least some neighboring flow-partitioning structures.

[0212] The systems and examples discussed above may be used to implement a postexposure bake process and subsequent dry-development process development process for wafers with EUV-photoresists that have been subjected to EUV exposure. As discussed earlier, a treatment and cooling process may be performed in between the post-exposure bake process and the dry-development process.

[0213] For example, a wafer that has previously had a layer of EUV-sensitive photoresist applied to it, e.g., via deposition using vapor or gas-phase reactants or via some other technique, such as spin-coating, may be subjected to EUV exposure in an EUV scanner. Such EUV exposure may be performed with the aid or a mask or pattern that modulates which regions of the EUV-sensitive photoresist are actually exposed to EUV radiation. Subsequent to such EUV exposure, the EUV-exposed wafer may be removed from the EUV scanner and conveyed to a combined post-exposure bake and dry-development tool that also has a cooling and treatment chamber integrated into it. The EUV-sensitive photoresist may, for example, be a metal-containing photoresist.After the EUV-exposed wafer has been transferred into the combined post-exposure bake and dry-development tool, e.g., such as the tools shown in FIGS. 2 and 3, the EUV-exposed wafer may be moved into a post-exposure bake chamber of such a tool and subjected to a postexposure bake operation. In some implementations of the post-exposure bake operation, the EUV-exposed wafer may be heated to a temperature of between 130°C and 300°C (or higher) for a period of time, e.g., between 30 and 240 seconds. In some instances, one or more reactive gases, e.g., ammonia, may be flowed across the wafer during the post-exposure bakeprocess. These steps may harden and densify areas of the film that have been exposed to EUV radiation (or other types of lithographic patterning radiation). In other implementations, the post-exposure bake process may be a conventional post-exposure bake in which reactive gases are not provided to the substrate and / or the wafer is baked in a non-controlled atmosphere.

[0214] A number of different reactive gases may be used. Examples of useful reactive gases include water (H2O), hydrogen (H2), oxygen (02), ozone (03), hydrogen peroxide (H2O2), carbon monoxide (CO), carbon dioxide (CO2), ammonia (NH3), nitrous oxide (N2O), nitric oxide (NO), methylamine (CH3NH2), dimethylamine ((CH3)2NH), trimethylamine (N(CH3)3), ethylamine (CH3CH2NH2), diethylamine ((CHsCHzhNH), triethylamine (N(CH2CH3)3), alcohols (CnH2n+10H, including but not limited to methanol, ethanol, propanol, and butanol), acetyl acetone (CH3COCH2COCH3), formic acid (HCOOH), oxalyl chloride ((COCI)2), carboxylic acids (CnH2n+lCOOH), and other small molecule amines (NR1R2R3, where each of Rl, R2, and R3 is independently selected from hydrogen, hydroxyl, aliphatic, haloaliphatic, haloheteroaliphatic, heteroaliphatic, aromatic, aliphatic-aromatic, heteroaliphatic-aromatic, or any combinations thereof), etc. Substituted forms of these reactive gases may also be used. In some cases, the substrate may be exposed to two or more reactive gases during a photoresist post-exposure bake operation.

[0215] The reactive gas may interact with the photoresist via oxidation, coordination, or acid / base chemistry. In some cases where the reactive gas is delivered during a PEB operation, the reactive gas may preferentially interact with the photoresist in areas that were exposed to EUV radiation. This preferential interaction may arise due to the chemical changes that occur during EUV exposure, for example the loss of alkyl groups within the photoresist.

[0216] Subsequent to the post-exposure bake process being performed, the wafer may be caused to be moved from the post-exposure bake chamber to the cooling and treatment chamber, where it may be placed on the temperature-controlled wafer support of the cooling and treatment chamber. For example, a wafer-handling robot located within a transfer chamber that is connected with the post-exposure bake chamber may be controlled to remove the wafer from the post-exposure bake chamber and then place the wafer onto the temperature-controlled wafer support of the cooling and treatment chamber.

[0217] As discussed earlier, a wafer that is processed in the cooling and treatment chamber may be subjected to several temperature regimes. For example, there may be three general temperatures or temperature ranges that the wafer may be subjected to— these temperatureranges may be referred to herein as TPEB (referring to the temperature or temperature range at which the wafer is at when it is first introduced into the cooling and treatment chamber after completing a post-exposure bake operation in the post-exposure bake chamber), TCAT (referring to the temperature or temperature range at which the wafer is held to during the DtS recovery process), and TDD (referring to the temperature that the wafer is to be cooled to in preparation for transfer into the dry development chamber). The TPEB may, for example, generally be near or slightly below the temperature that the wafer was in when the postexposure bake process completed, e.g., 130°C or more. The wafer may then be cooled to the TCAT in preparation for, or as part of, exposure to various gases or elements, such as oxygen, carbon dioxide, water vapor, and / or potential inert or non-reactive carrier gases, for a predetermined period of time in order to facilitate recovery of wafer DtS. The wafer may then be cooled to the TDD in preparation for being removed from the cooling and treatment chamber and transfer to the dry-development chamber of the tool. It will be understood that the various temperatures discussed above may be specific, discrete temperature values, e.g., the TCAT may be 100°C, or may be ranges of temperatures, e.g., the TCAT may be 90°C to 110’C.

[0218] After the wafer is placed on the temperature-controlled wafer support, a cooling system that is connected with the temperature-controlled wafer support may be controlled to cause the temperature-controlled wafer support, as well as the wafer supported thereon, to rapidly cool from the TPEB (or whatever temperature the wafer has cooled to at that point) to the TCAT, e.g., such as 50°C to 100°C ° (or more), and to flow one or more gases across the wafer during a treatment process that is carried out for a predetermined period of time. The combination of exposing the wafer to the gases while maintaining the wafer at the TCAT for the predetermined period of time causes at least partial, if not complete, recovery in any degradation of the DtS of the wafer that may occur due to the wafer staying resident in the tool during, and in between, the post-exposure bake and dry development processes that are discussed above. At the same time, having the wafer stay resident in the tool during, and in between, the post-exposure bake and dry development processes may reduce or eliminate the wafer-to-wafer non-uniformities and in-wafer non-uniformities that the wafer might otherwise experience during transit between different tools, e.g., via FOUP, that may separately house post-exposure bake chambers and dry-development chambers.

[0219] Once the above- referenced treatment process has been performed on the wafer, the temperature-controlled wafer support may be caused to further cool the wafer to TDD in preparation for moving the wafer from the cooling and treatment chamber to the drydevelopment chamber.

[0220] Generally speaking, TPEB may be in the range of 130°C to 300°C, e.g., 180°C to 300°C or 200°C to 300°C (or higher), TCAT may be in the range of 50°C to 200°C, e.g., 70°C to 200°C or 80°C to 200°C, or, in some cases, 50°C to 150°C, e.g., 70°C to 150°C or 80°C to 150°C, or, in some further cases, 50°C to 125°C, e.g., 70°C to 125°C or 80°C to 125°C, or, in some additional further cases, 50°C to 100°C, e.g., 70°C to 100°C or 80°C to 100°C (or higher, although TCAT will generally be lower than TPEB), and TDD may be in the range of -10°C to 40°C or -10°C to 20°C or to 25°C.

[0221] In some implementations, the cooling system may be configured to selectively flow coolant from different reservoirs through the temperature-controlled wafer support at different times. For example, the tool may be equipped with different coolant reservoirs that hold coolant at different temperatures, e.g., a first reservoir may hold coolant that is kept at TCAT, while a second reservoir may hold coolant that is kept at TDD. The cooling system may include various valves that may be selectively controlled by a controller in order to switch between the different reservoirs and thus allow coolant from a particular reservoir to be selectively routed through the temperature-controlled wafer support.

[0222] In some instances, a controller that controls the flow of coolant through the temperature-controlled wafer support may be configured to cause coolant from the first reservoir to flow through the temperature-controlled wafer support during a first time period in which the wafer is to be cooled from the TPEB to the TCAT. The coolant flow from the first reservoir may be maintained for a period of time to keep the wafer at the TCAT (or near the TCAT), and may then be switched such that the coolant flow from the first reservoir is replaced by coolant flow from the second reservoir. When the cooler-temperature coolant from the second reservoir is flowed through the temperature-controlled wafer support, the temperature-controlled wafer support will drop further in temperature, thereby cooling the wafer to TDD in preparation for removing the wafer from the temperature-controlled wafer support and moving it to the dry-development chamber.

[0223] It will be understood, of course, that reference above to cooling the wafer and / or temperature-controlled wafer support to a particular temperature by circulating coolant of thattemperature through the temperature-controlled wafer support encompasses cooling the wafer and / or temperature-controlled wafer support to a temperature somewhat higher than that stated, the rate of heat transfer between the coolant and the temperature-controlled wafer support and / or wafer will reduce as the difference between the coolant temperature and the temperature-controlled wafer support / wafer temperature decreases. Given the durations of various stages of cooling, the temperature-controlled wafer support and / or the wafer may not actually reach the designated temperature before the next phase of cooling is to begin.

[0224] In some instances, the controller may cause coolant from the second reservoir, e.g., at TDD, to flow through the temperature-controlled wafer support during at least part of a first cooling phase in which the wafer is cooled from the TPEB to the TCAT before causing the coolant from the first reservoir, e.g., at TCAT, to flow through the temperature-controlled wafer support for the remainder of the first cooling phase. For example, since heat transfer is a function of temperature differential, it may be desirable in some cases to first circulate the lower-temperature coolant from the first reservoir through the temperature-controlled wafer support such that the temperature differential between the coolant and the temperature- controlled wafer support / wafer is greater than it would be if the coolant from the second reservoir were to be circulated through the temperature-controlled wafer support. Adopting this approach may allow the temperature-controlled wafer support and / or wafer to be cooled to TCAT more quickly, thereby reducing the total amount of time that the wafer must reside in the cooling and treatment chamber. Once the temperature-controlled wafer support and / or wafer have reached the TCAT (or once the temperature-controlled wafer support and / or wafer have reached a designated temperature, e.g., a few° above the TCAT), the controller may cause the coolant flow from the second reservoir into the temperature-controlled wafer support to be stopped and for coolant flow from the first reservoir into the temperature-controlled wafer support to be initiated, thereby allowing the temperature-controlled wafer support and / or wafer to be kept at the TCAT for a particular duration, e.g., 20 seconds, 30 seconds, 40 seconds, 50 seconds, 60 seconds, etc.

[0225] It will be understood that while the system discussed above utilizes two reservoirs, additional reservoirs that hold coolant at other temperatures may also be used to allow for additional flexibility in cooling of the wafer. For example, in some implementations, a third reservoir may be provided that may provide coolant that is kept at a temperature higher than the TCAT, e.g., at or near the TPEB; such coolant may, for example, be flowed into thetemperature-controlled wafer support after the wafer has been removed for transfer to the dry development chamber, thereby allowing the temperature-controlled wafer support to be brought to a temperature that is higher than the TCAT prior to placement of the wafer onto the temperature-controlled wafer support. Such implementations may, for example, reduce the potential for a thermal shock to be delivered to the wafer, e.g., if the wafer at TPEB were to be placed on a temperature-controlled wafer support at TCAT, the resulting temperature differential might be on the order of 100°C or more, which might raise the risk of damage to the wafer. Heating the temperature-controlled wafer support to a higher temperature may act to reduce such a temperature differential and mitigate the potential for thermal shock to the wafer.

[0226] The controller may also, as alluded to earlier, control one or more valves to actuate to cause one or more gases or elements, such as oxygen, carbon dioxide, water vapor, and / or inert or non-reactive carrier gas, such as argon, to be flowed across the wafer while the wafer is resident on the temperature-controlled wafer support in the cooling and treatment chamber. In some implementations, such gas flow(s) may be caused to occur while the wafer is held at TCAT, whereas in other implementations, such gas flow(s) may be caused to occur at least partially while the wafer is held at TCAT but also as the wafer is being further cooled to TDD.

[0227] Once the wafer is cooled to TDD (or to a temperature close to TDD), the waferhandling robot may be caused to remove the wafer from the cooling and treatment chamber and deliver the cooled wafer to the dry-development chamber, where the wafer may be placed on a wafer support and then subjected to one or more dry-development processes.

[0228] The dry-development process may occur in a dry-development chamber and may involve developing the photopatterned metal-containing resist by selectively removing a portion of the resist by exposure to a development chemistry comprising a halide to form a resist mask.

[0229] For example, in some implementations, the photopatterned metal-containing resist is a photopatterned metal-containing EUV resist. In some implementations, developing the photopatterned metal-containing EUV resist includes selectively removing an EUV-unexposed portion of the EUV resist relative to an EUV-exposed portion by flowing process gases, e.g., the development chemistry, from a showerhead positioned above the wafer in order to form the resist mask. In some implementations, the development chemistry includes a hydrogen halide, hydrogen gas and halide gas, an organic halide, an acyl halide, a carbonyl halide, a thionylhalide, or mixtures thereof. In some implementations, the development chemistry includes hydrogen fluoride, hydrogen chloride, hydrogen bromide, or hydrogen iodide. In some implementations, developing the photopatterned metal-containing resist by exposure to the development chemistry comprises dry developing the photopatterned metal-containing resist by exposure to a dry-development chemistry. In some implementations, dry developing the photopatterned metal-containing resist comprises applying a remote plasma including radicals of the halide to the resist or generating a plasma including radicals of the halide within the dry development chamber above the wafer, e.g., a direct plasma. In some implementations, dry developing the photopatterned metal-containing resist occurs at a wafer temperature between -10°C and 40°C, at a chamber pressure between 0.1 mTorr and 500 mTorr or between about 0.5 Torr and about 760 Torr, at a gas flow rate of the halide between 100 seem and 2000 seem, an etch selectivity of the resist mask being tunable based at least in part on the wafer temperature, the chamber pressure, the gas flow rate, or combinations thereof. In some implementations, the wafer temperature is kept to between -10°C and 20°C. In some implementations, the photopatterned metal-containing resist comprises an element selected from the group consisting of: tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. In some implementations, the method further includes exposing, after developing the photopatterned metal-containing resist, the photopatterned metal-containing resist to an inert gas plasma. In some implementations, the method further includes depositing a metalcontaining EUV resist film on the semiconductor substrate, and non-selectively removing the metal-containing EUV resist film from the semiconductor substrate without removing the substrate layer prior to providing the photopatterned metal-containing resist.

[0230] It will be further understood that while the above discussion has focused on an implementation in which the cooling and treatment chamber or station, post-exposure bake chamber or station, and dry development chamber or station are all connected with a common transfer chamber or transfer chambers, such that the wafer need not be removed from the vacuum environment in between the start of the post-exposure bake and the conclusion of the dry development process, alternative implementations may potentially include configurations in which the cooling-and-treatment chamber is connected with a transfer chamber that is not connected with a post-exposure bake chamber (or, at least, not connected in a way that allows for such wafers to be transferred between the post-exposure bake chamber and the cooling and treatment chamber without a vacuum break). For example, decoupling the post-exposure bake chamber from the vacuum environment of the transfer chamber / cooling and treatmentchamber / dry development chamber may reduce the potential of a halt or slow-down in throughput through the cooling and treatment chamber and dry development chamber since wafers from other post-exposure bake chambers may be routed to the tool housing the cooling and treatment chamber and dry development chamber while the out-of-commission postexposure bake chamber is repaired. In such implementations, there may be different benefits to using the cooling and treatment chamber as compared to the DtS-recovery benefits discussed above. For example, when a wafer is transferred from a separate post-exposure bake tool to a tool having the cooling and treatment chamber and dry development chamber, the wafer may be exposed to atmospheric or near-atmospheric conditions that may result in non- uniform chemical reactions or physiological effects across the surface of the wafer. For example, some regions of the wafer may become dryer or moister than others, which may result in downstream uniformity issues during the dry development process. Using a temperature-controlled treatment chamber, such as or similar to the cooling and treatment chamber discussed above, may potentially allow for the surface(s) of the wafer to be "normalized" or "reset" with respect to, for example, exposure to water vapor, carbon dioxide, and / or oxygen. By performing such exposure under controlled conditions, e.g., at specified temperatures, at a specified pressure, and / or with specified gas flows, it may be possible to counteract or eliminate such potential sources of non-uniformity. In such implementations, the wafers would most likely be cooled from their post-exposure bake temperatures to a temperature suitable for transport between tools, e.g., to a temperature compatible with transport in a FOUR or similar conveyance. Thus, when the wafer is then transferred from the FOUR to the transfer chamber for introduction into the cooling and treatment station, the wafer may actually be lower in temperature than the temperature that the treatment process is to be performed at. In such instances, the temperature-controlled wafer support in the cooling and treatment chamber may instead be caused to heat the wafer up to the desired temperature for the treatment process, e.g., to 100°C, and then later used to cool the wafer down to a temperature compatible with the requirements of the dry development process / chamber.

[0231] For example, a further or related issue that was identified for wafers being subjected to post-exposure bake operations and subsequent dry development operations in the EUV resist context was that wafers that were subjected to such operations in a decoupled manner, e.g., where the wafers were first subjected to a post-exposure bake operation in a first tool or chamber, cooled, and then placed in a front-opening unified pod (FOUP) and held atatmospheric or similar conditions for a relatively long duration of time, e.g., two or more days, and then ultimately delivered to a second tool or chamber in which the dry development process was performed, were found to exhibit wafer-to-wafer uniformity issues within a given batch of wafers (i.e ., within the group of wafers contained within the same FOUP). For example, when the wafers are stored in a FOUP, they are typically arranged in a vertical stack, with each wafer positioned above the wafer(s) below it and vertically offset from the wafer below it by a gap. Such stacks typically include up to 25 wafers. It was found that the wafer that was in the topmost position in the stack exhibited a markedly different etch rate compared to the wafers in other positions in the stack when subjected to the same dry development process conditions. For example, the etch amount that the topmost wafer in a FOUP stack exhibited was found to be at around 96.5% to 97.5% of the average etch amount across all of the wafers in the stack, whereas all of the other wafers in the stack were between approximately 99% and 101% of the average etch amount (summarizing the results of processing the wafers in two 25-wafer FOUPs under identical process conditions). Thus, the etch amount in the topmost wafer in the FOUP stack was over 100% more than the etch amount in the wafer in the FOUP stack that had the next highest etch amount.

[0232] After investigation, it was found that the topmost wafer in the FOUP stack appeared to have much higher moisture adsorption than the other wafers in the FOUP stack. This increased moisture adsorption by the topmost wafer in the FOUP stack is believed to be the main contributor (or one of the main contributors) to such variation in the topmost wafer etch amount from the average etch amount of the FOUP wafer stack as a whole.

[0233] Various approaches were tested to see if such variability in the topmost wafer etch amount could be reduced. In one such test, wafers in a stack of wafers (22, in this example) in a FOUP were each introduced into a post-exposure bake chamber and subjected to the same post-exposure bake process (performed in vacuum) before being removed from the postexposure bake chamber and cooled for three minutes in the EFEM (i.e., at atmospheric or near- atmospheric pressure), after which each was moved to a dry development chamber and subjected to the same dry development process, again at vacuum. In this test, the wafer that was in the topmost position of the wafer stack in the FOUP exhibited an etch amount that was much closer to the average etch amount across the population of wafers from that FOUP. In fact, the etch amount of the topmost wafer from the FOUP stack was almost exactly the same as the average etch amount of the stack. The remainder of the wafers exhibited etch amountsthat were within 1% of the average etch amount for the wafer stack, except for the second wafer that was processed (i.e., the second wafer from the bottom of the stack), which was within 2% of the average etch amount for the wafer stack.

[0234] As discussed earlier, wafer-to-wafer and in-wafer uniformity issues may, in some instances, be mitigated by eliminating wafers' exposure to uncontrolled atmospheric conditions in between the post-exposure bake process and the dry development process, e.g., keeping the wafer entirely in a vacuum environment in during, and between, the post-exposure bake process and the dry development process. Such an approach may, however, cause an increase in the DtS of the wafers. To mitigate or eliminate such a DtS penalty, a wafer being processed may be actively cooled while being exposed to an oxygen, carbon dioxide, and / or watercontaining atmospheric (still in vacuum) in between the post-exposure bake and dry deposition operations.

[0235] There may be additional advantages to such a process, e.g., the same strategy (or portions thereof) may also act to mitigate discrepancies in etch amount between the topmost wafer in a FOUP stack being processed and other wafers in the FOUP during dry development. For example, if the wafers are unloaded from the FOUP and then introduced to a vacuum environment for a post-exposure bake that is then followed by a cooling operation and subsequent dry development process, all performed within the vacuum environment, this strategy may also allow etch amount variation in the topmost wafer from the FOUP to be controlled or reduced. This benefit may arise even without actively cooling the wafer during the cooling operation and / or flowing oxygen, carbon dioxide, and / or water-containing gas across the wafer during the cooling operation. For example, the wafers in four different FOUPs were processed in such a manner, with each wafer of each FOUP being removed from its respective FOUP and introduced into a vacuum environment before being subjected to the same post-exposure bake operation, followed by the same cooling operation and the same subsequent dry development operation — all of which were performed in a vacuum environment (the cooling operation was performed without active cooling and without the flow of oxygen, carbon dioxide, and / or water-containing gas across the wafer during the cooling operation). For the 25 wafers in the first FOUP, the 24 wafers in the second FOUP (one was missing), and the 20 wafers in the third FOUP (the bottom 5 were missing), all 69 wafers exhibited etch amounts that were within 0.8% of the average etch amount of those wafers. For the 25 wafers in the fourth FOUP, all of the wafers but the topmost wafer in the FOUP exhibitedetch amounts that were within 1% of the average etch amount for the wafers in that FOUP.The topmost wafer in the fourth FOUP exhibited an etch amount that was within 1.4% of the average etch amount for the wafers in the fourth FOUP.

[0236] The above experiments demonstrate that there is a beneficial effect with respect to reducing etch amount variability in the topmost wafer of a stack of wafers in a FOUP that may be achieved using both equipment and techniques similar to those discussed earlier herein with respect to performing post-exposure bakes, subsequent cooling, and then dry deposition within a vacuum environment without a vacuum break as well as equipment in which the wafers are subjected to a vacuum break in between the post-exposure bake and the dry deposition. In the latter, case, the wafers may be removed from the vacuum environment and introduced into a controlled atmospheric environment such as an EFEM (atmospheric, at least, with respect to pressure— in some EFEMs, the composition of the gas flowed through the EFEM may be different from the composition of atmospheric air, e.g., pure nitrogen or having a much higher nitrogen concentration as compared with atmospheric air). The residence time of the wafers in the cooling environment in the latter case may be kept the same for each wafer, thereby generally causing each wafer to experience similar environmental conditions in between the post-exposure bake operation and the dry deposition operation. For example, the wafers may each be kept in the EFEM for a similar amount of time in order to cool.

[0237] In some implementations, the cooling station that is described above in the context of being located within the vacuum environment may instead be positioned outside of the vacuum environment, e.g., in the EFEM or a vestibule, alcove, or chamber attached to the EFEM. Such a configuration may allow the wafers to be cooled in a more repeatable manner (e.g., by using active cooling and temperature control to cool the wafers according to a particular temperature profile).

[0238] Put generally, the issue with the topmost wafer in a FOUP stack exhibiting etch amounts that deviate significantly from the average etch amount of the wafers in the FOUP stack to a much greater extent than the etch amounts exhibited by the other wafers in the stack (for the same process conditions) is believed to arise due to the wafers being positioned in a stacked arrangement within a FOUP in between a post-exposure bake operation and a subsequent dry development operation and then kept in that arrangement for relatively lengthy time periods, e.g., hours or days. The spacing between wafers in a FOUP is constant and relatively small, e.g., on the order of 10 mm pitch between wafers. However, the gapbetween the topmost wafer and the ceiling of the FOUP may be larger than the inter-wafer pitch, resulting in a larger free volume above the topmost wafer than is above the other wafers in the FOUP wafer stack. This may cause the upper side of the topmost wafer to be exposed to a greater quantity of moisture and / or contaminants that may be resident in the atmosphere within the FOUP as compared with wafers lower down in the FOUP wafer stack.

[0239] There may also be convective movement of the atmosphere within the FOUP that causes circulation of gases from lower reaches of the FOUP into the space above the topmost wafer. This, in turn, may act to increase the concentration of some gas constituents and / or water vapor that may be in the atmosphere of the FOUP in the region above the topmost wafer. Thus, there may not only be more gas volume above the topmost wafer in the FOUP as compared with the volumes of gas immediately above the other wafers in the FOUP stack, but such gas may also have a higher concentration of gases or substances that may cause the etch amount that the topmost wafer may experience to vary more compared to the etch amounts exhibited by the other wafers in the FOUP stack during similar processing. The length of time that the wafers may reside in the FOUP will also affect the extent to which the wafers may be affected by the atmosphere within the FOUP— the longer the wafers are resident in the FOUP, generally the more opportunity there is for the upper surfaces of the wafers to be affected by the surrounding gases. In view of this, strategies for avoiding anomalous topmost-wafer etch behavior (as compared with the etch behavior of wafers in other positions in the FOUP wafer stack) may generally include avoiding placing such wafers into an environment in which the wafers may be exposed to different environmental conditions in between the post-exposure bake operation(s) and the dry deposition operation(s) as compared with the other wafers in a set of wafers. For example, while the wafers that are provided for a post-exposure bake operation may be delivered in a FOUP, e.g., as a set of 25 wafers, the wafers may not be reintroduced into the FOUP (or a FOUP) until after they have undergone the dry development operation. Such wafers may, however, be exposed to atmospheric air in between the postexposure bake and dry-development operations, but such exposure may be controlled so as to limit the environmental variation experienced by the wafers, e.g., such that each wafer is exposed for the same duration or approximate duration, exposed at the same temperature, exposed to generally the same atmosphere, etc. Such measures may, for example, reduce the amount of variance in the etch amount that the topmost wafer exhibits (compared to the other wafers in the FOUP stack) when processed in the same manner as the other wafers in the FOUP stack. For example, such wafers may be stored in a semi-controlled environment, e.g., anenvironment that is not at vacuum but which may be at atmospheric or near-atmospheric pressure. Such an environment may, for example, be within the EFEM that may be used to transfer wafers from FOUPs into the tool having the post-exposure bake chamber. EFEMs are typically designed to maintain a slightly higher-than-atmospheric pressure in order to prevent ambient air (including potential contaminants / particulates) from being drawn into the interior of the EFEM where the wafers are resident. EFEMs may also include systems to maintain the atmospheric conditions within the interior of the EFEM, e.g., heaters / coolers to maintain gas / atmosphere temperature within the interior of the EFEM within set limits, dehumidifiers to maintain atmospheric humidity within set limits, gas supply systems that may be used to tailor the gas composition of the atmosphere in the EFEM, etc. As such, an EFEM, or a station (alcove, buffer, vestibule, etc.) attached to the EFEM may be kept at relatively consistent atmospheric conditions during operation. Wafers that are placed in the EFEM or such an attached structure and that are allowed to cool in the EFEM after the post-exposure bake operation and before the dry development operation for similar, e.g., the same, periods of time may avoid the issues with the topmost wafer in a FOUR exhibiting significantly different etch amount characteristics when subjected to the dry development process used on the non- topmost wafers in a FOUP. In contrast, wafers that are instead placed into FOUPs in between the post-exposure back operation and the dry development operation for unpredictable amounts of time may result in the topmost wafer in the FOUP exhibiting significantly different etch amounts during the same dry development processes that are used to process the other wafers in the FOUP.

[0240] As discussed above, tools that incorporate the equipment discussed above and / or that may implement the techniques discussed above may include a controller that is configured to control various systems and subsystems of such tools, such as valves, robots, temperature control systems, etc. Such controllers may be part of a system that may include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, platform or platforms for processing, and / or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the "controller," which may control various components or subparts of the system or systems. The controller, depending on the processing requirements and / or the type of system, may be programmed to control any of the processes disclosed herein, as well as various parameters affecting semiconductor processing, such as the delivery of processinggases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and / or load locks connected to or interfaced with a specific system.

[0241] Broadly speaking, the controller may be defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out the various wafer-treatment techniques discussed above.

[0242] The controller, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. In some examples, a remote computer (e.g., a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. Thus, as described above, the controller may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

[0243] Without limitation, the techniques and systems discussed above may be used in example systems that may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamberor module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and / or manufacturing of semiconductor wafers.

[0244] Depending on the process step or steps to be performed by the tool(s) discussed above, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory. For example, the controller may communicate with a remote system that may dispatch a post-EUV exposure wafer to a tool for post-exposure bake operations, cooling and treatment, and then dry-development.

[0245] The term "wafer," as used herein, may refer to semiconductor wafers or substrates or other similar types of wafers or substrates.

[0246] It is also to be understood that the use of ordinal indicators, e.g., (a), (b), (c), ..., herein is for organizational purposes only, and is not intended to convey any particular sequence or importance to the items associated with each ordinal indicator. For example, "(a) obtain information regarding velocity and (b) obtain information regarding position" would be inclusive of obtaining information regarding position before obtaining information regarding velocity, obtaining information regarding velocity before obtaining information regarding position, and obtaining information regarding position simultaneously with obtaining information regarding velocity. There may nonetheless be instances in which some items associated with ordinal indicators may inherently require a particular sequence, e.g., "(a) obtain information regarding velocity, (b) determine a first acceleration based on the information regarding velocity, and (c) obtain information regarding position"; in this example, (a) would need to be performed (b) since (b) relies on information obtained in (a)— (c), however, could be performed before or after either of (a) or (b).

[0247] It is to be understood that use of the word "each," such as in the phrase "for each <item> of the one or more <items>" or "of each <item>," if used herein, should be understood to be inclusive of both a single-item group and multiple-item groups, i.e., the phrase "for ... each" is used in the sense that it is used in programming languages to refer to each item ofwhatever population of items is referenced. For example, if the population of items referenced is a single item, then "each" would refer to only that single item (despite the fact that dictionary definitions of "each" frequently define the term to refer to "every one of two or more things") and would not imply that there must be at least two of those items. Similarly, when a selected item may have one or more sub-items and a selection of one of those sub-items is made, it will be understood that in the case where the selected item has one and only one sub-item, selection of that one sub-item is inherent in the selection of the item itself.

[0248] For the purposes of this disclosure, the term "fluidically connected" is used with respect to volumes, plenums, holes, etc., that may be connected with one another, either directly or via one or more intervening components or volumes, in order to form a fluidic connection, similar to how the term "electrically connected" is used with respect to components that are connected together to form an electric connection. The term "fluidically interposed," if used, may be used to refer to a component, volume, plenum, or hole that is fluidically connected with at least two other components, volumes, plenums, or holes such that fluid flowing from one of those other components, volumes, plenums, or holes to the other or another of those components, volumes, plenums, or holes would first flow through the "fluidically interposed" component before reaching that other or another of those components, volumes, plenums, or holes. For example, if a pump is fluidically interposed between a reservoir and an outlet, fluid that flowed from the reservoir to the outlet would first flow through the pump before reaching the outlet. The term "fluidically adjacent," if used, refers to placement of a fluidic element relative to another fluidic element such that there are no potential structures fluidically interposed between the two elements that might potentially interrupt fluid flow between the two fluidic elements. For example, in a flow path having a first valve, a second valve, and a third valve placed sequentially therealong, the first valve would be fluidically adjacent to the second valve, the second valve fluidically adjacent to both the first and third valves, and the third valve fluidically adjacent to the second valve.

[0249] Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein.

[0250] Certain features that are described in this specification in the context of separate implementations also can be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation also can be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination.

[0251] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Further, the drawings may schematically depict one more example processes in the form of a flow diagram. However, other operations that are not depicted can be incorporated in the example processes that are schematically illustrated. For example, one or more additional operations can be performed before, after, simultaneously, or between any of the illustrated operations. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Additionally, other implementations are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results.

[0252] The present disclosure, while directed at the various concepts discussed above, will be understood, at a minimum and not to the exclusion of other implementations not listed below, to be directed to at least the following numbered implementations.

[0253] I mplementation 1: An apparatus including: a temperature-controllable wafer support, the wafer support having: a body having a first side and a second side facing in an opposite direction from the first side; a first plenum located within the body, extending radially outward from one or more inlet ports located near a centerline of the body, bounded on one side by a firstsurface, and bounded on another side by a second surface that faces towards the first surface; a second plenum located within the body, extending radially outward from one or more outlet ports located near the centerline of the body, bounded on one side by a third surface and bounded on another side by a fourth surface that faces towards the third surface; a plurality of inter-plenum passages distributed along an outer perimeter of the first plenum, each inter-plenum passage located within the body and spanning between the first plenum and the second plenum; an inlet fluidically connected with the one or more inlet ports via one or more inlet passages located at least partially within the body; and an outlet fluidically connected with the one or more outlet ports via one or more outlet passages located at least partially within the body, in which the first plenum, the plurality of inter-plenum passages, and the second plenum are all fluidically interposed between the inlet and the outlet.

[0254] I mplementation 2: The apparatus of implementation 1, in which: the body includes a plurality of layer parts that are positioned in a stacked arrangement, each layer part joined to the adjacent layer part or adjacent layer parts via a corresponding diffusion bond or corresponding diffusion bonds, the plurality of layer parts including at least a first layer part, a second layer part, and a third layer part, the first surface is provided by the first layer part and the second surface is provided by the second layer part, the third surface is provided by the second layer part and the fourth surface is provided by the fourth layer part the one or more inlet passages are at least partially defined by one or more surfaces of the second layer part and one or more surfaces of the third layer part, and the one or more outlet passages are at least partially defined by one or more surfaces of the second layer part and one or more surfaces of the third layer part.

[0255] I mplementation 3: The apparatus of implementation 2, in which: the one or more inlet passages are also at least partially defined by one or more surfaces of the first layer part and one or more surfaces of the second layer part, and the one or more outlet passages are also at least partially defined by one or more surfaces of the first layer part and one or more surfaces of the second layer part.

[0256] Implementation 4: The apparatus of implementation 3, in which the second layer part includes a first through-hole that defines part of the one or more inlet passages and a second through-hole that defines part of the one or more outlet passages.

[0257] I mplementation 5: The apparatus of implementation 4, in which the first through-hole and the second through-hole extend along corresponding centerlines that form respective acute angles with respect to the first surface.

[0258] I mplementation 6: The apparatus of implementation 5, in which the inlet and the outlet are located at positions offset from, and in a direction perpendicular to, a reference plane that is parallel to the first side and that intersects either the first plenum or the second plenum.

[0259] Implementation 7: The apparatus of implementation 2, in which: the one or more inlet passages include a first inlet passage having a first portion that extends along the centerline of the body, the one or more outlet passages include a first outlet passage having a first portion that extends at least partially around the first portion of the first inlet passage, and the first portion of the first outlet passage encircles the first portion of the first inlet passage.

[0260] I mplementation 8: The apparatus of implementation 2, further including a ring of baffle wall segments and a ring of inlet baffle ports encircling the one or more inlet ports, each baffle wall segment extending from the first surface to the second surface and each inlet baffle port interposed between at least portions of two adjacent ones of the baffle wall segments.

[0261] I mplementation 9: The apparatus of implementation 1 or implementation 2, in which the one or more outlet ports includes a plurality of outlet ports.

[0262] I mplementation 10: The apparatus of implementation 9, in which: the one or more inlet passages include a first inlet passage having a first portion that extends along the centerline of the body, and the one or more outlet passages include a first outlet passage having a first portion that extends at least partially around the first portion of the first inlet passage.

[0263] Implementation 11: The apparatus of implementation 10, further including a radial support structure connected with the body and extending outward from the body relative to the centerline of the body, in which:the inlet and the outlet are both located in the radial support structure, a second portion of the first inlet passage extends from the body into the radial support structure, and a second portion of the first outlet passage extends from the body into the radial support structure.

[0264] Implementation 12: The apparatus of implementation 11, in which: the body includes a center portion that contains the first portion of the first inlet passage and the first portion of the first outlet passage, the body further includes a first radial portion that extends from the center portion to an outermost surface of the second plenum, the first radial portion spans between the third surface and the fourth surface and prevents the second plenum from extending a full 360° about the centerline, and the second portions of the first inlet passage and the first outlet passage extend from the center portion and through the first radial portion before reaching the radial support structure.

[0265] I mplementation 13: The apparatus of implementation 11, in which: the body further includes a second radial portion that extends from an outermost surface of the first plenum radially inward towards the centerline of the body, a temperature sensor bore extends from the radial support structure and into the second radial portion, and a temperature sensor is positioned within the temperature sensor bore.

[0266] I mplementation 14: The apparatus of implementation 10, in which the first portion of the first outlet passage encircles the first portion of the first inlet passage.

[0267] I mplementation 15: The apparatus of implementation 10, further including an axial support structure connected with the body and extending downward from the body along the centerline of the body, in which: the inlet and the outlet are both located in the axial support structure, a second portion of the first inlet passage extends from the body into the axial support structure, and a second portion of the first outlet passage extends from the body into the axial support structure.

[0268] I mplementation 16: The apparatus of implementation 15, in which:the body includes a center portion that contains the first portion of the first inlet passage and the first portion of the first outlet passage, and the second portions of the first inlet passage and the first outlet passage extend from the center portion and through the axial support structure.

[0269] I implementation 17: The apparatus of implementation 15, in which: the body further includes a temperature sensor bore that extends from the axial support structure, through the second plenum, and into the first plenum, the temperature sensor bore is fluid ica I ly isolated from the first plenum and the second plenum within the body, and a temperature sensor is positioned within the temperature sensor bore.

[0270] I mplementation 18: The apparatus of implementation 1 or implementation 2, in which: the first side of the body is planar, and at least one of the first surface and the second surface is axially symmetric and nonparallel with the first side.

[0271] I mplementation 19: The apparatus of implementation 18, in which the first plenum has a plenum thickness closest to the centerline of the body that is greater than the plenum thickness of the first plenum closest to the inter-plenum passages.

[0272] I mplementation 20: The apparatus of implementation 18, in which: the first surface is interposed between the first side and the second surface, and the first surface defines a conical frustum.

[0273] I mplementation 21: The apparatus of implementation 20, in which the conical frustum defines a cone angle of 175° to 179°.

[0274] I mplementation 22: The apparatus of implementation 1 or implementation 2, in which the body further includes a plurality of first flow-partitioning structures distributed throughout the first plenum.

[0275] I mplementation 23: The apparatus of implementation 22, in which each first flow-partitioning structure spans between the first surface and the second surface.

[0276] I mplementation 24: The apparatus of implementation 23, in which the first flow-partitioning structures have obround cross-sections in a plane perpendicular to the centerline of the body.

[0277] I mplementation 25: The apparatus of implementation 24, in which:the first flow-partitioning structures include multiple first sets of first flow-partitioning structures, the first flow-partitioning structures in each first set of first flow-partitioning structures each have a respective long axis that is colinear with the long axes of the other first flowpartitioning structures in that first set of first flow-partitioning structures, and the first sets of first flow-partitioning structures are arranged in a circular array about the centerline of the body.

[0278] I implementation 26: The apparatus of implementation 25, in which: lengths of the first flow-partitioning structures in each first set of first flow-partitioning structures along the respective long axes of those first flow-partitioning structures do not increase with increasing distance from the centerline of the body, and the lengths of the first flow-partitioning structures in the first sets of first flowpartitioning structures that are closest to the centerline are longer than the lengths of the first flow-partitioning structures in the first sets of first flow-partitioning structures that are furthest from the centerline.

[0279] I mplementation 27: The apparatus of implementation 25, in which: the first flow-partitioning structures include multiple second sets of first flowpartitioning structures, the first flow-partitioning structures in each second set of first flow-partitioning structures each have a respective long axis that is colinear with the long axes of the other first flow-partitioning structures in that second set of first flow-partitioning structures, the second sets of first flow-partitioning structures are arranged in a circular array about the centerline of the body, the first sets and second sets of first flow-partitioning structures are arranged in alternating fashion about the centerline of the body, and the first flow-partitioning structures in the first set of first flow-partitioning structures that are closest to the centerline are closer to the centerline than the first flow-partitioning structures in the second set of first flow-partitioning structures that are closest to the centerline.

[0280] I mplementation 28: The apparatus of implementation 22, in which the first flow-partitioning structures are distributed throughout the first plenum with each first flow-partitioning structure being within a first distance of any directly neighboring first flow-partitioning structures.

[0281] Implementation 29: The apparatus of implementation 28, in which the first distance is 10mm.

[0282] I mplementation 30: The apparatus of implementation 28, in which the first flow-partitioning structures each have a long axis that is at an oblique angle relative to a radial line drawn from, and perpendicular to, the centerline of the body to the center of the respective first flow-partitioning structure.

[0283] I mplementation 31: The apparatus of implementation 30, in which the oblique angle increases with increasing distance from the centerline of the body.

[0284] Implementation 32: The apparatus of implementation 22, in which the body further includes a plurality of second flow-partitioning structures distributed throughout the first plenum.

[0285] Implementation 33: The apparatus of implementation 32, in which each second flow-partitioning structure spans between the third surface and the fourth surface.

[0286] Implementation 34: The apparatus of implementation 33, in which the second flow-partitioning structures have obround cross-sections in a plane perpendicular to the centerline of the body.

[0287] Implementation 35: The apparatus of implementation 34, in which: the second flow-partitioning structures include multiple first sets of second flowpartitioning structures, the second flow-partitioning structures in each first set of second flow-partitioning structures each have a respective long axis that is colinear with the long axes of the other second flow-partitioning structures in that first set of second flow-partitioning structures, and the first sets of second flow-partitioning structures are arranged in a circular array about the centerline of the body.

[0288] Implementation 36: The apparatus of implementation 35, in which: lengths of the second flow-partitioning structures in each first set of second flowpartitioning structures along the respective long axes of those second flow-partitioning structures do not increase with increasing distance from the centerline of the body, and the lengths of the second flow-partitioning structures in the first sets of second flowpartitioning structures that are closest to the centerline are longer than the lengths of the second flow-partitioning structures in the first sets of second flow-partitioning structures that are furthest from the centerline.

[0289] I mplementation 37: The apparatus of implementation 35, in which:the second flow-partitioning structures include multiple second sets of second flowpartitioning structures, the second flow-partitioning structures in each second set of second flow-partitioning structures each have a respective long axis that is colinear with the long axes of the other second flow-partitioning structures in that second set of second flow-partitioning structures, the second sets of second flow-partitioning structures are arranged in a circular array about the centerline of the body, the first sets and second sets of second flow-partitioning structures are arranged in alternating fashion about the centerline of the body, and the second flow-partitioning structures in the first set of second flow-partitioning structures that are closest to the centerline are closer to the centerline than the second flowpartitioning structures in the second set of second flow-partitioning structures that are closest to the centerline.

[0290] Implementation 38: The apparatus of implementation 1 or implementation 2, in which: the first plenum is positioned in between the second plenum and the first side, the second plenum is positioned in between the first plenum and the second side, the body has a plurality of through-holes extending from the first side to the second side, and each through-hole is fluidically isolated from the first plenum and the second plenum within the body.

[0291] I mplementation 39: The apparatus of implementation 38, in which the first side has a plurality of raised regions distributed thereacross.

[0292] I mplementation 40: The apparatus of implementation 1 or implementation 2, in which the body has a solid volume that is less than 6 times a combined volume of the first plenum, the inter-plenum passages, and the second plenum.

[0293] I mplementation 41: The apparatus of implementation 40, in which the solid volume of the body is less than 5 times the combined volume of the first plenum, the inter-plenum passages, and the second plenum.

[0294] I mplementation 42: The apparatus of implementation 40, in which the solid volume of the body is less than 4.5 times the combined volume of the first plenum, the inter-plenum passages, and the second plenum.

[0295] Implementation 43: The apparatus of implementation 1 or implementation 2, further including: a plurality of reservoirs, each reservoir associated with a corresponding temperature control system configured to maintain a heat transfer fluid, when present in that reservoir, within a corresponding temperature range, in which the plurality of reservoirs includes at least: a first reservoir associated with a first temperature control system configured to maintain the heat transfer fluid, when present in the first reservoir, within a first temperature range, and a second reservoir associated with a second temperature control system configured to maintain the heat transfer fluid, when present in the second reservoir, within a second temperature range; one or more coolant control valves, one or more fluid transfer lines, and one or more pumps, in which the one or more coolant control valves and the one or more pumps are configured to be controllable so as to cause the heat transfer fluid contained within each reservoir, when present in that reservoir, to selectively flow into the inlet of the temperature - controllable wafer support; and a controller configured to: control the first temperature control system and the second temperature control system such that the first temperature range is higher than the second temperature range, and control the one or more coolant control valves and the one or more pumps to cause the heat transfer fluid, when present in the first reservoir and the second reservoir, to flow from the first reservoir to the inlet during a first time period and to flow from the second reservoir to the inlet during a second time period.

[0296] Implementation 44: The apparatus of implementation 1 or implementation 2, further including: a cooling-and-treatment chamber, in which the body of the temperature-controllable wafer support is positioned within the cooling-and-treatment chamber; and a showerhead having a plurality of gas distribution ports located about the temperature- controllable wafer support.

[0297] Implementation 45: The apparatus of implementation 44, further including: a transfer chamber housing a wafer-handling robot;a dry-development chamber connected with the transfer chamber and accessible to the wafer-handling robot; and a post-exposure bake chamber connected with the transfer chamber and accessible to the wafer-handling robot, in which the cooling-and-treatment chamber is also connected with the transfer chamber and accessible to the wafer-handling robot.

[0298] Implementation 46: The apparatus of implementation 45, further including: a source of non-reactive carrier gas; a source of oxygen gas; a source of water vapor; and one or more showerhead control valves, in which the one or more showerhead control valves are configured to selectively flow the non-reactive carrier gas, the oxygen gas, and the water vapor through the showerhead and towards the temperature-controllable wafer support via the gas distribution ports responsive to receipt of one or more control signals.

[0299] Implementation 47: The apparatus of implementation 46, further including a load-lock connected with the transfer chamber and accessible to the wafer-handling robot, in which the cooling-and-treatment chamber is positioned above the load-lock.

[0300] Implementation 48: A semiconductor processing system including: one or more transfer chambers housing one or more wafer-handling robots; a dry-development chamber connected with the one or more transfer chambers, accessible to at least one of the one or more wafer-handling robots, and configured to facilitate performance of one or more dry-development processes on a substrate having a photopatterned extreme ultraviolet photoresist layer; a post-exposure bake chamber connected with the one or more transfer chambers, accessible to at least one of the one or more wafer-handling robots, and configured to facilitate performance of a post-exposure bake process on the substrate having the photopatterned extreme ultraviolet photoresist layer; and a cooling-and-treatment chamber connected with the one or more transfer chambers, accessible to at least one of the one or more wafer-handling robots, and configured to facilitate performance of a cooling-and-treatment process on the substrate having the photo patterned extreme ultraviolet photoresist layer, in which: the cooling-and-treatment process includes cooling the substrate having the photopatterned extreme ultraviolet photoresist layer to a temperature in a first temperature range, flowing one or more of oxygen gas, carbon dioxide gas, and watervapor-containing gas into contact with the substrate having the photopatterned extreme ultraviolet photoresist layer, and then cooling the substrate having the photopatterned extreme ultraviolet photoresist layer to a temperature in a second temperature range, the first temperature range is between 50°C to 200°C, and the second temperature range is 40°C or lower.

[0301] Implementation 49: The semiconductor processing system of implementation48, in which at least one of the one or more dry-development processes includes flowing one or more process gases across the substrate having the photopatterned extreme ultraviolet photoresist layer to remove portions of the photopatterned extreme ultraviolet photoresist layer.

[0302] I mplementation 50: The semiconductor processing system of implementation49, in which the at least one of the dry-development processes is performed with the substrate having the photopatterned extreme ultraviolet photoresist layer held at a temperature of 40°C or lower.

[0303] Implementation 51: The semiconductor processing system of implementation50, in which the at least one of the dry-development processes is performed with the substrate having the photopatterned extreme ultraviolet photoresist layer held at a temperature of 20°C or lower.

[0304] I mplementation 52: The semiconductor processing system of any of implementations 48 through 51, in which the post-exposure bake process includes heating the substrate having the photopatterned extreme ultraviolet photoresist layer to a temperature greater than or equal to a third temperature of at least 130°C for a first time period.

[0305] I mplementation 53: The semiconductor processing system of implementation 52, in which the third temperature is at least 200°C.

[0306] I mplementation 54: The semiconductor processing system of implementation 52, in which the third temperature is at least 250°C.

[0307] Implementation 55: The semiconductor processing system of any of implementations 48 through 51, further including a controller configured to control the one or more wafer-handling robots and the cooling-and-treatment chamber and to cause:a) one of the one or more wafer-handling robots to place a first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer in the post-exposure bake chamber, b) the post-exposure bake chamber to perform the post-exposure bake process on the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer after (a), c) one of the one or more wafer-handling robots to move, after (b), the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer from the postexposure bake chamber to the cooling-and-treatment chamber, d) the cooling-and-treatment chamber to perform, after (c), a cooling-and-treatment process on the first instance of the substrate having the photo patterned extreme ultraviolet photoresist layer, and e) one of the one or more wafer-handling robots to move, after (d), the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer from the cooling- and-treatment chamber to the dry-development chamber.

[0308] I mplementation 56: The semiconductor processing system of implementation 55, further including a loadlock connected with the one or more transfer chambers and accessible to one of the one or more wafer-handling robots, in which: the loadlock is configured to facilitate transfer of the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer between the one or more transfer chambers and an atmospheric pressure environment, and the controller is configured to perform (a) through (e) without placing the first instance of the substrate having the photo patterned extreme ultraviolet photoresist layer in the loadlock.

[0309] Implementation 57: The semiconductor processing system of implementation 55, further including an oxygen source connected with the cooling-and-treatment chamber, in which the controller is further configured to cause oxygen from the oxygen source to flow into the cooling-and-treatment chamber during at least part of (d).

[0310] I mplementation 58: The semiconductor processing system of implementation 57, further including a vaporizer and a water source, in which the controller is further configured to cause: water vapor generated by the vaporizer using water from the water source to flow into the cooling-and-treatment chamber during at least part of (d).

[0311] Implementation 59: The semiconductor processing system of implementation57, further including a carbon dioxide source, in which the controller is further configured to cause carbon dioxide from the carbon dioxide source to flow into the cooling-and-treatment chamber during at least part of (d).

[0312] I mplementation 60: The semiconductor processing system of implementation55, in which: the cooling-and-treatment chamber includes a temperature-controlled wafer support configured to receive the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer when the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer is moved into the cooling-and-treatment chamber by one of the one or more wafer-handling robots, and the controller is configured to cause the temperature-controlled wafer support to, while the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer is supported by the temperature-controlled wafer support: i) maintain a temperature in the first temperature range during at least part of(d), and ii) maintain a temperature in the second temperature range during at least part of (d) and after (i).

[0313] I mplementation 61: The semiconductor processing system of implementation60, in which the first temperature range is between 75°C and 200°C.

[0314] I mplementation 62: The semiconductor processing system of implementation61, in which the first temperature range is between 95°C and 200°C.

[0315] Implementation 63: The semiconductor processing system of implementation60, in which the second temperature range is between -10°C and 25°C.

[0316] Implementation 64: The semiconductor processing system of implementation63, in which the second temperature range is between -10°C and 20°C.

[0317] I mplementation 65: The semiconductor processing system of implementation60, further including: a plurality of reservoirs, each reservoir associated with a corresponding temperature control system configured to maintain a heat transfer fluid, when present in that reservoir, within a corresponding temperature range, in which the plurality of reservoirs includes at least:a first reservoir associated with a first temperature control system configured to maintain the heat transfer fluid, when present in the first reservoir, within the first temperature range, and a second reservoir associated with a second temperature control system configured to maintain the heat transfer fluid, when present in the second reservoir, within the second temperature range; one or more coolant control valves, one or more fluid transfer lines, and one or more pumps, in which the one or more coolant control valves and the one or more pumps are configured to be controllable so as to cause the heat transfer fluid contained within each reservoir, when present in that reservoir, to selectively flow into an inlet of the wafer support; and a controller configured to: control the one or more coolant control valves and the one or more pumps to cause the heat transfer fluid, when present in the first reservoir and the second reservoir, to flow from the first reservoir to the inlet during at least part of (i) and to flow from the second reservoir to the inlet during at least part of (ii).

[0318] Implementation 66: A method including:(a) introducing a substrate having a photopatterned extreme ultraviolet photoresist layer into one or more transfer chambers housing one or more wafer-handling robots;(b) causing one of the one or more wafer-handling robots to transfer the substrate having the photopatterned extreme ultraviolet photoresist layer into a post-exposure bake chamber connected with the one or more transfer chambers;(c) causing the substrate having the photopatterned extreme ultraviolet photoresist layer to undergo a post-exposure bake process in the post-exposure bake chamber;(d) causing one of the one or more wafer-handling robots to transfer the substrate having the photopatterned extreme ultraviolet photoresist layer from the post-exposure bake chamberto a cooling-and-treatment chamber connected with the one or more transfer chambers;(e) causing the substrate having the photopatterned extreme ultraviolet photoresist layer to undergo a cooling and treatment process in the cooling-and-treatment chamber;(f) causing one of the one or more wafer-handling robots to transfer the substrate having the photopatterned extreme ultraviolet photoresist layer from the cooling-and-treatment chamber to a dry-development chamber connected with the one or more transfer chambers; and(g) causing the substrate having the photopatterned extreme ultraviolet photoresist layer to undergo one or more dry-development processes in the dry-development chamber, in which: the cooling-and-treatment process includes cooling the substrate having the photopatterned extreme ultraviolet photoresist layer to a temperature in a first temperature range, flowing one or more of oxygen gas, carbon dioxide gas, and water vapor-containing gas into contact with the substrate having the photopatterned extreme ultraviolet photoresist layer, and then cooling the substrate having the photopatterned extreme ultraviolet photoresist layer to a temperature in a second temperature range, the first temperature range is between 50°C to 200°C, and the second temperature range is 40°C or lower.

[0319] Implementation 67: The method of implementation 66, in which at least one of the one or more dry-development processes includes flowing one or more process gases across the substrate having the photopatterned extreme ultraviolet photoresist layer to remove portions of the photopatterned extreme ultraviolet photoresist layer.

[0320] I mplementation 68: The method of implementation 67, in which the at least one of the dry-development processes is performed with the substrate having the photopatterned extreme ultraviolet photoresist layer held at a temperature of 40°C or lower.

[0321] I mplementation 69: The method of implementation 68, in which the at least one of the dry-development processes is performed with the substrate having the photopatterned extreme ultraviolet photoresist layer held at a temperature of 20°C or lower.

[0322] I mplementation 70: The method of implementation 66, in which the postexposure bake process includes heating the substrate having the photopatterned extreme ultraviolet photoresist layer to a temperature greater than or equal to a third temperature of at least 130°C for a first time period.

[0323] I mplementation 71: The method of implementation 70, in which the third temperature is at least 200°C.

[0324] I mplementation 72: The method of implementation 70, in which the third temperature is at least 250°C.

[0325] Implementation 73: The method of implementation 66, further including:(h) causing the substrate having the photopatterned extreme ultraviolet photoresist layer to be removed from the dry-development chamber after (g); and(i) causing the substrate having the photopatterned extreme ultraviolet photoresist layer to be removed from the one or more transfer chambers after (h).

[0326] Implementation 74: The method of implementation 73, in which a loadlock is connected with the one or more transfer chambers and is accessible to one of the one or more wafer-handling robots, in which: the loadlock is configured to facilitate removal of the substrate having the photopatterned extreme ultraviolet photoresist layer from the one or more transfer chambers and into an atmospheric pressure environment, and the method includes performing (a) through (h) without placing the substrate having the photopatterned extreme ultraviolet photoresist layer in the loadlock.

[0327] Implementation 75: The method of implementation 73, further including causing oxygen to flow into the cooling-and-treatment chamber during at least part of (e).

[0328] Implementation 76: The method of implementation 75, further including causing water vapor to flow into the cooling-and-treatment chamber during at least part of (e).

[0329] Implementation 77: The method of implementation 75, further including causing carbon dioxide to flow into the cooling-and-treatment chamber during at least part of (e).

[0330] Implementation 78: The method of implementation 73, in which: the cooling-and-treatment chamber includes a temperature-controlled wafer support, and the method further includes: causing the substrate having the photopatterned extreme ultraviolet photoresist layer to be placed on the temperature-controlled wafer support; and causing the temperature-controlled wafer support to, while the substrate having the photopatterned extreme ultraviolet photoresist layer is supported by the temperature-controlled wafer support:1) maintain a temperature in the first temperature range during at least part of (e), and2) maintain a temperature in the second temperature range during at least part of (e) and after (1).

[0331] I mplementation 79: The method of implementation 78, in which the first temperature range is between 75°C and 200°C.

[0332] I mplementation 80: The method of implementation 79, in which the first temperature range is between 95°C and 200°C.

[0333] I mplementation 81: The method of implementation 78, in which the second temperature range is between -10°C and 25°C.

[0334] Implementation 82: The method of implementation 81, in which the second temperature range is between -10°C and 20°C.

[0335] I mplementation 83: The method of implementation 78, further including: causing a heat transfer fluid to flow from a first reservoir to an inlet of the temperature- controlled wafer support during at least part of (1); and causing a heat transfer fluid to flow from a second reservoir to the inlet of the temperature-controlled wafer support during at least part of (2), in which: the first reservoir is associated with a first temperature control system configured to maintain the heat transfer fluid present in the first reservoir within the first temperature range, and the second reservoir is associated with a second temperature control system configured to maintain the heat transfer fluid present in the second reservoir within the second temperature range.

[0336] I mplementation 84: A semiconductor processing system including: an equipment front-end module (EFEM), a post-exposure bake chamber configured to facilitate performance of a post-exposure bake process on a substrate having a photopatterned extreme ultraviolet photoresist layer; a dry-development chamber configured to facilitate performance of one or more drydevelopment processes on the substrate having the photo patterned extreme ultraviolet photoresist layer; and a cooling station positioned in the EFEM, in which: the post-exposure bake chamber is configured to be at a sub-atmospheric pressure while the post-exposure bake process is being performed, the dry-development chamber is configured to be at a sub-atmospheric pressure while the one or more dry development processes are being performed,the EFEM is configured to receive a front-opening unified pod (FOUR) containing a stack of substrates, and the semiconductor processing system is configured to: cause each substrate in the stack of substates to be removed from theFOUR and introduced into the post-exposure bake chamber, cause the post-exposure bake process to be performed on each substrate, cause each substrate to be returned to the EFEM after the post-exposure bake process is performed on that substrate, cause each substrate to remain in the EFEM for a determined period of time to cool to a lower temperature, cause each substrate to be introduced into the dry development chamber, cause the one or more dry development processes to be performed on each substrate after that substrate has cooled to the lower temperature in the EFEM and has been introduced into the dry development chamber, and cause each substrate to be removed from the dry development chamber after the one or more dry development processes have been performed on that substrate.

Claims

CLAIMSWhat is claimed is:

1. An apparatus comprising: a temperature-controllable wafer support, the wafer support having: a body having a first side and a second side facing in an opposite direction from the first side; a first plenum located within the body, extending radially outward from one or more inlet ports located near a centerline of the body, bounded on one side by a first surface, and bounded on another side by a second surface that faces towards the first surface; a second plenum located within the body, extending radially outward from one or more outlet ports located near the centerline of the body, bounded on one side by a third surface and bounded on another side by a fourth surface that faces towards the third surface; a plurality of inter-plenum passages distributed along an outer perimeter of the first plenum, each inter-plenum passage located within the body and spanning between the first plenum and the second plenum; an inlet fluidically connected with the one or more inlet ports via one or more inlet passages located at least partially within the body; and an outlet fluidically connected with the one or more outlet ports via one or more outlet passages located at least partially within the body, wherein the first plenum, the plurality of inter-plenum passages, and the second plenum are all fluidically interposed between the inlet and the outlet.

2. The apparatus of claim 1, wherein: the body comprises a plurality of layer parts that are positioned in a stacked arrangement, each layer part joined to the adjacent layer part or adjacent layer parts via a corresponding diffusion bond or corresponding diffusion bonds, the plurality of layer parts including at least a first layer part, a second layer part, and a third layer part,the first surface is provided by the first layer part and the second surface is provided by the second layer part, the third surface is provided by the second layer part and the fourth surface is provided by the fourth layer part the one or more inlet passages are at least partially defined by one or more surfaces of the second layer part and one or more surfaces of the third layer part, and the one or more outlet passages are at least partially defined by one or more surfaces of the second layer part and one or more surfaces of the third layer part.

3. The apparatus of claim 2, wherein: the one or more inlet passages are also at least partially defined by one or more surfaces of the first layer part and one or more surfaces of the second layer part, and the one or more outlet passages are also at least partially defined by one or more surfaces of the first layer part and one or more surfaces of the second layer part.

4. The apparatus of claim 3, wherein the second layer part includes a first through-hole that defines part of the one or more inlet passages and a second through-hole that defines part of the one or more outlet passages.

5. The apparatus of claim 4, wherein the first through-hole and the second through-hole extend along corresponding centerlines that form respective acute angles with respect to the first surface.

6. The apparatus of claim 5, wherein the inlet and the outlet are located at positions offset from, and in a direction perpendicular to, a reference plane that is parallel to the first side and that intersects either the first plenum or the second plenum.

7. The apparatus of claim 2, wherein: the one or more inlet passages include a first inlet passage having a first portion that extends along the centerline of the body, the one or more outlet passages include a first outlet passage having a first portion that extends at least partially around the first portion of the first inlet passage, and the first portion of the first outlet passage encircles the first portion of the first inlet passage.

8. The apparatus of claim 2, further comprising a ring of baffle wall segments and a ring of inlet baffle ports encircling the one or more inlet ports, each baffle wall segment extending from the first surface to the second surface and each inlet baffle port interposed between at least portions of two adjacent ones of the baffle wall segments.

9. A semiconductor processing system comprising: one or more transfer chambers housing one or more wafer-handling robots; a dry-development chamber connected with the one or more transfer chambers, accessible to at least one of the one or more wafer-handling robots, and configured to facilitate performance of one or more dry-development processes on a substrate having a photopatterned extreme ultraviolet photoresist layer; a post-exposure bake chamber connected with the one or more transfer chambers, accessible to at least one of the one or more wafer-handling robots, and configured to facilitate performance of a post-exposure bake process on the substrate having the photopatterned extreme ultraviolet photoresist layer; and a cooling-and-treatment chamber connected with the one or more transfer chambers, accessible to at least one of the one or more wafer-handling robots, and configured to facilitate performance of a cooling-and-treatment process on the substrate having the photo patterned extreme ultraviolet photoresist layer, wherein: the cooling-and-treatment process includes cooling the substrate having the photopatterned extreme ultraviolet photoresist layer to a temperature in a firsttemperature range, flowing one or more of oxygen gas, carbon dioxide gas, and water vapor-containing gas into contact with the substrate having the photopatterned extreme ultraviolet photoresist layer, and then cooling the substrate having the photopatterned extreme ultraviolet photoresist layer to a temperature in a second temperature range, the first temperature range is between 50°C to 200°C, and the second temperature range is 40°C or lower.

10. The semiconductor processing system of claim 9, wherein at least one of the one or more dry-development processes includes flowing one or more process gases across the substrate having the photopatterned extreme ultraviolet photoresist layer to remove portions of the photopatterned extreme ultraviolet photoresist layer.

11. The semiconductor processing system of claim 10, wherein the at least one of the drydevelopment processes is performed with the substrate having the photopatterned extreme ultraviolet photoresist layer held at a temperature of 40°C or lower.

12. The semiconductor processing system of claim 11, wherein the at least one of the drydevelopment processes is performed with the substrate having the photopatterned extreme ultraviolet photoresist layer held at a temperature of 20°C or lower.

13. The semiconductor processing system of any of claims 9 through 12, wherein the postexposure bake process includes heating the substrate having the photopatterned extreme ultraviolet photoresist layer to a temperature greater than or equal to a third temperature of at least 130°C for a first time period.

14. The semiconductor processing system of claim 13, wherein the third temperature is at least 200°C.

15. The semiconductor processing system of claim 13, wherein the third temperature is at least 250°C.

16. The semiconductor processing system of any of claims 9 through 12, further comprising a controller configured to control the one or more wafer-handling robots and the cooling-and- treatment chamber and to cause: a) one of the one or more wafer-handling robots to place a first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer in the post-exposure bake chamber, b) the post-exposure bake chamber to perform the post-exposure bake process on the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer after (a), c) one of the one or more wafer-handling robots to move, after (b), the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer from the postexposure bake chamber to the cooling-and-treatment chamber, d) the cooling-and-treatment chamber to perform, after (c), a cooling-and-treatment process on the first instance of the substrate having the photo patterned extreme ultraviolet photoresist layer, and e) one of the one or more wafer-handling robots to move, after (d), the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer from the cooling- and-treatment chamber to the dry-development chamber.

17. The semiconductor processing system of claim 16, further comprising a loadlock connected with the one or more transfer chambers and accessible to one of the one or more wafer-handling robots, wherein: the loadlock is configured to facilitate transfer of the first instance of the substrate having the photopatterned extreme ultraviolet photoresist layer between the one or more transfer chambers and an atmospheric pressure environment, andthe controller is configured to perform (a) through (e) without placing the first instance of the substrate having the photo patterned extreme ultraviolet photoresist layer in the loadlock.

18. The semiconductor processing system of claim 16, further comprising an oxygen source connected with the cooling-and-treatment chamber, wherein the controller is further configured to cause oxygen from the oxygen source to flow into the cooling-and-treatment chamber during at least part of (d).

19. The semiconductor processing system of claim 18, further comprising a vaporizer and a water source, wherein the controller is further configured to cause: water vapor generated by the vaporizer using water from the water source to flow into the cooling-and-treatment chamber during at least part of (d ).

20. A semiconductor processing system comprising: an equipment front-end module (EFEM), a post-exposure bake chamber configured to facilitate performance of a post-exposure bake process on a substrate having a photopatterned extreme ultraviolet photoresist layer; a dry-development chamber configured to facilitate performance of one or more drydevelopment processes on the substrate having the photo patterned extreme ultraviolet photoresist layer; and a cooling station positioned in the EFEM, wherein: the post-exposure bake chamber is configured to be at a sub-atmospheric pressure while the post-exposure bake process is being performed, the dry-development chamber is configured to be at a sub-atmospheric pressure while the one or more dry development processes are being performed, the EFEM is configured to receive a front-opening unified pod (FOUR) containing a stack of substrates, andthe semiconductor processing system is configured to: cause each substrate in the stack of substates to be removed from the FOUP and introduced into the post-exposure bake chamber, cause the post-exposure bake process to be performed on each substrate, cause each substrate to be returned to the EFEM after the post-exposure bake process is performed on that substrate, cause each substrate to remain in the EFEM for a determined period of time to cool to a lower temperature, cause each substrate to be introduced into the dry development chamber, cause the one or more dry development processes to be performed on each substrate after that substrate has cooled to the lower temperature in the EFEM and has been introduced into the dry development chamber, and cause each substrate to be removed from the dry development chamber after the one or more dry development processes have been performed on that substrate.

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