Ldmos device and preparation method therefor

Abstract

Provided in the present application are an LDMOS device and a preparation method therefor. A substrate has a channel region and a drift region, a drain region is provided in the drift region, and a trench, which has a first field plate region, a second field plate region and a third field plate region connected in sequence, is provided between the drain region and the channel region; a first field oxide is located in the first field plate region, a second field oxide is located in the second field plate region, and a third field oxide is located in the third field plate region, with the thicknesses of the third field oxide and the first field oxide both being greater than the thickness of the second field oxide, and the height of the first field oxide being less than or equal to the distance between the bottom of the trench and the channel region; in the direction from the bottom of the trench to the opening of the trench, a gate oxide layer is disposed on the first field oxide and is located in the trench; gate polycrystalline silicon fills the space above the first field oxide and the second field oxide in the trench, and the surfaces of the gate polycrystalline silicon and the third field oxide away from the trench are flush with the opening of the trench; and the gate oxide layer and the third field oxide are disposed on the side surfaces of the gate polycrystalline silicon, so as to reduce the transverse dimensions of the device and improve voltage resistance.

Description

A LDMOS device and its preparation method Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an LDMOS device and a method for manufacturing the same. Background Art

[0002] The BCD process is a process for fabricating bipolar junction transistors (BJTs), complementary metal oxide semiconductors (CMOS), and diffused metal oxide semiconductors (DMOS) on the same chip. In the fabrication of laterally diffused metal oxide semiconductor (LDMOS) transistors, field plates are typically used to reduce the peak surface electric field and improve withstand voltage. The field plates are typically formed by extending the gate polysilicon across the field oxide layer. However, this LDMOS structure has large lateral dimensions, which prevents efficient use of chip area. Summary of the Invention

[0003] In view of this, the present application provides an LDMOS device and a method for manufacturing the same, so as to reduce the lateral size of the LDMOS device and improve the voltage resistance of the LDMOS device.

[0004] The present application provides an LDMOS device, comprising:

[0005] A substrate having a channel region and a drift region disposed on one side of the channel region, wherein a drain region is disposed in the drift region, a trench is disposed between the drain region and the channel region, and the trench is spaced apart from the drain region, the trench having a first field plate region, a second field plate region, and a third field plate region connected in sequence, and a direction from the bottom of the trench toward the notch of the trench is a first direction;

[0006] a first field oxygen, a second field oxygen, and a third field oxygen, wherein the first field oxygen, the second field oxygen, and the third field oxygen are sequentially connected and filled in the trench, the first field oxygen is located in the first field plate region, the second field oxygen is located in the second field plate region, and the third field oxygen is located in the third field plate region, wherein the thickness of the first field oxygen and the thickness of the third field oxygen are both greater than the thickness of the second field oxygen, the height of the first field oxygen is less than and equal to the distance from the bottom of the trench to the channel region, and the side of the third field oxygen away from the trench is flush with the notch of the trench;

[0007] a gate oxide layer, wherein in the first direction, the gate oxide layer is disposed on the first field oxide and is located in the trench;

[0008] The gate polysilicon is filled on the first field oxygen and the second field oxygen in the trench. The side of the gate polysilicon away from the trench is flush with the notch of the trench. The gate oxide layer and the third field oxygen are provided on the side of the gate polysilicon.

[0009] In some embodiments, the thickness of the first field oxide decreases gradually in the first direction.

[0010] In some embodiments, the first field oxygen has an arc shape.

[0011] In some embodiments, the gate oxide layer is disposed in contact with the channel region.

[0012] In some embodiments, a surface of the gate oxide layer away from the bottom of the trench is flush with a notch of the trench.

[0013] In some embodiments, the thickness of the gate oxide layer is

[0014] In some embodiments, the LDMOS device further includes a dielectric layer, and the dielectric layer is disposed on the substrate, the gate polysilicon, and the gate oxide layer.

[0015] The present application also provides a method for preparing an LDMOS device, which is used to prepare the LDMOS device described above, comprising:

[0016] providing a substrate having a drift region;

[0017] Performing patterning on the substrate to form a trench in the drift region, wherein the trench has a first field plate region, a second field plate region, and a third field plate region connected in sequence, and a direction from the bottom of the trench toward the notch of the trench is a first direction;

[0018] Disposing an oxide material layer on the substrate, wherein the oxide material layer extends into the trench;

[0019] performing a thinning process on the oxide material layer located on the second field plate region to form a second field oxide;

[0020] performing a dry etching process on the oxide material layer to remove a portion of the oxide material layer located on the first field plate region and the oxide material layer located on the substrate near the first field plate region to form a first field oxide located in the first field plate region;

[0021] forming a gate oxide layer on the first field oxide in the first direction;

[0022] Providing a polysilicon layer on the substrate, the gate oxide layer, and the oxide material layer, and performing patterning to form a gate polysilicon layer flush with the notch of the trench and a third field oxygen layer, wherein the second field oxygen layer is located in the second field plate region, the third field oxygen layer is located in the third field plate region, and a side of the third field oxygen layer away from the trench is flush with the notch of the trench;

[0023] Ions are implanted into the substrate to form a channel region and a drain region, wherein the trench is located between the channel region and the drain region, and the trench is spaced apart from the drain region.

[0024] The thickness of the first field oxygen and the thickness of the third field oxygen are both greater than the thickness of the second field oxygen, and the height of the first field oxygen is less than and equal to the distance between the bottom of the trench and the channel region.

[0025] In some embodiments, after thinning the oxide material layer on the second field plate region to form the second field oxide, and before dry etching the oxide material layer to remove a portion of the oxide material layer on the first field plate region and the oxide material layer on the substrate near the first field plate region to form the first field oxide in the first field plate region, the method further includes:

[0026] The oxide material layer is wet-treated.

[0027] In some embodiments, the thickness of the first field oxide decreases gradually in the first direction.

[0028] The present application provides an LDMOS device and a preparation method thereof, wherein the LDMOS device includes a substrate, a first field oxide, a second field oxide, a third field oxide, a gate oxide layer, and a gate polysilicon. The substrate has a channel region and a drift region arranged on one side of the channel region. A drain region is arranged in the drift region. A trench is arranged between the drain region and the channel region, and the trench is spaced apart from the drain region. The trench has a first field plate region, a second field plate region, and a third field plate region connected in sequence. The first field oxide, the second field oxide, and the third field oxide are connected in sequence and filled in the trench. The first field oxide is located in the first field plate region, and the second field oxide is located in the third field plate region. The second field oxygen is located in the second field plate area, and the third field oxygen is located in the third field plate area, wherein the thickness of the first field oxygen and the thickness of the third field oxygen are both greater than the thickness of the second field oxygen, the height of the first field oxygen is less than and equal to the distance between the bottom of the trench and the channel area, and the side of the third field oxygen away from the trench is flush with the groove of the trench; the gate oxide layer is filled in the trench and is located on the first field oxygen; the gate polysilicon is filled on the first field oxygen and the second field oxygen in the trench, and the side of the gate polysilicon away from the trench is flush with the groove of the trench, and the gate oxide layer and the third field oxygen are provided on the side of the gate polysilicon. The first field oxygen, the second field oxygen, the third field oxygen, the gate polysilicon, and the gate oxide layer are all arranged in the trench, and the side of the gate polysilicon away from the trench is flush with the notch of the trench, so as to reduce the lateral size of the LDMOS device. At the same time, the thickness of the first field oxygen and the thickness of the third field oxygen are set to be greater than the thickness of the second field oxygen, the height of the first field oxygen is set to be less than and equal to the distance from the bottom of the trench to the channel region, and the side of the third field oxygen away from the trench is flush with the notch of the trench, so that there are three independent field plates in the trench, which can respectively adjust the electric field and current flow path on the left side, the bottom of the trench, and the right side of the trench, thereby improving the breakdown voltage of the LDMOS device, that is, improving the voltage resistance of the LDMOS device. In addition, the current can be moved close to the surface of the gate polysilicon, resulting in a reduction in specific on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0030] FIG1 is a schematic diagram of the cross-sectional structure of an LDMOS device provided in the present application;

[0031] FIG2 is a schematic diagram of the physical structure of a simulation experiment (TCAD) of an LDMOS device provided by the present application;

[0032] FIG3 is a schematic diagram of the electric field intensity distribution effect of the LDMOS device provided in this application;

[0033] FIG4 is a data diagram of the electric field intensity of the LDMOS device in FIG3 along the tangent line a;

[0034] FIG5 is a schematic diagram of the electric field intensity distribution effect of a conventional LDMOS device;

[0035] FIG6 is a data diagram of the electric field intensity of the LDMOS device in FIG5 along the tangent line b;

[0036] FIG7 is a schematic diagram of the current density distribution effect of the LDMOS device provided in this application;

[0037] FIG8 is a schematic diagram of the current density distribution effect of an existing LDMOS device;

[0038] FIG9 is a schematic flow chart of a method for preparing an LDMOS device provided in the present application;

[0039] 10 to 18 are schematic flow charts of the method for manufacturing an LDMOS device provided in this application.

[0040] Figure numerals: 10, LDMOS device; 100, substrate; 110, channel region; 111, source region; 112, body region; 120, drift region; 121, drain region; 130, trench; 131, first field plate region; 132, second field plate region; 133, third field plate region; 200, first field oxygen; 201, oxide material layer; 202, photoresist layer; 300, second field oxygen; 400, third field oxygen; 500, gate oxide layer; 600, gate polysilicon; 700, dielectric layer; 800, first connection portion; 900, second connection portion; 1000, third connection portion. DETAILED DESCRIPTION

[0041] The following, in conjunction with the accompanying drawings, clearly and completely describes the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0042] The present application provides an LDMOS device, which includes a substrate, a first field oxide, a second field oxide, a third field oxide, a gate oxide layer, and a gate polysilicon. The substrate has a channel region and a drift region arranged on one side of the channel region. A drain region is arranged in the drift region. A trench is arranged between the drain region and the channel region, and the trench is spaced apart from the drain region. The trench has a first field plate region, a second field plate region, and a third field plate region connected in sequence. The first field oxide, the second field oxide, and the third field oxide are connected in sequence and filled in the trench. The direction of the bottom of the trench toward the notch of the trench is a first direction. The first field oxide is located in the first field region. plate area, the second field oxygen is located in the second field plate area, and the third field oxygen is located in the third field plate area, wherein the thickness of the first field oxygen and the thickness of the third field oxygen are both greater than the thickness of the second field oxygen, the height of the first field oxygen is less than and equal to the distance between the bottom of the trench and the channel area, and a side of the third field oxygen away from the trench is flush with the notch of the trench; in the first direction, the gate oxide layer is arranged on the first field oxygen and is located in the trench; the gate polysilicon is filled on the first field oxygen and the second field oxygen in the trench, a side of the gate polysilicon away from the trench is flush with the notch of the trench, and the side of the gate polysilicon is provided with a gate oxide layer and a third field oxygen.

[0043] In the present application, the first field oxygen, the second field oxygen, the third field oxygen, the gate polysilicon, and the gate oxide layer are all arranged in the trench, and the side of the gate polysilicon away from the trench is flush with the notch of the trench, so as to reduce the lateral size of the LDMOS device. At the same time, the thickness of the first field oxygen and the thickness of the third field oxygen are set to be greater than the thickness of the second field oxygen, the height of the first field oxygen is set to be less than and equal to the distance between the bottom of the trench and the channel region, and the side of the third field oxygen away from the trench is flush with the notch of the trench, so that there are three independent field plates in the trench, which can respectively adjust the electric field and current flow path on the left side, the bottom of the trench, and the right side of the trench, thereby improving the breakdown voltage of the LDMOS device, that is, improving the voltage resistance of the LDMOS device. In addition, the current can be moved close to the surface of the gate polysilicon, resulting in a reduction in the specific on-resistance.

[0044] Please refer to Figure 1, which is a schematic diagram of the cross-sectional structure of the LDMOS device provided in this application. It should be noted that y in Figure 1 represents the current path. This application provides an LDMOS device 10, which includes a substrate 100, a first field oxide 200, a second field oxide 300, a third field oxide 400, a gate oxide layer 500, a gate polysilicon 600, a dielectric layer 700, a metal silicide, a first connecting portion 800, a second connecting portion 900, and a third connecting portion 1000. A detailed description is as follows.

[0045] The substrate 100 is a P-type substrate 100, and the substrate 100 has a channel region 110 and a drift region 120 arranged on one side of the channel region 110. A drain region 121 is arranged in the drift region 120, and the drain region 121 is spaced apart from the channel region 110. A connected source region 111 and a body region 112 are provided in the channel region 110, and the source region 111 is located on a side of the body region 112 close to the drain region 121. A trench 130 is provided between the drain region 121 and the channel region 110, and the trench 130 is spaced apart from the drain region 121 and is in contact with the channel region 110. The trench 130 has a first field plate region 131, a second field plate region 132, and a third field plate region 133 connected in sequence. The first field plate region 131 is located on a side of the second field plate region 132 close to the source region 111, and the direction of the bottom of the trench 130 toward the notch of the trench 130 is the first direction. Optionally, the characteristic dimension (CD) of the trench 130 is 0.5-3 μm, the depth of the trench 130 is 0.5-5 μm, and the angle of the trench 130 is 70-90 degrees. Optionally, an epitaxial layer may be provided on the substrate 100, and the thickness of the epitaxial layer may be 3 μm, 5 μm, 8 μm, 10 μm, or 12 μm.

[0046] The first field oxygen 200, the second field oxygen 300, and the third field oxygen 400 are sequentially connected and filled in the trench 130. The first field oxygen 200 is located in the first field plate region 131, the second field oxygen 300 is located in the second field plate region 132, and the third field oxygen 400 is located in the third field plate region 133. The thickness d1 of the first field oxygen 200 and the thickness d1 of the third field oxygen 400 are both greater than the thickness d2 of the second field oxygen 300. The height h1 of the first field oxygen 200 is less than and equal to the distance t between the bottom of the trench 130 and the channel region 110. The surface of the third field oxygen 400 away from the trench 130 is flush with the notch of the trench 130. h2 is the height of the third field oxygen 400, that is, the height h1 of the first field oxygen 200 is less than the height h2 of the third field oxygen 400. In other words, the field oxygen, the gate oxide layer 500, and the gate polysilicon 600 are all filled in the trench 130.

[0047] In one embodiment, the thickness d1 of the first field oxide 200 decreases in the first direction, i.e., the thickness d1 of the first field oxide 200 close to the gate oxide layer 500 is smaller, and the thickness d1 of the first field oxide 200 away from the gate oxide layer 500 is larger. The thickness d1 of the first field oxide 200 away from the gate oxide layer 500 is equal to the thickness d3 of the third field oxide 400, i.e., the thickness d1 of the first field oxide 200 at the bottom of the trench 130 is equal to the thickness d3 of the third field oxide 400.

[0048] In one embodiment, the first field oxide 200 is in an arc shape.

[0049] In the first direction, the gate oxide layer 500 is disposed on the first field oxide 200 and is located in the trench 130. Optionally, the side of the gate oxide layer 500 away from the bottom of the trench 130 is flush with the notch of the trench 130. Furthermore, in the direction from the first field oxide 200 toward the third field oxide 400, the thickness of the gate oxide layer 500 is

[0050] The gate polysilicon 600 is filled on the first field oxide 200 and the second field oxide 300 in the trench 130. The side of the gate polysilicon 600 away from the trench 130 is flush with the notch of the trench 130. The side of the gate polysilicon 600 is provided with a gate oxide layer 500 and a third field oxide 400. Optionally, in the direction from the dielectric layer 700 toward the substrate 100.

[0051] Metal silicide is disposed on the channel region 110, the source region 111, the body region 112, the gate polysilicon 600, and the drain region 121. A dielectric layer 700 is disposed on the metal silicide, the gate oxide layer 500, the third field oxide 400, and the drift region 120. The dielectric layer 700 has a plurality of through-holes that penetrate the dielectric layer 700 and expose the metal silicide. A first connecting portion 800, a second connecting portion 900, and a third connecting portion 1000 are alternately disposed on the dielectric layer 700. The first connecting portion 800 is filled in the through-holes located on the source region 111 and the body region 112 to connect the body region 112 to the source region 111. The second connecting portion 900 is filled in the through-hole located on the gate polysilicon 600. The third connecting portion 1000 is filled in the through-hole located on the drain region 121.

[0052] Please refer to Table 1, which shows the performance parameters of device 1 and device 2.

[0053] Table 1

[0054] It should be noted that device 1 in Table 1 is the trench gate LDMOS device 10 provided in this application, device 2 is the existing planar gate LDMOS device, Vtgm is the turn-on voltage under the maximum transconductance method in the linear region, Idlin is the drain current measured when the device operates in the linear region, Ron,sp ratio is the on-resistance, BV is the breakdown voltage, pitch is the lateral dimension of the LDMOS device 10, and FOM is the figure of merit of the device.

[0055] Please refer to Figures 2 to 8. Figure 2 is a schematic diagram of the physical structure of the simulation experiment (TCAD) of the LDMOS device 10 provided in the present application; Figure 3 is a schematic diagram of the electric field intensity distribution effect of the LDMOS device 10 provided in the present application; Figure 4 is a data diagram of the electric field intensity of the LDMOS device 10 along the tangent line a in Figure 3; Figure 5 is a schematic diagram of the electric field intensity distribution effect of the existing LDMOS device 10; Figure 6 is a data diagram of the electric field intensity of the LDMOS device 10 along the tangent line b in Figure 5; Figure 7 is a schematic diagram of the current density distribution effect of the LDMOS device 10 provided in the present application; and Figure 8 is a schematic diagram of the current density distribution effect of the existing LDMOS device 10.

[0056] It can be seen from this that in the LDMOS device 10 provided in the present application, its breakdown voltage value BV and device figure of merit FOM are both greater than the breakdown voltage value BV and device figure of merit FOM of the existing LDMOS device, and the lateral dimension Pitch of the LDMOS device 10 of the present application is also smaller than the lateral dimension Pitch of the existing LDMOS device, that is, the LDMOS device 10 provided in the present application has a high voltage resistance and a small lateral dimension, that is, while improving the voltage resistance of the LDMOS device 10, the integration of the LDMOS device 10 can be improved.

[0057] It can be seen from this that three independent field plates are provided in the groove 130 of the LDMOS device 10 provided in the present application to regulate the electric field and the current path respectively, so that the electric field distribution on the left side of the groove 130, the bottom of the groove 130, and the right side of the groove 130 is more uniform, so as to effectively improve the electric field distribution of the drift region 120, so that it has a higher breakdown voltage, that is, multiple independent field plates are used to regulate the electric field and current density respectively, thereby improving the voltage resistance of the LDMOS device 10, and because the current moves close to the surface of the gate polysilicon 600, the specific on-resistance is reduced.

[0058] In the present application, the first field oxide 200, the second field oxide 300, the third field oxide 400, the gate polysilicon 600 and the gate oxide layer 500 are all arranged in the trench 130 and the side of the gate polysilicon 600 away from the trench 130 is flush with the notch of the trench 130, so as to reduce the lateral size of the LDMOS device 10. At the same time, the thickness d1 of the first field oxide 200 and the thickness d3 of the third field oxide 400 are set to be greater than the thickness d2 of the second field oxide 300, and the height h1 of the first field oxide 200 is set to be less than and equal to the thickness d2 of the trench 130. 0 to the channel region 110, and a surface of the third field oxide 400 away from the trench 130 is flush with the notch of the trench 130, so that there are three independent field plates in the trench 130, which can respectively adjust the electric field and current flow path on the left side of the trench 130, the bottom of the trench 130, and the right side of the trench 130, thereby improving the breakdown voltage of the LDMOS device 10, that is, improving the voltage resistance of the LDMOS device 10. In addition, the current can be made to move close to the surface of the gate polysilicon 600, resulting in a reduction in the specific on-resistance.

[0059] In the present application, the thickness d1 of the first field oxide 200 is set to decrease gradually, so as to further adjust the electric field and the current flow path on the left side of the trench 130, the bottom of the trench 130, and the right side of the trench 130, so that the breakdown voltage of the LDMOS device 10 is improved, that is, the voltage resistance of the LDMOS device 10 is improved.

[0060] In the present application, the shape of the first field oxide 200 is set to be an arc shape, so as to further adjust the electric field and the current flow path on the left side of the trench 130, the bottom of the trench 130, and the right side of the trench 130, so that the breakdown voltage of the LDMOS device 10 is improved, that is, the voltage resistance of the LDMOS device 10 is improved.

[0061] Please refer to Figures 9-18. Figure 9 is a schematic flow chart of the method for manufacturing an LDMOS device provided in this application; Figures 10-18 are schematic flow charts of the method for manufacturing an LDMOS device provided in this application. This application also provides a method for manufacturing an LDMOS device provided in this application, comprising:

[0062] S11. Provide a substrate having a drift region.

[0063] Specifically, a substrate 100 is provided, and ion implantation is performed on a portion of the substrate 100 to form a drift region 120 .

[0064] S12. Patterning the substrate to form a trench in the drift region, wherein the trench has a first field plate region, a second field plate region, and a third field plate region connected in sequence, and the direction from the bottom of the trench toward the notch of the trench is a first direction.

[0065] Specifically, the substrate 100 is etched to form the trench 130 .

[0066] S13 , disposing an oxide material layer 201 on the substrate 100 , wherein the oxide material layer 201 extends into the trench 130 .

[0067] Specifically, an oxide material layer 201 is formed on the substrate 100 by CVD deposition or furnace growth, and extends into the trench 130 .

[0068] S14 , thinning the oxide material layer located on the second field plate region to form a second field oxide.

[0069] Specifically, the oxide material layer 201 located on the second field plate region 132 is thinned by etching back to form a second field oxide 300. The thickness of the second field oxide 300 is thinned to 0.1-0.9 times the thickness of the original oxide material layer 201, so as to further adjust the electric field and current flow path at the bottom of the trench 130.

[0070] In one embodiment, after step S14 , the process further includes: performing a wet treatment on the oxide material layer 201 to eliminate damage caused by plasma during the etch-back in step S14 , thereby improving device performance.

[0071] S15 , performing dry etching on the oxide material layer to remove a portion of the oxide material layer located on the first field plate region and the oxide material layer located on the substrate near the first field plate region to form a first field oxide located in the first field plate region.

[0072] Specifically, a photoresist layer 202 is formed on the oxide material layer 201. The photoresist layer 202 exposes the oxide material layer 201 located on the first field plate region 131 and the oxide material layer 201 located on the substrate 100 near the first field plate region. The oxide material layer 201 is dry-etched to remove a portion of the oxide material layer 201 located on the first field plate region 131 and the oxide material layer 201 located on the substrate 100 near the first field plate region, thereby forming a first field oxide 200 located in the first field plate region 131. The thickness of the oxide material layer 201 removed from the first field plate region 131 is 0.1-0.8 times the depth of the trench 130, so as to further adjust the electric field and current flow path on the left side of the trench 130. Then, the photoresist layer 202 is removed.

[0073] In one embodiment, the thickness d1 of the first field oxide 200 decreases from the first field oxide 200 toward the third field oxide 400 , that is, the thickness d1 of the first field oxide 200 close to the gate oxide layer 500 is smaller, and the thickness d1 of the first field oxide 200 far from the gate oxide layer 500 is larger.

[0074] S16. Form a gate oxide layer on the first field oxide in the first direction.

[0075] S17. A polysilicon layer is provided on the substrate, the gate oxide layer and the oxide material layer, and patterned to form a gate polysilicon and a third field oxygen that are flush with the notch of the trench, the second field oxygen is located in the second field plate region, the third field oxygen is located in the third field plate region, and the side of the third field oxygen away from the trench is flush with the notch of the trench.

[0076] S18. Ions are implanted into the substrate to form a channel region and a drain region, wherein a trench is located between the channel region and the drain region, and the trench and the drain region are spaced apart, wherein the thickness of the first field oxygen and the thickness of the third field oxygen are both greater than the thickness of the second field oxygen, and the height of the first field oxygen is less than and equal to the distance from the bottom of the trench to the channel region.

[0077] In one embodiment, after step S18, the process further includes forming a metal silicide, a dielectric layer 700, a first connecting portion 800, a second connecting portion 900 and a third connecting portion 1000 on the substrate 100, the gate polysilicon 600, the third field oxide 400 and the gate oxide layer 500, wherein the metal silicide is disposed on the channel region 110, the source region 111, the body region 112, the gate polysilicon 600 and the drain region 121. The dielectric layer 700 is disposed on the metal silicide, the gate oxide layer 500, the third field oxide 400, and the drift region 120. The dielectric layer 700 has a plurality of through holes that penetrate the dielectric layer 700 and expose the metal silicide. The first connecting portion 800, the second connecting portion 900, and the third connecting portion 1000 are alternately disposed on the dielectric layer 700. The first connecting portion 800 is filled in the through hole located on the source region 111 and the body region 112 to connect the body region 112 to the source region 111. The second connecting portion 900 is filled in the through hole located on the gate polysilicon 600. The third connecting portion 1000 is filled in the through hole located on the drain region 121.

[0078] In the present application, the LDMOS device 10 is prepared by the preparation method provided in the present application. The preparation method is simple, easy to implement, and well compatible with other BCD device processes. At the same time, it improves the voltage resistance of the LDMOS device 10 and reduces the specific on-resistance.

[0079] The above description is merely an embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An LDMOS device, characterized in that: include: A substrate having a channel region and a drift region disposed on one side of the channel region, wherein a drain region is disposed in the drift region, a trench is disposed between the drain region and the channel region, and the trench is spaced apart from the drain region, the trench having a first field plate region, a second field plate region, and a third field plate region connected in sequence, and a direction from the bottom of the trench toward the notch of the trench is a first direction; a first field oxygen, a second field oxygen, and a third field oxygen, wherein the first field oxygen, the second field oxygen, and the third field oxygen are sequentially connected and filled in the trench, the first field oxygen is located in the first field plate region, the second field oxygen is located in the second field plate region, and the third field oxygen is located in the third field plate region, wherein the thickness of the third field oxygen and the thickness of the first field oxygen are both greater than the thickness of the second field oxygen, the height of the first field oxygen is less than and equal to the distance from the bottom of the trench to the channel region, and the side of the third field oxygen away from the trench is flush with the notch of the trench; a gate oxide layer, wherein in the first direction, the gate oxide layer is disposed on the first field oxide and is located in the trench; The gate polysilicon is filled on the first field oxygen and the second field oxygen in the trench. The side of the gate polysilicon away from the trench is flush with the notch of the trench. The gate oxide layer and the third field oxygen are provided on the side of the gate polysilicon.

2. The LDMOS device according to claim 1, wherein: In the first direction, the thickness of the first field oxygen decreases gradually.

3. The LDMOS device according to claim 2, wherein: The first field oxygen has an arc shape.

4. The LDMOS device according to claim 1, wherein: The gate oxide layer is arranged in contact with the channel region.

5. The LDMOS device according to claim 1, wherein: A surface of the gate oxide layer away from the bottom of the trench is flush with the notch of the trench.

6. The LDMOS device according to claim 1, wherein: The thickness of the gate oxide layer is 7. The LDMOS device according to claim 1, wherein: The LDMOS device further includes a dielectric layer, which is arranged on the substrate, the gate polysilicon and the gate oxide layer.

8. A method for preparing an LDMOS device, characterized in that: Used to prepare the LDMOS device according to any one of claims 1 to 7, comprising: providing a substrate having a drift region; Performing patterning on the substrate to form a trench in the drift region, wherein the trench has a first field plate region, a second field plate region, and a third field plate region connected in sequence, and a direction from the bottom of the trench toward the notch of the trench is a first direction; Disposing an oxide material layer on the substrate, wherein the oxide material layer extends into the trench; performing a thinning process on the oxide material layer located on the second field plate region to form a second field oxide; performing a dry etching process on the oxide material layer to remove a portion of the oxide material layer located on the first field plate region and the oxide material layer located on the substrate near the first field plate region to form a first field oxide located in the first field plate region; forming a gate oxide layer on the first field oxide in the first direction; Providing a polysilicon layer on the substrate, the gate oxide layer, and the oxide material layer, and performing patterning to form a gate polysilicon layer flush with the notch of the trench and a third field oxygen layer, wherein the second field oxygen layer is located in the second field plate region, the third field oxygen layer is located in the third field plate region, and a side of the third field oxygen layer away from the trench is flush with the notch of the trench; Implanting ions into the substrate to form a channel region and a drain region, wherein the trench is located between the channel region and the drain region, and the trench is spaced apart from the drain region; The thickness of the first field oxygen and the thickness of the third field oxygen are both greater than the thickness of the second field oxygen, and the height of the first field oxygen is less than and equal to the distance between the bottom of the trench and the channel region.

9. The method for preparing an LDMOS device according to claim 8, wherein: After thinning the oxide material layer on the second field plate region to form a second field oxide, and before dry-etching the oxide material layer to remove the oxide material layer on the first field plate region and the oxide material layer on the substrate near the first field plate region to form a first field oxide in the first field plate region, the method further includes: The oxide material layer is wet-treated.

10. The method for preparing an LDMOS device according to claim 8, wherein: In the first direction, the thickness of the first field oxygen decreases gradually.

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