Array substrate and manufacturing method therefor, and display panel

Abstract

The present disclosure provides an array substrate and a manufacturing method therefor, and a display panel. The array substrate comprises a substrate, a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer which are sequentially stacked. The first conductive layer comprises a data line. The semiconductor layer comprises a plurality of active regions. One active region is divided into a channel region and a source region and a drain region respectively located at two sides of the channel region. The second conductive layer comprises a gate of a transistor and a first overlapping structure. The first overlapping structure is at least partially overlapped on the surface of the source region. The third conductive layer comprises a connecting structure. The array substrate is provided with a first via hole at least running through the third insulating layer and the first insulating layer. The connecting structure is at least partially located in the first via hole, and the data line is connected to the first overlapping structure. The data line is connected to the active region by means of the connecting structure and the first overlapping structure. The product yield can be improved.

Description

Array substrate and manufacturing method thereof, and display panel Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, and a display panel. Background Art

[0002] An array substrate is a substrate on which a large number of transistors, resistors, capacitors, and other components are fabricated in an array through semiconductor processes such as coating, gluing, exposure, development, and etching to achieve driving functions. For example, when used in a display panel, the array substrate contains pixel circuits composed of transistors and other components. The pixel circuits can drive the display panel's pixel units to light up or turn off, thereby achieving the display function.

[0003] The array substrate used in the display panel is provided with a data line, and the data line is connected to the active layer of the transistor in the pixel circuit. The data line and the active layer of the transistor are usually provided in different film layers of the array substrate. In order to avoid a large parasitic capacitance between the data line and the pixel electrode and other components in the array substrate, the data line can be provided in the film layer on the side of the active layer of the transistor away from the pixel electrode, so as to increase the distance between the data line and the pixel electrode and other structures and reduce the parasitic capacitance. The film layer where the data line is located and the film layer where the active layer is located are separated by an insulating layer. Currently, after the active layer is manufactured, it is necessary to open a via hole in the insulating layer between the data line and the active layer to connect the data line and the active layer. During the opening process, the etching gas is likely to over-etch the exposed active layer, causing the active layer to be disconnected, resulting in the data line being unable to form a connection with the transistor, resulting in a higher risk of defects.

[0004] Summary of the Invention

[0005] The present disclosure provides an array substrate and a manufacturing method thereof, and a display panel, so as to improve the yield rate of the array substrate.

[0006] According to a first aspect of the present disclosure, an array substrate is provided, comprising:

[0007] substrate;

[0008] A first conductive layer is located on the substrate; the first conductive layer includes a data line;

[0009] a first insulating layer, located on a side of the first conductive layer facing away from the substrate;

[0010] a semiconductor layer located on a side of the first insulating layer facing away from the substrate; the semiconductor layer includes a plurality of active regions, one active region is used to form a transistor; one active region is divided into a channel region and a source region and a drain region respectively located on both sides of the channel region;

[0011] a second insulating layer located on a side of the semiconductor layer facing away from the substrate; the second insulating layer and at least a portion of the source region do not overlap with each other;

[0012] a second conductive layer located on a side of the second insulating layer facing away from the substrate; the second conductive layer includes a gate of the transistor and a first overlapping structure; the first overlapping structure at least partially overlaps a surface of a portion of the source region that does not overlap with the second insulating layer;

[0013] a third insulating layer, located on a side of the second conductive layer facing away from the substrate;

[0014] a third conductive layer, located on a side of the third insulating layer facing away from the substrate; the third conductive layer includes a connecting structure;

[0015] The array substrate is provided with a first via hole which at least passes through the third insulating layer and the first insulating layer; the connection structure is at least partially located in the first via hole, connecting the data line with the first overlapping structure; the data line is connected to the active area through the connection structure and the first overlapping structure.

[0016] In the array substrate provided by the present disclosure, an orthographic projection of the first overlapping structure on the substrate overlaps with an orthographic projection of a data line connected to the first overlapping structure on the substrate.

[0017] In the array substrate provided by the present disclosure, the data line includes a first portion and a second portion adjacent to each other along the width direction of the data line; wherein the orthographic projection of the first portion on the substrate overlaps with the orthographic projection of the first overlapping structure on the substrate, and the orthographic projection of the second portion on the substrate does not overlap with the orthographic projection of the first overlapping structure on the substrate;

[0018] An end portion of the first via hole close to the substrate overlaps at least a portion of the surface of the second portion.

[0019] In the array substrate provided by the present disclosure, the first overlapping structure includes a third part and a fourth part; the orthographic projection of the third part on the substrate overlaps with the orthographic projection of the source region on the substrate; the orthographic projection of the fourth part on the substrate does not overlap with the orthographic projection of the active region on the substrate.

[0020] In the array substrate provided by the present disclosure, the first via hole at least partially exposes the fourth portion of the first overlapping structure; the orthographic projection of the first via hole on the substrate does not overlap with the orthographic projection of the third portion on the substrate.

[0021] In the array substrate provided by the present disclosure, the third portion is entirely directly overlapped on the surface of the source region; and the fourth portion is entirely directly overlapped on the surface of the first insulating layer.

[0022] In the array substrate provided by the present disclosure, the fourth portion does not overlap with the sidewall of the first via hole located in the first insulating layer.

[0023] In the array substrate provided by the present disclosure, the orthographic projection of the second insulating layer on the substrate is located within the orthographic projection of the second conductive layer on the substrate.

[0024] In the array substrate provided by the present disclosure, the first insulating layer includes a recessed area; the recessed area is adjacent to the portion of the first via hole located in the first insulating layer; the height of the first insulating layer in the recessed area is less than the height of the first insulating layer in the area covered by the orthographic projection of the fourth part.

[0025] In the array substrate provided by the present disclosure, the orthographic projection of the gate on the substrate is located within the orthographic projection of the second insulating layer on the substrate; the third portion is a certain distance away from the edge of the second insulating layer on the side close to the third portion.

[0026] In the array substrate provided by the present disclosure, a height of the first insulating layer located in the orthographic projection coverage area of ​​the fourth portion is lower than a height of the first insulating layer located in the orthographic projection coverage area of ​​the third portion.

[0027] In the array substrate provided by the present disclosure, the third conductive layer further includes a pixel electrode; the pixel electrode is electrically connected to the drain region through a second via hole penetrating the third insulating layer.

[0028] In the array substrate provided by the present disclosure, the array substrate further includes a fourth conductive layer and a fourth insulating layer located between the fourth conductive layer and the third conductive layer;

[0029] The fourth conductive layer includes a common electrode.

[0030] In the array substrate provided by the present disclosure, the third conductive layer further includes a common electrode; and the drain region is reused as a pixel electrode.

[0031] In the array substrate provided by the present disclosure, the third conductive layer further includes a common electrode; the array substrate further includes a fifth conductive layer and a fifth insulating layer located between the fifth conductive layer and the third conductive layer;

[0032] The fifth conductive layer further includes a pixel electrode, which is connected to the drain region via a third via hole at least penetrating the third insulating layer.

[0033] In the array substrate provided by the present disclosure, the second conductive layer further includes a second overlapping structure; the second overlapping structure is located between the pixel electrode and the drain region, and is used for connecting the pixel electrode and the drain region.

[0034] In the array substrate provided by the present disclosure, the first conductive layer further includes a light-shielding area; the orthographic projection of the channel area on the substrate is located within the orthographic projection of the light-shielding area on the substrate;

[0035] The orthographic projection of the channel region on the substrate is located within the orthographic projection of the gate on the substrate;

[0036] The doping concentration of the source region and the doping concentration of the drain region are both greater than the doping concentration of the channel region;

[0037] The material of the semiconductor layer is oxide semiconductor.

[0038] According to a second aspect of the present disclosure, a display panel is provided, comprising the array substrate provided by any one of the above embodiments.

[0039] According to a third aspect of the present disclosure, a display device is provided, comprising the display panel provided by any one of the above embodiments.

[0040] A fourth aspect of the present disclosure provides a method for manufacturing an array substrate, comprising:

[0041] forming a first conductive layer on the substrate; the first conductive layer includes a data line;

[0042] forming a first insulating layer on a side of the first conductive layer facing away from the substrate;

[0043] A semiconductor layer is formed on a side of the first insulating layer facing away from the substrate; the semiconductor layer includes a plurality of active regions, one active region is used to form a transistor; the active region is divided into a channel region and a source region and a drain region respectively located on both sides of the channel region;

[0044] forming a second insulating layer on a side of the semiconductor layer facing away from the substrate; wherein the second insulating layer and at least a portion of the source region do not overlap with each other;

[0045] A second conductive layer is formed on a side of the second insulating layer facing away from the substrate; the second conductive layer includes a first overlapping structure and a gate of the transistor; the first overlapping structure at least partially overlaps a surface of a portion of the source region that does not overlap with the second insulating layer;

[0046] forming a third insulating layer on a side of the second conductive layer facing away from the substrate, and providing a first via hole for exposing the first bonding structure and the data line;

[0047] A third conductive layer is formed on a side of the third insulating layer facing away from the substrate; the third conductive layer includes a connecting structure; and the connecting structure connects the first overlapping structure with the data line through a first via hole.

[0048] In the method provided in the present disclosure, forming a second insulating layer on a side of the semiconductor layer facing away from the substrate specifically includes:

[0049] forming a second insulating layer on a side of the semiconductor layer facing away from the substrate;

[0050] Etching the second insulating layer to form an opening penetrating the second insulating layer; the opening simultaneously exposes at least a portion of a source region of an active area and a portion of the first insulating layer surrounding the source region, and an orthographic projection of the opening on the substrate at least partially overlaps with an orthographic projection of the data line on the substrate;

[0051] Continue etching the first insulating layer exposed by the opening to form a recessed portion on the surface of the first insulating layer;

[0052] Producing a first via hole for exposing the first bonding structure and the data line specifically includes:

[0053] A first via hole is opened to expose the first overlapping structure and the data line, and an orthographic projection of a portion of the first via hole located in the first insulating layer on the substrate is located within an orthographic projection of the recess on the substrate.

[0054] The beneficial effects of the present disclosure are as follows:

[0055] The present disclosure provides an array substrate and a manufacturing method thereof, and a display panel. The array substrate includes:

[0056] A substrate, a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer. The first conductive layer is located on the substrate and includes a data line. The first insulating layer is located on a side of the first conductive layer facing away from the substrate. The semiconductor layer is located on a side of the first insulating layer facing away from the substrate. The semiconductor layer includes multiple active regions, each of which is used to form a transistor. An active region is divided into a channel region and a source region and a drain region located on either side of the channel region. The second insulating layer is located on a side of the semiconductor layer facing away from the substrate. The second insulating layer and at least a portion of the source region do not overlap. The second conductive layer is located on a side of the second insulating layer facing away from the substrate. The second conductive layer includes a transistor gate and a first overlapping structure. The first overlapping structure at least partially overlaps the surface of the source region that does not overlap with the second insulating layer. The third insulating layer is located on a side of the second conductive layer facing away from the substrate. The third conductive layer is located on a side of the third insulating layer facing away from the substrate. The third conductive layer includes a connecting structure. The array substrate is provided with a first via hole that penetrates at least the third insulating layer and the first insulating layer; a connecting structure is at least partially located in the first via hole, connecting the data line to the first overlapping structure; and the data line is connected to the active area via the connecting structure and the first overlapping structure. In the array substrate provided by the present disclosure, the first overlapping structure is provided on the surface of the source area, and the first overlapping structure is connected to the data line via the connecting structure. This facilitates avoiding over-etching of the active area during etching of the first insulating layer when the first via hole is provided, thereby preventing disconnection of the active area and the inability to connect the data line to the transistor, thereby improving product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments of the present disclosure. Obviously, the drawings introduced below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0058] FIG1 is a schematic diagram of a typical circuit structure of a liquid crystal display panel;

[0059] FIG2 is a schematic diagram of a circuit structure of an array substrate according to an embodiment of the present disclosure;

[0060] FIG3 is a schematic diagram of a cross-sectional structure of an array substrate provided in an embodiment of the present disclosure;

[0061] FIG4A is a schematic diagram of a manufacturing process of an array substrate according to an embodiment of the present disclosure;

[0062] FIG4B is a second schematic diagram of the manufacturing process of the array substrate provided in an embodiment of the present disclosure;

[0063] FIG5A is a schematic diagram of a manufacturing process of an array substrate for comparison; ...

[0064] FIG5B is a second schematic diagram of the array substrate manufacturing process for comparison;

[0065] FIG6 is a second schematic diagram of the cross-sectional structure of the array substrate provided in an embodiment of the present disclosure;

[0066] FIG7A is a schematic diagram of a top view of a first overlapping structure and a data line according to an embodiment of the present disclosure;

[0067] FIG7B is a second schematic diagram of a top view of the first overlapping structure and the data line provided in an embodiment of the present disclosure;

[0068] FIG8 is a third schematic diagram of the cross-sectional structure of the array substrate provided in an embodiment of the present disclosure;

[0069] FIG9 is a third schematic diagram of the manufacturing process of the array substrate provided in an embodiment of the present disclosure;

[0070] FIG10 is a fourth schematic diagram of the cross-sectional structure of the array substrate provided in an embodiment of the present disclosure;

[0071] FIG11 is a fourth schematic diagram of a manufacturing process of an array substrate provided in an embodiment of the present disclosure;

[0072] FIG12 is a fifth schematic diagram of the cross-sectional structure of the array substrate provided in an embodiment of the present disclosure;

[0073] FIG13A is a fifth schematic diagram of a manufacturing process of an array substrate provided in an embodiment of the present disclosure;

[0074] FIG13B is a sixth schematic diagram of the manufacturing process of the array substrate provided in an embodiment of the present disclosure;

[0075] FIG14 is a sixth schematic diagram of the cross-sectional structure of the array substrate provided in an embodiment of the present disclosure;

[0076] FIG15A is a seventh schematic diagram of a cross-sectional structure of an array substrate provided in an embodiment of the present disclosure;

[0077] FIG15B is an eighth schematic diagram of the cross-sectional structure of the array substrate provided in an embodiment of the present disclosure;

[0078] FIG16 is a second schematic diagram of the circuit structure of the array substrate provided in an embodiment of the present disclosure;

[0079] FIG17A is a ninth schematic diagram of a cross-sectional structure of an array substrate provided in an embodiment of the present disclosure;

[0080] FIG17B is a tenth schematic diagram of the cross-sectional structure of an array substrate provided in an embodiment of the present disclosure;

[0081] FIG17C is an eleventh schematic diagram of a cross-sectional structure of an array substrate provided in an embodiment of the present disclosure;

[0082] FIG18 is a twelfth schematic diagram of a cross-sectional structure of an array substrate provided in an embodiment of the present disclosure;

[0083] FIG19 is a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0084] In order to make the above-mentioned purposes, features and advantages of the present disclosure more obvious and easy to understand, the present disclosure will be further described below with reference to the accompanying drawings and examples. However, the example embodiments can be implemented in various forms and should not be understood as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided to make the present disclosure more comprehensive and complete, and to fully convey the concepts of the example embodiments to those skilled in the art. The same figure marks in the figures represent the same or similar structures, and their repeated descriptions will be omitted. The words expressing position and direction described in the present disclosure are all explained using the accompanying drawings as examples, but changes can be made as needed, and all changes are included in the scope of protection of the present disclosure. The drawings of the present disclosure are only used to illustrate relative position relationships and do not represent true proportions.

[0085] An array substrate is a substrate on which a large number of transistors, resistors, capacitors, and other components are fabricated in an array through semiconductor processes such as coating, gluing, exposure, development, and etching to achieve driving functions. For example, when used in a display panel, the array substrate contains pixel circuits composed of transistors and other components. The pixel circuits can drive the display panel's pixel units to light up or turn off, thereby achieving the display function.

[0086] FIG1 is a schematic diagram of a typical circuit structure of a liquid crystal display panel.

[0087] Taking a typical liquid crystal display panel as an example, as shown in Figure 1, an array substrate is provided with multiple data lines DL and multiple scan lines GL that intersect horizontally and vertically. Adjacent data lines DL and scan lines GL define the pixel unit arrangement area. The liquid crystal display panel is provided with multiple pixel units, each of which includes a display device and a pixel circuit PX connected to the display device. Specifically, in the liquid crystal display panel, the display device can be a liquid crystal capacitor Clc. The liquid crystal capacitor Clc includes a pixel electrode connected to the output terminal of the pixel circuit and a common electrode connected to a common electrode line Vcom. By applying a deflection voltage between the pixel electrode and the common electrode, the liquid crystal molecules located between the pixel electrode and the common electrode are driven to deflect, adjusting the amount of light passing through the liquid crystal capacitor Clc, thereby achieving different grayscales. The pixel circuit PX includes a transistor TR and a storage capacitor Cst connected in parallel with the liquid crystal capacitor Clc. The pixel electrode of the liquid crystal capacitor Clc is connected to the drain D of the transistor TR. The source S of the transistor TR is connected to the data line DL, and the gate of the transistor TR is connected to the scan line GL. The scan line GL is used to provide a gate control signal, which is used to control the transistor TR to turn on or off. The data line DL is used to provide a data signal. When the transistor TR is turned on, the data signal is input to the pixel electrode of the liquid crystal capacitor Clc through the transistor, forming a voltage difference between the pixel electrode and the common electrode, thereby driving the liquid crystal molecules to deflect.

[0088] During specific implementation, the data line DL and the active layer of the transistor TR are usually arranged in different film layers of the array substrate. In order to avoid a large parasitic capacitance between the data line and the pixel electrode and other components in the array substrate, which affects the size of the data signal, the data line can be arranged in the film layer on the side of the active layer of the transistor TR away from the pixel electrode, so as to increase the distance between the data line and the pixel electrode and other structures and reduce the parasitic capacitance. The film layer where the data line is located and the film layer where the active layer is located are separated by an insulating layer. Currently, after the active layer is made, it is necessary to open a via hole in the insulating layer between the data line and the active layer to connect the data line and the active layer. During the hole opening process, the etching gas is likely to over-etch the exposed active layer, causing the active layer to be disconnected, resulting in the data line being unable to form a connection with the transistor.

[0089] In view of this, an embodiment of the present disclosure provides an array substrate to solve the above-mentioned problem.

[0090] FIG2 is one of the schematic diagrams of the circuit structure of the array substrate provided in an embodiment of the present disclosure; FIG3 is one of the schematic diagrams of the cross-sectional structure of the array substrate provided in an embodiment of the present disclosure.

[0091] In an embodiment of the present disclosure, as shown in FIG2 , an array substrate is provided with a plurality of data lines DL and a plurality of scan lines GL that intersect horizontally and vertically. Adjacent data lines DL and scan lines GL define the arrangement area of ​​the pixel units. The array substrate is also provided with a pixel circuit PX, which is used to drive the display device to display images. The pixel circuit PX is connected to the data lines DL and the scan lines GL, respectively, so that data signals and scan signals are input into the pixel circuit PX via the data lines DL and the scan lines GL. A pixel circuit PX may include at least one transistor. The data line DL is connected to the source of at least one transistor in the pixel circuit PX, and the scan line GL is connected to the gate of at least one transistor in the pixel circuit PX. Typically, the data line DL and the scan line GL are connected to the same transistor. For example, as shown in FIG2 , the data line DL and the scan line GL are connected to the same transistor in the pixel circuit PX, such as the first transistor TR1, where the data line DL is connected to the source of the first transistor TR1 and the scan line GL is connected to the gate of the first transistor TR1.

[0092] From the cross-sectional structure of the array substrate, as shown in FIG3 , the array substrate provided by the embodiment of the present disclosure includes the following structure:

[0093] Substrate 1 is located at the bottom of the array substrate. Substrate 1 has a supporting and load-bearing function and is used to support other film layers located thereon. The shape of substrate 1 can generally be set to be rectangular, square, etc. Depending on the specific shape of the array substrate, substrate 1 can also be set to a circular or other special shape, which is not limited here. Depending on the type of display panel used to manufacture the array substrate, the material of substrate 1 can be made of different materials. For example, when used in a transparent display panel such as a liquid crystal display (LCD) display panel, substrate 1 can be made of a transparent material. When used in a non-transparent display panel such as an organic light emitting diode (OLED) display panel or a micro light emitting diode (Micro LED) display panel, substrate 1 can be made of a non-transparent material. When used in a flexible display panel, substrate 1 can be made of a flexible material. When used in a non-flexible display panel, substrate 1 can be made of a rigid material, which is not limited here. In specific implementations, the material of substrate 1 can be glass, resin, etc., which is not limited here.

[0094] The first conductive layer 2 is located on the substrate 1. The data line DL is formed in the first conductive layer 2. The material of the first conductive layer 2 can be conductive metals and their alloys, conductive metal oxides, conductive polymers and other conductive materials, such as copper (Cu), aluminum (Al), silver (Ag), indium tin oxide (ITO), etc., which are not limited here. The first conductive layer 2 can be a single-layer structure or a multi-layer structure in which multiple film layers are stacked. For example, the first conductive layer 2 can be a titanium / aluminum / titanium (Ti / Al / Ti) triple-layer structure, which is not limited here. During the specific production, the first conductive material layer can be formed on the substrate 1 by deposition or the like, and then the pattern of the data line DL can be produced by a patterning process such as etching, which is not limited here.

[0095] The first insulating layer 3 is located on the side of the first conductive layer 2 facing away from the substrate 1. The first insulating layer 3 is made of an insulating material and is used to separate the first conductive layer 2 from the semiconductor layer or other conductive film layer to protect the first conductive layer 2. The first insulating layer 3 can also serve as a buffer layer to prevent the free metal ions in the first conductive layer 2 from diffusing into the semiconductor layer, thereby reducing the leakage current of the transistor. In specific implementation, the first insulating layer 3 can be made of silicon oxide (SiO x ), silicon nitride (SiN X ) or inorganic insulating materials such as silicon oxynitride (SiON), or organic insulating materials such as resin, are not limited here.

[0096] The semiconductor layer 4 is located on the side of the first insulating layer 3 facing away from the substrate 1. The semiconductor layer 4 includes a plurality of active regions 41, and one active region 41 is used to form a transistor TR. In a specific implementation, the transistor TR can be a thin film transistor (TFT), and the material of the semiconductor layer 4 can be single crystal silicon, amorphous silicon (a-Si), low temperature polysilicon (p-Si), or a metal oxide semiconductor, such as indium gallium zinc oxide (IGZO), etc., which are not limited here. An active region 41 is divided into a channel region 412 and a source region 411 and a drain region 413 respectively located on two layers of the channel region 412. The channel region 412 is used to form the channel of the transistor TR, and the source region 411 and the drain region 413 are used to form the source and drain of the transistor TR, respectively. In the embodiment of the present disclosure, the source region 411 and the drain region 413 of the active region 41 can be heavily doped by ion implantation or the like, thereby directly making the source region 411 and the drain region 413 of the active region 41 conductive, respectively forming the source and drain of the transistor TR, thereby reducing the manufacturing process of separately manufacturing the source and drain.

[0097] The second insulating layer 5 is located on the side of the semiconductor layer 4 facing away from the substrate 1. The second insulating layer 5 is made of an insulating material and can serve as a gate insulator (GI) layer to separate the semiconductor layer 4 from the gate of the transistor. The second insulating layer 5 can be made of the same or different material as the first insulating layer 3, and is not limited here. In a specific implementation, the second insulating layer 5 does not overlap with at least a portion of the source region 411. The second insulating layer 5 exposes the area of ​​the source region 411 that does not overlap with the second insulating layer 5, so as to facilitate the subsequent connection of the first overlapping structure with the source region 411.

[0098] The second conductive layer 6 is located on the side of the second insulating layer 5 facing away from the substrate 1. The second conductive layer 6 includes the gate 62 of the transistor TR and a first overlapping structure 61. The second conductive layer 6 can be made of the same or different material as the first conductive layer 2. In specific production, a second conductive material layer can be formed on the second insulating layer 5 by deposition or other methods, and then the pattern of the gate 62 and the first overlapping structure 61 can be formed by a patterning process such as etching, which is not limited here. In specific implementation, as shown in Figure 1, the orthographic projection of the channel region 412 of the transistor TR on the substrate 1 is located within the orthographic projection of the gate 63 on the substrate 1. The scan line GL is connected to the gate of the transistor, so the scan line GL and the gate can be set on the same layer, which is not limited here. The first overlapping structure 61 at least partially overlaps the surface of the source region 411 that does not overlap with the second insulating layer 5. The portion of the first overlapping structure 61 overlapping the surface of the source region 411 is in direct contact with the source region 411, thereby facilitating the subsequent connection of the source of the transistor TR to the data line via the first overlapping structure 61. It should be noted that, in order to clearly highlight the main inventive point of the present disclosure, in the embodiment shown in FIG3 , only the structure of one transistor TR connected to the data line DL via the first bridging structure 61 is shown. When a pixel circuit PX includes multiple transistors TR, the source of generally only one transistor TR in the pixel circuit PX needs to be connected to the data line DL, such as the source of the first transistor TR1 shown in FIG2 being connected to the data line. Therefore, it can be understood that when a pixel circuit PX includes only one transistor TR, the first bridging structure 61 is bridging the surface of the source region 411 of the transistor TR in the pixel circuit PX to facilitate the subsequent connection of the transistor to the data line DL via the first bridging structure. When a pixel circuit PX includes multiple (such as at least two) transistors, the first overlap structure 61 is only overlapped on the surface of the source region 411 corresponding to the transistor TR that needs to be connected to the data line DL. For example, the first overlap structure 61 is only overlapped on the surface of the source region 411 corresponding to the first transistor TR1. The other transistors in the pixel circuit PX (not shown in the figure) do not need to be connected to the data line DL through the first overlap structure 61. Therefore, the other transistors in the pixel circuit PX (not shown in the figure) can be connected with reference to the connection method in the prior art, which will not be elaborated here.

[0099] The third insulating layer 7 is located on the side of the second conductive layer 6 facing away from the substrate 1. The first insulating layer 3 is made of an insulating material and is used to separate the second conductive layer 6 from other conductive film layers and protect the second conductive layer 6. The third insulating layer 7 can be made of the same or different material as the first insulating layer 3, without limitation.

[0100] The third conductive layer 8 is located on the side of the third insulating layer 7 facing away from the substrate 1. The third conductive layer 8 includes a connecting structure 81. The connecting structure 81 is used to connect the first bonding structure 61 to the data line DL.

[0101] In a specific implementation, as shown in FIG3 , a first via hole H1 is defined in the array substrate, penetrating at least the third insulating layer 7. A connecting structure 81 is at least partially located within the first via hole H1, connecting the first bridging structure 61 to the data line DL via the first via hole H1. The data line DL is connected to the active area 41 via the connecting structure 81 and the first bridging structure 61.

[0102] In the array substrate provided by the present disclosure, the first conductive layer 2 where the data line DL is located is arranged between the first insulating layer 3 and the substrate 1, that is, the data line DL is placed below the semiconductor layer 4, thereby increasing the distance between the data line DL and other signal lines (such as the scan line GL) in the array substrate, which is beneficial to reducing the parasitic capacitance generated by the data line DL. And according to actual needs, the parasitic capacitance generated by the data line DL can be further reduced by adjusting the thickness of the first insulating layer 3. In addition, in the array substrate provided by the present disclosure, the source region 411 and the drain region 413 in the active region 41 are made conductive by heavy doping, and the source and drain are directly made, thereby reducing the process of using a separate conductive film layer to make the source and drain, which is beneficial to reducing process steps and improving production efficiency.

[0103] In particular, in the array substrate provided by the present disclosure, a first overlapping structure 61 is set on the surface of the source area 411, and the first overlapping structure 61 is connected to the data line DL through the connecting structure 81. This is beneficial for avoiding over-etching of the active area 41 during the etching of the first insulating layer 3 when opening the first via hole H1, thereby avoiding disconnection of the active area 41 and the inability to connect the data line and the transistor, thereby improving product yield.

[0104] Figure 4A is one of the schematic diagrams of the manufacturing process of the array substrate provided in an embodiment of the present disclosure; Figure 4B is a second schematic diagram of the manufacturing process of the array substrate provided in an embodiment of the present disclosure; Figure 5A is one of the schematic diagrams of the manufacturing process of the array substrate for comparison; Figure 5B is a second schematic diagram of the manufacturing process of the array substrate for comparison.

[0105] Specifically, during the manufacturing process of the array substrate provided by the present invention, since the connecting structure 81 connects the first overlapping structure 61 with the data line DL by exposing the first via H1 of the first overlapping structure 61 and the data line DL, it is not necessary to perform an etching step on the first insulating layer 3 before manufacturing the first overlapping structure 61, thereby avoiding over-etching of the active area 411 in this step.

[0106] During the specific production, as shown in Figure 4A, after the active area 41 is formed, a second insulating layer 5 is formed on the side of the active area 41 facing away from the substrate 1, and then an opening K is opened in the second insulating layer 5. The opening K passes through the second insulating layer 5 and exposes at least part of the source region 411 of the active area 41 to facilitate the subsequent connection between the first overlapping structure 61 and the source region 411.

[0107] After the opening K is opened in the second insulating layer 5, a second conductive material layer is formed on the side of the second insulating layer 5 facing away from the substrate 1. The second conductive material layer covers the second insulating layer 5 and covers the source region 411 exposed by the opening K in the second insulating layer 5. The second conductive material layer is then patterned by etching and other processes to produce a gate 62 and a first overlapping structure 61 to form a second conductive layer 6. The first overlapping structure 61 is at least partially overlapped on the surface of the source region 411 exposed by the opening K.

[0108] As shown in FIG4B , after the second conductive layer 6 is formed, a third insulating layer 7 is formed on the side of the second conductive layer 6 facing away from the substrate 1. A first via hole H1 is then formed in the third insulating layer 7 starting from the surface of the third insulating layer 7 facing away from the substrate 1. The first via hole H1 penetrates the third insulating layer 7 and exposes a portion of the first lap joint structure 61. The first via hole H1 also penetrates the first insulating layer 3, thereby exposing a portion of the data line DL. After the first via hole H1 is formed, a third conductive material layer is formed on the side of the first insulating layer 3 facing away from the substrate 1. The third conductive material layer covers the third insulating layer 7 and the first lap joint structure 61 and data line DL exposed by the first via hole H1. The third conductive material layer is then patterned, such as by etching, to form a connection structure 81 connecting the first lap joint structure 61 and the data line DL, thereby forming the third conductive layer 8.

[0109] The first bonding structure 61 does not need to be directly connected to the data line DL. Therefore, when the opening K is formed in the second insulating layer 5, the first insulating layer 3 does not need to be etched to expose the data line DL. This avoids over-etching of the active area 411 exposed by the opening K during the etching of the first insulating layer 3 due to the thickness of the first insulating layer 3. When the first via hole H1 is subsequently formed in the array substrate to expose the first bonding structure 61 and the data line DL, since the first via hole H1 does not need to directly expose the surface of the source region 411, etching of the source region 411 in subsequent processes is avoided, thereby ensuring effective connection of the data line DL to the transistor through the first bonding structure 61.

[0110] Figures 5A and 5B illustrate a comparative array substrate manufacturing process. The array substrates shown in Figures 5A and 5B are susceptible to the problem of active region cutouts during manufacturing. Specifically, as shown in Figure 5A , a second insulating layer 5 is formed on the side of the active region 41 facing away from the substrate 1. An opening K is then formed in the second insulating layer 5. The opening K exposes a portion of the source region 411 and a portion of the surface of the first insulating layer 3 adjacent to the source region 411. Since in the array substrate shown in Figure 5A, the source region 411 is directly connected to the data line DL through the second overlapping structure 63, in the step of opening the opening K in the second insulating layer 5, after the opening K is formed through the second insulating layer 5, it is necessary to etch the first insulating layer 5 exposed by the opening K in this step to form a via hole that penetrates the first insulating layer 3 and exposes the data line DL. Since the source region 411 exposed by the opening K is not protected by the second insulating layer 5, the source region 411 exposed by the opening K is etched to a certain extent, resulting in that after the etching step is completed, the thickness of the source region 411 exposed by the opening K is significantly thinner than the thickness of the active region 41 in the area covered by the second insulating layer 5.

[0111] After etching the second insulating layer 5 and the first insulating layer 3, a conductive material is deposited on the side of the second insulating layer 5 facing away from the substrate 1 to form a second conductive material layer 60. The second conductive material layer 60 covers the second insulating layer 5, the active area 41 exposed by the opening K, and the data line DL exposed by the via hole in the first insulating layer 3. The second conductive material layer 60 is then etched to form a pattern of a gate 62 and a second overlapping structure 63. The second overlapping structure 63 partially overlaps the surface of the source area 411 and partially overlaps the surface of the data line DL exposed by the via hole, thereby connecting the active area 41 and the data line. During the etching process of the second conductive material layer 60, part of the source region 4111 exposed by the opening K (the width of this part of the source region 4111 is the reserved distance between the second overlap structure 63 and the second insulating layer 5, which is used to avoid the second overlap structure 63 in this area overlapping the surface of the second insulating layer 5, resulting in the subsequent inability to conduct the source region in this area), is not protected by the second insulating layer 5 and the second overlap structure 63. Therefore, the thickness of this part of the source region 4111 is further reduced due to the over-etching generated during the etching process of the second conductive material layer 60.

[0112] After etching the second conductive material layer 60, the active area 41 under the area covered by the second insulating layer 5 needs to be conductively treated. In some conductive treatment processes, it is necessary to first remove the second insulating layer 5 covering the active area 41 through an etching process to completely expose the active area 41. During the etching process of the second insulating layer 5 covering the active area 41, part of the source area 4111 is further etched because it is not protected by the second insulating layer 5 and the second bonding structure 63, and its thickness is further reduced.

[0113] In conjunction with the array substrate fabrication process shown in FIG5A and FIG5B , after the semiconductor layer 4 is patterned to form the active area 41, a portion of the source region 4111 is further etched at least three times, respectively, during the steps of etching the first insulating layer 3, etching the second insulating layer 5, and etching the second conductive layer 6. If the etching depth in each etching step is large, a portion of the source region 4111 may be completely etched through, forming a fracture F between the second bridging structure 63 and the active area 41, thereby preventing the data line DL from properly connecting to the transistor via the second bridging structure 63. This is particularly true when the thickness of the first insulating layer 3 needs to be increased to further reduce the parasitic capacitance generated by the data line DL. For example, the thickness of the first insulating layer 3 is generally set to approximately 400 nm, but in some cases needs to be increased to 600 nm to 800 nm. Or when the thickness of the semiconductor layer 4 needs to be reduced to improve transistor device performance, the risk of partially etching through the source region 4111 is further increased, making it difficult to ensure a stable connection between the data line DL and the transistor during the fabrication process.

[0114] In summary, the array substrate structure provided by the present disclosure is conducive to avoiding over-etching of the active area 41 during the etching step of the first insulating layer 3, thereby avoiding disconnection of the active area 41 and failure to connect the data line to the transistor.

[0115] In some embodiments, as shown in FIG3 , the first via H1 is a single-hole structure that simultaneously penetrates the third insulating layer 7 and the first insulating layer 3, and simultaneously exposes a portion of the first overlapping structure 61 and a portion of the data line DL connected to the first overlapping structure 61. It will be appreciated that because the second insulating layer 5 is located between the third insulating layer 7 and the first insulating layer 3, the first via H1 referred to in this disclosure as simultaneously penetrating the third insulating layer 7 and the first insulating layer 3 also includes the case where the first via H1 simultaneously penetrates the second insulating layer 5, which will not be further described below. As shown in FIG3 , the first via H1 is configured as a single-hole structure, which helps reduce the number of openings and reduces the difficulty of mask production.

[0116] FIG6 is a second schematic diagram of the cross-sectional structure of the array substrate provided in an embodiment of the present disclosure.

[0117] In some embodiments, the first via H1 can be configured as a multi-hole structure. For example, as shown in FIG6 , the first via H1 can be configured as a dual-hole structure. A first via H1 includes a first sub-hole H11 that penetrates both the third insulating layer 7 and the first insulating layer 3 and exposes the data line DL, and a second sub-hole H12 that penetrates only the third insulating layer 7 and exposes the first overlapping structure 61. The first sub-hole H11 and the second sub-hole H12 are not interconnected within the array substrate, forming a dual-hole structure. The first via H1 forms a dual-hole structure, and the connecting structure 81 fills the first sub-hole H11 and the second sub-hole H12, respectively, connecting the data line DL to the first overlapping structure 61. The first via H1 forms a dual-hole structure, and the apertures of the first sub-hole H11 and the second sub-hole H12 of the first via H1 can both be smaller, which helps reduce the size of the opening, facilitates subsequent planarization processing, and improves the surface flatness of the array substrate.

[0118] In the following content of this disclosure, the specific structure of the array substrate provided by this disclosure is described with the first via hole H1 being a single hole structure. When the first via hole H1 is a multi-hole structure, its specific implementation can refer to the case where the first via hole H1 is a single hole structure, and will not be repeated in this disclosure.

[0119] FIG7A is a schematic diagram of a top view of a first overlapping structure and a data line according to an embodiment of the present disclosure; FIG7B is a schematic diagram of a top view of a first overlapping structure and a data line according to an embodiment of the present disclosure.

[0120] In some embodiments, as shown in FIG7A and FIG7B , the orthographic projection of the first bridge structure 61 on the substrate overlaps with the orthographic projection of the data line DL connected to the first bridge structure 61. That is, in a specific implementation, the first bridge structure 61 is positioned close to the data line DL in a horizontal direction parallel to the substrate to reduce the horizontal distance between the first bridge structure 61 and the data line DL, thereby facilitating a reduction in the opening size of the first via H1 (indicated by the solid oval circle in FIG7A ) and making the connection between the first bridge structure 61 and the data line DL more compact, thereby saving more space for routing other signal lines.

[0121] In some embodiments, as shown in Figures 3 and 7A, along the width direction W of the data line DL, the data line DL includes a first portion DL1 and a second portion DL2 adjacent to each other. The orthographic projection of the first portion DL1 on the substrate overlaps with the orthographic projection of the first overlapping structure 61 on the substrate, while the orthographic projection of the second portion DL2 on the substrate does not overlap with the orthographic projection of the first overlapping structure 61 on the substrate. The width of the data line DL in the width direction W generally defines the thickness of the data line DL and primarily affects the conductivity of the data line. A wider data line DL exhibits relatively stronger conductivity and lower loss. The width direction of the data line DL is perpendicular to the extension direction of the data line. Specifically, along the width direction of the data line DL, the orthographic projection of the first overlapping structure 61 on the substrate does not completely cover the orthographic projection of the data line on the substrate. When the first opening H1 is opened, it can simultaneously expose the first overlapping structure 61 and the data line DL located near multiple side surfaces of the first overlapping structure 61. This increases the contact area between the data line DL and the connecting structure in the first via H1, reduces contact resistance, and improves connection quality. In a specific implementation, as shown in FIG3 and FIG7A , the end portion of the first via hole H1 close to the substrate 1 may be arranged to overlap at least partially with the surface of the second portion DL2 , that is, when the first via hole H1 is opened, the first via hole H1 at least partially exposes the second portion DL2 of the data line DL, which is not limited here.

[0122] In some embodiments, as shown in FIG7A , the first overlapping structure 61 includes a third portion 611 and a fourth portion 612. The orthographic projection of the third portion 611 on the substrate overlaps with the orthographic projection of the source region 411 on the substrate. The orthographic projection of the fourth portion 612 on the substrate does not overlap with the orthographic projection of the active region 41 on the substrate. The orthographic projection of the first overlapping structure 61 on the substrate only partially overlaps with the active region 41. When the first via H1 is formed, the first via H1 can be formed as far as possible in an area where the first overlapping structure 61 and the active region 41 do not overlap, thereby making the first via H1 away from the active region 41 and avoiding over-engraving of the active region 41 when forming the first via H1. In some embodiments, the orthographic projection of the first overlapping structure 61 on the substrate can also fall entirely within the orthographic projection of the active region 41 on the substrate, that is, the area of ​​the fourth portion 612 can be set to 0, which is not limited here.

[0123] In some embodiments, as shown in Figures 3 and 7A, the first via H1 at least partially exposes the fourth portion 612 of the first overlapping structure 61, that is, the orthographic projection of the first via H1 on the substrate overlaps with at least a portion of the orthographic projection of the fourth portion 612 of the first overlapping structure 61 on the substrate. The connecting structure 81 contacts the fourth portion 612 of the first overlapping structure 61 and the second portion DL of the data line DL exposed by the first via H1, thereby achieving a connection between the first overlapping structure 61 and the data line DL. It will be understood that in a specific implementation, the orthographic projection of the first portion DL1 of the data line DL on the substrate can be set to at least partially overlap with the orthographic projection of the fourth portion 612 of the first overlapping structure 61 on the substrate.

[0124] In some embodiments, as shown in Figures 3 and 7A, the orthographic projection of the first via H1 on the substrate and the orthographic projection of the third portion 611 of the first overlapping structure 61 on the substrate do not overlap with each other, that is, the first via H1 does not expose the third portion 611 of the first overlapping structure 61, and the first via H1 is arranged away from the active area 41 not covered by the first overlapping structure 61, thereby avoiding fracture caused by over-engraving of the active area 41 when making the first via H1.

[0125] In some embodiments, as shown in FIG3 and FIG7A , the entire third portion 611 of the first overlapping structure 61 directly overlaps the surface of the source region 411, that is, the third portion 611 is in direct contact with the source region 411. The entire fourth portion 612 of the first overlapping structure 61 directly overlaps the surface of the first insulating layer 3, that is, the fourth portion 612 is in direct contact with the first insulating layer 3. In specific manufacturing, as shown in FIG4A , when an opening K is formed in the second insulating layer 5, the opening K simultaneously exposes at least a portion of the source region 411 and the surface of the first insulating layer 3 near the portion of the source region. When manufacturing the first overlapping structure 61, the first overlapping structure 61 is formed within the area exposed by the opening K, and a portion of the first overlapping structure 61 is directly overlapped with the surface of the source region 411 to form the third portion 611, and the remaining portion is directly overlapped with the surface of the first insulating layer 3 to form the fourth portion 612. The source region 411 exposed by the opening K can be conductively connected during the same step as forming the opening K in the second insulating layer 5, thereby avoiding the situation where the source region 411 in the area covered by the third portion 611 cannot be conductively connected after the first overlapping structure 61 is subsequently formed. In a specific implementation, as shown in FIG3 , the fourth portion 612 of the first overlapping structure 61 does not overlap with the sidewall of the first via H1 located in the first insulating layer 3.

[0126] FIG8 is a third schematic diagram of the cross-sectional structure of the array substrate provided in an embodiment of the present disclosure.

[0127] In some embodiments, as shown in FIG8 , the third portion 611 of the first overlapping structure 61 is directly overlapped on the surface of the source region 411 , and part of the second insulating layer 5 may be retained between the fourth portion 612 and the first insulating layer 3 , which is not limited here.

[0128] FIG9 is a third schematic diagram of the manufacturing process of the array substrate provided in an embodiment of the present disclosure.

[0129] In some embodiments, as shown in Figures 3, 6, and 8, the orthographic projection of the second insulating layer 5 on the substrate 1 is located within the orthographic projection of the second conductive layer 6 on the substrate 1. Specifically, as shown in Figure 9, a patterned second conductive layer 6 is formed on the side of the second insulating layer 5 facing away from the substrate 1. After forming the first overlapping structure 61 and the gate 62, the second insulating layer 5 is etched across its entire surface, removing the second insulating layer 5 in the areas not covered by the second conductive layer 6. This exposes the source region 411 and the drain region 413 covered by the second insulating layer 5 for conductorization. As shown in Figure 9, while etching the second insulating layer 5, the areas of the first insulating layer 3 not covered by the second insulating layer 5 and the first conductive layer 6 are also etched by the etching gas, forming a pit on the surface of the first insulating layer 3. When opening the first via, the portion of the first via located in the first insulating layer 3 can be opened within the area where the pit is located, thereby reducing the opening depth of the first via and simplifying the difficulty of opening the via. The gas used to etch the second insulating layer 5 and the gas used to make the source region 411 and the drain region 413 conductive can be the same gas, so that the etching of the second insulating layer 5 and the conductive formation of the source region 411 and the drain region 413 can be completed in a single step. For example, the etching gas can be an ion gas of boron (B), phosphorus (P), helium (He), or hydrogen (H), etc., which is not limited here.

[0130] FIG10 is a fourth schematic diagram of the cross-sectional structure of the array substrate provided in an embodiment of the present disclosure; FIG11 is a fourth schematic diagram of the manufacturing process of the array substrate provided in an embodiment of the present disclosure.

[0131] In some embodiments, as shown in FIG10 , the orthographic projection of the gate 62 on the substrate 1 is located within the orthographic projection of the second insulating layer 5 on the substrate 1. In specific production, as shown in FIG11 , the difference from FIG9 is that a patterned second conductive layer 6 is formed on the side of the second insulating layer 5 facing away from the substrate 1. After forming the first overlapping structure 61 and the gate 62, the second insulating layer 5 is not etched on the entire surface, but the second insulating layer 5 covering the surface of the source region 411 and the drain region 413 is retained. Then, by ion implantation or other methods, ions are directly implanted into the source region 411 and the drain region 413 through the second insulating layer 5 for conductorization, so that the orthographic projection of the gate 62 on the substrate 1 is finally located within the orthographic projection of the second insulating layer 5 on the substrate 1. The ions implanted into the source region 411 and the drain region 413 by ion implantation can be boron ions, phosphorus ions, etc., which are not limited here.

[0132] In some embodiments, as shown in Figures 10 and 11, the third portion 611 of the first overlapping structure 6 is spaced a certain distance d from the edge of the second insulating layer 5 on the side close to the third portion 611. This prevents the third portion 611 of the first overlapping structure 6 from overlapping the upper surface of the second insulating layer 5 during the manufacturing process, which prevents ions from being implanted into the source region 411 through the third portion 611 of the first overlapping structure 6. Similarly, in the manufacturing process shown in Figure 9, it should also be avoided that the third portion 611 of the first overlapping structure 6 overlaps the upper surface of the second insulating layer 5, resulting in the inability to etch the second insulating layer 5 below the third portion 611 during etching, and the source region 411 below this portion of the second insulating layer 5 cannot be conductively converted.

[0133] Figure 12 is the fifth schematic diagram of the cross-sectional structure of the array substrate provided in the embodiment of the present disclosure; Figure 13A is the fifth schematic diagram of the manufacturing process of the array substrate provided in the embodiment of the present disclosure; Figure 13B is the sixth schematic diagram of the manufacturing process of the array substrate provided in the embodiment of the present disclosure.

[0134] In some embodiments, as shown in Figures 12 and 7A, the height h1 of the first insulating layer 3 within the orthographic projection coverage area of ​​the fourth portion 612 is lower than the height h2 of the first insulating layer 3 within the orthographic projection coverage area of ​​the third portion 611. During specific fabrication, as shown in Figure 13A, after forming a second insulating layer 5 on the side of the semiconductor layer 4 facing away from the substrate 1, the second insulating layer 5 is etched to form an opening K that penetrates the second insulating layer. Each opening K simultaneously exposes at least a portion of the source region 411 of an active region 41 and a portion of the first insulating layer 3 surrounding the source region 411. The orthographic projection of the opening K on the substrate 1 at least partially overlaps with the orthographic projection of the data line DL on the substrate 1. During the step of etching the second insulating layer 5, after the opening K exposes the first insulating layer 3, the first insulating layer 3 exposed by the opening K is further etched using an etching gas to form a recess R having a certain depth, thereby thinning the first insulating layer 3 within the region of the recess R. During the process of thinning the first insulating layer 3 in the recessed portion R, the etching gas simultaneously conducts the source region 411 exposed by the opening K, and the etching gas etches the source region 411 exposed by the opening K. In order to avoid etching the source region 411 too thin in this process, the depth of the recessed portion R should not be too large to ensure that the source region 411 retains sufficient thickness, so that the thickness of the source region 411 can pass through subsequent manufacturing processes without generating fractures.

[0135] As shown in Figures 13A and 13B, the subsequent manufacturing process includes sequentially manufacturing the second insulating layer 5, the second conductive layer 6, the third insulating layer 7, and the third conductive layer 8 according to the process flow. The relevant process flow can be referred to the description of the aforementioned content and will not be repeated here. The difference is that, when the first insulating layer 3 exposed by the opening K is etched, the first insulating layer 3 below the source region 411 is protected by the source region 411 from being etched, resulting in the height of the first insulating layer 3 below the source region 411 being greater than the height of the first insulating layer 3 exposed by the opening K after being etched. Therefore, after the first overlapping structure 61 is formed, the height h1 of the first insulating layer 3 within the orthographic projection coverage area of ​​the fourth portion 612 is lower than the height h2 of the first insulating layer 3 within the orthographic projection coverage area of ​​the third portion 611. In addition, when opening the first via H1 for exposing the first overlapping structure 61 and the data line DL, the orthographic projection of the portion of the first via H1 located in the first insulating layer 3 on the substrate 1 can be set to be within the orthographic projection of the recessed portion R on the substrate 1. Since the thickness of the first insulating layer 3 in the area where the recessed portion R is located is relatively thin, it is beneficial to reduce the difficulty of manufacturing the first via H1.

[0136] In some embodiments, the first insulating layer includes a recessed region. The recessed region is adjacent to the portion of the first via located in the first insulating layer. The height of the first insulating layer in the recessed region is less than the height of the first insulating layer in the area covered by the orthographic projection of the fourth portion. In a specific manufacturing process, as shown in FIG13B , after the second conductive layer 6 is manufactured and before the third insulating layer 7 is formed, the second insulating layer 5 can be etched on the entire surface, and the active area 41 exposed after the entire surface of the second insulating layer 5 is etched with an etching gas to be conductorized. During the entire surface etching of the second insulating layer 5, the portion of the first insulating layer 3 exposed by the second insulating layer 5 and the second conductive layer 6 is etched simultaneously to form a pit S1. The first insulating layer 3 in the area corresponding to the pit S1 is further thinned, reducing the thickness of the first insulating layer 3 in this area. Specifically, the height h3 of the first insulating layer 3 in the area corresponding to the pit S1 is less than the height h1 of the first insulating layer 3 in the area covered by the orthographic projection of the fourth portion of the first overlapping structure 61. When forming the first via hole H1, the portion of the first via hole H1 located in the first insulating layer 3 can be formed within the region where the pit S1 is located, thereby further reducing the difficulty of forming the first via hole H1 later. In some embodiments, the opening area of ​​the first via hole H1 in the first insulating layer 3 is smaller than the area where the pit S1 is located. After the first via hole H1 is formed in the region corresponding to the pit S1, the first insulating layer 3 in the region corresponding to the pit S1 is completely etched, thereby forming the portion of the first via hole H1 in the first insulating layer 3. The first insulating layer 3 in the region corresponding to the pit S1 is not completely etched and is retained, forming a recessed region S2 adjacent to the first via hole H1.

[0137] In some embodiments, as shown in FIG13B , the first via hole H1 in the first insulating layer 3 is provided on a side of the pit S1 that is close to the first overlapping structure 61. Therefore, the first insulating layer 3 in a portion corresponding to the portion of the pit S1 that is away from the first overlapping structure 61 is retained, forming a recessed region S2 adjacent to the first via hole H1. Specifically, the recessed region S2 is located on a side of the first via hole H1 that is away from the first overlapping structure 61. In specific implementations, the position of the recessed region S2 may vary depending on the position of the first via hole H1 in the pit S1. For example, the recessed region S2 may be provided around the first via hole H1 in the first insulating layer 3, although this is not limited herein.

[0138] In some embodiments, the area where the first via hole H1 is disposed in the first insulating layer 3 completely overlaps with the area of ​​the pit S1 , which is not limited here.

[0139] In some embodiments, the third conductive layer 8 also includes a pixel electrode. Specifically, the connection structure 81 can be made in the same film layer as the pixel electrode. During the specific production, the pattern of the connection structure 8 and the pattern of the pixel electrode are simultaneously formed in the third conductive layer 8 through a patterning process, which is conducive to reducing the film layer structure and simplifying the process steps. In specific implementation, the array substrate can be used to produce LCD display panels, OLED display panels or Micro LED display panels, etc., which are not limited here. When the array substrate is used to make an LCD display panel, the pixel electrode can form a display device with the common electrode and the liquid crystal located between the pixel electrode and the common electrode. When the array substrate is used to make an OLED display panel, the pixel electrode can serve as the anode of the OLED device. When the array substrate is used to make a Micro LED display panel, the pixel electrode can serve as a pad for welding the Micro LED device. In specific implementation, the specific function of the pixel electrode can be adjusted according to the type of display panel used to make the array substrate, which will not be described in detail here.

[0140] FIG14 is a sixth schematic diagram of the cross-sectional structure of the array substrate provided in an embodiment of the present disclosure.

[0141] Figure 14 illustrates the structure of an array substrate using an example of an array substrate used to manufacture an LCD display panel. As shown in Figure 1 , when the array substrate is used to manufacture an LCD display panel, typically only one transistor TR is required in a pixel circuit PX. As shown in Figure 14 , the data line DL is connected to the first bridging structure 61 via a connection structure 81, and further connected to the transistor TR via the first bridging structure 61. The drain of the transistor TR is electrically connected to the pixel electrode P. Specifically, the pixel electrode P is electrically connected to the drain region 413 corresponding to the transistor TR via a second via H2 that penetrates the third insulating layer 7. In some embodiments, the pixel electrode P directly bridging the surface of the drain region 413 via the second via H2 that penetrates the third insulating layer 7, thereby directly contacting the drain region 413. In some embodiments, the second conductive layer 6 further includes a second bridging structure 63, which is located between the pixel electrode P and the drain region 413. The pixel electrode P and the drain region 413 are connected via the second bridging structure 63. The second overlap structure 63 can be produced simultaneously when the second conductive layer 6 is patterned to produce the first overlap structure 61 and the gate 62. The second overlap structure 63 can protect the drain region 413 in the via hole for opening the second via hole 2 in the third insulating layer 7, thereby avoiding over-etching of the drain region 413. The second overlap structure 63 can also be used to reduce the contact resistance between the pixel electrode and the drain region 413, thereby improving signal transmission efficiency.

[0142] When the array substrate is used to manufacture an LCD display panel, the transistor TR in the pixel circuit PX of the array substrate is usually used as a switching transistor. The material of the semiconductor layer 4 can be an oxide semiconductor, which is conducive to improving the switching performance of the transistor. The material of the semiconductor layer 4 can also be other materials, which are not limited here.

[0143] In the embodiment of the present disclosure, the LCD display panel includes an array substrate and an opposite substrate arranged opposite to the array substrate, and liquid crystal layers are arranged in the array substrate and the opposite substrate.

[0144] In some embodiments, as shown in FIG14 , the pixel electrode P is fabricated in the array substrate, and the common electrode is fabricated in the counter substrate. The LCD display panel may be a twisted nematic (TN) type or a vertical alignment (VA) type LCD display panel, which is not limited here.

[0145] FIG15A is the seventh schematic diagram of the cross-sectional structure of the array substrate provided in the embodiment of the present disclosure; FIG15B is the eighth schematic diagram of the cross-sectional structure of the array substrate provided in the embodiment of the present disclosure.

[0146] In some embodiments, as shown in Figures 15A and 15B, the array substrate further includes a fourth conductive layer 10 and a fourth insulating layer 9 located between the fourth conductive layer 10 and the third conductive layer 8, wherein a common electrode C is provided in the fourth conductive layer 10, so that the pixel electrode P and the common electrode C can be provided in the array substrate. The array substrate can be used to manufacture LCD display panels of types such as in-plane switching (IPS), advanced-super dimension switch (ADS) or high advanced-super dimension switch (HADS), which are not limited here.

[0147] In some embodiments, as shown in FIG. 15A , the fourth insulating layer 9 is located on a side of the third conductive layer 8 facing away from the substrate 1 , and the fourth conductive layer 10 is located on a side of the fourth insulating layer 9 facing away from the third conductive layer 8 .

[0148] In some embodiments, as shown in FIG15B , the fourth conductive layer 10 is located between the third insulating layer 7 and the third electrode layer 8, the fourth insulating layer 9 is located on a side of the fourth conductive layer 10 facing away from the third insulating layer 7, and the third conductive layer 8 is located on a side of the fourth insulating layer 9 facing away from the fourth conductive layer 10. The first via hole H1 and the second via hole H1 also penetrate the fourth insulating layer 9, respectively.

[0149] FIG16 is a second schematic diagram of the circuit structure of the array substrate provided in an embodiment of the present disclosure.

[0150] When an array substrate is used to manufacture an OLED display panel or a Micro LED display panel, as shown in FIG14 , a pixel circuit PX typically includes at least two transistors TR. In specific implementations, not all of the multiple transistors TR in the same pixel circuit PX need to be connected to the data line DL. It is understood that in the array substrate provided by the present disclosure, when the transistors TR in the same pixel circuit PX are connected to the data line DL, they can be connected via a first bridge structure 61 to avoid disconnection. For example, as shown in FIG14 , in a typical 2T1C pixel circuit, two transistors TR and a storage capacitor Cst are included, wherein the source of the first transistor TR1 is connected to the data line DL, the gate of the first transistor TR1 is connected to the scan line GL, the drain of the first transistor TR1 is connected to the gate of the second transistor TR2 and one end of the storage capacitor Cst, and the other end of the storage capacitor Cst is connected to the pixel electrode P. The source of the second transistor TR2 is connected to the power signal line Vdd, and the drain of the second transistor TR2 is connected to the pixel electrode P. The first transistor TR1 acts as a switch, also known as a switching transistor, and the second transistor TR2 acts as a driver, also known as a driver transistor. The data line DL is usually connected to the switching transistor. In a specific implementation, a source region corresponding to the switching transistor that needs to be connected to the data line DL can be set, such as the source region corresponding to the first transistor TR1 in the figure, which is connected to the data line through a first overlap structure and a connection structure. Other transistors in the pixel circuit that do not need to be connected to the data line can be connected in a conventional manner. A pixel circuit PX can also include other numbers of transistors to achieve special functions, which are not limited here. Since the transistor connected to the data line is usually a switching transistor, the material of the semiconductor layer corresponding to the transistor connected to the data line can be set to an oxide semiconductor to improve the switching performance of the switching transistor. In some embodiments, on the basis of setting the semiconductor layer corresponding to the switching transistor as an oxide semiconductor layer, a layer of low-temperature polysilicon semiconductor layer can also be set in the array substrate to be used for making a driving transistor to improve the driving performance, which is not limited here.

[0151] Figure 17A is the ninth schematic diagram of the cross-sectional structure of the array substrate provided in an embodiment of the present disclosure; Figure 17B is the tenth schematic diagram of the cross-sectional structure of the array substrate provided in an embodiment of the present disclosure; and Figure 17C is the eleventh schematic diagram of the cross-sectional structure of the array substrate provided in an embodiment of the present disclosure.

[0152] In some embodiments, as shown in Figures 17A to 17C, the third conductive layer 8 further includes a common electrode C. Specifically, the connection structure 81 can be made in the same film layer as the common electrode C. During the specific production, the pattern of the connection structure 81 and the pattern of the common electrode C are simultaneously formed on the third conductive layer 8 through a patterning process, thereby facilitating the reduction of the film layer structure and simplifying the process steps. In specific implementation, the pixel electrode can also be made in the array substrate to form a capacitor structure with the common electrode. The array substrate can be used to make an LCD display panel, specifically an in-plane switching (IPS) type, an advanced super dimension switch (ADS) type, or a high advanced super dimension switch (HADS) type LCD display panel, which is not limited here.

[0153] In some embodiments, as shown in FIG17A , the drain region 413 of the active region 41 can be reused as the pixel electrode P, thereby eliminating the need for a separate conductive film layer for fabricating the pixel electrode P, thereby reducing the number of film layers and fabrication difficulty.

[0154] 17B and 16C , the array substrate further includes a fifth conductive layer 12 and a fifth insulating layer 11 between the fifth conductive layer 12 and the third conductive layer 8 . The pixel electrode P is disposed in the fifth conductive layer 12 .

[0155] 17B , the fifth conductive layer 12 is located on a side of the third conductive layer 8 facing away from the substrate 1. The second via H2 also penetrates the fifth insulating layer 11. The pixel electrode P is electrically connected to the drain region 413 through the second via H2.

[0156] 17C , the fifth conductive layer 12 is located between the third insulating layer 7 and the third conductive layer 8. The first via hole H1 also penetrates the fifth insulating layer 11. The pixel electrode P is electrically connected to the drain region 413 through the second via hole H2.

[0157] In some embodiments, as shown in Figures 17B and 16C, the second conductive layer 6 further includes a second overlapping structure 63. The second overlapping structure 63 is located between the pixel electrode P and the drain region 413 and is used to connect the pixel electrode P and the drain region 413. The configuration and function of the second overlapping structure 63 can be referred to above and will not be described in detail here.

[0158] FIG18 is a twelfth schematic diagram of the cross-sectional structure of the array substrate provided in an embodiment of the present disclosure.

[0159] In some embodiments, as shown in FIG18 , the first conductive layer 2 further includes a light-shielding region 21. The orthographic projection of the channel region 412 on the substrate 1 is located within the orthographic projection of the light-shielding region 21 on the substrate 1. The light-shielding region 21 is used to block light directed toward the channel region 412 from the side of the substrate 1 facing away from the channel region 412, thereby reducing leakage current caused by light exposure in the transistor and improving transistor performance.

[0160] In the embodiment of the present disclosure, the orthographic projection of the channel region 412 on the substrate 1 is located within the orthographic projection of the gate 62 on the substrate 1 to improve the gate control capability of the transistor. The doping concentration of the source region and the doping concentration of the drain region are both greater than the doping concentration of the channel region to ensure that the source region and the drain region have high conductivity.

[0161] The array substrate provided in the embodiment of the present disclosure also includes some structures necessary to realize specific functions. During specific implementation, the specific structure of the array substrate can be adjusted according to the setting method in the relevant technology, which will not be described in detail here.

[0162] The present disclosure also provides a display panel. The display panel includes the array substrate provided by any of the aforementioned embodiments. The display panel provided by the present disclosure, when implemented, has the same or similar technical effects as the array substrate provided by the aforementioned embodiments, and thus is not further described here.

[0163] The present disclosure also provides a display device. The display device includes the display panel provided by any of the aforementioned embodiments. The display device provided by the present disclosure, when implemented, has the same or similar technical effects as the display panel provided by the aforementioned embodiments, and is not further described here. In a specific implementation, the display device can be a mobile phone, television, tablet computer, laptop computer, display, monitor, or other device with a display function, and is not further described here.

[0164] FIG19 is a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present disclosure.

[0165] The present disclosure also provides a method for manufacturing an array substrate. As shown in FIG19 , the method includes the following steps:

[0166] S191: forming a first conductive layer on a substrate; the first conductive layer includes a data line;

[0167] S192: forming a first insulating layer on a side of the first conductive layer facing away from the substrate;

[0168] S193: forming a semiconductor layer on a side of the first insulating layer facing away from the substrate; the semiconductor layer includes a plurality of active regions, each active region is used to form a transistor; the active region is divided into a channel region and a source region and a drain region respectively located on both sides of the channel region;

[0169] S194: forming a second insulating layer on a side of the semiconductor layer facing away from the substrate; the second insulating layer and at least a portion of the source region do not overlap with each other;

[0170] S195: forming a second conductive layer on a side of the second insulating layer facing away from the substrate; the second conductive layer includes a first overlapping structure and a gate of the transistor; the first overlapping structure at least partially overlaps a surface of a portion of the source region that does not overlap with the second insulating layer;

[0171] S196: forming a third insulating layer on a side of the second conductive layer facing away from the substrate, and forming a first via hole for exposing the first bonding structure and the data line;

[0172] S197: forming a third conductive layer on a side of the third insulating layer facing away from the substrate; the third conductive layer includes a connecting structure; the connecting structure connects the first overlapping structure to the data line through a first via hole.

[0173] The manufacturing method of the array substrate provided by the present disclosure, during specific implementation, is provided with a first overlapping structure on the surface of the source region. The first overlapping structure is connected to the data line via a connecting structure. This is beneficial for avoiding over-etching of the active region during the etching of the first insulating layer when opening the first via hole, thereby avoiding disconnection of the active region and the inability to connect the data line to the transistor, thereby improving the product yield.

[0174] In some embodiments, the specific process of forming a second insulating layer on the side of the semiconductor layer facing away from the substrate includes: forming the second insulating layer on the side of the semiconductor layer facing away from the substrate; then etching the second insulating layer to open an opening through the second insulating layer. One opening simultaneously exposes at least a portion of the source region of an active area and a portion of the first insulating layer surrounding the source region, and the orthographic projection of the opening on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate. Continue etching the first insulating layer exposed by the opening to form a recessed portion on the surface of the first insulating layer. The specific process of opening a first via hole for exposing the first overlapping structure and the data line includes: opening a first via hole for exposing the first overlapping structure and the data line, wherein the orthographic projection of the portion of the first via hole located in the first insulating layer on the substrate is located within the orthographic projection of the recessed portion on the substrate.

[0175] The specific structure of the array substrate provided by the present disclosure and the manufacturing process related to the specific structure of the array substrate have been described in detail in the aforementioned embodiments of the array substrate. When implementing the manufacturing method of the array substrate provided by the present disclosure, reference can be made to the relevant records about the array substrate structure in the aforementioned content of the present disclosure, and no further details will be given here.

[0176] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0177] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. An array substrate, wherein: include: substrate; a first conductive layer, located on the substrate; The first conductive layer includes a data line; a first insulating layer, located on a side of the first conductive layer facing away from the substrate; a semiconductor layer located on a side of the first insulating layer facing away from the substrate; the semiconductor layer comprising a plurality of active regions, one of the active regions being used to form a transistor; and one of the active regions being divided into a channel region and a source region and a drain region respectively located on both sides of the channel region; a second insulating layer, located on a side of the semiconductor layer facing away from the substrate; the second insulating layer and at least a portion of the source region do not overlap with each other; a second conductive layer, located on a side of the second insulating layer facing away from the substrate; the second conductive layer includes a gate of the transistor and a first lap structure; The first overlapping structure at least partially overlaps the surface of the source region at a portion that does not overlap with the second insulating layer; a third insulating layer, located on a side of the second conductive layer facing away from the substrate; a third conductive layer, located on a side of the third insulating layer facing away from the substrate; the third conductive layer includes a connecting structure; The array substrate is provided with a first via hole that at least penetrates the third insulating layer and the first insulating layer; the connecting structure is at least partially located in the first via hole, connecting the data line to the first bonding structure; The data line is connected to the active area through the connecting structure and the first overlapping structure.

2. The array substrate according to claim 1, wherein: An orthographic projection of the first overlapping structure on the substrate overlaps with an orthographic projection of the data line connected to the first overlapping structure on the substrate.

3. The array substrate according to claim 2, wherein: Along the width direction of the data line, the data line includes a first portion and a second portion adjacent to each other; wherein an orthographic projection of the first portion on the substrate overlaps with an orthographic projection of the first overlapping structure on the substrate, and an orthographic projection of the second portion on the substrate does not overlap with an orthographic projection of the first overlapping structure on the substrate; An end portion of the first via hole close to the substrate at least overlaps a portion of a surface of the second portion.

4. The array substrate according to any one of claims 1 to 3, wherein: The first overlapping structure includes a third portion and a fourth portion; the orthographic projection of the third portion on the substrate overlaps with the orthographic projection of the source region on the substrate; An orthographic projection of the fourth portion on the substrate does not overlap with an orthographic projection of the active region on the substrate.

5. The array substrate according to claim 4, wherein: The first via hole at least partially exposes the fourth portion of the first overlapping structure; an orthographic projection of the first via hole on the substrate and an orthographic projection of the third portion on the substrate do not overlap with each other.

6. The array substrate according to claim 4 or 5, wherein: The entire third portion is directly overlapped on the surface of the source region; the entire fourth portion is directly overlapped on the surface of the first insulating layer.

7. The array substrate according to claim 6, wherein: The fourth portion does not overlap with a sidewall of the first via hole in the first insulating layer.

8. The array substrate according to claim 6 or 7, wherein: An orthographic projection of the second insulating layer on the substrate is located within an orthographic projection of the second conductive layer on the substrate.

9. The array substrate according to claim 8, wherein: The first insulating layer includes a recessed area; the recessed area is adjacent to a portion of the first via located in the first insulating layer; a height of the first insulating layer within the recessed area is less than a height of the first insulating layer within an area covered by an orthographic projection of the fourth portion.

10. The array substrate according to claim 6 or 7, wherein: The orthographic projection of the gate on the substrate is located within the orthographic projection of the second insulating layer on the substrate; The third portion is spaced a certain distance from an edge of the second insulating layer on a side close to the third portion.

11. The array substrate according to any one of claims 6 to 10, wherein: A height of the first insulating layer within an orthographic projection coverage area of ​​the fourth portion is lower than a height of the first insulating layer within an orthographic projection coverage area of ​​the third portion.

12. The array substrate according to any one of claims 1 to 11, wherein: The third conductive layer further includes a pixel electrode; the pixel electrode is electrically connected to the drain region through a second via hole penetrating the third insulating layer.

13. The array substrate according to claim 11, wherein: The array substrate further includes a fourth conductive layer and a fourth insulating layer located between the fourth conductive layer and the third conductive layer; The fourth conductive layer includes a common electrode.

14. The array substrate according to any one of claims 1 to 12, wherein: The third conductive layer further includes a common electrode; The drain region is reused as a pixel electrode.

15. The array substrate according to claim 13, wherein: The third conductive layer further includes a common electrode; The array substrate further includes a fifth conductive layer and a fifth insulating layer located between the fifth conductive layer and the third conductive layer; The fifth conductive layer further includes a pixel electrode, and the pixel electrode is connected to the drain region through a third via hole that at least penetrates the third insulating layer.

16. The array substrate according to claim 12, 13 or 15, wherein: The second conductive layer further includes a second overlapping structure; the second overlapping structure is located between the pixel electrode and the drain region, and is used for connecting the pixel electrode and the drain region.

17. The array substrate according to any one of claims 1 to 16, wherein: The first conductive layer further includes a light-shielding area; the orthographic projection of the channel area on the substrate is located within the orthographic projection of the light-shielding area on the substrate; The orthographic projection of the channel region on the substrate is located within the orthographic projection of the gate on the substrate; The doping concentration of the source region and the doping concentration of the drain region are both greater than the doping concentration of the channel region; The material of the semiconductor layer is oxide semiconductor.

18. A display panel, wherein: It comprises the array substrate according to any one of claims 1 to 17.

19. A method for manufacturing an array substrate, wherein: include: forming a first conductive layer on a substrate; The first conductive layer includes a data line; forming a first insulating layer on a side of the first conductive layer facing away from the substrate; A semiconductor layer is formed on a side of the first insulating layer facing away from the substrate; the semiconductor layer includes a plurality of active regions, each active region is used to form a transistor; the active region is divided into a channel region and a source region and a drain region respectively located on both sides of the channel region; forming a second insulating layer on a side of the semiconductor layer facing away from the substrate; wherein the second insulating layer and at least a portion of the source region do not overlap with each other; forming a second conductive layer on a side of the second insulating layer facing away from the substrate; the second conductive layer includes a first overlapping structure and a gate of the transistor; The first overlapping structure at least partially overlaps the surface of the source region at a portion that does not overlap with the second insulating layer; forming a third insulating layer on a side of the second conductive layer facing away from the substrate, and defining a first via hole for exposing the first bonding structure and the data line; A third conductive layer is formed on a side of the third insulating layer facing away from the substrate; the third conductive layer includes a connecting structure; and the connecting structure connects the first overlapping structure to the data line through the first via hole.

20. The method of claim 19, wherein: The forming of a second insulating layer on a side of the semiconductor layer facing away from the substrate specifically includes: forming a second insulating layer on a side of the semiconductor layer facing away from the substrate; Etching the second insulating layer to form an opening penetrating the second insulating layer; wherein the opening simultaneously exposes at least a portion of the source region of one of the active areas and a portion of the first insulating layer surrounding the source region, and an orthographic projection of the opening on the substrate at least partially overlaps with an orthographic projection of the data line on the substrate; Continue etching the first insulating layer exposed by the opening to form a recessed portion on the surface of the first insulating layer; The first via hole for exposing the first bonding structure and the data line specifically includes include: A first via hole is opened to expose the first overlapping structure and the data line, wherein an orthographic projection of a portion of the first via hole located in the first insulating layer on the substrate is located within an orthographic projection of the recessed portion on the substrate.

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