Memory expansion board and memory expansion method

Abstract

The present application relates to the technical field of the design of storage devices. Disclosed are a memory expansion board and a memory expansion method. The memory expansion board comprises a memory expansion processing chip, a CDFP module, a gold finger connector and a memory module, wherein the memory expansion processing chip comprises CXL signal interfaces; a first transmission interface set of the CDFP module is connected to the CXL signal interfaces, and a second transmission interface set of the CDFP module is connected to an external host device in a wired manner; a third transmission interface set of the gold finger connector is connected to the CXL signal interfaces, and a fourth transmission interface set of the gold finger connector is connected to the host device; and both the CDFP module and the gold finger connector can be used for CXL message data transmission between the host device and the memory expansion board. The memory expansion board in the present application realizes an expanded function of external interconnection on the basis of internal interconnection, and can access a plurality of host devices and perform CXL message data transmission with same.

Description

Memory expansion board and memory expansion method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on March 29, 2024, with application number 202410374181.8, and application name “A Memory Expansion Board and Memory Expansion Method”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the technical field of storage device design, and in particular to a memory expansion board and a memory expansion method. Background Art

[0004] With the continuous development of high-performance computing and AI (Artificial Intelligence) computing, computer systems have placed higher requirements on storage capacity and latency.

[0005] Currently, storage boards that use the CXL (Compute Express Link, processor-to-peripheral / accelerator link protocol) protocol use a memory expansion processing chip as the memory expansion controller chip. The CXL port of the memory expansion processing chip has an x8 bandwidth, and the CXL signal of the memory expansion processing chip interacts with the outside world through the x8 gold finger. This is limited to interconnection within a single machine, and its application form is limited to single-host device access, and cannot support scenarios where multiple host devices access it. Summary of the Invention

[0006] In view of this, the present application provides a memory expansion board and a memory expansion method to solve the problem of not supporting multi-host device access.

[0007] In a first aspect, the present application provides a memory expansion board, comprising a memory expansion processing chip, a CDFP (CDFP connector and cable assembly) module, a gold finger connector, and a memory module, wherein the memory expansion processing chip is connected to the memory module;

[0008] The memory expansion processing chip includes a CXL signal interface;

[0009] The CDFP module includes a first transmission interface set and a second transmission interface set, and the gold finger connector includes a third transmission interface set and a fourth transmission interface set;

[0010] The CDFP module is connected to the CXL signal interface of the memory expansion processing chip through the first transmission interface set, and the gold finger connector is connected to the CXL signal interface of the memory expansion processing chip through the third transmission interface set;

[0011] The CDFP module is wiredly connected to at least one external host device via a second transmission interface set, the first transmission interface set being used to receive CXL message data transmitted from the CXL signal interface, and the second transmission interface set being used to transmit the CXL message data to the host device;

[0012] The gold finger connector is internally connected to at least one host device via a fourth transmission interface set. The third transmission interface set is used to receive CXL message data transmitted from the CXL signal interface. The fourth transmission interface set is used to transmit the CXL message data to the host device.

[0013] Related technology: Memory devices using the CXL protocol can only interact with the outside world through the x8 (8-channel) gold finger connector, are limited to interconnection within a single machine, and the application form is limited to access by a single host device, and cannot support scenarios where multiple host devices access. The present application innovates to the above problems and provides a memory expansion board that uses a memory expansion processing chip. The memory expansion processing chip includes a CXL signal interface. The memory expansion board is equipped with a CDFP module. It receives CXL message data transmitted by the CXL signal interface through a first transmission interface set and transmits the CXL message data to the host device through a second transmission interface set. The second transmission interface set is wired to at least one external host device, breaking through the limitations of interconnection within a single machine and can interact with multiple host devices, effectively solving the above problems.

[0014] The memory expansion board is equipped with a gold finger connector that allows for CXL message data transmission within the device. The third transmission interface of the gold finger connector connects to the CXL signal interface of the memory expansion processing chip, and the fourth transmission interface connects to the host device, transmitting CXL message data output from the CXL signal interface to the host device. The memory expansion board can interact with the external host device through the CDFP module and also interact with the host device internally through the gold finger connector.

[0015] In some embodiments of the present application, the gold finger connector is a x16 gold finger connector.

[0016] The gold finger connector used in the memory expansion board is expanded on the basis of the common x8 gold finger connector. This application uses an x16 gold finger connector to expand the signal path and effectively solve the problem of insufficient memory bandwidth.

[0017] In some embodiments of the present application, the memory module includes one or more DDR5 slots;

[0018] The memory expansion processing chip also includes 2n DIMM (Dual Inline Memory Module) controller interfaces, where n is ≥ 1 and is a positive integer;

[0019] The 2n DIMM controller interfaces of the memory expansion processing chip are used to connect to the DDR5 slots.

[0020] The current memory expansion board can only expand two DDR5 (double data rate fifth-generation synchronous dynamic random-access memory) slots through the chip's controller port; the memory expansion board provided in this application is expanded through the DIMM controller interface and DIMM slots, and can connect to more than two DDR5 memory sticks. Compared with the original board that can only connect to two DDR5 memory sticks, it significantly increases the memory capacity.

[0021] In some embodiments of the present application, the memory module is used for data caching and data reading and writing.

[0022] The memory module is used to provide data cache and data read and write functions for CXL message data communication and information interaction between modules within the board.

[0023] In some embodiments of the present application, the memory expansion board further includes an I2C module;

[0024] The I2C module is connected to the memory expansion processing chip, and is used to collect data information and temperature information of the memory module connected to the memory expansion processing chip.

[0025] The I2C module obtains the data transmission status of the memory module through the I2C communication protocol, thereby confirming the data polling mechanism. The collected temperature data information can adjust the fan speed according to the actual temperature.

[0026] In some embodiments of the present application, the I2C module includes an I2C signal expansion module, which is used to expand additional connection interfaces to connect with the memory expansion processing chip.

[0027] The I2C signal expansion module is used to expand general-purpose I / O ports, expanding them into 8 or 16-bit GPIOs via I2C. In this solution, it is used to expand additional I / O ports to connect to the memory expansion processing chip, enabling interrupt and operating status information exchange.

[0028] The I2C signal expansion module expands the signal path of the I2C module, allowing the I2C module to communicate with multiple modules through the I2C signal expansion module, thereby increasing the communication quantity of the I2C module and effectively improving the communication efficiency between modules.

[0029] In some embodiments of the present application, the memory expansion board further includes a clock module;

[0030] The clock module is connected to the memory expansion processing chip. The clock module is used to provide a reference clock signal when the CDFP module transmits CXL message data to the host device through the second transmission interface set, and is also used to provide a reference clock signal when the gold finger connector transmits CXL message data to the host device through the fourth transmission interface set.

[0031] The clock module provides a reference clock signal when CXL message data is transmitted between the memory expansion processing chip and the CDFP module and the gold finger connector, ensuring that the CXL message data has stable clock signal support during transmission.

[0032] In some embodiments of the present application, the memory expansion board further includes a CPLD (Complex Programming Logic Device) module;

[0033] The CPLD module is connected to the CDFP module, the memory expansion processing chip and the gold finger connector respectively;

[0034] The CPLD module is used to receive the I2C signal of the CDFP module and the gold finger connector to perform the power-on operation when the system is powered on, and is used to send the reset signal of the CDFP module and the gold finger connector to the memory expansion processing chip after delay processing to reset the memory expansion processing chip.

[0035] The CPLD module is responsible for the intelligent power-on and power-off management of the entire board. After receiving the power input from the connector module, it completes the board power-on action and simultaneously receives the control signal from the host device to realize information acquisition and control management functions.

[0036] In some embodiments of the present application, the memory expansion board further includes an SPI (SDH Physical Interface) flash memory module;

[0037] The memory expansion processing chip is connected to the SPI flash memory module. The SPI flash memory module is used to store firmware programs. The firmware programs are used to execute CXL message communication between the memory expansion processing chip and the CPLD module.

[0038] The SPI flash memory module stores firmware programs, which are used to execute CXL message communication between the memory expansion processing chip and the CPLD module. By burning the firmware through the SPI flash memory module, other firmware programs can be implanted into the memory expansion processing chip.

[0039] In some embodiments of the present application, the memory expansion board further includes a voltage level conversion module;

[0040] The voltage level conversion module is connected between the CPLD module and the memory expansion processing chip. The voltage level conversion module is used to receive the input signal of the CPLD module, convert the first voltage domain of the input signal of the CPLD module, generate an input signal of the second voltage domain, and transmit the input signal of the second voltage domain to the memory expansion processing chip.

[0041] The CPLD module is used to manage power on and off. The voltage level conversion module receives the input signal of the CPLD module, converts the first voltage domain of the input signal of the CPLD module, generates an input signal of the second voltage domain, and transmits the input signal of the second voltage domain to the memory expansion processing chip. After the voltage domain conversion, the signal input to the memory expansion processing chip prevents the memory expansion processing chip from being damaged by excessive high voltage shock.

[0042] In some embodiments of the present application, the memory expansion board further includes an expansion connector;

[0043] The expansion connector is connected to the memory expansion processing chip, and the expansion connector is used to interact with external devices after connection.

[0044] The expansion connector is connected to the memory expansion processing chip as an expansion interface. The external device is connected to the expansion connector, and the external device interacts with the memory expansion processing chip.

[0045] In some embodiments of the present application, the memory expansion board further includes a clock processing module and a differential signal module;

[0046] The clock module is connected to the memory expansion processing chip through the clock processing module. The clock processing module is used to receive the differential signal from the differential signal module and then perform frequency division. It is also used to de-jitter the reference clock signal output by the clock module.

[0047] The differential signal module inputs the differential signal as the signal source. The clock processing module divides the differential signal after receiving it, transmits the divided signal to the clock module, and de-jitters the reference clock signal output by the clock module to ensure the accuracy of the reference clock signal.

[0048] In some embodiments of the present application, the memory expansion board further includes a first multiplexer;

[0049] The first multiplexer includes a first signal selection interface and a second signal selection interface;

[0050] The CDFP module is connected to the CXL signal interface via the first signal selection interface;

[0051] The gold finger connector is connected to the CXL signal interface through the second signal selection interface.

[0052] In some embodiments of the present application, the memory expansion board further includes a second multiplexer;

[0053] The second multiplexer includes a third signal selection interface and a fourth signal selection interface;

[0054] The CDFP module is connected to the CXL signal interface via the third signal selection interface;

[0055] The gold finger connector is connected to the CXL signal interface through the fourth signal selection interface.

[0056] In a second aspect, the present application provides a method for memory expansion between multiple host devices, the method comprising:

[0057] When multiple external host devices are connected to the CDFP module, the CPLD module controls the first signal selection interface of the first multiplexer to be connected to the third signal selection interface of the second multiplexer;

[0058] The CXL signal interface of the memory expansion processing chip outputs CXL message data;

[0059] The first transmission interface set of the CDFP module receives CXL message data;

[0060] After the first transmission interface set receives the CXL message data, the second transmission interface set of the CDFP module transmits the CXL message data to the external host device via wired transmission;

[0061] After the external host device connected to the CDFP module receives the CXL message data, the data is transmitted to the memory module via a wired manner through the second transmission interface set, the first transmission interface set, the CXL signal interface, and the DIMM controller interface. The external host device and the memory expansion board complete the memory expansion.

[0062] In some embodiments of the present application, the memory expansion method between multiple host devices further includes:

[0063] When multiple external host devices are connected to the gold finger connector, the CPLD module controls the second signal selection interface of the first multiplexer to be connected to the fourth signal selection interface of the second multiplexer;

[0064] The CXL signal interface of the memory expansion processing chip outputs CXL message data;

[0065] The third transmission interface set of the gold finger connector receives CXL message data;

[0066] After the first transmission interface set receives the CXL message data, the second transmission interface set of the CDFP module transmits the CXL message data to the external host device via wired transmission;

[0067] After the host device connected to the gold finger connector receives the CXL message data, the data is transmitted to the memory module through the fourth transmission interface set, the third transmission interface set, the CXL signal interface, and the DIMM controller interface in sequence, and the external host device and the memory expansion board complete the memory expansion.

[0068] In some embodiments of the present application, the memory expansion method between multiple host devices further includes:

[0069] When multiple external host devices are connected to the CDFP module and the gold finger connector at the same time, the CPLD module controls the second signal selection interface of the first multiplexer to be connected to the third signal selection interface of the second multiplexer;

[0070] The CXL signal interface of the memory expansion processing chip outputs CXL message data;

[0071] The third transmission interface set of the gold finger connector receives CXL message data;

[0072] After the first transmission interface set receives the CXL message data, the second transmission interface set of the CDFP module transmits the CXL message data to the external host device via wired transmission;

[0073] After the external host device connected to the CDFP module receives the CXL message data, the data is transmitted to the memory module in a wired manner through the second transmission interface set, the first transmission interface set, the CXL signal interface, and the DIMM controller interface. The external host device and the memory expansion board complete the memory expansion.

[0074] After the host device connected to the gold finger connector receives the CXL message data, the data is transmitted to the memory module through the fourth transmission interface set, the third transmission interface set, the CXL signal interface, and the DIMM controller interface in sequence, and the external host device and the memory expansion board complete the memory expansion.

[0075] In some embodiments of the present application, the present application provides a memory space sharing method, which is applied to a memory expansion board, and the method includes:

[0076] After the host device is connected to the CDFP module or the gold finger connector, the firmware program of the memory expansion processing chip is modified through the SPI flash module;

[0077] By modifying, all memory addresses are mapped to at least two host devices simultaneously;

[0078] After the memory address is mapped, at least two host devices can read and write data in the memory.

[0079] The modified firmware program is burned into the SPI flash memory module by burning, and the modified memory expansion processing chip maps the memory address to at least two host devices at the same time. At least two host devices can read and write data in the memory module. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0081] FIG1 is a schematic diagram of a module structure of a memory expansion board according to some embodiments of the present application;

[0082] FIG2 is a schematic diagram of the product structure of a memory expansion board according to some embodiments of the present application;

[0083] FIG3 is a top view of a memory expansion board according to some embodiments of the present application;

[0084] FIG4 is a schematic diagram of a structure of expanding the internal memory capacity of a single host device according to some embodiments of the present application;

[0085] FIG5 is a schematic diagram of a structure of remote memory capacity expansion of a single host device according to some embodiments of the present application;

[0086] FIG6 is a schematic diagram of a structure of expanding the internal memory capacity of multiple host devices according to some embodiments of the present application;

[0087] FIG7 is a schematic diagram of a structure of remote memory capacity expansion of multiple host devices according to some embodiments of the present application;

[0088] FIG8 is a schematic structural diagram of internal and remote memory capacity expansion of multiple host devices according to some embodiments of the present application. DETAILED DESCRIPTION

[0089] To make the objectives, technical solutions, and advantages of some embodiments of the present application more clear, the technical solutions in some embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of some embodiments of the present application. Obviously, some of the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on some embodiments of the present application, other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of this application.

[0090] Based on the problem that current memory devices do not support access by multiple host devices, this application provides a memory expansion board. This board is an innovative memory expansion design that supports multiple application scenarios, has high bandwidth, low latency, and large capacity. Compared with traditional storage and memory solutions, the cost is greatly reduced, meeting the urgent demand for low-cost non-volatile memory in data-intensive applications such as high-performance computing and artificial intelligence.

[0091] The chip system design of this memory expansion board can also be applied to multi-chip integrated development, massively expanding memory capacity and achieving memory pooling. This board can be used as a standard PCIE (Peripheral Component Interconnect Express) card within a server. It can also extend transmission distances via CDFP cables, making it suitable for use in various scenarios, from entire cabinets to data centers.

[0092] As shown in FIG1 , and in combination with FIG2 and FIG3 , the present application provides a memory expansion board, including a memory expansion processing chip, a CDFP module, and a memory module, wherein the memory expansion processing chip is connected to the memory module;

[0093] The memory expansion processing chip includes 2n CXL signal interfaces, where n is greater than or equal to 1 and is a positive integer.

[0094] In some embodiments of this application, LEO chips are used, and the memory expansion processing chip may include, but is not limited to, LEO chips. LEO is a memory expansion chip launched by Asteralabs based on the CXL2.0 protocol, belonging to the third device type defined by the CXL protocol. This chip supports JEDEC (Joint Electron Device Engineering Council) DDR4 (Double-Data-Rate Fourth Generation Synchronous Dynamic Random Access Memory) and DDR5 standards, and also complies with the CXL2.0 specification and supports PCIe5.0 speeds. This chip can provide a high-bandwidth, low-latency, high-speed interconnection solution for the CPU (Central Processing Unit) and devices based on the CXL protocol, thereby realizing memory sharing between the CPU and each CXL device, significantly improving system performance while significantly reducing software stack complexity and the total cost of ownership of the data center; the MXC (Memory Expander Controller) chip is designed for memory expansion cards, backplanes and memory modules, and can significantly expand memory capacity and bandwidth to meet the growing needs of data-intensive applications such as high-performance computing and artificial intelligence.

[0095] In some embodiments of the present application, the CXL signal interface is CXL / PCIE[15:8] and CXL / PCIE[7:0] inside the memory expansion processing chip in FIG1 .

[0096] The CDFP module includes a first transmission interface set and a second transmission interface set. The CDFP module is connected to 2n CXL signal interfaces of the memory expansion processing chip through the first transmission interface set.

[0097] Electronic device designers are seeking higher speeds, and one way to achieve this is through the use of new connector specifications. The CDFP module can achieve a data rate of 25Gbps (Gigabits per second) per channel on 16 channels, resulting in a total data transmission speed of 400Gbps.

[0098] CDFP is a fourth-generation system, but it is also the first larger 16x25G = 400G module and interconnect system. The CDFP structure uses a mezzanine connector, two PCBs (printed circuit boards), and four rows of edge socket connectors, providing 120 contacts in a 29.71mm (millimeter) module version.

[0099] The CDFP module is designed for client interfaces within data centers and can achieve extremely high port density. The module has a compact design and is particularly suitable for low-power applications based on copper, VCSEL (Vertical-Cavity Surface-Emitting Laser) or silicon photonics technology. It is expected that the CDFP module can be applied to industry standards up to 100 meters of MMF (Multi Mode Fiber) and 2 kilometers of SMF (Single Mode Fiber). For example, the CDFP module can be used for one 400Gbps interface, or sixteen interfaces with a rate of 25Gbps or four interfaces with a rate of 100Gbps.

[0100] The CDFP module is wiredly connected to at least one external host device via a second transmission interface set. The first transmission interface set is used to receive CXL message data transmitted from the CXL signal interface, and the second transmission interface set is used to transmit the CXL message data to the host device.

[0101] Related technology: Memory devices using the CXL protocol can only interact with the outside world through the x8 gold finger connector, are limited to interconnection within a single machine, and the application form is limited to access by a single host device, and cannot support scenarios where multiple host devices access. The present application innovates to the above problems and provides a memory expansion board that uses a memory expansion processing chip. The memory expansion processing chip includes 2n CXL signal interfaces. The memory expansion board is equipped with a CDFP module. It receives CXL message data transmitted by the CXL signal interface through a first transmission interface set and transmits the CXL message data to the host device through a second transmission interface set. The second transmission interface set is wired to at least one external host device, breaking through the limitations of interconnection within a single machine and can interact with multiple host devices, effectively solving the above problems.

[0102] Based on the above design, this application provides an implementation method of a memory expansion board: the memory expansion board mainly includes a memory expansion processing chip module, a memory module, an I2C module (Inter-Integrated Circuit, a bidirectional two-wire synchronous serial bus), a clock module CLK BUFFER, a CPLD module (Complex Programmable Logic Device, complex programmable logic device), a CDFP and a gold finger connector. The CDFP module and the gold finger connector are responsible for the input of the CXL signal. Through the Colay (co-design) design of resistors and capacitors, the free selection of input signals is achieved. The connector includes power supply, 1 CXLx16 (16 channels) signal, 2 clock signals, 2 I2C signals, 2 PERST (reset) and other control signals. All signals require Colay design. The memory expansion processing chip has two DDR5 memory controllers, each of which can connect to two DIMM slots, for a total of four DIMM slots. The clock module, CLK BUFFER, provides coherent and non-coherent clocks, switching between them to achieve the desired function. The memory expansion processing chip uses signals such as I2C (Inter-Integrated Circuit), UART (Universal Asynchronous Receiver / Transmitter), and JTAG (Joint Test Action Group) to exchange information and conduct debugging with the host device. The CPLD module is responsible for intelligent power management for the entire board. After receiving power input from the connector module, it powers on the board and receives control signals from the host device, such as I2C, PERST (PCIe Express Reset), PWRST (Power Reset), PWREN (Power Enable), and PWRGD (Power-Good), to implement information acquisition and control management.

[0103] In some embodiments of the present application, the memory expansion board also includes a gold finger connector.

[0104] The gold finger connector includes a third transmission interface set and a fourth transmission interface set.

[0105] The gold finger connector is connected to the 2n CXL signal interfaces of the memory expansion processing chip through a third transmission interface set.

[0106] The gold finger connector is connected to at least one host device via a fourth transmission interface set. The third transmission interface set is used to receive CXL message data transmitted from the CXL signal interface. The fourth transmission interface set is used to transmit the CXL message data to the host device.

[0107] The memory expansion board is equipped with a gold finger connector that allows for CXL message data transmission within the device. The third transmission interface of the gold finger connector connects to the CXL signal interface of the memory expansion processing chip, and the fourth transmission interface connects to the host device, transmitting CXL message data output from the CXL signal interface to the host device. The memory expansion board can interact with the external host device through the CDFP module and also interact with the host device internally through the gold finger connector.

[0108] In some embodiments of the present application, the gold finger connector is a x16 gold finger connector.

[0109] The gold finger connector used in the memory expansion board is expanded on the basis of the common x8 gold finger connector. This application uses an x16 gold finger connector to expand the signal path and effectively solve the problem of insufficient memory bandwidth.

[0110] In some embodiments of the present application, the memory module includes one or more DDR5 slots.

[0111] The memory expansion processing chip also includes 2n DIMM controller interfaces, where n is greater than or equal to 1 and is a positive integer.

[0112] The 2n DIMM controller interfaces of the memory expansion processing chip are used to connect to the DDR5 slots.

[0113] The current memory expansion board can only expand two DDR5 slots through the chip's controller port; the memory expansion board provided in this application is expanded through the DIMM controller interface and DIMM slots, and can connect to but not limited to two DDR5 memory sticks. Compared with the original board that can only connect to two DDR5 memory sticks, it significantly increases the memory capacity.

[0114] In some embodiments of the present application, the memory module is used for data caching and data reading and writing.

[0115] The memory module is used to provide data cache and data read and write functions for CXL message data communication and information interaction between modules within the board.

[0116] In some embodiments of the present application, the memory expansion board also includes an I2C module. The I2C module in some embodiments of the present application uses but is not limited to the PCA9548 chip.

[0117] The I2C module is connected to the memory expansion processing chip, and is used to collect data information and temperature information of the memory module connected to the memory expansion processing chip.

[0118] The I2C module obtains the data transmission status of the memory module through the I2C communication protocol, thereby confirming the data polling mechanism. The collected temperature data information can adjust the fan speed according to the actual temperature.

[0119] In some embodiments of the present application, the I2C module includes an I2C signal expansion module IIC_EXPANDER (expander), and the I2C signal expansion module IIC_EXPANDER is used to expand additional connection interfaces to connect with the memory expansion processing chip.

[0120] The I2C signal expansion module, IIC_EXPANDER, is used to expand general-purpose I / O ports, creating 8 or 16-bit GPIO (General-purpose input / output) pins via I2C. In this solution, it is used to expand additional I / O (Input / Output) ports to connect to the memory expansion processing chip, enabling interrupt, operating status, and information exchange.

[0121] The I2C signal expansion module IIC_EXPANDER expands the signal path of the I2C module, allowing the I2C module to communicate with multiple modules through the I2C signal expansion module IIC_EXPANDER, thereby increasing the number of communications between the I2C modules and effectively improving the communication efficiency between modules.

[0122] In some embodiments of the present application, the memory expansion board further includes a clock module CLK BUFFER.

[0123] The clock module CLK BUFFER is connected to the memory expansion processing chip. The clock module CLK BUFFER is used to provide a reference clock signal when the CDFP module transmits CXL message data to the host device through the second transmission interface set, and is also used to provide a reference clock signal when the gold finger connector transmits CXL message data to the host device through the fourth transmission interface set.

[0124] The clock module CLK BUFFER provides a reference clock signal when CXL message data is transmitted between the memory expansion processing chip and the CDFP module and the gold finger connector, ensuring that the CXL message data has stable clock signal support during transmission.

[0125] In some embodiments of the present application, the memory expansion board also includes a CPLD module.

[0126] The CPLD module is connected to the CDFP module, the memory expansion processing chip and the gold finger connector respectively.

[0127] The CPLD module is used to receive the I2C signal of the CDFP module and the gold finger connector to perform the power-on operation when the system is powered on, and is used to send the reset signal of the CDFP module and the gold finger connector to the memory expansion processing chip after delay processing to reset the memory expansion processing chip.

[0128] During power-up, the CPLD module sends a power-on enable signal, which the power chip receives and outputs voltage. The CPLD module obtains the real-time status of the memory expansion processing chip (transmitting and receiving status, operating frequency, operating temperature, etc.) through the I2C module and manages the LEO by sending corresponding information based on actual conditions.

[0129] The CPLD module is responsible for the intelligent power-on and power-off management of the entire board. After receiving the power input from the connector module, it completes the board power-on action and simultaneously receives the control signal from the host device to realize information acquisition and control management functions.

[0130] In some embodiments of the present application, the memory expansion board also includes an SPI flash memory module, and the SPI flash memory module is the SPI Flash in Figure 1.

[0131] The memory expansion processing chip is connected to the SPI flash memory module. The SPI flash memory module is used to store firmware programs. The firmware programs are used to execute CXL message communication between the memory expansion processing chip and the CPLD module.

[0132] The SPI flash memory module stores firmware programs, which are used to execute CXL message communication between the memory expansion processing chip and the CPLD module. By burning the firmware through the SPI flash memory module, other firmware programs can be implanted into the memory expansion processing chip.

[0133] In some embodiments of the present application, the memory expansion board further includes a voltage level conversion module Level Shift.

[0134] The voltage level conversion module Level Shift is connected between the CPLD module and the memory expansion processing chip. The voltage level conversion module Level Shift is used to receive the input signal of the CPLD module, convert the first voltage domain of the input signal of the CPLD module, generate an input signal in the second voltage domain, and transmit the input signal in the second voltage domain to the memory expansion processing chip.

[0135] The CPLD module manages power on and off. The voltage level shift module receives input signals from the CPLD module, converts the input signals into a first voltage domain, generates input signals into a second voltage domain, and transmits the input signals into the memory expansion processing chip. After voltage domain conversion, the signals input into the memory expansion processing chip protect the memory expansion processing chip from damage caused by excessive voltage shocks.

[0136] In some embodiments of the present application, the memory expansion board also includes an expansion connector, which is the Header interface in Figure 1.

[0137] The expansion connector is connected to the memory expansion processing chip, and the expansion connector is used to interact with external devices after connection.

[0138] The expansion connector is connected to the memory expansion processing chip as an expansion interface. The external device is connected to the expansion connector, and the external device interacts with the memory expansion processing chip.

[0139] As shown in FIG. 2 and FIG. 3 , in some embodiments of the present application, the full height of the memory expansion board is 111.15 mm, the half length is 169.33 mm, and the double width is 39.04 mm.

[0140] The memory expansion board in this application is in the form of a standard PCIe CEM AIC (PCIE integrated circuit) and can be flexibly applied to different scenarios.

[0141] The CXL memory expansion board of this application is in the form of a standard PCIe CEM AIC, with dimensions of full height (111.15mm), half length (169.33mm), and double width (39.04mm), which can be flexibly applied to different scenarios. This solution uses the CXL cache consistency bus to achieve memory remoteness, solving the current pain points of insufficient memory bandwidth and large capacity requirements, and solving the problems of inability to effectively expand server memory capacity, cache consistency, and a single board application form that cannot perform multi-host, long-distance data transmission, and interconnection. At the same time, the intelligent power-on and power-off and information interaction management functions of the board make the board application more flexible. It is positioned as a PCIe standard card that maximizes CXL serial memory expansion, meeting the needs of flexible expansion of CXL serial memory for general server projects such as Intel, AMD (Advanced Micro Devices, AMD Semiconductor) and other platforms, and meeting the growing demand for data-intensive applications such as high-performance computing and artificial intelligence.

[0142] In some embodiments of the present application, the memory expansion board also includes a clock processing module and a differential signal module. The clock processing module in some embodiments of the present application is the Au5329 chip in Figure 1, and the differential signal module is the 80MHz LVDS in Figure 1.

[0143] The clock module CLK BUFFER is connected to the memory expansion processing chip through the clock processing module. The clock processing module is used to receive the differential signal from the differential signal module and then perform frequency division. It is also used to de-jitter the reference clock signal output by the clock module CLK BUFFER.

[0144] The differential signal module serves as the signal source and inputs the differential signal. The clock processing module receives the differential signal and divides the frequency of the differential signal. The divided signal is transmitted to the clock module CLK BUFFER and the reference clock signal output by the clock module CLK BUFFER is de-jittered to ensure the accuracy of the reference clock signal.

[0145] In some embodiments of the present application, the memory expansion board further includes a first multiplexer MUX0.

[0146] The first multiplexer MUX0 (Multiplexer0) includes a first signal selection interface IN0 and a second signal selection interface IN1 (Input 1).

[0147] The CDFP module is connected to the CXL signal interface via the first signal selection interface IN0.

[0148] The gold finger connector is connected to the CXL signal interface through the second signal selection interface IN1.

[0149] In some embodiments of the present application, the memory expansion board further includes a second multiplexer MUX1.

[0150] The second multiplexer MUX1 includes a third signal selection interface IN2 (Input 2) and a fourth signal selection interface IN3 (Input 3).

[0151] The CDFP module is connected to the CXL signal interface via the third signal selection interface IN2.

[0152] The gold finger connector is connected to the CXL signal interface through the fourth signal selection interface IN3.

[0153] This application provides a memory space sharing method, which is applied to a memory expansion board, and includes:

[0154] Modify the firmware program of the memory expansion processing chip through the SPI flash module.

[0155] By modifying it, all memory addresses are mapped to at least two host devices simultaneously.

[0156] After the memory address is mapped, at least two host devices can read and write data in the memory.

[0157] The modified firmware program is burned into the SPI flash memory module by burning, and the modified memory expansion processing chip maps the memory address to at least two host devices at the same time. At least two host devices can read and write data in the memory module.

[0158] The memory expansion board in some embodiments of the present application can expand the memory capacity of a single host device and multiple host devices. Based on actual usage, the present application provides the following embodiments.

[0159] When it is necessary to expand the internal memory capacity of a single host device, use the connection method shown in Figure 4 to plug the memory expansion board into the motherboard of the host device HOST through the gold finger connector. At this time, the host device HOST transmits the data that needs to be cached, read and written through the CXL link to the memory expansion board through the gold finger connector. The data is then transmitted to the memory module via the memory expansion processing chip. At this time, the cached data is waiting to be read by the host device HOST or forwarded in the next step.

[0160] When it is necessary to expand the remote memory capacity of a single host device, use the connection method shown in Figure 5 to fix the memory expansion board to the motherboard of the host device HOST through the gold finger connector. At this time, the host device HOST is connected to the CDFP module of the memory expansion board through an external CDFP cable. The data that needs to be cached, read and written is transmitted to the memory expansion board through the CXL link. The data is transmitted to the memory module via the memory expansion processing chip. At this time, the cached data is waiting for the host device HOST to read or forward the next instruction.

[0161] In some embodiments of the present application, a method for memory expansion between multiple host devices is provided:

[0162] When multiple external host devices are connected to the gold finger connector, the CPLD module controls the second signal selection interface IN1 of the first multiplexer MUX0 to be turned on and the fourth signal selection interface IN3 of the second multiplexer MUX1 to be turned on.

[0163] The CXL signal interface of the memory expansion processing chip outputs CXL message data.

[0164] The third transmission interface set of the gold finger connector receives CXL message data.

[0165] After the first transmission interface set receives the CXL message data, the second transmission interface set of the CDFP module transmits the CXL message data to the external host device via a wired connection.

[0166] After the host device connected to the gold finger connector receives the CXL message data, the data is transmitted to the memory module through the fourth transmission interface set, the third transmission interface set, the CXL signal interface, and the DIMM controller interface in sequence, and the external host device and the memory expansion board complete the memory expansion.

[0167] The above method is suitable for expanding the internal memory capacity of multiple host devices. Using the connection method shown in Figure 6, the memory expansion board is plugged into the host device's motherboard via a gold finger connector. One CXL x8 signal from host device HOST0 and one CXL x8 signal from host device Host1 are connected to the gold finger connectors. The two CXL x8 signals are then connected to the two CXL x8 inputs of the memory expansion processing chip. Data that needs to be cached, read, or written is then transmitted to the memory expansion board via the CXL link. The memory expansion processing chip then transfers the data to the memory module, where it awaits read or forwarding instructions from the host device. Modifying the memory expansion processing chip's firmware to shared firmware allows all memory addresses to be mapped to both host devices simultaneously. This allows both hosts to share the entire memory space and read and write data. Modifying the memory expansion processing chip's firmware to pooled firmware allows all memory addresses to be allocated to both host devices, allowing different memory capacities to be assigned to different host devices. This allows for on-demand and flexible memory allocation.

[0168] In some embodiments of the present application, a method for memory expansion between multiple host devices is provided, further comprising:

[0169] When multiple external host devices are connected to the CDFP module, the CPLD module controls the first signal selection interface IN0 of the first multiplexer MUX0 to be turned on and the third signal selection interface IN2 of the second multiplexer MUX1 to be turned on.

[0170] The CXL signal interface of the memory expansion processing chip outputs CXL message data.

[0171] The first transmission interface set of the CDFP module receives CXL message data.

[0172] After the first transmission interface set receives the CXL message data, the second transmission interface set of the CDFP module transmits the CXL message data to the external host device via a wired connection.

[0173] After the external host device connected to the CDFP module receives the CXL message data, the data is transmitted to the memory module via a wired manner through the second transmission interface set, the first transmission interface set, the CXL signal interface, and the DIMM controller interface. The external host device and the memory expansion board complete the memory expansion.

[0174] The above method is suitable for remote memory expansion of multiple host devices. Using the connection method shown in Figure 7, the memory expansion board is plugged into the host device's motherboard via a gold finger connector. One CXL x8 signal from host device HOST0 and one CXL x8 signal from host device Host1 are connected to the CDFP module via CDFP cables. The two CXL x8 signals are then connected to the two CXL x8 inputs of the memory expansion processing chip. Data that needs to be cached and read / written is then transmitted to the memory expansion board via the CXL link. The memory expansion processing chip then transfers the data to the memory module, where it awaits read or forwarding instructions from the host device. Modifying the memory expansion processing chip's firmware to shared firmware allows all memory addresses to be mapped to both host devices simultaneously. This allows both hosts to share the entire memory space and read and write data. Modifying the memory expansion processing chip's firmware to pooled firmware allows all memory addresses to be allocated to both host devices, allowing different memory capacities to be assigned to different host devices. This allows for on-demand and flexible memory allocation.

[0175] In some embodiments of the present application, a method for memory expansion between multiple host devices is provided, further comprising:

[0176] When multiple external host devices are connected to the CDFP module and the gold finger connector at the same time, the CPLD module controls the second signal selection interface IN1 of the first multiplexer MUX0 to be connected to the third signal selection interface IN2 of the second multiplexer MUX1.

[0177] The CXL signal interface of the memory expansion processing chip outputs CXL message data.

[0178] The third transmission interface set of the gold finger connector receives CXL message data.

[0179] After the first transmission interface set receives the CXL message data, the second transmission interface set of the CDFP module transmits the CXL message data to the external host device via a wired connection.

[0180] After the external host device connected to the CDFP module receives the CXL message data, the data is transmitted to the memory module via a wired manner through the second transmission interface set, the first transmission interface set, the CXL signal interface, and the DIMM controller interface. The external host device and the memory expansion board complete the memory expansion.

[0181] After the host device connected to the gold finger connector receives the CXL message data, the data is transmitted to the memory module through the fourth transmission interface set, the third transmission interface set, the CXL signal interface, and the DIMM controller interface in sequence, and the external host device and the memory expansion board complete the memory expansion.

[0182] The above method is suitable for expanding the internal and remote memory capacity of multiple host devices. Using the connection method shown in Figure 8, the memory expansion board is plugged into the host device's motherboard via a gold finger connector. The CDFP module is connected to an external host device via a CDFP cable. One CXL x8 signal from host device HOST0 is connected to the CDFP module, and another CXL x8 signal from host device Host1 is connected to the gold finger connector. The two CXL x8 signals are then connected to the two CXL x8 inputs of the memory expansion processing chip. Data that needs to be cached, read, or written is then transmitted to the memory expansion board via the CXL link. The memory expansion processing chip then transmits the data to the memory module, where it awaits read or forwarding instructions from the host device. Modifying the memory expansion processing chip's firmware to shared firmware allows all memory addresses to be mapped to both host devices simultaneously. This allows the two hosts to share the entire memory space and read and write data from the memory. By modifying the firmware program of the memory expansion processing chip to pooled firmware, all memory addresses can be allocated to two host devices respectively, and different capacities of memory can be allocated to different host devices. At this time, the functions of on-demand allocation and flexible access of memory space can be realized.

[0183] The memory expansion board in some embodiments of the present application can realize the interconnection of the internal gold finger connector of the whole machine and the external CDFP module to realize the memory expansion function, effectively expand the external transmission distance of the CXL protocol, and the integration form is relatively flexible. This solution can realize the switching selection of single host device and multiple host device modes, and can realize the pooling and sharing functions of expanded memory, and realize the functions of on-demand allocation, shared expansion, and flexible matching of memory capacity. The single-board integrated CPLD module of this solution can realize intelligent power-on and power-off management of the board, automatically switch according to different host device modes, adapt to corresponding functions, and the integration form is relatively flexible and easy to expand, which is conducive to external interconnection between devices.

[0184] The system architecture involved in this application is clear, the system interconnection solution is highly feasible, and the application method of the entire system is flexible. The technologies involved, such as board processing and PCB design, are also tending to be completed in the industry, which can well support the implementation of this solution.

[0185] In the description of this specification, the description with reference to the terms "this embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least some embodiments or examples of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials or characteristics described may be combined in an appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are mutually inconsistent.

[0186] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0187] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0188] In this application, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0189] Although some embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims

1. A memory expansion board, characterized in that: It includes a memory expansion processing chip, a CDFP module, a gold finger connector and a memory module, wherein the memory expansion processing chip is connected to the memory module; The memory expansion processing chip includes a CXL signal interface; The CDFP module includes a first transmission interface set and a second transmission interface set, and the gold finger connector includes a third transmission interface set and a fourth transmission interface set; The CDFP module is connected to the CXL signal interface of the memory expansion processing chip through the first transmission interface set, and the gold finger connector is connected to the CXL signal interface of the memory expansion processing chip through the third transmission interface set; The CDFP module is wiredly connected to at least one external host device via the second transmission interface set, the first transmission interface set being used to receive CXL message data transmitted from the CXL signal interface, and the second transmission interface set being used to transmit the CXL message data to the host device; The gold finger connector is internally connected to at least one host device via the fourth transmission interface set. The third transmission interface set is used to receive CXL message data transmitted from the CXL signal interface. The fourth transmission interface set is used to transmit the CXL message data to the host device.

2. The memory expansion board according to claim 1, wherein: The number of the CXL signal interfaces is 2n, where n≥1 and is a positive integer.

3. The memory expansion board according to claim 1, wherein: The gold finger connector is a x16 gold finger connector.

4. The memory expansion board according to claim 1, wherein: The memory module includes one or more DDR5 slots; The memory expansion processing chip further includes 2n DIMM controller interfaces, where n≥1 and is a positive integer; The 2n DIMM controller interfaces of the memory expansion processing chip are used to connect to the DDR5 slots.

5. The memory expansion board according to claim 4, wherein: The memory module is used for data caching and data reading and writing.

6. The memory expansion board according to claim 1, wherein: The memory expansion board also includes an I2C module; The I2C module is connected to the memory expansion processing chip, and is used to collect data information and temperature information of the memory module connected to the memory expansion processing chip.

7. The memory expansion board according to claim 6, wherein: The collecting of data information and temperature information of the memory module connected to the memory expansion processing chip includes: Obtaining the data transmission status of the memory module through the I2C communication protocol, and confirming the data polling mechanism according to the data transmission status; Collect temperature data information of the memory module.

8. The memory expansion board according to claim 6, wherein: The I2C module includes an I2C signal expansion module, and the I2C signal expansion module is used to expand an additional connection interface to connect with the memory expansion processing chip.

9. The memory expansion board according to claim 1, wherein: The memory expansion board also includes a clock module; The clock module is connected to the memory expansion processing chip. The clock module is used to provide a reference clock signal when the CDFP module transmits the CXL message data to the host device through the second transmission interface set, and is also used to provide a reference clock signal when the gold finger connector transmits the CXL message data to the host device through the fourth transmission interface set.

10. The memory expansion board according to claim 1, wherein: The memory expansion board also includes a CPLD module; The CPLD module is connected to the CDFP module, the memory expansion processing chip and the gold finger connector respectively; The CPLD module is used to receive the I2C signals of the CDFP module and the gold finger connector to perform a power-on operation when the system is powered on, and is used to send the reset signals of the CDFP module and the gold finger connector to the memory expansion processing chip after delayed processing to reset the memory expansion processing chip.

11. The memory expansion board according to claim 10, wherein: The memory expansion board also includes an SPI flash memory module; The memory expansion processing chip is connected to the SPI flash memory module, the SPI flash memory module is used to store firmware programs, and the firmware programs are used to execute CXL message communication between the memory expansion processing chip and the CPLD module.

12. The memory expansion board according to claim 10, wherein: The memory expansion board also includes a voltage level conversion module; The voltage level conversion module is connected between the CPLD module and the memory expansion processing chip. The voltage level conversion module is used to receive the input signal of the CPLD module, convert the first voltage domain of the input signal of the CPLD module, generate an input signal in the second voltage domain, and transmit the input signal in the second voltage domain to the memory expansion processing chip.

13. The memory expansion board according to claim 1, wherein: The memory expansion board also includes an expansion connector; The expansion connector is connected to the memory expansion processing chip, and the expansion connector is used to interact with an external device after being connected.

14. The memory expansion board according to claim 7, wherein: The memory expansion board also includes a clock processing module and a differential signal module; The clock module is connected to the memory expansion processing chip through a clock processing module. The clock processing module is used to receive the differential signal from the differential signal module and then perform frequency division. It is also used to de-jitter the reference clock signal output by the clock module.

15. The memory expansion board according to claim 1, wherein: The memory expansion board also includes a first multiplexer; The first multiplexer includes a first signal selection interface and a second signal selection interface; The CDFP module is connected to the CXL signal interface via the first signal selection interface; The gold finger connector is connected to the CXL signal interface through the second signal selection interface.

16. The memory expansion board according to claim 1, wherein: The memory expansion board also includes a second multiplexer; The second multiplexer includes a third signal selection interface and a fourth signal selection interface; The CDFP module is connected to the CXL signal interface via the third signal selection interface; The gold finger connector is connected to the CXL signal interface through the fourth signal selection interface.

17. A memory expansion method between multiple host devices, characterized in that: The method is applied to the memory expansion board according to any one of claims 1 to 16, and the method comprises: When multiple external host devices are connected to the CDFP module, the CPLD module controls the first signal selection interface of the first multiplexer to be connected to the third signal selection interface of the second multiplexer; The CXL signal interface of the memory expansion processing chip outputs CXL message data; The first transmission interface set of the CDFP module receives the CXL message data; After the first transmission interface set receives the CXL message data, the second transmission interface set of the CDFP module transmits the CXL message data to an external host device via a wired connection; After the external host device connected to the CDFP module receives the CXL message data, the data is transmitted to the memory module in a wired manner through the second transmission interface set, the first transmission interface set, the CXL signal interface, and the DIMM controller interface, and the external host device and the memory expansion board complete the memory expansion.

18. The memory expansion method according to claim 17, wherein: The method further comprises: When multiple external host devices are connected to the gold finger connector, the CPLD module controls the second signal selection interface of the first multiplexer to be connected to the fourth signal selection interface of the second multiplexer; The CXL signal interface of the memory expansion processing chip outputs CXL message data; The third transmission interface set of the gold finger connector receives the CXL message data; After the first transmission interface set receives the CXL message data, the second transmission interface set of the CDFP module transmits the CXL message data to an external host device via a wired connection; After the host device connected to the gold finger connector receives the CXL message data, the data is transmitted to the memory module through the fourth transmission interface set, the third transmission interface set, the CXL signal interface, and the DIMM controller interface in sequence, and the external host device and the memory expansion board complete the memory expansion.

19. The memory expansion method according to claim 18, wherein: The method further comprises: When multiple external host devices are connected to the CDFP module and the gold finger connector at the same time, the CPLD module controls the second signal selection interface of the first multiplexer to be connected to the third signal selection interface of the second multiplexer; The CXL signal interface of the memory expansion processing chip outputs CXL message data; The third transmission interface set of the gold finger connector receives the CXL message data; After the first transmission interface set receives the CXL message data, the second transmission interface set of the CDFP module transmits the CXL message data to an external host device via a wired connection; After the external host device connected to the CDFP module receives the CXL message data, the data is transmitted to the memory module in a wired manner through the second transmission interface set, the first transmission interface set, the CXL signal interface, and the DIMM controller interface in sequence, and the external host device and the memory expansion board complete the memory expansion; After the host device connected to the gold finger connector receives the CXL message data, the data is transmitted to the memory module through the fourth transmission interface set, the third transmission interface set, the CXL signal interface, and the DIMM controller interface in sequence, and the external host device and the memory expansion board complete the memory expansion.

20. The memory expansion method according to claim 17, wherein: The method further comprises: After the host device is connected to the CDFP module or the gold finger connector, the firmware program of the memory expansion processing chip is modified through the SPI flash module; By modifying, all memory addresses are mapped to at least two host devices simultaneously; After the memory address is mapped, at least two host devices can read and write data in the memory module.

Images