Chip, electronic assembly and electronic device

Abstract

Provided in the present application are a chip, an electronic assembly and an electronic device. The electronic assembly comprises a chip and a circuit board. The surface of the chip that faces the circuit board comprises a central area and an edge area, wherein the edge area is located on a peripheral side of the central area, and the edge area is located on the side of the central area that faces an edge. The edge area of the chip is connected to the circuit board by means of a first solder joint, and the central area is connected to the circuit board by means of a second solder joint. A cross-sectional area of the first solder joint is larger than that of the second solder joint, and connection strength of the first solder joint is larger than that of the second solder joint, thereby improving the connection strength between the chip and the circuit board. Particularly, the first solder joint connected to the edge area achieves an obvious effect of inhibiting warpage, and an assembling window for the chip and the circuit board is expanded, thereby reducing a long-term service failure risk of a large-size chip, improving the reliability of the electronic assembly, and prolonging the service life of the electronic assembly.

Description

Chip, electronic component and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on March 29, 2024, with application number 202410382686.9 and invention name "A chip, electronic component and electronic device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the technical field of electronic equipment, and in particular to a chip, an electronic component and an electronic device. Background Art

[0004] With the development of technology, the more interfaces a packaged chip has, the more power it consumes and the larger its size becomes. When in use, the packaged chip needs to be connected to a circuit board to form an electronic component. In the prior art, solder balls are used to achieve the connection between the packaged chip and the circuit board. In this connection method, due to the different materials and thermal expansion coefficients of the packaged chip and the circuit board, the high temperature generated during welding can easily cause the packaged chip and the circuit board to warp, and there is a hidden danger of solder ball cracking, so the connection reliability between the packaged chip and the circuit board is poor. In addition, during use, the heat generated by the packaged chip with high power consumption is also high, which can easily cause the packaged chip and the circuit board to warp, resulting in a shorter service life of the electronic component. Especially for packaged chips with larger sizes, the warping between the packaged chip and the circuit board is also more obvious, and the hidden danger of solder ball cracking between the packaged chip and the circuit board is also greater.

[0005] In addition, during the long-term service of electronic components, the solder joints between the packaged chip and the circuit board will be subjected to stress caused by thermal cycles, mechanical vibrations and impacts, and are prone to cracks. As the strain accumulates, they continue to expand until they break and cause electrical failure. Summary of the Invention

[0006] This application provides a chip, electronic component, and electronic device that expands the mounting window for the chip and circuit board. This allows for smooth assembly of the electronic component even when thermal deformation does not meet standards, reducing the risk of long-term service failure of large-sized chips. This solution can improve the reliability and service life of electronic components.

[0007] In a first aspect, the present application provides a chip comprising a die and a substrate. The die is secured to the substrate. The surface of the substrate facing away from the die includes a central region and an edge region, with the edge region located peripherally of the central region and the central region located inwardly of the edge region. The surface of the substrate facing away from the die includes a first solder pad and a second solder pad, with the first solder pad located in the edge region and the second solder pad located in the central region. The first and second solder pads are each configured to be soldered to a circuit board to connect the chip and the circuit board to form an electronic assembly. The area of ​​the first solder pad is larger than the area of ​​the second solder pad, so that the cross-sectional area of ​​a first solder joint formed by soldering the first solder pad to the circuit board is larger than the cross-sectional area of ​​a second solder joint formed by soldering the second solder pad to the circuit board. The connection strength of the first solder joint is greater than the connection strength of the second solder joint, thereby improving the connection strength between the chip and the circuit board. In particular, the first solder joint being located in the edge region significantly reduces warping. This ensures a relatively stable connection between the chip and the circuit board, both under the influence of heat generated during soldering and the significant heat released during the operation of the electronic assembly. This allows the electronic components in this application to be well installed even when the thermal deformation does not meet the standards, and reduces the risk of long-term service failure of large-size chips.

[0008] There are also many ways to arrange the first pad and the second pad of the substrate. For example, the substrate can be a polygonal structure. In one implementation, the first pad is provided in the corner area of ​​the substrate, while the first pad is not provided in the straight edge area. This can improve the connection between the chip and the circuit board in a targeted manner in areas where stress concentration is more obvious. This solution is particularly suitable for situations where the chip substrate space is limited. The first pad with a larger area is set as far as possible in the corner area of ​​the substrate to maximize the connection strength between the chip and the circuit board.

[0009] In another implementation, the plurality of first pads on the substrate surface are arranged in a ring shape, which can enhance the connection strength between the chip and the circuit board on the peripheral side of the substrate, thereby improving the reliability of the electronic component.

[0010] In a further technical solution, multiple first pads on the substrate surface are arranged in a ring shape of equal width. This solution is mainly aimed at situations where there is relatively uniform space around the signal pins of the chip to set the first pads. This solution can improve the strength between the chip and the circuit board from all sides of the substrate, and can also greatly improve the connection reliability between the chip and the circuit board.

[0011] In another implementation, the plurality of first pads are arranged in a ring shape, and the number of first pads arranged in the corner region of the substrate toward the substrate edge is greater than the number of first pads arranged in the straight edge region of the substrate toward the substrate edge. This can also be understood as the arrangement width of the plurality of first pads in the corner region of the chip substrate being greater than the arrangement width of the first pads in the straight edge region of the chip substrate. This further enhances the connection strength between the chip and the circuit board.

[0012] In the embodiments of the present application, the shape of the first pad can be selected from a variety of options. For example, the first pad can include at least one of a square pad, a parallelogram pad, a circular pad, an elliptical pad, a triangular pad, or a trapezoidal pad. The specific shape can be selected based on the needs. The shape of the second pad is typically a circular pad.

[0013] In addition, the substrate may further include a first pad, which may be a U-shaped structure or a mouth-shaped structure. The U-shaped structure of the first pad facilitates the welding of the second pad of the chip with the circuit board.

[0014] In a specific implementation, the area S1 of the first pad and the area S2 of the second pad satisfy the following relationship: 20*S2 ≥ S1 ≥ 1.5*S2. This ensures that the connection strength of the first solder joint connected to the first pad is significantly greater than the connection strength of the second solder joint connected to the second pad, thereby improving the connection strength between the chip and the circuit board. Furthermore, the substrate space can be rationally utilized. While the first pads sufficiently enhance the connection strength between the chip and the circuit board, the substrate can be provided with as many pads for signal transmission as possible within the limited space.

[0015] There are various options for connecting the first and second pads to the die. For example, in one technical solution, the die includes a signal pin connected to the second pad, enabling the second pad to transmit signals. Specifically, all signal pins of the die are connected to the second pad, and the second pad is located in the center region. The second pad can be manufactured according to standardized requirements.

[0016] For the first pads with a larger area, at least part of the first pads can be disconnected from the pins of the bare chip, that is, the first pads of this part are not used to transmit any signals and are not electrically connected to the bare chip. Therefore, the size of the first pads can be designed according to the requirements of physical connection without being restricted by the requirements of electrical signal transmission. Alternatively, the bare chip can also include a ground pin, then at least part of the first pads can be connected to the ground pin of the bare chip to achieve grounding of the bare chip. The size limit of the first pad for grounding is also smaller, so the size of the first pad can also be designed according to the requirements of physical connection.

[0017] The corner areas of the chip substrate include a first support block area, which is used to accommodate support blocks. This support block supports the chip and circuit board, maintaining a certain gap between the chip and the circuit board, which helps improve solder bridging. This helps increase the mounting window and improve the installation reliability between the chip and the circuit board. Providing the first support block area in the corner area provides more uniform support between the chip and the circuit board without occupying space in the center area of ​​the substrate.

[0018] The first support block area at least partially overlaps with the first solder pad, so no additional space is required to arrange the support block, which is conducive to improving space utilization.

[0019] In addition to setting support blocks at the edge of the substrate, a second support block area can also be set in the center of the substrate. This second support block area is also used to set support blocks. Providing support for the chip in the middle area of ​​the chip is conducive to keeping the gap between the chip and the circuit board uniform and stable at all positions. Specifically, the distance between the second support block area and each corner area of ​​the substrate is the same, that is, the second support block area is located in the center of the substrate, which is conducive to improving uniformity.

[0020] The second support block area at least partially overlaps with the second solder pad. For example, a support block may be provided within the second solder joint to improve space utilization of the substrate.

[0021] In a second aspect, the present application also provides an electronic component. The electronic component includes a chip and a circuit board, and the chip is soldered to the circuit board via solder joints. Wherein: the surface of the chip facing the circuit board includes a central area and an edge area, and the edge area is located on the peripheral side of the central area. It can be understood that the edge area is located on the side of the central area facing the edge. The edge area of ​​the chip is connected to the circuit board via a first solder joint, while the central area of ​​the chip is connected to the circuit board via a second solder joint. If the cross-sectional area of ​​the first solder joint is larger than the cross-sectional area of ​​the second solder joint, the connection strength of the first solder joint is greater than the connection strength of the second solder joint, thereby improving the connection strength between the chip and the circuit board. In particular, the first solder joint is connected to the edge area, which is more effective in suppressing warping. Whether under the influence of the heat generated in the process of soldering the chip and the circuit board, or under the influence of the large amount of heat released during the service of the electronic component, the chip and the circuit board of the electronic component can maintain a relatively stable connection relationship.

[0022] The electronic assembly provided in this application can achieve an expanded assembly window. This assembly window refers to the maximum height fluctuation that the solder joint between the chip and the circuit board can absorb through compression and tension. Beyond this assembly window, the solder joint is at risk of bridging or open soldering failure. Therefore, the electronic assembly in this application can be well installed even if the thermal deformation does not meet the standard. In addition, during the long-term service of the electronic assembly, the stress threshold of the solder joint can be increased, reducing the risk of long-term service failure of large-sized chips.

[0023] In one specific implementation, the solder joints for transmitting signals between the chip and the circuit board are signal solder joints. These signal solder joints are used to transmit signals between the chip and the circuit board. Each signal solder joint is a second solder joint located in the center region and can be manufactured according to standardized requirements.

[0024] There are also multiple options for the type of first solder joint. For example, the first solder joint can include a non-functional solder joint or a grounding solder joint. The aforementioned non-functional solder joint refers to a solder joint that does not have an electrical transmission function and is primarily used to achieve a physical connection between the chip and the circuit board, rather than an electrical connection. The aforementioned grounding solder joint is primarily used for grounding. Since there are no strict size restrictions on grounding solder joints, the first solder joint can also be used as a grounding solder joint.

[0025] Alternatively, the first solder joints may include both non-functional solder joints and ground solder joints. In addition, the first solder joints may also include power solder joints, which are used to transmit power signals to achieve power supply functions, thereby improving the current flow capacity of the chip.

[0026] The cross-sectional area S3 of the first solder joint and the cross-sectional area S4 of the second solder joint satisfy the following: 20*S4 ≥ S3 ≥ 1.5*S4. That is, the cross-sectional area of ​​the first solder joint is at least 1.5 times the cross-sectional area of ​​the second solder joint. This ensures that the connection strength of the first solder joint is significantly greater than that of the second solder joint, thereby improving the connection strength between the chip and the circuit board. Furthermore, the substrate space can be rationally utilized. While the first solder joint sufficiently improves the connection strength between the chip and the circuit board, the substrate can accommodate as many signal transmission pads as possible within the limited space.

[0027] There are also multiple options for the specific placement and arrangement of the first solder joints. For example, in one technical solution, the chip substrate has a polygonal structure, with first solder joints located at least in the edge regions (corners) of the polygonal structure, while no first solder joints are located in the straight edge regions. This can specifically enhance the connection strength between the chip and the circuit board and suppress warping of the chip and circuit board.

[0028] In one technical solution, the first solder joints are arranged in a ring shape. The connection strength between the chip and the circuit board can be improved around the second solder joints to improve the reliability of the electronic component.

[0029] In one possible technical solution, a first solder joint with a relatively large area is included between the chip and the circuit board. Alternatively, it can be understood that multiple first solder joints are integrated into one structure, which is conducive to further improving the connection strength of the first solder joints.

[0030] The cross-sectional shape of the first welding spot in the present application also has multiple options, for example, the cross-sectional shape of the first welding spot includes at least one of a square, a parallelogram, a circle, a triangle, or a trapezoid, and can be designed and selected according to actual needs.

[0031] In one technical solution, a support block is provided between the chip and the circuit board. This supports the gap between the chip and the circuit board. This block maintains a certain gap between the chip and the circuit board, improving solder bridging resistance. It also increases the mounting window and enhances the reliability of the chip-to-circuit board connection.

[0032] The surface of the chip facing the circuit board includes a plurality of chip pads, and the side of the circuit board facing the chip includes a plurality of circuit board pads. The plurality of chip pads have the same area, the plurality of circuit board pads include a third pad and a fourth pad, the area of ​​the third pad is larger than the area of ​​the fourth pad, the third pad is connected to the first solder joint, and the fourth pad is connected to the second solder joint. This solution can achieve a normalized design of chip pads, which is conducive to simplifying the chip preparation process. In this technical solution, a third pad can be connected to at least two chip pads. In some implementations, a third pad can also be connected to a chip pad.

[0033] In another technical solution, the multiple circuit board pads have the same area, the multiple chip pads include a first pad and a second pad, the first pad has a larger area than the second pad, the first pad is connected to a first solder joint, and the second pad is connected to a second solder joint. This solution can achieve a normalized design of circuit board pads. In a specific implementation, one first pad can be connected to at least two circuit board pads. In some implementations, one first pad can also be connected to one circuit board pad.

[0034] On the third aspect, the present application provides a circuit board. The circuit board is used to connect the chip, and the area of ​​the circuit board used to connect the chip includes a central area and an edge area, and the edge area is located on the peripheral side of the central area. The above-mentioned circuit board includes a third solder pad and a fourth solder pad, the third solder pad is located in the edge area, and the fourth solder pad is located in the central area, and the area of ​​the third solder pad is larger than the area of ​​the fourth solder pad. In this technical solution, the third solder pad of the circuit board is welded to the chip solder pad to form a first solder joint, and the fourth solder pad of the circuit board is welded to the chip solder pad to form a second solder joint, so that the cross-sectional area of ​​the first solder joint is larger than the cross-sectional area of ​​the second solder joint. The connection strength between the circuit board and the chip is improved, the assembly window of the chip and the circuit board is expanded, and the good installation of electronic components can be achieved even when the thermal deformation does not meet the standards, thereby reducing the risk of long-term service failure of large-size chips.

[0035] In a fourth aspect, the present application further provides an electronic device comprising an electronic device and the electronic assembly provided in the first aspect, wherein the electronic device is electrically connected to the electronic assembly. The electronic assembly has a high structural reliability, which is conducive to improving the reliability and service life of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG1 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

[0037] FIG2 is a schematic side view of the structure of an electronic component according to an embodiment of the present application;

[0038] FIG3 is a schematic cross-sectional view of an electronic component according to an embodiment of the present application;

[0039] FIG4 is a schematic cross-sectional view of an electronic component according to an embodiment of the present application;

[0040] FIG5 is a schematic cross-sectional view of an electronic component according to an embodiment of the present application;

[0041] FIG6 is a schematic cross-sectional view of an electronic component according to an embodiment of the present application;

[0042] FIG7 is a schematic cross-sectional view of an electronic component according to an embodiment of the present application;

[0043] FIG8 is a schematic diagram of a partial cross-sectional structure of an electronic component in an embodiment of the present application;

[0044] FIG9 is a schematic diagram of a lateral structure of an electronic component in an embodiment of the present application;

[0045] FIG10 is a schematic diagram of a lateral structure of an electronic component in an embodiment of the present application;

[0046] FIG11 is a schematic diagram of a lateral structure of an electronic component in an embodiment of the present application;

[0047] FIG12 is a schematic diagram of a lateral structure of an electronic component in an embodiment of the present application;

[0048] FIG13 is a schematic diagram of a lateral structure of an electronic component in an embodiment of the present application;

[0049] FIG14 is a schematic diagram of a lateral structure of an electronic component in an embodiment of the present application;

[0050] FIG15 is a schematic diagram of a lateral structure of an electronic component in an embodiment of the present application;

[0051] FIG16 is a schematic cross-sectional view of an electronic component according to an embodiment of the present application;

[0052] FIG17 is a schematic cross-sectional view of an electronic component according to an embodiment of the present application;

[0053] FIG18 is a schematic cross-sectional view of an electronic component in an embodiment of the present application.

[0054] Figure numerals: 1-shell; 2-electronic device; 3-electronic component; 31-chip; 311-center area; 312-edge area; 313-chip pad; 3131-first pad; 3132-second pad; 314-bare die; 315-substrate; 316-first support block area; 317-second support block area; 32-circuit board; 321-circuit board pad; 3211-third pad; 3212-fourth pad; 33-first solder joint; 34-second solder joint; 35-support block. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of this application clearer, this application will be further described in detail below with reference to the accompanying drawings.

[0056] The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification and appended claims of this application, the singular expressions "a", "an", "said", "above", "the", and "this" are intended to also include expressions such as "one or more", unless the context clearly indicates otherwise.

[0057] References in this specification to "one embodiment" or "a specific embodiment" mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. The terms "including," "comprising," "having," and their variations all mean "including but not limited to," unless otherwise specifically stated.

[0058] To facilitate understanding of the chips, electronic components, and electronic devices provided in the embodiments of the present application, the following first introduces their application scenarios.

[0059] The electronic devices provided in the embodiments of the present application may be communication devices (such as routers), computing devices (such as servers), network devices (such as switches), or storage devices (such as storage arrays); or they may be optical modules, vehicle-mounted devices, electric vehicles, or terminal devices. The present application provides multiple options for the specific type of electronic device.

[0060] For ease of description, the embodiment of the present application is described by taking the electronic device as a server as an example. Figure 1 is a schematic structural diagram of an electronic device in an embodiment of the present application. As shown in Figure 1, the above-mentioned electronic device may include a housing 1, an electronic device 2 and an electronic component 3, wherein the electronic device 2 and the electronic component 3 are arranged in the housing 1. Specifically, when the above-mentioned electronic device is a cabinet server, the above-mentioned housing 1 can be understood as the cabinet of the cabinet server. There is no specific restriction on the connection method between the above-mentioned electronic device 2 and the electronic component 3. In one possible embodiment, as shown in Figure 1, the electronic device 2 and the electronic component 3 are electrically connected through a circuit board. Alternatively, in some embodiments, the above-mentioned electronic device 2 and the electronic component 3 can also be electrically connected through flexible electrical connectors such as cables or flexible circuit boards.

[0061] FIG2 is a side structural diagram of an electronic component in an embodiment of the present application. As shown in FIG2 , in one embodiment, the electronic component 3 includes a chip 31 and a circuit board 32, and the chip 31 and the circuit board 32 are connected by solder joints. In a specific embodiment, the chip 31 can be a packaged chip. As shown in FIG2 , the chip 31 includes a bare chip 314 and a substrate 315, and the bare chip 314 is fixed to the substrate 315 to form a packaged chip. With the development of technology, the chip 31 integrates more and more functions and circuit patterns, resulting in an increasingly larger area of ​​the chip 31. Due to the different thermal expansion coefficients between the chip 31 and the circuit board 32, different degrees of thermal deformation are prone to occur. The connection reliability between the chip 31 and the circuit board 32 is low, which has an adverse effect on the working performance and service life of the electronic component 3.

[0062] FIG3 is a schematic cross-sectional view of an electronic assembly according to an embodiment of the present application. Specifically, FIG3 is a cross-sectional view taken along line AA in FIG2 . As shown in FIG3 , in this embodiment, the surface of the substrate 315 of the chip 31 facing the circuit board 32 includes a central region 311 and an edge region 312. The edge region 312 is located around the central region 311. It is understood that the central region 311 is located inward of the edge region 312. The edge region 312 of the substrate 315 of the chip 31 is connected to the circuit board 32 via first solder joints 33, while the central region 311 of the substrate 315 of the chip 31 is connected to the circuit board 32 via second solder joints 34. The first solder joints 33 are generally located around the second solder joints 34, or in other words, the first solder joints 33 are connected to the edge region 312 of the substrate 315 of the chip 31. The cross-sectional area of ​​the first solder joints 33 is larger than that of the second solder joints 34. Therefore, the connection strength of the first solder joints 33 is greater than that of the second solder joints 34, thereby increasing the solder stress threshold between the chip 31 and the circuit board 32. This improves the connection strength between the chip 31 and the circuit board 32. In particular, the first solder joint 33, connected to the edge region 312, significantly reduces warping. This ensures a relatively stable connection between the chip 31 and the circuit board 32, regardless of the heat generated during soldering or the significant heat released during the operation of the electronic component 3.

[0063] The electronic assembly 3 provided in the embodiments of the present application can achieve an expanded assembly window. This window refers to the maximum height fluctuation that the solder joint between the chip 31 and the circuit board 32 can absorb through compression and tension. Beyond this window, the solder joint risks bridging or open soldering failure. This allows for good assembly even when thermal deformation does not meet the required standards. Furthermore, during the long-term service life of the electronic assembly 3, the stress threshold of the solder joint can be increased, reducing the risk of long-term service failure of large-sized chips.

[0064] In one embodiment, signal transmission is required between the chip 31 and the circuit board 32. In the technical solution of this application, the solder joints for transmitting signals between the chip 31 and the circuit board 32 are signal solder joints. These signal solder joints are connected to the signal pins of the die 314 and are used to transmit signals between the chip 31 and the circuit board 32. In a specific embodiment, these signal solder joints can be used to transmit any type of signal, such as control signals or data signals. These signal solder joints are all second solder joints 34. In this embodiment of the application, the size of the signal solder joints for transmitting signals between the chip 31 and the circuit board 32 is generally required to improve signal transmission efficiency and speed. In addition to the signal solder joints for transmitting signals, this embodiment of the application adds first solder joints 33 with a larger cross-sectional area, which helps to improve the connection strength between the chip 31 and the circuit board 32. In addition, the first solder joints 33 are also used to connect areas without signal pins, increasing the connection area between the chip 31 and the circuit board 32 and also improving the connection strength between the chip 31 and the circuit board 32.

[0065] It is worth noting that, in one embodiment, the second solder joints 34 may all be signal solder joints. Alternatively, in another embodiment, the second solder joints 34 may include other types of solder joints in addition to signal solder joints. For example, the second solder joints 34 may also include ground solder joints. A ground solder joint refers to a solder joint used to connect to the ground. The ground solder joint may be connected to a ground pin of the die 314.

[0066] There are also various options for the type of first solder joint 33. For example, the first solder joint 33 can include a non-functional solder joint or a grounding solder joint. A non-functional solder joint is a solder joint that does not have electrical transmission capabilities and is disconnected from the pins of the die 314. It primarily serves to physically connect the chip 31 to the circuit board 32, rather than electrically connecting them. The grounding solder joint is primarily used for grounding, so the size restrictions on the grounding solder joint are not particularly strict. Therefore, the first solder joint 33 can also be used as a grounding solder joint.

[0067] In one embodiment, the first solder joint 33 may also include a power solder joint, which is connected to the power pin of the bare die 314 to transmit a power signal to achieve power supply. Currently, the power of the chip 31 is gradually increasing, and higher requirements are placed on the power supply capacity. In this embodiment, the larger first solder joint 33 is used as the power solder joint, which is conducive to improving the current flow capacity of the chip 31.

[0068] In the electronic component 3 provided in the present application, it is sufficient as long as the cross-sectional area of ​​the first solder joint 33 is greater than the cross-sectional area of ​​the second solder joint 34. However, in order to significantly improve the connection strength and reliability between the chip 31 and the circuit board 32. In a specific embodiment, the cross-sectional area S1 of the first solder joint 33 and the cross-sectional area S2 of the second solder joint 34 satisfy: S1 ≥ 1.5 * S2. That is, the cross-sectional area of ​​the first solder joint 33 is at least 1.5 times the cross-sectional area of ​​the second solder joint 34. As a result, the connection strength of the first solder joint 33 can be greatly greater than the connection strength of the second solder joint 34, thereby improving the connection strength between the chip and the circuit board.

[0069] Continuing with FIG3 , the substrate 315 of the chip 31 is a polygonal structure, with at least the edge region 312 being located at the corners of the polygonal structure and having first solder joints 33 provided therein, while the straight edge regions are not provided with first solder joints 33. Generally, the corners of the chip 31 are prone to warping and stress concentration. This embodiment, by providing first solder joints 33 at the corners of the chip 31, specifically enhances the connection strength between the chip 31 and the circuit board 32, thereby suppressing warping of the chip 31 and the circuit board 32. Furthermore,

[0070] Alternatively, Figure 4 is a schematic cross-sectional view of an electronic assembly according to an embodiment of the present application. Specifically, Figure 4 is a cross-sectional view taken along line AA in Figure 2 . As shown in Figure 4 , in one embodiment, first solder joints 33 are arranged in a ring shape, and second solder joints 34 are located within the ring of the first solder joints 33. The connection strength between chip 31 and circuit board 32 can be enhanced around second solder joints 34, thereby improving the reliability of electronic assembly 3.

[0071] Alternatively, FIG5 is a schematic cross-sectional view of an electronic component in an embodiment of the present application. Specifically, FIG5 is a cross-sectional view taken along line AA in FIG2 . As shown in FIG5 , in one embodiment, in addition to the first solder joints 33 being arranged in a ring shape, additional first solder joints 33 are provided in the corner regions of the chip 31. The width of the first solder joints 33 in the corner regions of the chip 31 is greater than the width of the first solder joints 33 in the straight edge regions of the chip 31. This further enhances the connection strength between the chip 31 and the circuit board 32.

[0072] Alternatively, Figure 6 is a schematic diagram of a cross-sectional structure of an electronic component in an embodiment of the present application, and Figure 7 is a schematic diagram of a cross-sectional structure of an electronic component in an embodiment of the present application. Specifically, Figures 6 and 7 are cross-sectional views of AA in Figure 2, respectively. As shown in Figures 6 and 7, in one embodiment, a first solder joint 33 is included between the chip 31 and the circuit board 32. As shown in Figure 6, in one embodiment, the first solder joint 33 can be an integrated annular structure, which is arranged around the second solder joint 34. Specifically, the cross-sectional shape of the first solder joint 33 is a mouth-shaped structure. Alternatively, as shown in Figure 7, in one embodiment, the first solder joint 33 can also be an open-loop structure, which is also arranged around the second solder joint 34. Specifically, the cross-sectional shape of the first solder joint 33 is a U-shaped structure, which is beneficial for machining the second solder joint 34 in the center area. In the above embodiment, there is only one first solder joint 33 between the chip 31 and the circuit board 32, and the area of ​​the first solder joint 33 is relatively large. Compared with the arrangement of multiple first solder joints 33 at intervals, the space in the gap is also used to arrange the first solder joint 33, which is beneficial to fully utilize the space on the surface of the substrate 315 and also beneficial to improving the connection strength between the chip 31 and the circuit board 32.

[0073] In one embodiment, the distance between the second solder joint 34 and the first solder joint 33 is ≥0.1 mm, so that a solder resist layer is prepared between the second solder joint 34 and the first solder joint 33 to reduce the risk of soldering between the first solder joint 33 and the second solder joint 34 .

[0074] In the embodiments of the present application, the cross-sectional shape of the first solder joint 33 also has multiple options. For example, the cross-sectional shape of the first solder joint 33 includes at least one of a square, a parallelogram, a circle, a triangle, or a trapezoid. In the embodiment shown in FIG4 , the cross-sectional shape of the first solder joint 33 is a square. In the embodiments shown in FIG3 and FIG5 , the cross-sectional shape of the first solder joint 33 includes a square and a triangle. FIG8 is a schematic diagram of a partial cross-sectional structure of an electronic component in the embodiments of the present application. As shown in FIG8 , in one embodiment, the cross-sectional shape of the first solder joint 33 includes a trapezoid and a parallelogram.

[0075] Figure 9 is a schematic diagram of a side view of an electronic assembly in an embodiment of the present application, and Figure 10 is a schematic diagram of a side view of an electronic assembly in an embodiment of the present application. As shown in Figures 9 and 10, in order to achieve soldering between the chip 31 and the circuit board 32, the substrate 315 of the chip 31 includes a plurality of chip pads 313 on the surface facing the circuit board 32, and the side of the circuit board 32 facing the chip 31 includes a plurality of circuit board pads 321. The chip pads 313 and the circuit board pads 321 are connected by solder joints, thereby achieving a connection between the chip 31 and the circuit board 32.

[0076] In one embodiment, the area S5 of the circuit board pad 321 connected to the second solder joint 34 and the area S6 of the chip pad 313 satisfy 0.6*S6≤S5≤1.4*S6. The area of ​​the circuit board pad 321 connected to the first solder joint 33 and the area of ​​the chip pad 313 can be the same or different.

[0077] Continuing with FIG9 , in one embodiment, the substrate 315 of the chip 31 includes a plurality of chip pads 313 , including a first pad 3131 and a second pad 3132 . The first pad 3131 is located in the edge region 312 , and the second pad 3132 is located in the center region 311 . The area of ​​the first pad 3131 is larger than the area of ​​the second pad 3132 . The first pad 3131 is connected to the first solder joint 33 , and the second pad 3132 is connected to the second solder joint 34 , such that the cross-sectional area of ​​the first solder joint 33 is larger than the cross-sectional area of ​​the second solder joint 34 . This improves the connection between the chip and the circuit board, expands the chip assembly window, and increases the yield and service life of the electronic component.

[0078] In this embodiment, the areas of the multiple circuit board pads 321 of the circuit board 32 can be made the same, achieving a normalized design of the circuit board pads 321. In this embodiment, one first pad 3131 can be connected to at least two circuit board pads 321. In some embodiments, one first pad 3131 can also be connected to one circuit board pad 321.

[0079] Continuing with FIG. 10 , in one embodiment, the plurality of circuit board pads 321 of the circuit board 32 include a third pad 3211 and a fourth pad 3212. The third pad 3211 is located in the edge region 312, and the fourth pad 3212 is located in the center region 311. The area of ​​the third pad 3211 is larger than that of the fourth pad 3212. The third pad 3211 is connected to the first solder joint 33, and the fourth pad 3212 is connected to the second solder joint 34, such that the cross-sectional area of ​​the first solder joint 33 is larger than the cross-sectional area of ​​the second solder joint 34. In this embodiment, the areas of the plurality of chip pads 313 of the chip 31 can be made uniform, achieving a standardized design of the chip pads 313 and simplifying the manufacturing process of the chip 31. In this embodiment, one third pad 3211 can be connected to at least two chip pads 313. In some embodiments, one third pad 3211 can also be connected to one chip pad 313.

[0080] Figure 11 is a schematic diagram of a side view of an electronic component in an embodiment of the present application. As shown in Figure 11, in one embodiment, the area of ​​the third solder pad 3211 on the circuit board 32 is larger than the area of ​​the fourth solder pad 3212, and the area of ​​the first solder pad 3131 on the substrate 315 of the chip 31 is larger than the area of ​​the second solder pad 3132. In this embodiment, the two ends of a first solder joint 33 can be connected to a third solder pad 3211 and a first solder pad 3131, respectively. Specifically, if one end of the first solder joint 33 is the first end and the other end is the second end, then the first end of the first solder joint 33 is connected to a third solder pad 3211, and the second end of the first solder joint 33 is connected to a first solder pad 3131. Alternatively, the two ends of a first solder joint 33 can be connected to at least two third solder pads 3211 and at least two first solder pads 3131, respectively. In this case, the first end of the first solder joint 33 is connected to at least two third solder pads 3211, and the second end of the first solder joint 33 is connected to at least two first solder pads 3131.

[0081] Figure 12 is a schematic diagram of a lateral structure of an electronic component in an embodiment of the present application. As shown in Figure 12, in one embodiment, the multiple chip pads 313 of the chip 31 have the same area, and the multiple circuit board pads 321 of the circuit board 32 have the same area. In this embodiment, the two ends of a first solder joint 33 can also be connected to at least two circuit board pads 321 and at least two chip pads 313, respectively. In this case, the first end of the first solder joint 33 is connected to at least two circuit board pads 321, and the second end of the first solder joint 33 is connected to at least two chip pads 313.

[0082] On the surface of the substrate 315 of the chip 31, the pads connected to the second solder joints 34 are typically solder ball pins, and the arrangement can be varied, ranging from a regular array to a staggered arrangement. The pads connected to the first solder joints 33 also have various pinning options, including direct soldering, tinning the pad surface, or pre-tinning the pad, with the tin cap height being less than or equal to 1.5 times the height of the solder ball on the pad connected to the second solder joint 34, to enhance stability between the chip 31 and the circuit board 32.

[0083] In one embodiment, the die 314 in the chip 31 may include a signal pin, a power pin, and a ground pin. The signal pin is used to transmit signals from the die 314, such as control signals, data signals, or any other type of signal. The power pin is used to transmit power to the die 314. The ground pin is used to connect the die 314 to the ground. The signal pin of the die 314 is connected to the second solder pad 3132, making the second solder pad 3132 a signal solder pad for transmitting signals to the chip 31. The size of the signal solder pads used to transmit signals between the chip 31 and the circuit board 32 generally has certain requirements to improve signal transmission efficiency and speed. In this application, the size of the solder pads used for signal transmission can be selected and designed according to communication requirements to ensure the signal transmission quality of the chip. In some embodiments, some of the multiple second solder pads 3132 on the substrate 315 may be connected to the ground pin, or some may be connected to the power pin.

[0084] There are also multiple options for the connection relationship and function of the first solder pad 3131 connected to the first solder point 33. In one embodiment, at least some of the multiple first solder pads 3131 of the substrate 315 are disconnected from the pins of the bare chip 314, that is, the first solder pads 3131 are not electrically connected to the bare chip 314 and are non-functional solder pads. And / or, at least some of the multiple first solder pads 3131 of the substrate 315 are connected to the ground pin of the bare chip 314, and the first solder pads 3131 are used to achieve grounding of the bare chip 314. Alternatively, in one embodiment, the multiple first solder pads 3131 of the substrate 315 can also include some of the first solder pads 3131 connected to the power pin of the bare chip 314, which is beneficial to improving the current flow capacity of the chip 31.

[0085] In one embodiment, the area S1 of the first solder pad 3131 and the area S2 of the second solder pad 3132 satisfy the following relationship: 20*S2 ≥ S1 ≥ 1.5*S2. This means that the area of ​​the first solder pad 3131 is at least 1.5 times the area of ​​the second solder pad 3132. This ensures that the cross-sectional area of ​​the first solder joint 33 is at least 1.5 times the cross-sectional area of ​​the second solder joint 34. The connection strength of the first solder joint 33 is significantly greater than that of the second solder joint 34, thereby improving the connection strength between the chip 31 and the circuit board 32. Furthermore, the area of ​​the first solder pad 3131 is no more than 20 times the area of ​​the second solder pad 3132. If the area of ​​the first solder pad 3131 is too large, it will occupy more substrate space, reducing the area available for the second solder pad 3132 or increasing the chip size. Therefore, this solution can improve the integration of the chip 31 while enhancing the connection strength between the chip 31 and the circuit board 32. In some embodiments, the area S1 of the first solder pad 3131 is greater than 20*S2. This solution is more suitable for situations where the substrate area is sufficient. It can improve the strength of the first solder joint connecting the chip 31 and the circuit board 32, thereby improving the connection reliability between the chip 31 and the circuit board 32.

[0086] Figures 3 to 8 can also be viewed as schematic diagrams of the surface of the substrate 315 of the chip 31 that is away from the bare die 314. As shown in Figure 3, in one embodiment, the substrate 315 is a polygonal structure, and a first solder pad 3131 is provided in the corner area of ​​the substrate 315. Generally, warping and stress concentration are prone to occur at the corners of the chip 31. In this embodiment, by providing the first solder pad 3131 at the corner of the chip 31, the connection strength between the chip 31 and the circuit board 32 in the corner area is specifically improved, thereby suppressing the warping of the chip 31 and the circuit board 32. This solution is particularly suitable for situations where the space of the substrate 315 of the chip 31 is limited. The first solder pad 3131 with a larger area is provided as much as possible in the corner area of ​​the substrate 315 to maximize the connection strength between the chip 31 and the circuit board 32.

[0087] In a specific embodiment, as shown in FIG3 , first solder pads 3131 may be provided only in the corner regions of substrate 315, while not provided in the straight edge regions of substrate 315. This embodiment can specifically enhance the connection strength at the corner regions where chip 31 connects to circuit board 32, and can also provide more space on substrate 315 for second solder pads 3132, thereby improving space utilization of substrate 315 and miniaturizing chip 31.

[0088] As shown in FIG4 , in one embodiment, a plurality of first solder pads 3131 are arranged in a ring shape. The first solder joints 33 are arranged on the peripheral side of the chip 31 to enhance the connection strength between the chip 31 and the circuit board 32, thereby enhancing the reliability of the electronic component. Specifically, when the first solder pads 3131 are arranged in a ring shape, as shown in FIG4 , the first solder pads 3131 can be arranged in a ring shape of equal width. For example, if the areas of different first solder pads 3131 are the same, the number of rows of the first solder pads 3131 arranged at different positions on the peripheral side of the substrate 315 is the same. In the embodiment shown in FIG4 , a row of first solder pads 3131 are arranged at different positions on the peripheral side of the substrate 315.

[0089] As shown in FIG5 , in a further embodiment, the number of first solder pads 3131 arranged in the corner regions of the substrate 315 toward the edge of the substrate 315 is greater than the number of first solder pads 3131 arranged in the straight-edge regions of the substrate 315 toward the edge of the substrate 315. That is, additional first solder pads 3131 are provided at the corners of the substrate 315. Alternatively, it can be understood that the arrangement width of the first solder pads 3131 in the corner regions of the chip 31 substrate 315 is greater than the arrangement width of the first solder pads 3131 in the straight-edge regions of the substrate 315. This further enhances the connection strength between the chip 31 and the circuit board 32. For example, in the embodiment shown in FIG5 , the arrangement width of the first solder pads 3131 increases the closer to the corner regions of the substrate. In the corner regions, the first solder pads 3131 are arranged in a triangular shape, while in the straight-edge regions, the first solder pads 3131 are arranged in a straight line.

[0090] Alternatively, as shown in Figures 6 and 7, in some embodiments, the substrate 315 of the chip 31 includes a first pad 3131. As shown in Figure 6, in one embodiment, the first pad 3131 is a mouth-shaped structure, which can also be understood as an integrated ring structure. The mouth-shaped first pad 3131 is arranged around the second pad 3132.

[0091] Alternatively, as shown in FIG7 , in one embodiment, the first solder pad 3131 can also be a U-shaped structure, which can be specifically understood as an open-loop structure, and is also arranged on the peripheral side of the second solder pad 3132 . This solution is beneficial for machining the second solder pad 3132 in the center area.

[0092] In the above embodiment, the substrate 315 of the chip 31 includes only one first solder pad 3131, and the area of ​​the first solder pad 3131 is relatively large. Compared with the arrangement of multiple first solder pads 3131 at intervals, the space in the gaps is also used to layout the first solder pads, which is beneficial to fully utilize the space on the surface of the substrate 315 and also beneficial to improving the connection strength between the chip 31 and the circuit board 32.

[0093] It is worth noting that, in the embodiment of the present application, the arrangement of the first solder pads 3131 can be designed and selected along with the arrangement of the second solder pads 3132. If there is sufficient space on the substrate 315, the first solder pads 3131 can be arranged over as much area as possible. If space is limited, a larger number of first solder pads 3131 or a larger total area can be arranged in the corners of the substrate 315 to maximize the connection strength between the chip 31 and the circuit board 32.

[0094] In the embodiment of the present application, the shape of the first pad 3131 also has multiple options. For example, the above-mentioned first pad 3131 includes at least one of a square pad, a parallelogram pad, a circular pad, an elliptical pad, a triangular pad or a trapezoidal pad. The specific selection and design can be based on the needs, and the shapes of different first pads 3131 of the same chip 31 can be the same or different. For example, in the embodiment shown in Figure 4, the first pad 3131 is a square pad; in the embodiments shown in Figures 3 and 5, the first pad 3131 includes a square pad and a triangular pad. As shown in Figure 8, in one embodiment, the first pad 3131 includes a trapezoidal pad and a parallelogram pad.

[0095] Figure 13 is a schematic diagram of the lateral structure of an electronic assembly in an embodiment of the present application. As shown in Figure 13, in one embodiment, a support block 35 is further provided between the chip 31 and the circuit board 32 of the electronic assembly 3. This support block 35 supports the gap between the chip 31 and the circuit board 32, maintaining a certain level of clearance between the chip 31 and the circuit board 32, thereby improving the solder bridging resistance. This solution helps to increase the mounting window and enhance the installation reliability between the chip 31 and the circuit board 32.

[0096] When the support block 35 is specifically provided, the shape of the support block 35 is not limited and may be cylindrical, cubic or spherical, etc. The shape of the support block 35 may be selected according to specific needs.

[0097] Regarding the setting position of the support block 35, as shown in Figure 13, the support block 35 can be independent of the solder joint and be set between the chip 31 and the circuit board 32 as a separate structure. Alternatively, Figure 14 is a schematic diagram of a lateral structure of the electronic component in an embodiment of the present application, and Figure 15 is a schematic diagram of a lateral structure of the electronic component in an embodiment of the present application. As shown in Figures 14 and 15, in one embodiment, the above-mentioned support block 35 can be located in the solder joint. In one embodiment, the support block 35 can be set in some of the solder joints, specifically, the support block 35 can be set in some of the second solder joints 34, as shown in Figure 14. Alternatively, in one embodiment, support blocks 35 can be set in all solder joints, or support blocks 35 can be set in all second solder joints 34, as shown in Figure 15.

[0098] In the embodiment of the present application, a plurality of support blocks 35 can be arranged between the chip 31 and the circuit board 32. There are multiple options for the positions of the plurality of support blocks 35, and the sizes of different support blocks 35 may also be inconsistent. Figure 16 is a schematic diagram of a cross-sectional structure of an electronic component in the embodiment of the present application. As shown in Figure 16, in one embodiment, support blocks 35 are respectively arranged at the center and four corners of the chip 31. In a specific embodiment, the size of the support blocks 35 located at the four corners can be larger than the size of the support block 35 located at the center. Figure 17 is a schematic diagram of a cross-sectional structure of an electronic component in the embodiment of the present application. As shown in Figure 17, in one embodiment, support blocks 35 are arranged at the center of the chip 31 and in the area between the first solder joint 33 and the second solder joint 34. Figure 18 is a schematic diagram of a cross-sectional structure of an electronic component in the embodiment of the present application. As shown in Figure 18, in one embodiment, support blocks 35 are arranged at the center and edge of the chip 31. In summary, in a preferred embodiment, support blocks 35 are arranged at the center and all around the chip 31.

[0099] In order to set the above-mentioned support block 35, a support block area is reserved on the side of the chip 31, and the support block 35 is set in the above-mentioned support block area. For example, Figures 16 to 18 can also serve as structural schematic diagrams of the surface of the chip substrate facing away from the bare die. As shown in Figure 16, in one embodiment, the corner area of ​​the substrate 315 of the chip 31 includes a first support block area 316, and the first support block area 316 is used to set the support block 35 (since the support block area and the support block have the same position and shape, no additional number is given). By setting the first support block area 316 in the corner area, more uniform support can be provided between the chip 31 and the circuit board 32, and the space in the center area of ​​the substrate 315 is not occupied.

[0100] When specifically arranging the first support block area 316, the first support block area 316 can overlap with the first pad 3131, or the first pad 3131 can avoid the first support block area 316. As shown in FIG16, in one embodiment, the first support block area 316 is located in a direction away from the second pad 3132 from the first pad 3131, and the first pad 3131 avoids the first support block area 316. As shown in FIG17 and FIG18, in another embodiment, the first support block area 316 at least partially overlaps with the first pad 3131. This allows the first solder joint 33 to accommodate the support block 35, thereby improving space utilization.

[0101] Referring to Figures 16 to 18 , in one embodiment, the central region of the substrate 315 further includes a second support block region 317, which is also used to position the support block 35. For larger chips 31, providing support for the chip 31 from the central region of the chip 31 helps maintain a uniform and stable gap between the chip 31 and the circuit board 32 at all locations. The position of the second support block region 317 can be such that the distance between the second support block region 317 and each corner region of the substrate 315 is the same, that is, the second support block region 317 is located in the exact center of the substrate 315, thereby enhancing the support effect of the support block 35.

[0102] Furthermore, the second support block region 317 can at least partially overlap with the second pads 3132 to improve space utilization of the substrate 315 of the chip 31, thereby facilitating the placement of more pads. Alternatively, the second support block region 317 can avoid the second pads 3132, i.e., the support block 35 can be placed in an area where the second pads 3132 are not placed.

[0103] In a specific embodiment, the size of the first support block regions 316 located at the four corners can be larger than the size of the second support block region 317 located in the center. Since the corner regions of the chip 31 are not provided with pads for signal transmission, there is more space for the first support block regions 316. The second support block region 317 located in the center of the chip 31 is smaller, which helps reduce the impact of the second support block region 317 on the pad configuration.

[0104] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A chip, characterized in that: The die is fixed to the substrate, and the surface of the substrate facing away from the die includes a central area and an edge area, wherein the edge area is located on the periphery of the central area. A surface of the substrate facing away from the die includes a first pad and a second pad. The first pad is located in the edge region, the second pad is located in the center region, and an area of ​​the first pad is larger than an area of ​​the second pad.

2. The chip according to claim 1, wherein: The first pad is provided in the corner area of ​​the substrate, and the first pad is not provided in the straight edge area of ​​the substrate.

3. The chip according to claim 1, wherein: The plurality of first pads are arranged in a ring shape.

4. The chip according to claim 3, wherein: The plurality of first pads are arranged in a ring shape with equal width.

5. The chip according to claim 3, wherein: The arrangement width of the plurality of first pads in the corner area of ​​the substrate is greater than the arrangement width in the straight edge area of ​​the substrate.

6. The chip according to claim 1, wherein: The substrate includes one first pad, and one first pad is a U-shaped structure, or one first pad is a mouth-shaped structure.

7. The chip according to any one of claims 1 to 5, wherein: The first pad includes at least one of a square pad, a parallelogram pad, a circular pad, an elliptical pad, a triangular pad or a trapezoidal pad.

8. The chip according to any one of claims 1 to 3, wherein: The area S1 of the first pad and the area S2 of the second pad satisfy: 20*S2≥S1≥1.5*S2.

9. The chip according to any one of claims 1 to 8, wherein: The corner area of ​​the substrate includes a first support block area, and the first support block area is used to set a support block.

10. The chip according to claim 9, wherein: The first support block area at least partially overlaps with the first pad.

11. The chip according to claim 9 or 10, characterized in that: The central area of ​​the substrate further includes a second support block area, and the second support block area is used to set a support block.

12. The chip according to claim 11, wherein: The second supporting block area is at the same distance from each corner area of ​​the substrate.

13. The chip according to claim 11 or 12, characterized in that: The second support block area at least partially overlaps with the second pad.

14. The chip according to any one of claims 1 to 13, wherein: The signal pin of the bare chip is connected to the second pad.

15. The chip according to any one of claims 1 to 14, wherein: The first pad is disconnected from a pin of the bare chip, and / or the first pad is connected to a ground pin of the bare chip.

16. An electronic component, characterized in that The chip comprises a die and a substrate, wherein: the chip comprises a die and a substrate, the die is fixed to the substrate, the surface of the substrate facing away from the die comprises a central area and an edge area, and the edge area is located on the periphery of the central area; The edge area of ​​the substrate is connected to the circuit board via a first solder point, and the center area of ​​the substrate is connected to the circuit board via a second solder point; the cross-sectional area of ​​the first solder point is greater than the cross-sectional area of ​​the second solder point.

17. The electronic component according to claim 16, wherein: The cross-sectional area S3 of the first welding point and the cross-sectional area S4 of the second welding point satisfy: 20*S4≥S3≥1.5*S4.

18. The electronic component according to claim 16 or 17, wherein: The first welding spot is provided in the corner area of ​​the substrate, and the first welding spot is not provided in the straight edge area of ​​the substrate.

19. The electronic component according to any one of claims 16 to 18, wherein: The first welding points are arranged in a ring shape.

20. The electronic component according to claim 19, wherein The arrangement width of the plurality of first welding points in the corner area of ​​the substrate is greater than the arrangement width in the straight edge area of ​​the substrate.

21. The electronic component according to any one of claims 16 to 20, wherein: The cross-sectional shape of the first welding spot includes at least one of a square, a parallelogram, a circle, an ellipse, a triangle or a trapezoid.

22. The electronic component according to any one of claims 16 to 21, wherein: A support block is further provided between the substrate and the circuit board, and the support block is supported between the chip and the circuit board.

23. The electronic component according to any one of claims 16 to 22, wherein: The surface of the substrate facing the circuit board includes a plurality of chip pads, and the side of the circuit board facing the chip includes a plurality of circuit board pads, wherein: The areas of the multiple chip pads are the same, and the multiple circuit board pads include a third pad and a fourth pad. The area of ​​the third pad is larger than that of the fourth pad. The third pad is connected to the first solder point, and the fourth pad is connected to the second solder point.

24. The electronic component according to any one of claims 16 to 23, wherein: The surface of the substrate facing the circuit board includes a plurality of chip pads, and the side of the circuit board facing the chip includes a plurality of circuit board pads, wherein: The areas of the multiple circuit board pads are the same, and the multiple chip pads include a first pad and a second pad, the area of ​​the first pad is larger than the area of ​​the second pad, the first pad is connected to the first solder point, and the second pad is connected to the second solder point.

25. An electronic device, characterized in that: The electronic device comprises an electronic component and the electronic component according to any one of claims 16 to 24, wherein the electronic device is electrically connected to the electronic component.

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