Polishing method for bonded wafer

Abstract

A polishing method for a bonded wafer, comprising: providing a bonded wafer, which comprises a substrate layer, a top silicon layer and an insulating buried oxide layer; executing a grinding process on the top silicon layer, the thickness of the top silicon layer after being ground being greater than a target thickness of the top silicon layer; and providing a carrier corresponding to the thickness obtained by matching, and placing the bonded wafer into the carrier to execute a double-sided polishing process, wherein before the substrate layer and the top silicon layer are provided, matching is performed on the target thickness of the top silicon layer, the thickness of the carrier and the thickness of the substrate layer, the matching being set as: the thickness of the carrier being x, the thickness of the substrate layer being y, the target thickness of the top silicon layer being z, and x‑y+0.5≤z≤x‑y+2, and the thickness of the carrier and the thickness of the substrate layer are obtained after matching. The polishing method can improve the thickness uniformity of top silicon layers which have been subjected to double-sided polishing, and can reduce abrasion of carriers.

Description

Bond wafer polishing method Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a bonding wafer polishing method. Background Art

[0002] Silicon on insulator (SOI) technology has become one of the mainstream products in most electronic materials fields. With the rapid development of new energy vehicles, automotive-grade SOI materials are becoming increasingly integrated with automotive chips. The transition from 200mm to 300mm SOI is an inevitable development trend, and high uniformity and polishing stability are particularly important.

[0003] The uneven thickness of the top silicon layer in the SOI wafer may cause unstable device performance, resulting in inconsistent current density in local electron channels, uneven thermal effects and even line width variations. Double-sided polishing of SOI wafers is one of the main processes in wafer manufacturing. Its main function is to eliminate stress damage caused by cutting and thinning, improve wafer uniformity, and obtain wafers with high flatness and low roughness. The working principle of double-sided polishing is to achieve the goal of low roughness under the combined action of slurry and mechanical action. During the double-sided polishing process, the SOI wafer is placed in a planetary wheel bushing, and driven by the inner and outer rings of the double-sided polishing machine, the planetary wheel rotates on the polishing disk with a polishing pad, thereby achieving the purpose of polishing and removal.

[0004] As one of the key components in the double-sided polishing process, the selection of the carrier planetary wheel is crucial. The mechanical properties, microstructure, and quality characteristics of the planetary wheel directly affect the thickness uniformity of the top silicon layer after polishing. In addition, because the wafer removal rate in the double-sided polishing machine does not change linearly with polishing time, when the top silicon layer in the SOI wafer is less than 10μm, the double-sided polishing machine's laser thickness measurement function will fail. The subsequent thickness removal time will be calculated according to the removal rate within the laser-measurable thickness range. Therefore, by selecting a suitable carrier, adjusting the disc shape and the pressure distribution between the polishing discs, and reasonably matching the carrier and the thickness of the top silicon layer, the thickness can be controlled when the double-sided polishing stops, thereby achieving the goal of improving the flatness of the top silicon layer. Summary of the Invention

[0005] The object of the present invention is to provide a bonding wafer polishing method, which can improve the thickness uniformity of the top silicon layer after double-sided polishing and reduce the wear of the carrier.

[0006] In order to achieve the above object, the present invention provides a bonding wafer polishing method, comprising:

[0007] Providing a bonding wafer, including a substrate layer, a top silicon layer and an insulating buried oxide layer;

[0008] performing a grinding process on the top silicon layer, wherein the thickness of the top silicon layer after grinding is greater than a target thickness of the top silicon layer;

[0009] Providing a carrier corresponding to the thickness obtained by matching, placing the bonding wafer in the carrier and performing a double-side polishing process;

[0010] Before providing the bonding wafer, matching is performed according to the target thickness of the top silicon layer, the thickness of the carrier and the thickness of the substrate layer. The matching setting is that the thickness of the carrier is x, the thickness of the substrate layer is y, and the target thickness of the top silicon layer is z, x-y+0.5≤z≤x-y+2, wherein the units of the thickness of the carrier, the thickness of the substrate layer and the target thickness of the top silicon layer are μm, and the thickness of the carrier and the thickness of the substrate layer are obtained after matching.

[0011] Optionally, the thickness of the substrate layer is 750 μm to 800 μm.

[0012] Optionally, the thickness difference of the substrate layer is less than 0.15 μm.

[0013] Optionally, after grinding, the thickness of the top silicon layer is greater than the target thickness of the top silicon layer by 8 μm to 12 μm.

[0014] Optionally, the thickness difference of the top silicon layer after grinding is 0.5 μm to 1.5 μm.

[0015] Optionally, the target thickness of the top silicon layer has been obtained before the matching is performed.

[0016] Optionally, after performing the double-side polishing process, the thickness difference of the top silicon layer is less than 0.2 μm.

[0017] Optionally, the polishing rate of the double-sided polishing process is 0.5 μm / min to 2.5 μm / min.

[0018] Optionally, the double-sided polishing process is monitored in sections using a laser thickness meter.

[0019] Optionally, the vehicle is a planetary wheel.

[0020] In the bonding wafer polishing method provided by the present invention, a bonding wafer is provided, comprising a substrate layer, a top silicon layer and an insulating buried oxide layer; a grinding process is performed on the top silicon layer, and the thickness of the top silicon layer after grinding is greater than the target thickness of the top silicon layer; a carrier corresponding to the thickness obtained by matching is provided, and the bonding wafer is placed in the carrier to perform a double-sided polishing process; wherein, before providing the substrate layer and the top silicon layer, matching is performed according to the target thickness of the top silicon layer, the thickness of the carrier and the thickness of the substrate layer, and the matching is set as the thickness of the carrier is x, the thickness of the substrate layer is y, and the target thickness of the top silicon layer is z, x-y+0.5≤z≤x-y+2, wherein the units of the thickness of the carrier, the thickness of the substrate layer and the target thickness of the top silicon layer are μm, and the thickness of the carrier and the thickness of the substrate layer are obtained after matching. The present invention matches the target thickness of the top silicon layer, the thickness of the carrier and the thickness of the substrate layer to obtain the thickness of the carrier and the thickness of the substrate layer, and uses the carrier corresponding to the matched thickness to perform a double-sided polishing process, which can effectively control the polishing removal amount of the top silicon layer, improve the thickness uniformity of the top silicon layer after double-sided polishing, and reduce the wear of the carrier. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG1 is a flow chart of a bonding wafer polishing method provided in one embodiment of the present invention.

[0022] FIG. 2 is a graph showing the relationship between the target thickness of the top silicon layer and the polishing rate in the bond wafer polishing method provided by one embodiment of the present invention.

[0023] FIG3 is a diagram showing the relationship between the target thickness of the top silicon layer and the thickness difference of the top silicon layer in the bond wafer polishing method provided by one embodiment of the present invention. DETAILED DESCRIPTION

[0024] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0025] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, and "one end" and "the other end" generally refer to two corresponding parts. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0026] FIG1 is a flow chart of a bonding wafer polishing method provided in this embodiment. Referring to FIG1 , this embodiment provides a bonding wafer polishing method, including:

[0027] Step S1: providing a bonding wafer, comprising a substrate layer, a top silicon layer and an insulating buried oxide layer;

[0028] Step S2: performing a grinding process on the top silicon layer, wherein the thickness of the top silicon layer after grinding is greater than the target thickness of the top silicon layer;

[0029] Step S3: providing a carrier corresponding to the matched thickness, placing the bond wafer in the carrier and performing a double-sided polishing process;

[0030] Before providing the substrate layer and the top silicon layer, matching is performed according to the target thickness of the top silicon layer, the thickness of the carrier and the thickness of the substrate layer. The matching setting is that the thickness of the carrier is x, the thickness of the substrate layer is y, and the target thickness of the top silicon layer is z, x-y+0.5≤z≤x-y+2, wherein the units of the thickness of the carrier, the thickness of the substrate layer and the target thickness of the top silicon layer are μm. After matching, the thickness of the carrier and the thickness of the substrate layer are obtained.

[0031] The bonding wafer polishing method provided in this embodiment is described in detail below.

[0032] Execute step S1: provide a bonding wafer, comprising a substrate layer, a top silicon layer and an insulating buried oxide layer. The substrate layer and the top silicon layer are isolated by the insulating buried oxide layer and bonded together to form a bonding wafer (the substrate layer, the insulating buried oxide layer and the top silicon layer are stacked in sequence from bottom to top). In this embodiment, the diameter of the substrate layer and the top silicon layer may be 200mm to 300mm, the thickness of the substrate layer may be 750μm to 800μm, the thickness difference of the substrate layer may be less than 0.15μm, and the thickness difference is the difference between the maximum thickness and the minimum thickness, but is not limited thereto. After bonding, the bonding wafer is also subjected to reinforcement heat treatment and edge chamfering treatment.

[0033] Before providing the bonding wafer, the target thickness of the polished top silicon layer can be known during the design phase. The target thickness is a design requirement, so the target thickness of the top silicon layer is obtained before matching. Matching is performed based on the target thickness of the top silicon layer, the thickness of the carrier, and the thickness of the substrate layer. The matching setting is that the thickness of the carrier is x, the thickness of the substrate layer is y, and the target thickness of the top silicon layer is z, x-y+0.5≤z≤x-y+2, where the units of the thickness of the carrier, the thickness of the substrate layer, and the target thickness of the top silicon layer are μm. After matching, the thickness of the carrier and the thickness of the substrate layer are obtained.

[0034] In this embodiment, the carrier is a planetary wheel, and a number of workpiece holes are provided on the planetary wheel body. When double-sided polishing is performed subsequently, the bonding sheet is placed in the workpiece hole of the planetary wheel. The thickness of the planetary wheel affects the polishing removal amount of the bonding sheet. The thickness of the planetary wheel represents the hole depth of the workpiece hole. The planetary wheel includes a stainless steel bushing and a DLC (diamond-like carbon) coating. In this embodiment, the target thickness of the top silicon layer, the thickness of the carrier, and the thickness of the substrate layer are related and have a matching relationship. Selecting a carrier of appropriate thickness can effectively control the polishing removal amount of the top silicon layer, improve the thickness uniformity of the top silicon layer after double-sided polishing, and reduce the wear of the carrier. Therefore, in the design stage, it is necessary to first set the thickness of the carrier and the thickness of the substrate layer through the matching relationship among the target thickness of the top silicon layer, the thickness of the carrier, and the thickness of the substrate layer. It is known that the target thickness of the top silicon layer is z, so that the thickness of the carrier and the thickness of the substrate layer meet x-y+0.5≤z≤x-y+2. During the design stage, if the thickness of the substrate layer has been set, the thickness of the carrier is obtained according to x-y+0.5≤z≤x-y+2; if the thickness of the carrier has been set, the thickness of the substrate layer is obtained according to x-y+0.5≤z≤x-y+2; when providing the substrate layer, a substrate layer of the set thickness is provided; if the thickness of the carrier and the thickness of the substrate layer are not set, the thickness of the carrier and the thickness of the substrate layer that satisfy the matching relationship are freely set according to x-y+0.5≤z≤x-y+2.

[0035] Executing step S2: performing a grinding process on the top silicon layer, wherein the thickness of the top silicon layer after grinding is greater than the target thickness of the top silicon layer. In this embodiment, the thickness of the top silicon layer after grinding can be greater than the target thickness of the top silicon layer by 8 μm to 12 μm (i.e., the thickness of the top silicon layer after grinding is greater than the target thickness of the top silicon layer by 8 μm to 12 μm). The thickness difference of the top silicon layer after grinding can be 0.5 μm to 1.5 μm, but is not limited thereto.

[0036] Execute step S3: After matching in the design phase, the thickness of the carrier is known. A carrier corresponding to the thickness obtained by matching is provided (this thickness is the thickness of the carrier obtained through matching), and the bond wafer is placed in the carrier to perform a double-sided polishing process. In this embodiment, after performing the double-sided polishing process using the carrier corresponding to the matched thickness, the thickness difference of the top silicon layer can be less than 0.2μm, thereby improving the thickness uniformity of the top silicon layer after double-sided polishing; the polishing rate of the double-sided polishing process can be 0.5μm / min to 2.5μm / min, and the double-sided polishing process is monitored in sections using a laser thickness meter.

[0037] Figure 2 is a graph showing the relationship between the target thickness of the top silicon layer and the polishing rate in the bond wafer polishing method provided in this embodiment. Figure 3 is a graph showing the relationship between the target thickness of the top silicon layer and the thickness difference of the top silicon layer in the bond wafer polishing method provided in this embodiment. Please refer to Figure 2, the horizontal axis is the target thickness of the top silicon layer, the vertical axis is the polishing rate, x in the horizontal axis is the thickness of the carrier, y is the thickness of the substrate layer, xy-0.5 to x-y+2.5 indicates that the target thickness of the top silicon layer increases, and when the target thickness of the top silicon layer reaches x-y+0.5, the polishing rate begins to stabilize. Please refer to Figure 3, the horizontal axis is the target thickness of the top silicon layer, the vertical axis is the thickness difference of the top silicon layer, xy-0.5 to x-y+2.5 indicates that the target thickness of the top silicon layer increases, and when the target thickness of the top silicon layer is less than x-y+2.5, the thickness difference of the top silicon layer is less than or equal to 0.2μm. In order to ensure both the polishing rate and the small thickness difference of the top silicon layer, it is preferred that the target thickness of the top silicon layer is greater than or equal to x-y+0.5 and less than or equal to x-y+2, that is, the target thickness of the top silicon layer is z, x-y+0.5≤z≤x-y+2, and the units of the thickness of the above-mentioned carrier, the thickness of the substrate layer and the target thickness of the top silicon layer are μm.

[0038] The following example illustrates the bonding wafer polishing method provided in this embodiment.

[0039] A bonding wafer is provided, which includes a substrate layer, a top silicon layer and an insulating buried oxide layer. The top silicon layer in the bonding wafer is ground and thinned using a dual-axis grinder. The grinding removal amount is greater than 20 μm, preferably greater than 25 μm. The thickness of the top silicon layer after grinding is greater than 10 μm, preferably greater than 13 μm. The thickness difference of the top silicon layer after grinding is less than 1 μm. The bonding wafer is then cleaned individually. After cleaning, the thickness of the top silicon layer is tested. The laser thickness meter selects a Fourier transform infrared absorption spectrometer (FTIR). Among them, taking the thickness of the carrier planetary wheel as 780μm and the thickness of the substrate layer in the bond wafer as 775μm as an example, 75 bond wafers were provided and divided into 5 groups, each with 15 bond wafers, and double-sided polishing process was carried out separately. The double-sided polishing process is divided into two stages: rough polishing and fine polishing. The pH value of the polishing liquid used in the rough polishing stage is 10.9, the temperature is controlled at 24℃, the liquid-to-water ratio is 1:25, and the polishing pressure is 650kg; the pH value of the polishing liquid used in the fine polishing stage is 9.0, the temperature is controlled at 22℃, the liquid-to-water ratio is 1:30, and the polishing pressure is 400kg. The initial thickness of the top silicon layer was obtained by laser thickness meter testing and was 788μm. After the double-sided polishing was completed, the final thickness of the top silicon layer was obtained by laser thickness meter testing and was z1 = 5μm, z2 = 5.5μm, z3 = 6μm, z4 = 6.5μm, and z5 = 7μm respectively (z1 to z5 are the average thickness of each group of bond wafers). Since the thickness of the carrier planetary wheel is 780μm and the thickness of the substrate layer in the bonding wafer is 775μm, that is, x=780μm, y=775μm, the target thickness z of the top silicon layer should be in the range of (x-y+0.5,x-y+2), that is, 5.5μm≤z≤7μm, among which the measured thicknesses of z2, z3, z4, and z5 meet the matching relationship between the target thickness of the top silicon layer, the thickness of the carrier, and the thickness of the substrate layer, which can effectively control the polishing removal amount of the top silicon layer, improve the thickness uniformity of the top silicon layer after double-sided polishing, and reduce the wear of the carrier.

[0040] In summary, in the bonding wafer polishing method provided by the present invention, a bonding wafer is provided, comprising a substrate layer, a top silicon layer and an insulating buried oxide layer; a grinding process is performed on the top silicon layer, and the thickness of the top silicon layer after grinding is greater than the target thickness of the top silicon layer; a carrier corresponding to the thickness obtained by matching is provided, and the bonding wafer is placed in the carrier to perform a double-sided polishing process; wherein, before providing the substrate layer and the top silicon layer, matching is performed according to the target thickness of the top silicon layer, the thickness of the carrier and the thickness of the substrate layer, and the matching is set as the thickness of the carrier is x, the thickness of the substrate layer is y, and the target thickness of the top silicon layer is z, x-y+0.5≤z≤x-y+2, wherein the units of the thickness of the carrier, the thickness of the substrate layer and the target thickness of the top silicon layer are μm, and the thickness of the carrier and the thickness of the substrate layer are obtained after matching. The present invention matches the target thickness of the top silicon layer, the thickness of the carrier and the thickness of the substrate layer to obtain the thickness of the carrier and the thickness of the substrate layer, and uses a carrier corresponding to the matched thickness to perform a double-sided polishing process, which can effectively control the polishing removal amount of the top silicon layer, improve the thickness uniformity of the top silicon layer after double-sided polishing, and reduce the wear of the carrier.

[0041] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A bonding wafer polishing method, characterized in that: include: Providing a bonding wafer, including a substrate layer, a top silicon layer and an insulating buried oxide layer; performing a grinding process on the top silicon layer, wherein the thickness of the top silicon layer after grinding is greater than a target thickness of the top silicon layer; Providing a carrier corresponding to the thickness obtained by matching, placing the bonding wafer in the carrier and performing a double-side polishing process; Before providing the bonding wafer, matching is performed according to the target thickness of the top silicon layer, the thickness of the carrier and the thickness of the substrate layer, and the matching setting is that the thickness of the carrier is x, the thickness of the substrate layer is y, and the target thickness of the top silicon layer is z, x-y+0.5≤z≤x-y+2, wherein the units of the thickness of the carrier, the thickness of the substrate layer and the target thickness of the top silicon layer are μm, and the thickness of the carrier and the thickness of the substrate layer are obtained after matching.

2. The bonding wafer polishing method according to claim 1, wherein: The thickness of the substrate layer is 750 μm to 800 μm.

3. The bonding wafer polishing method according to claim 2, wherein: The thickness difference of the substrate layer is less than 0.15 μm.

4. The bonding wafer polishing method according to claim 1, wherein: The thickness of the top silicon layer after grinding is greater than the target thickness of the top silicon layer by 8 μm to 12 μm.

5. The bonding wafer polishing method according to claim 4, wherein: The thickness difference of the top silicon layer after grinding is 0.5 μm to 1.5 μm.

6. The bonding wafer polishing method according to claim 1, wherein: The target thickness of the top silicon layer is obtained before matching is performed.

7. The bonding wafer polishing method according to claim 1, wherein: After the double-side polishing process is performed, the thickness difference of the top silicon layer is less than 0.2 μm.

8. The bonding wafer polishing method according to claim 1, wherein: The polishing rate of the double-sided polishing process is 0.5 μm / min to 2.5 μm / min.

9. The bonding wafer polishing method according to claim 1, wherein: The double-sided polishing process is monitored in sections using a laser thickness meter.

10. The bonding wafer polishing method according to claim 1, wherein: The vehicle is a planetary wheel.

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