Method of generating layout routing data

Abstract

A method for generating layout routing data includes determining a capacitance matrix for each of a plurality of sets of variable routing parameters for wiring connections, wherein each capacitance matrix includes a set of capacitance values for parasitic capacitances between the wiring connections. A processor determines a number of principal components for at least a subset of the capacitance values in a capacitance space spanned by the parasitic capacitances. The layout routing data is obtained based on information obtained from the principal components.

Description

[0001] METHOD OF GENERATING LAYOUT ROUTING DATA

[0002] The present disclosure generally relates to the field of integrated circuit (IC) design technologies and, more particularly, to techniques improving layout design.

[0003] BACKGROUND

[0004] Electronic design automation (EDA) for integrated circuits (IC) provides layout software that places the functional elements of the ICs on the chip and routes connection lines between the functional elements. The IC design needs various simulation steps to optimize the circuit design parameters. As the structure sizes in ICs continue to shrink, the influence of parasitic capacitances between the connection lines on the performance of an IC increases. Typically, the parasitic capacitances are computed through an extraction step from a layout and then annotated into a Standard Parasitic Exchange Format (SPEF), which is an IEEE standard for representing parasitic data of wires in a chip in ASCII format. The influence of the parasitic capacitances is analyzed in a post-layout simulation. The results of the post-layout simulation can be visualized. Increasingly, parasitic-aware design flows and machine learning techniques are applied to classify the effect of the parasitic capacitances and optimize place and route.

[0005] SUMMARY

[0006] The IC layout often includes portions with regular metal interconnection layers (also known as Front-End Layers) that form a fabric known as CrossBar or Via-Configurable Transistor Array (VCTA). Apart from operating frequencies where the wavelength is in the range of wiring dimensions, the main parasitic components characterizing such fabric are electrical resistance and capacitance. Taking into account all parasitic couplings in an extracted view can lead to a very large amount of unbalanced data.

[0007] The present disclosure mitigates such and other shortcomings of the prior art. For this purpose, a method for generating layout routing data includes determining a capacitance matrix for each of a plurality of sets of variable routing parameters for wiring connections, wherein each capacitance matrix includes a set of capacitance values for parasitic capacitances between the wiring connections. A processor determines a number of principal components for at least a subset of the capacitance values in a capacitance space spanned by the parasitic capacitances. The layout data is obtained based on information obtained from the principal components.

[0008] The method captures the maximum variance present in an overall unbalanced data set describing the layout routing, may compute the next orthogonal components in descending order of variance, and check after each computed orthogonal component, whether the computed orthogonal components represent the original data sufficiently accurate. The method reduces the computational burden for simulating the effects of parasitic capacitances and sensitivity analysis. Using learning methods, a better understanding of available layout options for optimization can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

[0010] FIG. 1 is a diagram for illustrating steps of a method for generating layout routing data in accordance with an embodiment of the present technology.

[0011] FIG. 2 is a schematic diagram showing a 3-dimensional capacitance matrix for illustration.

[0012] FIG. 3 includes three schematic diagrams showing a 2-dimensional capacitance matrix for illustration.

[0013] FIG. 4A to FIG. 4C show schematic diagrams with 2-dimensional capacitance matrices for illustration of an embodiment using capacitance matrices on a Pareto front.

[0014] FIG. 5A to FIG. 5C show schematic diagrams with 2-dimensional capacitance matrices for illustration of an embodiment using capacitance matrices on a Pareto front for sensitivity analysis.

[0015] FIG. 6 is a flow chart of a method for generating layout routing data according to an embodiment.

[0016] FIG. 7 is a flow chart of a method for generating layout routing data using principal components aligned to a Pareto front of capacitance values according to an embodiment.

[0017] FIG. 8 is a simplified block diagram of an electronic design automation apparatus according to an embodiment.

[0018] DETAILED DESCRIPTION

[0019] The present disclosure is related to a method for generating layout routing data (layout structure data). A capacitance matrix is determined for each of a plurality of sets of variable routing parameters for wiring connections, wherein each capacitance matrix includes a set of capacitance values for parasitic capacitances between the wiring connections. A processor determines a number of principal components for at least a subset of the capacitance values in a capacitance space spanned by the parasitic capacitances. The layout data is obtained based on information obtained from the principal components.

[0020] Each wiring connection electrically connects a first electric element or first contact pad with a second electric element or second contact pad. The wiring connection may include one or more line segments in one or more horizontal metallization planes and / or vias vertically connecting line segments formed in different metallization planes. The parasitic capacitance between two wiring connections describes the degree of unwanted capacitive coupling between the two wiring connections.

[0021] The routing parameters include geometric dimensions like length, width and thickness of line segments, distances between neighboring line segments, thickness of interlayer dielectrics between neighboring metallization planes, the diameter of vias, and others. The routing parameters may also include material parameters like the dielectric number of an interlayer dielectric. Each routing parameter spans one dimension of a multi-dimensional orthogonal routing parameter space. Each routing parameter combination corresponds to a routing position in the routing parameter space. For each routing parameter combination, a capacitance matrix exists that is defined by a position in the capacitance space.

[0022] Each sampled capacitance value is an element of a capacitance matrix. The capacitance matrix contains as many elements as parasitic capacitances are assessed for the same layout. Each parasitic capacitance spans one dimension of the multi-dimensional capacitance space. The high-dimensional capacitance matrix scales with the number of wiring connections (signals). Each signal forms a pair with every other signal. With N signals, an NxN capacitance matrix is formed, which is symmetric along the diagonal that represents the coupling (N*(N-l)) / 2. The diagonal can be used to embed the capacitance to the ground, wherein the diagonal becomes (N*(N-l)) / 2 + N.

[0023] Determining the capacitance values of parasitic capacitances for one set of routing parameters of the wiring connections corresponds to a sampling of one possible routing in the following.

[0024] By sampling a number of feasible routings, some specific volumes are defined in the capacitance space, wherein a first principal component represents the maximum variance direction of the capacitance values (capacitance matrices). The orientation of the second and following principal components reflect the second and following largest sources of variation in the capacitance values in the capacitance space while being orthogonal to each of the preceding principal components. The principal components can be obtained by principal component analysis (PCA) that maps correlated capacitance values into non-correlated values of capacitance in the space of the capacitance matrix, or by singular value decomposition (SVD). The number of principal components determined can be lower than the number of routing parameters. The principal component analysis (PCA) determines the direction of the optimization in the space of the capacitance matrix.

[0025] Determining the capacitance values of parasitic capacitances between the wiring connections for each of the plurality of sets of variable routing parameters may include (a) determining an initial set of capacitance values of parasitic capacitances couplings between wiring connections described by a set of routing parameters in an initial routing data set, and (b) iteratively varying the routing parameters to obtain the plurality of routing parameters sets and determining the capacitance values for the parasitic capacitances, wherein a set of capacitance values is obtained for each set of routing parameters. Step (a) may be executed by a routing module of an electronic design automation (EDA) system. The routing module can be a software module running on a processor or computer system. Step (b) can be performed by a simulation module of the EDA system. The simulation module may be a software module. Determining the principal components may be executed by a PCA module. The PCA module may be a software module integrated in the EDA system.

[0026] According to an embodiment, the number of determined principal components is selected so that the number of principal components determined represent at least 80% of a total variance of the capacitance values.

[0027] The number of principal components, which represent at least 80%, at least 90% or at least 95% of the total variance is typically significantly lower than the number of the routing parameters. Using a sufficient number of principal components instead of the original routing parameters reduces parameter dimensionality for further processing the capacitance values. If the original routing parameters are replaced with the significantly smaller number of principal components for fine-tuning the routing, computational effort can be significantly reduced with only a slight loss of information.

[0028] According to an embodiment, the layout routing data describes a wiring fabric.

[0029] The wiring fabric may be part of a greater, irregular wiring structure or a unit cell of a greater, regular wiring grid. The wiring fabric may include contact pads and / or parallel wiring segments of the wiring connections in the same metallization plane and / or in neighboring parallel metallization planes, crossing wiring segments in different metallization planes and / or vias connecting wiring segments and / or contact pads in different metallization planes. The wiring fabric may include a programmed crossbar network representing a network with input lines, output lines, and possible one-to-one interconnections between each input line with each output line, wherein only a subset of the possible one-to-one interconnections is physically implemented, and the others are left open. The wring fabric may be modeled after a via- configurable transistor array (VCTA).

[0030] According to an embodiment, obtaining the layout routing data includes performing an automated routing process using information obtained from the principal components.

[0031] The principle components indicate trends, jumps, clusters and outliers and may uncover the relationships between parasitic capacitance values and routing parameters (routing variables). Routing algorithms provided with more constraints derived from an assessment of the principle components can work more efficiently and faster. For example, routing solutions that do not comply with the routing constraints can be neglected for the automated routing process.

[0032] According to an embodiment, all parasitic capacitances are used to determine the principal components.

[0033] Determining the principal components by considering all available parasitic capacitances uses the available information completely and different benchmarks may be targeted. According to another embodiment, the principal components are derived predominantly or exclusively from Pareto efficient capacitance matrices.

[0034] The Pareto efficient capacitance matrices are the capacitance matrices located on the Pareto front. For some benchmarks, lower capacitance values are always better. In such case, the Pareto efficient capacitance matrices deliver the lowest possible capacitance values for the target layout.

[0035] According to an embodiment, obtaining the layout routing data includes determining benchmark sensitivities of the principal components to changes of the routing parameters or the capacitance values and determining the layout routing data based on the benchmark sensitivities of the principal components.

[0036] Each benchmark sensitivity describes the effect of a change of the capacitance on a predefined benchmark. If the principal components capture sufficiently the variance ratio, the benchmark sensitivity can be approximated by the effect of a change of a principal component on the predefined benchmark. An example for a benchmark is crosstalk. Another example may be the data transmission rate. The benchmark serves as optimization function (target).

[0037] The benchmark sensitivity indicates the sensitivity of the benchmark against a certain change in the routing of a wiring segment, e.g., a shift of a certain wiring into a horizontal direction.

[0038] The method analyzes the extent to which a variation of a certain principal component contributes to a variation of the parasitic capacitances and can exclude those principal components from further considerations for the routing whose contribution to a variation of the parasitic capacitances is low. The computational load for the sensitivity analysis can be reduced.

[0039] When the number of principal components, which represent at least 80%, at least 90% or at least 95% of the total variance, is significantly lower than the number of the routing parameters, performing the sensitivity analysis for the principal components instead of the original routing parameters reduces redundancy and computational effort with only a slight loss of information.

[0040] According to an embodiment, a routing described by the layout routing data is developed in a direction of a low benchmark sensitivity of the principal components.

[0041] According to an embodiment, a space of feasible routings defines a space of feasible capacitance values defining a rout-constrain and the rout-constrain is determined from the principal components. In an implementation without parametrized routing parameters, the space of feasible routings is determined by a collection of routings that follow predetermined design rules and match design constraints, for example, dimensions of the wirings and spaces in a fabric of interconnects.

[0042] The routing makes up capacitance matrices whose constraints are dictated by some requirements, for example, the numbers of signals, contacts to the front-end layers, and fabrication rules. From these layouts one can identify major contributions that explain the observed variations. These major contributions are described by the principal components. From there one can select new feasible layouts that fit the constraint but minimize principal components capacitances.

[0043] According to an embodiment, a best direction in the rout-constrain is computed based on the benchmark sensitivities and determining the layout routing data includes processing information about the best direction in the rout-constrain.

[0044] Another aspect of the present disclosure concerns an electronic design automation apparatus that includes a simulating module configured to determine a capacitance matrix for each of a plurality of sets of variable routing parameters for wiring connections, wherein each capacitance matrix includes a set of capacitance values for parasitic capacitances between the wiring connections. A PCA module is configured to determine a number of principal components for at least a subset of the capacitance values in a capacitance space spanned by the parasitic capacitances. A data interface is configured to output information obtained from the principal components.

[0045] According to an embodiment, the electronic design automation apparatus includes a Pareto module configured to determine the principal components predominantly or exclusively from Pareto efficient capacitance matrices.

[0046] According to a further embodiment, the electronic design automation apparatus further includes a sensitivity analysis module configured to determine benchmark sensitivities of the principal components to changes in the routing parameters or capacitive values; and a sensitivity minimization module configured to determine routing parameters for a robust routing, the robust routing being less sensitive to changes in the routing parameters than most or all other possible routings.

[0047] FIG. 1 shows repetitive layout blocks 11 of a wiring fabric with a set of wiring connections 12 (signals) and an example representation 19 of the mechanical cross-section content. For applying the method, the layout blocks 11 are assessed as isolated blocks 13 detached from the wiring environment.

[0048] FIG. 2 shows a high-dimensional capacitance space spanned by the parasitic capacitances cl, c2, c3, c4, . . . , cn. Each layout 21 has its own combination of n parasitic capacitance values (“capacitance matrix”). Each capacitance matrix is represented by a point 22 in the capacitance space.

[0049] In FIG. 3, the dots 30 indicate sampled capacitive values in a 2-dimensional capacitance space spanned by the parasitic capacitances cl, cl for illustration. For the computed sensitivities, the area on the left side of line 31 indicates the area of sampled capacitance values meeting a specification. The area on the right side of line 32 indicates the area of sampled capacitive values outside the specification. The area between lines 31, 32 shows the trade-off. The arrows indicate the direction of increasing distance to the specification. FIG. 4A to FIG. 4C refer to a benchmark benefitting from all parasitic capacitances being as low as possible.

[0050] In FIG. 4A the arrows 41, 42 indicate the direction of optimization in the illustrative 2D capacitance space spanned by the parasitic capacitances cl, c2.

[0051] In FIG. 4B, line 43 shows the Pareto front connecting the two-dimensional Pareto efficient capacitance matrices.

[0052] The left diagram in FIG. 4C shows an initial distribution of capacitance matrices 44 in the capacitance space spanned by the parasitic capacitances cl, c2. A Pareto optimizer changes the layout parameters in a way that the parasitic capacitances tend to smaller capacitance values as indicated in the diagram in the center of FIG. 4C. In the right diagram of FIG. 4C, line 43 shows the Pareto front connecting the two-dimensional Pareto efficient capacitance matrices.

[0053] The diagrams in FIG. 5A to FIG. 5C illustrate concepts of the sensitivity analysis with and without using the Pareto efficient capacitance matrices.

[0054] FIG. 5 A shows a plurality of capacitance matrices 55 obtained by sampling of all feasible layouts. The sensitivity analysis is performed in a high-dimensional capacitance space for each capacitance matrix 55 against each parasitic capacitance cl, c2, c3, ... , cn. For the illustrative 2-dimensional capacitance space, arrow 51 indicates the direction of the sensitivity analysis against the first parasitic capacitance cl, and arrow 52 indicates the direction of the sensitivity analysis against the second parasitic capacitance c2.

[0055] FIG. 5B shows the Pareto efficient capacitance matrices 59 on the Pareto front 53. A sensitivity analysis for the Pareto efficient capacitance matrices in the low-dimensional space of the Pareto layouts along the tangent or tangents onto the Pareto front can be highly efficient.

[0056] FIG. 5C shows the Pareto front 53 of FIG. 5B in combination with the first and second principal components pl, p2 obtained from the capacitance matrices 55 of FIG. 5A by PCA. Sensitivity analysis around a capacitance matrix on the Pareto front begins along the orientation of the first principal component pl, which indicates most of the variation.

[0057] FIG. 6 illustrates a method of generating layout data. The method is carried out by a processor executing a program code.

[0058] In a first step 602, layout structure data is imported. The layout structure data includes routing parameters of wiring connections described by the layout structure data. A second step 604 records the capacitance matrix containing the capacitance values of parasitic capacitances effective in a feasible layout. The second step 604 is repeated for each feasible layout. A third step 606 involves a PCA for reducing the dimensionality of the task, wherein the high-dimensional capacitance matrix is transferred and replaced into a lower-dimensional principal-component matrix. A fourth step 608 computes the sensitivities in the space of the lower-dimensional principal -component matrix. A fifth step 610 adjusts the layout data to the best direction found.

[0059] FIG. 7 illustrates a method of generating layout data using Pareto efficient coefficients. The method is carried out by a processor executing a program code.

[0060] In a first step 702, layout structure data is imported. A second step 704 records the capacitance matrix containing the capacitance values of parasitic capacitances effective in a feasible layout. The second step 704 is repeated for each feasible layout. A third step 706 computes the Pareto efficient coefficients defining the Pareto front. A fourth step 708 involves a PCA for reducing the dimensionality of the task, wherein the high-dimensional capacitance matrix is transferred to and replaced with a lower-dimensional principalcomponent matrix adjusted to the Pareto front. A fifth step 710 computes the sensitivities in the space of the lower-dimensional principal-component matrix. A sixth step 712 adjusts the layout data to the best direction found.

[0061] FIG. 8 shows an electronic design automation apparatus 80 that includes a simulating module 81 to determine a capacitance matrix for each of a plurality of sets of variable routing parameters for wiring connections, wherein each capacitance matrix includes a set of capacitance values for parasitic capacitances between the wiring connections. A PCA module 82 determines a number of principal components for at least a subset of the capacitance values in a capacitance space spanned by the parasitic capacitances. A data interface 83 outputs information obtained from the principal components.

[0062] A Pareto module may determine the principal components predominantly or exclusively from Pareto efficient capacitance matrices. A sensitivity analysis module may determine benchmark sensitivities of the principal components to changes in the routing parameters or capacitive values; and a sensitivity minimization module may determine routing parameters for a robust routing, wherein the robust routing is less sensitive to changes in the routing parameters than most or all other possible routings.

[0063] The present technology can also be configured as described below:

[0064] [1] A method for generating layout routing data, the method including: determining a capacitance matrix for each of a plurality of sets of variable routing parameters for wiring connections, wherein each capacitance matrix includes a set of capacitance values for parasitic capacitances between the wiring connections; determining, by a processor, a number of principal components for at least a subset of the capacitance values in a capacitance space spanned by the parasitic capacitances; and obtaining the layout routing data based on information obtained from the principal components. [2] The method according to [1], wherein the number of determined principal components is selected so that the number of principal components determined represent at least 80% of a total variance of the capacitance values.

[0065] [3] The method according to any of [1] and [2], wherein the layout routing data describes a wiring fabric.

[0066] [4] The method according to any of [1] to [3], wherein obtaining the layout routing data includes performing an automated routing process using information obtained from the principal components.

[0067] [5] The method according to any of [1] to [4], wherein all parasitic capacitances are used to determine the principal components.

[0068] [6] The method according to any of [1] to [4], wherein the principal components are derived predominantly or exclusively from Pareto efficient capacitance matrices.

[0069] [7] The method according to any of [1] to [6], wherein obtaining the layout routing data includes determining benchmark sensitivities of the principal components to changes of the routing parameters or the capacitance values and determining the layout routing data based on the benchmark sensitivities of the principal components.

[0070] [8] The method according to [7], wherein a routing described by the layout routing data is developed in a direction of a low benchmark sensitivity of the principal components.

[0071] [9] The method according to any of [1] to [8], wherein a space of feasible routings defines a space of feasible capacitance values defining a rout-constrain and the rout-constrain is determined from the principal components.

[0072]

[0010] The method according to any of [1] to [9], wherein a best direction in the rout-constrain is computed on the basis of the benchmark sensitivities and determining the layout routing data includes processing information about the best direction in the rout-constrain.

[0073]

[0011] An electronic design automation apparatus includes: a simulating module (81) configured to determine a capacitance matrix for each of a plurality of sets of variable routing parameters for wiring connections, wherein each capacitance matrix includes a set of capacitance values for parasitic capacitances between the wiring connections; a PCA module (82) configured to determine a number of principal components for at least a subset of the capacitance values in a capacitance space spanned by the parasitic capacitances; and a data interface (83) configured to output information obtained from the principal components.

[0074]

[0012] The electronic design automation apparatus according to

[0011] , further including: a Pareto module configured do determine the principal components predominantly or exclusively from Pareto efficient capacitance matrices.

[0013] The electronic design automation apparatus according to any of

[0011] and

[0012] , further including: a sensitivity analysis module configured to determine benchmark sensitivities of the principal components to changes in the routing parameters or capacitive values; and a sensitivity minimization module configured to determine routing parameters for a robust routing, the robust routing being less sensitive to changes in the routing parameters than most or all other possible routings.

Claims

CLAIMS1. A method for generating layout routing data, the method comprising: determining a capacitance matrix for each of a plurality of sets of variable routing parameters for wiring connections, wherein each capacitance matrix comprises a set of capacitance values for parasitic capacitances between the wiring connections; determining, by a processor, a number of principal components for at least a subset of the capacitance values in a capacitance space spanned by the parasitic capacitances; and obtaining the layout routing data based on information obtained from the principal components.

2. The method according to claim 1, wherein the number of determined principal components is selected so that the number of principal components determined represent at least 80% of a total variance of the capacitance values.

3. The method according to claim 1, wherein the layout routing data describes a wiring fabric.

4. The method according to claim 1, wherein obtaining the layout routing data comprises performing an automated routing process using information obtained from the principal components.

5. The method according to claim 1, wherein all parasitic capacitances are used to determine the principal components.

6. The method according to claim 1, wherein the principal components are derived predominantly or exclusively from Pareto efficient capacitance matrices.

7. The method according to claim 1, wherein obtaining the layout routing data comprises determining benchmark sensitivities of the principal components to changes of the routing parameters or the capacitance values and determining the layout routing data based on the benchmark sensitivities of the principal components.

8. The method according to claim 7, wherein a routing described by the layout routing data is developed in a direction of a low benchmark sensitivity of the principal components.

9. The method according to claim 1, wherein a space of feasible routings defines a space of feasible capacitance values defining a routconstrain and the rout-constrain is determined from the principal components.

10. The method according to claim 9, wherein a best direction in the rout-constrain is computed on the basis of the benchmark sensitivities and determining the layout routing data comprises processing information about the best direction in the rout-constrain.

11. An electronic design automation apparatus, comprising: a simulating module configured to determine a capacitance matrix for each of a plurality of sets of variable routing parameters for wiring connections, wherein each capacitance matrix comprises a set of capacitance values for parasitic capacitances between the wiring connections; a PCA module configured to determine a number of principal components for at least a subset of the capacitance values in a capacitance space spanned by the parasitic capacitances; and a data interface configured to output information obtained from the principal components.

12. The electronic design automation apparatus according to claim 11, further comprising: a Pareto module configured do determine the principal components predominantly or exclusively from Pareto efficient capacitance matrices.

13. The electronic design automation apparatus according to claim 11, further comprising: a sensitivity analysis module configured to determine benchmark sensitivities of the principal components to changes in the routing parameters or capacitive values; and a sensitivity minimization module configured to determine routing parameters for a robust routing, the robust routing being less sensitive to changes in the routing parameters than most or all other possible routings.

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