Laminated device, method for manufacturing laminated device, and electronic apparatus

Abstract

A laminated device according to one embodiment of the present disclosure comprises: a first substrate that includes a semiconductor layer having a first surface and a second surface that face each other and has a first functional element configured from the semiconductor layer; a second substrate that faces the second surface of the semiconductor layer and is laminated on the first substrate; and an alignment mark that is formed of a conductive film with visible light transmissivity and that is provided on the first substrate on the second surface side of the semiconductor layer.

Description

Stacked device, method for manufacturing the stacked device, and electronic device

[0001] The present disclosure relates to a laminated device, a manufacturing method thereof, and an electronic device including the same.

[0002] For example, Patent Document 1 discloses an imaging device in which a CMOS circuit section is formed on a silicon substrate, and then an alignment mark is formed through the CMOS circuit section to reach the silicon substrate.

[0003] JP 2019-201171 A

[0004] Incidentally, for example, in a stacked device formed by bonding together substrates of different sizes, there is a demand for improved alignment accuracy.

[0005] It is desirable to provide a stacked device that allows highly accurate alignment, a method for manufacturing the stacked device, and an electronic device.

[0006] A stacked device according to one embodiment of the present disclosure includes a first substrate including a semiconductor layer having opposing first and second surfaces and having a first functional element formed from the semiconductor layer; a second substrate stacked on the first substrate opposite the second surface of the semiconductor layer; and an alignment mark provided on the first substrate on the side of the second surface of the semiconductor layer and formed from a conductive film that is transparent to visible light.

[0007] A method for manufacturing a stacked device according to one embodiment of the present disclosure includes forming a semiconductor layer on a growth substrate by epitaxial growth, depositing a conductive film that is transparent to visible light on the semiconductor layer to form an alignment mark, dicing the semiconductor layer into multiple pieces, transferring the multiple diced semiconductor layers to a support substrate, processing each of the multiple semiconductor layers to form multiple first functional elements, and then hybrid-bonding and bonding the first substrate having the multiple first functional elements to a second substrate.

[0008] An electronic device according to an embodiment of the present disclosure includes the stacked device according to the embodiment of the present disclosure.

[0009] In a stacked device according to an embodiment of the present disclosure, a manufacturing method of the stacked device according to an embodiment, and an electronic device according to an embodiment, in a configuration in which a first substrate having a first functional element and a second substrate are stacked, an alignment mark formed of a conductive film that is transparent to visible light is formed on a surface (second surface) of a semiconductor layer that constitutes the first functional element that faces the second substrate, thereby facilitating alignment when the semiconductor layer is divided into individual pieces and transferred in the process of forming the first functional element.

[0010] FIG. 1 is a cross-sectional schematic diagram illustrating an example of a configuration of a light-emitting device according to an embodiment of the present disclosure. FIG. 2 is a schematic diagram illustrating an example of the overall planar configuration of the light-emitting device illustrated in FIG. 1. FIG. 3 is a schematic diagram illustrating an enlarged portion of the planar configuration of the light-emitting device illustrated in FIG. 2. FIG. 4A is a diagram illustrating an example of a planar shape of an alignment mark illustrated in FIG. 1, etc. FIG. 4B is a diagram illustrating another example of a planar shape of an alignment mark illustrated in FIG. 1, etc. FIG. 4C is a diagram illustrating another example of a planar shape of an alignment mark illustrated in FIG. 1, etc. FIG. 4D is a diagram illustrating another example of a planar shape of an alignment mark illustrated in FIG. 1, etc. FIG. 4E is a diagram illustrating another example of a planar shape of an alignment mark illustrated in FIG. 1, etc. FIG. 4F is a diagram illustrating another example of a planar shape of an alignment mark illustrated in FIG. 1, etc. FIG. 4G is a diagram illustrating another example of a planar shape of an alignment mark illustrated in FIG. 1, etc. FIG. 4H is a diagram illustrating another example of a planar shape of an alignment mark illustrated in FIG. 1, etc. FIG. 4I is a diagram illustrating another example of a planar shape of an alignment mark illustrated in FIG. 1, etc. FIG. 5A is a cross-sectional view illustrating an example of a manufacturing process for the light-emitting device shown in FIG. 1 . FIG. 5B is a cross-sectional view illustrating a process subsequent to FIG. 5A . FIG. 5C is a cross-sectional view illustrating a process subsequent to FIG. 5B . FIG. 5D is a cross-sectional view illustrating a process subsequent to FIG. 5C . FIG. 5E is a cross-sectional view illustrating a process subsequent to FIG. 5D . FIG. 5F is a cross-sectional view illustrating a process subsequent to FIG. 5E . FIG. 5G is a cross-sectional view illustrating a process subsequent to FIG. 5F . FIG. 5H is a cross-sectional view illustrating a process subsequent to FIG. 5G . FIG. 5I is a cross-sectional view illustrating a process subsequent to FIG. 5H . FIG. 5J is a cross-sectional view illustrating a process subsequent to FIG. 5A . FIG. 5K is a cross-sectional view illustrating a process subsequent to FIG. 5J . FIG. 5L is a cross-sectional view illustrating a process subsequent to FIG. 5K . FIG. 6A is a plan view corresponding to FIG. 5A . FIG. 6B is a plan view corresponding to FIG. 5B . FIG. 6C is a plan view corresponding to FIG. 5C . Fig. 6D is a schematic plan view corresponding to Fig. 5D. Fig. 7A is a schematic cross-sectional view showing a step following Fig. 5H. Fig. 7B is a schematic cross-sectional view showing a step following Fig. 7A. Fig. 7C is a schematic cross-sectional view showing a step following Fig. 7B. Fig. 7D is a schematic cross-sectional view showing a step following Fig. 7C. Fig. 7E is a schematic cross-sectional view showing a step following Fig. 7D.FIG. 7F is a schematic cross-sectional view showing a step subsequent to FIG. 7E. FIG. 7G is a schematic cross-sectional view showing a step subsequent to FIG. 7F. FIG. 7H is a schematic cross-sectional view showing a step subsequent to FIG. 7G. FIG. 7I is a schematic cross-sectional view showing a step subsequent to FIG. 7H. FIG. 7J is a schematic cross-sectional view showing a step subsequent to FIG. 7I. FIG. 7K is a schematic cross-sectional view showing a step subsequent to FIG. 7J. FIG. 7L is a schematic cross-sectional view showing a step subsequent to FIG. 4K. FIG. 7M is a schematic cross-sectional view showing a step subsequent to FIG. 7L. FIG. 7N is a schematic cross-sectional view showing a step subsequent to FIG. 7M. FIG. 7O is a schematic cross-sectional view showing a step subsequent to FIG. 7N. FIG. 7P is a schematic cross-sectional view showing a step subsequent to FIG. 7O. FIG. 7Q is a schematic cross-sectional view showing a step subsequent to FIG. 7P. FIG. 7R is a schematic cross-sectional view showing a step subsequent to FIG. 7Q. FIG. 7S is a schematic cross-sectional view showing a step subsequent to FIG. 7R. FIG. 7T is a schematic cross-sectional view showing a step subsequent to FIG. 7S. 7U is a cross-sectional view showing a step subsequent to FIG. 7T. FIG. 7V is a cross-sectional view showing a step subsequent to FIG. 7U. FIG. 7W is a cross-sectional view showing a step subsequent to FIG. 7V. FIG. 8A is a cross-sectional view (A) and a plan view (B) illustrating an example of a manufacturing process for the alignment mark and its surroundings shown in FIG. 1. FIG. 8B is a cross-sectional view (A) and a plan view (B) showing a step subsequent to FIG. 8A. FIG. 8C is a cross-sectional view (A) and a plan view (B) showing a step subsequent to FIG. 8B. FIG. 8D is a cross-sectional view showing a step subsequent to FIG. 8C. FIG. 8E is a cross-sectional view showing a step subsequent to FIG. 8D. FIG. 8F is a cross-sectional view showing a step subsequent to FIG. 8E. FIG. 9 is a cross-sectional view showing an example of a configuration of a light-emitting device according to Modification 1 of the present disclosure. FIG. 10 is a schematic view showing an example of the overall planar configuration of the light-emitting device shown in FIG. 9. Fig. 11A is a cross-sectional view (A) and a plan view (B) illustrating an example of a manufacturing process for an alignment mark and its surroundings according to Modification 2 of the present disclosure. Fig. 11B is a cross-sectional view (A) and a plan view (B) illustrating a process subsequent to Fig. 11A. Fig. 11C is a cross-sectional view (A) and a plan view (B) illustrating a process subsequent to Fig. 11B. Fig. 11D is a cross-sectional view (A) and a plan view (B) illustrating a process subsequent to Fig. 11C. Fig. 11E is a cross-sectional view (A) and a plan view (B) illustrating a process subsequent to Fig. 11D. Fig. 11F is a cross-sectional view (A) and a plan view (B) illustrating a process subsequent to Fig. 11E.12A is a cross-sectional view (A) and a plan view (B) illustrating an example of a manufacturing process for an alignment mark and its surroundings according to Variation 3 of the present disclosure. FIG. 12B is a cross-sectional view (A) and a plan view (B) illustrating a process subsequent to FIG. 12A. FIG. 12C is a cross-sectional view (A) and a plan view (B) illustrating a process subsequent to FIG. 12B. FIG. 12D is a cross-sectional view (A) and a plan view (B) illustrating a process subsequent to FIG. 12C. FIG. 12E is a cross-sectional view (B) illustrating a process subsequent to FIG. 12D. FIG. 13A is a front view illustrating an example of the appearance of a digital still camera as an application example of the present disclosure. FIG. 13B is a rear view illustrating an example of the appearance of the digital still camera shown in FIG. 13A. FIG. 14A is a perspective view illustrating the appearance of an example of a head-mounted display as an application example of the present disclosure. FIG. 14B is a perspective view illustrating the appearance of another example of a head-mounted display as an application example of the present disclosure. FIG. 15 is a perspective view illustrating an example of the appearance of a television device as an application example of the present disclosure.

[0011] An embodiment of the present disclosure will be described in detail below with reference to the drawings. The following description is a specific example of the present disclosure, and the present disclosure is not limited to the following aspects. Furthermore, the present disclosure is not limited to the arrangement, dimensions, dimensional ratios, etc. of the components shown in the drawings. The description will be given in the following order: 1. First embodiment (an example of a light emitting device in which an alignment mark made of a transparent conductive film is provided on the surface of a compound semiconductor layer facing a drive substrate) 2. Modifications 2-1. Modification 1 (another example of the position where the alignment mark is formed) 2-2. Modification 2 (another example of the position where the alignment mark is formed) 2-3. Modification 3 (another example of the position where the alignment mark is formed) 3. Application examples

[0012] 1. Embodiment Fig. 1 is a schematic diagram illustrating an example of a cross-sectional configuration of a light-emitting device (light-emitting device 1) according to an embodiment of the present disclosure. Fig. 2 is a schematic diagram illustrating an example of an overall planar configuration of the light-emitting device 1 illustrated in Fig. 1. The light-emitting device 1 is suitably applicable to image display devices known as LED displays (e.g., electronic viewfinder 1124 of a digital still camera 1120, see Fig. 13B).

[0013] The light-emitting device 1 is formed by stacking an element substrate 10 and a drive substrate 30, for example, by hybrid bonding. The element substrate 10 includes a compound semiconductor layer 110 having a pair of opposing surfaces (surfaces 11S1 and 11S2), and has a light-emitting element 11 configured with the compound semiconductor layer 110 (see, for example, FIG. 5A ). The drive substrate 30 is disposed facing a surface 11S2 of the compound semiconductor layer 110 opposite to the surface 11S1, which serves as a light extraction surface. The element substrate 10 has an alignment mark 116 on the surface 11S2 side of the compound semiconductor layer 110. The alignment mark 116 is formed of a transparent conductive film that is transparent to visible light.

[0014] Here, the light emitting device 1 corresponds to a specific example of a "laminated device" in an embodiment of the present disclosure. The element substrate 10 corresponds to a specific example of a "first substrate" in an embodiment of the present disclosure. The compound semiconductor layer 110 corresponds to a specific example of a "semiconductor layer" in an embodiment of the present disclosure. The surface 11S1 corresponds to a specific example of a "first surface" in an embodiment of the present disclosure, and the surface 11S2 corresponds to a specific example of a "second surface" in an embodiment of the present disclosure. The drive substrate 30 corresponds to a specific example of a "second substrate" in an embodiment of the present disclosure. The alignment mark 116 corresponds to a specific example of an "alignment mark" in an embodiment of the present disclosure.

[0015] [Configuration of Light-Emitting Device] The light-emitting device 1 has a pixel array section 100A in which a plurality of light-emitting elements 11 are arranged in a two-dimensional array, and a peripheral section 100B provided around the pixel array section 100A. The light-emitting device 1 is, for example, configured such that an element substrate 10 in which a plurality of light-emitting elements 11 are arranged in an array, and a wavelength conversion section 20 are stacked in this order on the surface 30S1 side of a drive substrate 30 having an opposing front surface (surface 30S1) and back surface (surface 30S2).

[0016] As described above, the element substrate 10 has a plurality of light-emitting elements 11 arranged in a two-dimensional array in the pixel array section 100A. For example, the plurality of light-emitting elements 11 have a generally regular hexagonal shape and are arranged in, for example, a honeycomb pattern, as shown in FIG. 3 . An electrode layer 12, an insulating layer 13, and an extraction electrode 14 are formed in this order on the surface 11S1 side of the plurality of light-emitting elements 11. An electrode layer 114, an insulating layer 115, and a protective layer 117 are formed for each element on the surface 11S2 side of the plurality of light-emitting elements 11. An insulating film 118A and a reflective film 118B are formed continuously with the plurality of light-emitting elements 11. An embedding layer 119 embedding the plurality of light-emitting elements 11 is also formed in this order on the surface 11S2 side of the plurality of light-emitting elements 11. A plug 15 is also formed for each element on the surface 11S2 side of the plurality of light-emitting elements 11. An insulating layer 17 including a pad portion 16A and a pad electrode 16B, and an insulating layer 18 including a pad portion 19 that electrically and physically bonds the element substrate 10 to the drive substrate 30. Furthermore, alignment marks 116 are formed on the surface 11S2 of the light-emitting element 11. The alignment marks 116 are provided on the surface 11S2 of the compound semiconductor layer 110 constituting the light-emitting element 11, which is present in the pixel array section 100A and the peripheral section 100B, as shown in Fig. 2, for example, and are arranged, for example, on the periphery of the pixel array section 100A and the peripheral section 100B, respectively.

[0017] The light-emitting element 11 is a solid-state light-emitting element that emits light in a predetermined wavelength band from a surface 11S1, such as an LED (Light Emitting Diode) chip. The LED chip refers to an LED cut from a wafer used for crystal growth, and is not a packaged type covered with a molded resin or the like. The LED chip has a size of, for example, 5 μm to 100 μm, and is known as a micro LED.

[0018] Light-emitting element 11 has a first conductivity type layer 111 and a second conductivity type layer 113 stacked in this order, with the upper surface of second conductivity type layer 113 serving as a light-emitting surface (surface 11S1). A light-emitting region 112 is formed between first conductivity type layer 111 and second conductivity type layer 113. Light in the blue band of, for example, 430 nm or more and 500 nm or less is extracted from light-emitting region 112. In addition to this, light with a wavelength corresponding to, for example, the ultraviolet region (ultraviolet light) may also be extracted from the light-emitting region.

[0019] The first conductivity type layer 111 is made of, for example, a p-type GaN-based semiconductor material, and the second conductivity type layer 113 is made of, for example, an n-type GaN-based semiconductor material.

[0020] The electrode layer 12 is formed continuously on the surface 11S1 of each of the light-emitting elements 11 as a common electrode for the light-emitting elements 11. The electrode layer 12 is in ohmic contact with the second conductivity type layer 113 and is formed of a transparent electrode material such as indium tin oxide (ITO), indium zinc oxide (IZO), tin oxide (SnO), or TiO.

[0021] The insulating layer 13 fills the irregularities formed above the plurality of light emitting elements 11. The insulating layer 13 is made of, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0022] The extraction electrode 14 applies a voltage to the second conductivity type layer 113 of each of the plurality of light-emitting elements 11 and is electrically connected to the electrode layer 12, for example, through an opening 13H (see FIG. 7Q) provided in the insulating layer 13 between adjacent light-emitting elements 11. In the pixel array section 100A, the extraction electrode 14 is formed continuously between adjacent light-emitting elements 11, for example, to avoid the surfaces 11S1 of the plurality of light-emitting elements 11 arranged in a honeycomb pattern, and extends to a portion of the peripheral section 100B. The extraction electrode 14 formed in the peripheral section 100B is electrically connected to the pad electrode 16B through an opening H1 that penetrates the insulating layer 13, the embedded layer 119, and the protective layer 117. The extraction electrode 14 is formed, for example, using a multilayer film (Ti / Al) of titanium (Ti) and aluminum (Al) or a multilayer film (Cr / Au) of chromium (Cr) and gold (Au).

[0023] An electrode layer 114 is formed on the lower surface (surface 11S2) of the first conductivity type layer 111 of the light emitting element 11. The electrode layer 114 is in ohmic contact with the first conductivity type layer 111 and is formed using a transparent conductive material such as a multilayer film (Ni / Au) of nickel (Ni) and gold (Au) or ITO.

[0024] The insulating layer 115 is provided on the electrode layer 114. The insulating layer 115 is made of, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0025] The alignment marks 116, which will be described in detail later, are used, for example, for alignment when transferring a plurality of singulated chips of the compound semiconductor layer 110 constituting the light-emitting element 11 onto the transfer substrate 53. The alignment marks 116 are provided on the surfaces 11S2 of the compound semiconductor layer 110 constituting the light-emitting element 11, which are present in the pixel array section 100A and the peripheral section 100B. As described above, the alignment marks 116 are respectively arranged on the periphery of the pixel array section 100A and the peripheral section 100B.

[0026] 4A to 4I are schematic diagrams showing examples of the planar shape of the alignment mark 116. The shape of the alignment mark 116 may be any shape that can be read by an exposure machine. For example, the alignment mark 116 may be cross-shaped, as shown in FIGS. 2 and 4A. The alignment mark 116 may be X-shaped, as shown in FIG. 4B, or circular, as shown in FIG. 4C. The alignment mark 116 may be flower-shaped, as shown in FIG. 4D, square-shaped, as shown in FIG. 4E, or diamond-shaped, as shown in FIG. 4F. The alignment mark 116 may be lattice-shaped, as shown in FIG. 4G, or fence-shaped, as shown in FIG. 4H. The alignment mark 116 may be a so-called Dutch windmill-shaped, as shown in FIG. 4I.

[0027] Similarly, the size and thickness of the alignment mark 116 may be, for example, a size and thickness that can be read by an exposure machine. For example, the size of the alignment mark 116 may be, for example, 10 μm or more and 100 μm or less. The thickness of the alignment mark 116 may be, for example, 200 nm or more.

[0028] The alignment mark 116 can be formed of, for example, a transparent conductive film that is transparent to visible light. Examples of transparent conductive films that are transparent to visible light include an ITO film, an IZO film, a SnO film, and a TiO film.

[0029] 2 shows an example in which the alignment marks 116 formed on each chip are provided at positions that will become the pixel array section 100A and the peripheral section 100B of the light-emitting device 1, but this is not limiting. For example, the alignment marks 116 formed on each chip may be provided at either the position that will become the pixel array section 100A or the position that will become the peripheral section 100B of the light-emitting device 1. Alternatively, without considering the positions that will become the pixel array section 100A and the peripheral section 100B of the light-emitting device 1, one alignment mark 116 may be provided at each of the four corners of each rectangular chip, as shown in FIG. 6C , for example.

[0030] The light emitting element 11 has a mesa shape on the drive substrate 30 side, including the first conductivity type layer 111, the light emitting region 112, and a part of the second conductivity type layer 113. A surface 11S2 of the light emitting element 11 processed into a mesa shape and side surfaces of the first conductivity type layer 111, the light emitting region 112, and a part of the second conductivity type layer 113 are covered with a protective layer 117. The protective layer 117 is formed of, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0031] Furthermore, the protective layer 117 and the side surfaces of the second conductivity type layer 113 exposed from the protective layer 117 are covered with a laminated film made of an insulating film 118A and a reflective film 118B. The laminated film is continuously formed on the plurality of light-emitting elements 11. The laminated film has an opening 118H on the surface 11S2 side of the light-emitting element 11, and a plug 15 is formed in the opening 118H. The insulating film 118A is formed of an insulating material such as silicon oxide (SiO) or silicon nitride (SiN). The reflective film 118B is formed of a metal having a high reflectivity in the visible light range. Specific examples of the material include silver (Ag), aluminum (Al), copper (Cu), gold (Au), platinum (Pt), rhodium (Rh), and alloys thereof.

[0032] The embedding layer 119 embeds the plurality of light emitting elements 11 and forms flat front and back surfaces of the element substrate 10. The embedding layer 119 is made of an insulating material such as silicon oxide (SiO) or silicon nitride (SiN).

[0033] The plugs 15 apply a voltage to the first conductivity type layers 111 of the plurality of light emitting elements 11. The plugs 15 are formed using, for example, copper (Cu), aluminum (Al), tungsten (W), silver (Ag), or alloys thereof.

[0034] An insulating layer 17 is provided on the drive substrate 30 side of the embedded layer 119. A plurality of pad portions 16A provided for each light-emitting element 11A in the pixel array section 100A, a plurality of pad electrodes 16B provided in the peripheral section 100B, and vias are formed in the insulating layer 17. The insulating layer 17 is formed of, for example, silicon oxide (SiO) or silicon nitride (SiN). The pad portions 16A, pad electrodes 16B, and vias are formed of, for example, copper (Cu), aluminum (Al), tungsten (W), silver (Ag), or an alloy thereof.

[0035] Further provided on the drive substrate 30 side of the insulating layer 17 are an insulating layer 18 that forms a bonding surface with the drive substrate 30, and a pad portion 19 that is embedded in the insulating layer 18. The insulating layer 18 is made of, for example, silicon oxide (SiO) or silicon nitride (SiN). The pad portion 19 is made of, for example, copper (Cu).

[0036] The wavelength conversion unit 20 is provided on the light extraction surface S1 side of the element substrate 10. The wavelength conversion unit 20 includes a planarization layer 21, a partition layer 22 having an opening 22H for each light emitting element 11, and a wavelength conversion layer 23 formed in the opening 22H. A reflective film 24 is further provided between the partition layer 22 and the wavelength conversion layer 23. A protective layer 25 is further provided on the light extraction surface S1 side of the wavelength conversion layer 23, and a wavelength selection layer 26 is provided in the protective layer 25. An on-chip lens layer 27 is further provided on the protective layer 25.

[0037] The planarization layer 21 is intended to planarize the surface on the light extraction surface S1 side of the element substrate 10. The planarization layer 21 is formed of, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0038] The partition layer 22 is intended to suppress color mixing due to light leakage between adjacent RGB subpixels (red pixel Pr, green pixel Pg, and blue pixel Pb) when the light-emitting device 1 is applied to the image display device 100. The partition layer 22 has, for example, a honeycomb structure. Specifically, as shown in FIG. 3 , the partition layer 22 has, for example, a substantially regular hexagonal opening 22H for each of the plurality of light-emitting elements 11 arranged in an array. In cross-sectional view, the opening 22H has, for example, a surface inclined at an angle of less than 90° with respect to the surface 20S2 of the wavelength conversion section 20 opposite the surface 20S1. In other words, in cross-sectional view, the partition layer 22 has a forward tapered shape between adjacent color pixels Pr, Pg, and Pb. The partition layer 22 is preferably formed using a material with high thermal conductivity and electrical conductivity, such as a metal material such as copper (Cu), aluminum (Al), gold (Au), nickel (Ni), or platinum (Pt).

[0039] The wavelength conversion layer 23 converts light emitted from the plurality of light-emitting elements 11 into a desired wavelength (e.g., red (R) / green (G) / blue (B)) and emits the converted light, and is formed in an opening 22H provided above each light-emitting element 11. Specifically, the red pixel Pr is provided with a red wavelength conversion layer 23R that converts light emitted from the light-emitting elements 11 into light in a red band (red light), the green pixel Pg is provided with a green wavelength conversion layer 23G that converts light emitted from the light-emitting elements 11 into light in a green band (green light), and the blue pixel Pb is provided with a blue wavelength conversion layer 23B that converts light emitted from the light-emitting elements 11 into light in a blue band (blue light).

[0040] Each wavelength conversion layer 23R, 23G, 23B can be formed using quantum dots corresponding to each color. Specifically, when red light is obtained, the quantum dots can be selected from, for example, InP, GaInP, InAsP, CdSe, CdZnSe, CdTeSe, or CdTe. When green light is obtained, the quantum dots can be selected from, for example, InP, GaInP, ZnSeTe, ZnTe, CdSe, CdZnSe, CdS, or CdSeS. When blue light is obtained, the quantum dots can be selected from, for example, ZnSe, ZnTe, ZnSeTe, CdSe, CdZnSe, CdS, CdZnS, and CdSeS. Note that when blue light is emitted from the light-emitting element 11 as described above, the blue wavelength conversion layer 23B may be formed from a light-transmitting resin layer.

[0041] The reflective film 24 is provided on the side surface of the opening 22H to efficiently extract the color light emitted from the light-emitting element 11 and converted in the wavelength conversion layers 23R, 23G, and 23B from the light extraction surface (surface 22S1) of the wavelength conversion layer 23. The reflective film 24 is formed using a metal material with light reflectivity. Examples of the metal material for forming the reflective film 24 include metals with high reflectivity in the visible light range. Specific examples of the material include silver (Ag), aluminum (Al), copper (Cu), gold (Au), platinum (Pt), rhodium (Rh), and alloys thereof.

[0042] It should be noted that the reflective film 24 does not necessarily have to be formed when the partition wall layer 22 is formed using the above-mentioned metal material having light reflectivity.

[0043] The protective layer 25 is for protecting the surface of the light emitting device 1 and is made of, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0044] A wavelength selection layer 26 is provided across the red pixel Pr and the green pixel Pg within the protective layer 25. The wavelength selection layer 26 selectively reflects, for example, light in the blue wavelength band (blue light), thereby improving the color purity of the red light and green light extracted from the red pixel Pr and the green pixel Pg, respectively.

[0045] The on-chip lens layer 27 is provided so as to cover the entire surfaces of the pixel array unit 100A and the peripheral unit 100B. The on-chip lens layer 27 is made of a light-transmitting material, and is made of, for example, a single-layer film made of any of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiCN), etc., or a stacked film made of two or more of these materials.

[0046] The peripheral portion 100B is provided with an opening H2 that penetrates the on-chip lens layer 27, the protective layer 25, the partition layer 22, the planarizing layer 21, the insulating layer 13, the embedded layer 119, and the protective layer 117 and reaches the pad electrode 18B. The pad electrode 18B exposed at the bottom of this opening H2 is used as an electrode for connection to the outside.

[0047] The drive substrate 30 is provided with a drive circuit and the like that controls the drive of the plurality of light-emitting elements 11 arranged in the pixel array section 100A. This drive circuit corresponds to a specific example of a "second functional element" in an embodiment of the present disclosure. The drive substrate 30 includes a support substrate 31 made of, for example, silicon (Si), an interlayer insulating layer 32 that is provided on the support substrate 31 and includes a plurality of wiring layers (e.g., wiring layers M1, M2, M3, M4, and M5) and vias that electrically connect the wiring layers, an insulating layer 33 that forms a bonding surface with the element substrate 10, and a pad portion 34 that is embedded in the insulating layer 33.

[0048] The interlayer insulating layer 32 is made of, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0049] The wiring layers M1, M2, M3, M4, and M5 and the vias electrically connecting the wiring layers are formed using, for example, copper (Cu), aluminum (Al), tungsten (W), silver (Ag), or alloys thereof. The insulating layer 33 is formed using, for example, silicon oxide (SiO), silicon nitride (SiN), or the like. The pad portion 35 is formed using, for example, copper (Cu).

[0050] [Method of Manufacturing Light-Emitting Device] The light-emitting device 1 of this embodiment can be manufactured, for example, as follows. Figures 5A to 5L, 6A to 6D, 7A to 7W, and 8A to 8F illustrate an example of a manufacturing process for the light-emitting device 1. Figures 5A to 5L and 7A to 7W are cross-sectional schematic views illustrating the manufacturing process for the light-emitting device 1. Figures 6A to 6D are plan schematic views corresponding to the respective steps in Figures 5A to 5D. Figures 8A to 8F are cross-sectional schematic views (A) and plan schematic views (B) illustrating the manufacturing process for the alignment mark between Figures 5A and 5B.

[0051] 5A and 6A , for example, a silicon substrate is used as a growth substrate 51, and a compound semiconductor layer 110 is formed by epitaxial crystal growth using a method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). Subsequently, a transparent conductive film 116A made of, for example, ITO is formed on the compound semiconductor layer 110 by, for example, chemical vapor deposition (CVD).

[0052] 5B and 6B , alignment marks 116 are formed on the compound semiconductor layer 110, for example, in alignment with the boundaries (see dotted lines in FIG. 6B ) that will be used when dividing the compound semiconductor layer 110. Subsequently, an electrode layer 114 made of, for example, ITO and an insulating layer 115 are formed, and then the surface of the insulating layer 115 is planarized by, for example, chemical mechanical polishing (CMP).

[0053] Specifically, as shown in FIG. 8A , a compound semiconductor layer 110 and a transparent conductive film 116A are sequentially formed on a growth substrate 51. Then, as shown in FIG. 8B , a resist film 201 is patterned, for example, in a cross shape, on the transparent conductive film 116A. Subsequently, as shown in FIG. 8C , the transparent conductive film 116A is processed by, for example, dry etching, and the resist film 201 is then peeled off. This results in a cross-shaped alignment mark 116 being formed on the compound semiconductor layer 110. Next, as shown in FIG. 8D , an electrode layer 114 made of, for example, ITO and an insulating layer 115, for example, a SiO film 115A and a SiN film 115B, are sequentially formed on the compound semiconductor layer 110. Subsequently, as shown in FIG. 8E , a tetraethyl orthosilicate (TEOS) film 115C is further formed as the insulating layer 115. Then, as shown in FIG. 8F , the surface of the insulating layer 115 (TEOS film 115C) is planarized by CMP.

[0054] 5C and 6C, the insulating layer 115, the electrode layer 114, and the compound semiconductor layer 110 are etched and patterned using, for example, photolithography. Next, as shown in FIGS. 5D and 6D, the growth substrate 51 is transferred to the support substrate 52 so that the insulating layer 115 faces the support substrate 52, and then the growth substrate 51 is cut into individual pieces.

[0055] 5E, each chip including the singulated growth substrate 51 is bonded to the transfer substrate 53 so that the insulating layer 115 faces the transfer substrate 53. At this time, by bonding the chips to the transfer substrate 53 while detecting the alignment marks 116 using a transfer machine, misalignment of each chip is reduced.

[0056] Next, as shown in Fig. 5F, the growth substrate 51 is thinned to a thickness of, for example, 500 nm by grinding and polishing. Subsequently, as shown in Fig. 5G, an inversion substrate 54 is bonded to the growth substrate 51 side and inverted, and the transfer substrate 53 is peeled off. Next, the surface of the insulating layer 115 is planarized again by, for example, CMP, and then, as shown in Fig. 5H, the insulating layer 115 is bonded to the support substrate 55, and the growth substrate 51 is removed by, for example, grinding and polishing.

[0057] Subsequently, as shown in Fig. 5I, a buried layer 119 is formed on the support substrate 55 by, for example, CVD and then planarized. Next, as shown in Fig. 5J, the edge of the support substrate 55 is trimmed together with the buried layer 119. Next, as shown in Fig. 5K, the buried layer 119 is bonded to the support substrate 56 by, for example, plasma bonding, and then the support substrate 55 is peeled off. Below, the inside of the frame X shown in Fig. 5L will be explained in enlarged form.

[0058] 7A, the insulating layer 115 and the electrode layer 114 are etched and patterned using, for example, photolithography. Then, as shown in FIG. 7B, a mesa structure including the first conductivity type layer 111, the light emitting region 112, and a portion of the second conductivity type layer 113 is formed by etching a portion of the compound semiconductor layer 110 using, for example, photolithography.

[0059] Next, for example, by atomic layer deposition (ALD), an AlO film is formed on the top surface of insulating layer 115 and on the side and bottom surfaces of insulating layer 115, electrode layer 114, and first conductivity type layer 111, light emitting region 112, and second conductivity type layer 113 that constitute the mesa structure, and then a SiN film is further formed by, for example, CVD. Thereafter, the SiN film is etched using, for example, photolithography to form protective layer 117 as sidewalls on the top surface and side surfaces of the mesa structure, as shown in FIG. 7C .

[0060] 7D , for example, photolithography is used to form separation portions 110H that penetrate the second conductivity type layer 113 exposed from the protective layer 117 and the growth substrate 51, thereby forming a plurality of light emitting elements 11. Next, an AlO film is formed by, for example, ALD to cover the upper surface of the protective layer 117 and the exposed side surfaces of the light emitting elements 11. Next, as shown in FIG. 7E , an insulating film 118A and a reflective film 118B are formed in this order by, for example, CVD, and then an opening 118H is formed in the upper surface of the mesa structure.

[0061] Next, as shown in Fig. 7F, a buried layer 119 is further formed by, for example, CVD to fill the isolation portion 110H and the opening 118H. After that, the buried layer 119 is planarized, and then, as shown in Fig. 7G, an insulating layer 17 is formed for each light-emitting element 11, in which a plug 15, a plurality of pad portions 16A, and a pad electrode 16B are buried. Subsequently, as shown in Fig. 7H, the insulating layer 17 is thickened, and an insulating layer 18 is formed on the insulating layer 17. After that, as shown in Fig. 7I, the edge of the support substrate 55 is trimmed.

[0062] 7J, openings 18H are formed on the pad portions 16A and the pad electrodes 16B, and then, as shown in Fig. 7K, the openings 18H are filled with, for example, Cu to form the plurality of pad portions 19. Thereafter, the surfaces of the insulating layer 18 and the plurality of pad portions 19 are polished by, for example, CMP to flatten the bonding surfaces with the drive substrate 30.

[0063] Next, as shown in FIG. 7L, a plurality of pad portions 34 of a separately formed drive substrate 30 and a plurality of pad portions 19 are bonded to each other by CuCu bonding, for example, at 400°C. Thereafter, as shown in FIG. 7M, the support substrate 55 is peeled off. Next, as shown in FIG. 7N, the surfaces of the plurality of light-emitting elements 11 (specifically, the second conductivity type layer 113) are exposed using, for example, photolithography. Next, as shown in FIG. 7O, an ITO film is formed by, for example, CVD, and then the ITO film is patterned using, for example, photolithography to form an electrode layer 12.

[0064] Next, as shown in Fig. 7P, an insulating layer 13 is formed by, for example, CVD, and an opening 13H is formed between adjacent light-emitting elements 11 by, for example, photolithography, and then an opening H1 reaching the pad electrode 16B is formed by, for example, photolithography, as shown in Fig. 7Q. Subsequently, a stacked film of, for example, Ti / W is formed by, for example, CVD, and then the stacked film is patterned by, for example, photolithography, to form an extraction electrode 14 as shown in Fig. 7R.

[0065] Next, as shown in Fig. 7S, a planarizing layer 21 and a partition layer 22 are formed in this order, for example, by CVD. Subsequently, as shown in Fig. 7T, openings 22H are formed in the partition layer 22 above each light-emitting element 11, for example, by photolithography. Next, as shown in Fig. 7U, an Al film is formed on the top surface of the partition layer 22 and the side and bottom surfaces of the openings 22H, for example, by CVD, and then the Al film formed on the top surface of the partition layer 22 and the bottom surface of the openings 22H is removed by etch-back to form a reflective film 24 on the side surfaces of the openings 22H.

[0066] Next, as shown in FIG. 7V , wavelength conversion layers 23 (23R, 23G, 23B) of each color are formed in the opening 22H using a coating method such as an inkjet method. Then, as shown in FIG. 7W , a protective layer 25 including a wavelength selection layer 26 is formed on the partition layer 22 and the wavelength conversion layer 23, and then the on-chip lens layer 27 is bonded to the protective layer 25. At this time, by bonding the on-chip lens layer 27 while detecting the alignment marks 116 using a transfer machine, each microlens of the on-chip lens layer 27 can be bonded to each light-emitting element 11 arranged in a two-dimensional array with high precision. The light-emitting device 1 shown in FIG. 1 is thus completed.

[0067] (1-3. Actions and Effects) In the light emitting device 1 of this embodiment, alignment marks 116 made of a transparent conductive film that is transparent to visible light are provided on the surface 11S2 of the compound semiconductor layer 110 that constitutes the plurality of light emitting elements 11 arranged in an array within the surface of the element substrate 10. This makes it easier to align, for example, when transferring individualized chips of the compound semiconductor layer 110 to a transfer substrate 53 or the like in the process of forming the light emitting elements 11. This will be described below.

[0068] In recent years, high-definition image display devices using light-emitting devices with gallium nitride (GaN) micro LEDs as light sources have become widespread. These light-emitting devices require singulation and bonding of multiple GaN chips to a wafer. When this process is performed, variations in the placement of the GaN chips bonded to the wafer can result in reduced alignment accuracy for each GaN chip during subsequent manufacturing processes.

[0069] In contrast, in the present embodiment, before the compound semiconductor layer 110 is singulated, alignment marks 116 made of a transparent conductive film (e.g., ITO) that is transparent to visible light are formed on the compound semiconductor layer 110. This allows each chip of the singulated compound semiconductor layer 110 to be transferred with precision to, for example, a transfer substrate 53. In a light-emitting device 1 in which an element substrate 10, on which a plurality of light-emitting elements 11 formed by the compound semiconductor layer 110 are arranged in an array in its surface, and a drive substrate 30 are stacked, the alignment marks 116 remain on, for example, the periphery of the pixel array section 100A or the peripheral section 100B on the surface 11S2 of the compound semiconductor layer 110 facing the drive substrate 30. In the light-emitting device 1, the on-chip lens layer 27 can be bonded with precision to each light-emitting element 11 using the alignment marks 116 as a reference.

[0070] As described above, the light emitting device 1 of this embodiment and the image display device 100 including the same enable highly accurate alignment.

[0071] Furthermore, in the light-emitting device 1 of this embodiment, the alignment mark 116 is formed in the same layer as the electrode layer 114. As a result, even if a step is created around the alignment mark 116 by providing the alignment mark 116, the step can be eliminated by flattening the surface of the insulating layer 115 (TEOS film 115C) formed on the alignment mark 116, for example, by CMP. This eliminates the need to consider the effect on bonding with the drive substrate 30.

[0072] Next, modified examples 1 to 3 and application examples of the present disclosure will be described. Note that components corresponding to those of the light emitting device 1 of the above embodiment will be assigned the same reference numerals and descriptions thereof will be omitted.

[0073] 2. Modifications (2-1. Modification 1) Fig. 9 is a schematic diagram showing an example of a cross-sectional configuration of a light-emitting device (light-emitting device 2) according to Modification 1 of the present disclosure. Fig. 10 is a schematic diagram showing an example of the overall planar configuration of the light-emitting device 2 shown in Fig. 9. As with the above embodiment, the light-emitting device 2 is suitably applicable to an image display device known as a so-called LED display (for example, the electronic viewfinder 1124 of a digital still camera 1120).

[0074] In the above embodiment, an example was shown in which alignment marks 116 were provided on the periphery of the pixel array section 100A and on the peripheral section 100B in a plan view, but this is not limited thereto. The light-emitting device 2 of this modified example has a dummy region 100C between the pixel array section 100A, in which a plurality of light-emitting elements 11 are arranged in a two-dimensional array, and the peripheral section 100B provided around the pixel array section 100A. Similar to the pixel array section 100A, the compound semiconductor layer 110 constituting the light-emitting elements 11 is arranged in the dummy region 100C. For example, one alignment mark 116 is provided on the surface 11S2 of the compound semiconductor layer 110 arranged in this dummy region 100C. Except for this point, the light-emitting device 2 has substantially the same configuration as the light-emitting device 1 of the above embodiment.

[0075] In this way, in the light emitting device 2 of this modified example, the dummy region 100C is formed between the pixel array section 100A and the peripheral section 100B, and the alignment mark 116 is provided in this dummy region 100C. Even with this configuration, the light emitting device 2 of this modified example can achieve the same effects as the light emitting device 1 of the above embodiment.

[0076] (2-2. Modification 2) FIGS. 11A to 11F illustrate an example of a manufacturing process for a light emitting device according to Modification 2 of the present disclosure.

[0077] In the above embodiment, an example has been shown in which alignment mark 116 is formed directly on compound semiconductor layer 110, but this is not limiting. For example, alignment mark 116 may be formed between SiO film 115A and SiN film 115B of the three layers (SiO film 115A, SiN film 115B, and TEOS film 115C) that make up insulating layer 115. Except for this point, this modification 2 has substantially the same configuration as the above embodiment.

[0078] Here, the SiO film 115A corresponds to a specific example of a "first insulating film" in an embodiment of the present disclosure, and the SiN film 115B corresponds to a specific example of a "second insulating film" in an embodiment of the present disclosure.

[0079] The alignment mark 116 of this modified example can be formed as follows.

[0080] First, as shown in FIG. 11A , a compound semiconductor layer 110, an electrode layer 114, a SiO film 115A, and a transparent conductive film 116A are formed in this order on a growth substrate 51. Next, as shown in FIG. 11B , a resist film 201 is patterned, for example, in a cross shape on the transparent conductive film 116A. Subsequently, as shown in FIG. 11C , the transparent conductive film 116A is processed, for example, by dry etching, and then the resist film 201 is peeled off. This forms a cross-shaped alignment mark 116 on the SiO film 115A.

[0081] Next, as shown in Fig. 11D, for example, a SiN film 115B is formed on the SiO film 115A. Subsequently, as shown in Fig. 11E, for example, a TEOS film 115C is further formed, and then, as shown in Fig. 11F, the surface of the insulating layer 115 (TEOS film 115C) is planarized by CMP. Thereafter, by performing the same steps as in the above embodiment, a light-emitting device having an alignment mark 116 between the SiO film 115A and the SiN film 115B is completed.

[0082] In this manner, in this modification, of the three layers (SiO film 115A, SiN film 115B, and TEOS film 115C) that make up insulating layer 115, alignment mark 116 is formed between SiO film 115A and SiN film 115B. Even with this configuration, the light emitting device of this modification can achieve the same effects as light emitting device 1 of the above embodiment.

[0083] (2-3. Modification 3) FIGS. 12A to 12E illustrate an example of a manufacturing process for a light emitting device according to Modification 2 of the present disclosure.

[0084] In the above embodiment, an example has been shown in which alignment mark 116 is formed directly on compound semiconductor layer 110, but this is not limiting. For example, alignment mark 116 may be formed between SiN film 115B and TEOS film 115C of the three layers (SiO film 115A, SiN film 115B, and TEOS film 115C) that make up insulating layer 115. Except for this point, this modification 2 has substantially the same configuration as the above embodiment.

[0085] Here, the SiO film 115A corresponds to a specific example of a "first insulating film" in an embodiment of the present disclosure, and the SiN film 115B corresponds to a specific example of a "second insulating film" in an embodiment of the present disclosure.

[0086] The alignment mark 116 of this modified example can be formed as follows.

[0087] First, as shown in FIG. 12A , a compound semiconductor layer 110, an electrode layer 114, a SiO film 115A, a SiN film 115B, and a transparent conductive film 116A are formed in this order on a growth substrate 51. Next, as shown in FIG. 12B , a resist film 201 is patterned, for example, in a cross shape on the transparent conductive film 116A. Subsequently, as shown in FIG. 12C , the transparent conductive film 116A is processed, for example, by dry etching, and then the resist film 201 is peeled off. This forms a cross-shaped alignment mark 116 on the SiO film 115A.

[0088] Next, as shown in Fig. 12D, for example, a TEOS film 115C is formed on the SiN film 115B. Subsequently, as shown in Fig. 12E, the surface of the insulating layer 115 (TEOS film 115C) is planarized by CMP. Thereafter, by performing the same steps as in the above embodiment, a light-emitting device having an alignment mark 116 between the SiN film 115B and the TEOS film 115C is completed.

[0089] In this manner, in this modification, of the three layers (SiO film 115A, SiN film 115B, and TEOS film 115C) that make up insulating layer 115, alignment mark 116 is formed between SiN film 115B and TEOS film 115C. Even with this configuration, the light emitting device of this modification can achieve the same effects as light emitting device 1 of the above embodiment.

[0090] 3. Application Examples Application Example 1 Fig. 13A is a front view showing an example of the appearance of a digital still camera (electronic device) 1120. Fig. 13B is a rear view showing an example of the appearance of the digital still camera 1120. The digital still camera 1120 is an interchangeable lens single-lens reflex camera. The digital still camera 1120 has an interchangeable taking lens unit (interchangeable lens) 1121 located approximately in the center of the front of a camera main body (camera body) 1122, and a grip portion 1123 for the photographer to hold on the left side of the front.

[0091] A monitor 1126 is provided at a position shifted to the left from the center of the back of the camera body 1122. An electronic viewfinder (eyepiece window) 1124 is provided above the monitor 1126. By looking through the electronic viewfinder 1124, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 1121 and determine the composition. The electronic viewfinder 1124 is equipped with a light-emitting device 1.

[0092] (Application Example 2) The light-emitting device (e.g., the light-emitting device 1) of the present disclosure can also be applied to a head-mounted display (hereinafter referred to as an HMD). The head-mounted display 1130A can be used for virtual reality (VR), augmented reality (AR), mixed reality (MR), substitutional reality (SR), or the like.

[0093] 14A is a perspective view showing the appearance of a head-mounted display (electronic device) 1130A. The head-mounted display 1130A has, for example, ear hooks 1131 on both sides of a glasses-shaped display unit 1132 for wearing on the user's head. The display unit 1132 is equipped with a light-emitting device 1.

[0094] FIG. 14B is a perspective view showing the appearance of another head-mounted display (electronic device). The head-mounted display is smart glasses 1130B that display various information on glasses 1133. The smart glasses 1130B include a main body, an arm 1135, and a lens barrel 1136. The main body 1134 is connected to the arm 1135. The main body 1134 is detachable from the glasses 1133. The main body 1134 incorporates a control board and a display unit for controlling the operation of the smart glasses 1130B. The main body 1134 and the lens barrel 1136 are connected to each other via the arm 1135. The lens barrel 1136 emits image light emitted from the main body 1134 via the arm 1135 toward the lenses 1137 of the glasses 1133. This image light enters the human eye through the lens 1137. 14B, a wearer of the smart glasses 1130B can visually recognize not only the surrounding situation but also various pieces of information emitted from the lens barrel 1136, as with normal glasses. The main body 1134 includes the light-emitting device 1.

[0095] 15 is a perspective view showing an example of the appearance of a television device (electronic device) 1140. This television device 1140 has, for example, an image display screen unit 1141 including a front panel 1142 and a filter glass 1143. The image display screen unit 1141 is equipped with the light-emitting device 1.

[0096] Although the present technology has been described above with reference to the embodiment, variations 1 to 3, and application examples, the present technology is not limited to the above-described embodiment, etc., and various modifications are possible. For example, in the above-described embodiment, etc., an example has been shown in which the light emitted from the light-emitting element 11 is blue light or ultraviolet light, but the present technology is not limited to this. For example, the light-emitting device 1 may use a light-emitting element that emits two or more types of light, such as blue light and green light, or ultraviolet light and green light.

[0097] In the above-described embodiment and the like, the separation portion 11H that separates the compound semiconductor layer 110 into the plurality of light-emitting elements 11 penetrates the compound semiconductor layer 110 from the surface 11S2 side, but the present invention is not limited to this. The separation portion 11H may be provided on both the surface 11S1 and the surface 11S2 of the compound semiconductor layer 110.

[0098] Furthermore, in the above embodiments, each component constituting the light emitting device 1 etc. has been specifically listed and described, but it is not necessary to include all components, and other components may also be included.

[0099] Furthermore, in the above-described embodiments, a light-emitting device in which an element substrate 10 having a plurality of light-emitting elements 11 arranged in a two-dimensional array and a drive substrate 30 are stacked is shown as an example of a stacked device, but the present technology is not limited to this. For example, the present technology can also be applied to a detection device in which an element substrate having light-emitting elements as first functional elements and a sensor substrate having sensor elements as second functional elements are stacked, and similar effects can be obtained.

[0100] The effects described in this specification are merely examples and are not limited to those described, and other effects may also be obtained.

[0101] The present technology can also be configured as follows. According to the present technology configured as follows, alignment is facilitated when dividing and transferring a semiconductor layer in a step of forming a first functional element. Therefore, high-precision alignment is possible. (1) A stacked device comprising: a first substrate including a semiconductor layer having opposing first and second surfaces, the first substrate having a first functional element formed by the semiconductor layer; a second substrate stacked on the first substrate facing the second surface of the semiconductor layer; and an alignment mark formed by a conductive film transparent to visible light, the alignment mark being provided on the second surface side of the semiconductor layer of the first substrate. (2) The stacked device according to (1), wherein the first substrate has a plurality of the first functional elements, and the plurality of first functional elements are arranged in an array within the plane. (3) The stacked device according to (2), wherein the first substrate has an array portion in which the plurality of first functional elements are arranged in an array and a peripheral portion provided around the array portion, and the alignment mark is provided in the array portion. (4) The stacked device according to (2), wherein the first substrate has an array section in which the first functional elements are arranged in an array and a peripheral section provided around the array section, and the alignment mark is provided in the peripheral section. (5) The stacked device according to (2), wherein the first substrate has an array section in which the first functional elements are arranged in an array and a peripheral section provided around the array section, and the alignment mark is provided in the array section and the peripheral section. (6) The stacked device according to any one of (2) to (5), wherein the first substrate has an array section in which the first functional elements are arranged in an array, a peripheral section provided around the array section, and a dummy region provided between the array section and the peripheral section and having substantially the same element structure as the array section, and the alignment mark is provided in the dummy region. (7) The stacked device according to any one of (1) to (6), wherein the semiconductor layer is made of a compound semiconductor.(8) The stacked device according to any one of (1) to (7), wherein the semiconductor layer is made of gallium nitride. (9) The stacked device according to any one of (1) to (8), wherein the alignment mark is provided directly on the second surface of the semiconductor layer. (10) The stacked device according to any one of (1) to (9), wherein the first substrate further has a first insulating film and a second insulating film stacked in that order on the second surface of the semiconductor layer, and the alignment mark is provided between the first insulating film and the second insulating film. (11) The stacked device according to any one of (1) to (10), wherein the first substrate further has a first insulating film and a second insulating film stacked in that order on the second surface of the semiconductor layer, and the alignment mark is provided on the second insulating film. (12) The stacked device according to any one of (1) to (11), wherein the alignment mark has a cross shape, a circle shape, a square shape, a lattice shape, or a pinwheel shape. (13) The stacked device according to any one of (1) to (12), wherein the first functional element is a light-emitting element. (14) The stacked device according to any one of (1) to (13), wherein the second substrate has a second functional element having a function different from that of the first functional element. (15) The stacked device according to any one of (14), wherein the second functional element is a sensor element. (16) The stacked device according to any one of (13) to (15), wherein the second substrate has a second functional element having a function different from that of the first functional element, and the second functional element is a drive circuit element that controls drive of the light-emitting element. (17) The stacked device according to any one of (1) to (16), wherein the first substrate and the second substrate are connected to each other by hybrid bonding. (18) The stacked device according to any one of (1) to (17), wherein the first substrate and the second substrate are connected to each other by CuCu bonding.(19) An electronic device comprising: a stacked device, the stacked device including a first substrate including a semiconductor layer having a first surface and a second surface opposite to each other, the first substrate having a first functional element constituted by the semiconductor layer; a second substrate stacked on the first substrate opposite the second surface of the semiconductor layer; and an alignment mark provided on the first substrate on the second surface side of the semiconductor layer and formed of a conductive film that is transparent to visible light. (20) A method for manufacturing a stacked device, comprising: forming a semiconductor layer on a growth substrate by epitaxial growth; forming an alignment mark on the semiconductor layer by depositing a conductive film that is transparent to visible light on the semiconductor layer; dicing the semiconductor layer into a plurality of pieces; transferring the diced semiconductor layers to a support substrate; processing each of the plurality of semiconductor layers to form a plurality of first functional elements; and bonding the first substrate having the plurality of first functional elements to a second substrate by hybrid bonding.

[0102] This application claims priority based on Japanese Patent Application No. 2024-048449, filed on March 25, 2024, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0103] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A stacked device comprising: a first substrate including a semiconductor layer having opposing first and second surfaces, the first substrate having a first functional element formed by the semiconductor layer; a second substrate stacked on the first substrate opposite the second surface of the semiconductor layer; and an alignment mark provided on the first substrate facing the second surface of the semiconductor layer, the alignment mark being formed of a conductive film that is transparent to visible light.

2. The stacked device according to claim 1, wherein the first substrate has a plurality of the first functional elements, and the plurality of first functional elements are arranged in an array on a surface thereof.

3. The stacked device described in claim 2, wherein the first substrate has an array section in which a plurality of the first functional elements are arranged in an array, and a peripheral section provided around the array section, and the alignment mark is provided in the array section.

4. The stacked device described in claim 2, wherein the first substrate has an array portion in which a plurality of the first functional elements are arranged in an array and a peripheral portion provided around the array portion, and the alignment mark is provided in the peripheral portion.

5. The stacked device described in claim 2, wherein the first substrate has an array section in which a plurality of the first functional elements are arranged in an array, and a peripheral section provided around the array section, and the alignment marks are provided in the array section and the peripheral section, respectively.

6. The stacked device according to claim 2, wherein the first substrate has an array section in which a plurality of the first functional elements are arranged in an array, a peripheral section provided around the array section, and a dummy section provided between the array section and the peripheral section and having substantially the same element structure as the array section, and the alignment mark is provided in the dummy section.

7. The stacked device according to claim 1, wherein the semiconductor layer is made of a compound semiconductor.

8. The stacked device according to claim 1, wherein the semiconductor layer is made of gallium nitride.

9. The stacked device according to claim 1, wherein the alignment mark is provided directly on the second surface of the semiconductor layer.

10. The stacked device according to claim 1, wherein the first substrate further has a first insulating film and a second insulating film stacked in that order on the second surface of the semiconductor layer, and the alignment mark is provided between the first insulating film and the second insulating film.

11. The stacked device according to claim 1, wherein the first substrate further has a first insulating film and a second insulating film stacked in that order on the second surface of the semiconductor layer, and the alignment mark is provided on the second insulating film.

12. The stacked device according to claim 1, wherein the alignment mark has a cross shape, a circle shape, a square shape, a grid shape, or a pinwheel shape.

13. The stacked device according to claim 1, wherein the first functional element is a light-emitting element.

14. The stacked device according to claim 1, wherein the second substrate has a second functional element having a function different from that of the first functional element.

15. The laminated device according to claim 14, wherein the second functional element is a sensor element.

16. The stacked device according to claim 13, wherein the second substrate has a second functional element having a different function from the first functional element, and the second functional element is a drive circuit element that controls the driving of the light-emitting element.

17. The stacked device of claim 1, wherein the first substrate and the second substrate are connected to each other by a hybrid bond.

18. The stacked device according to claim 1, wherein the first substrate and the second substrate are connected to each other by CuCu bonding.

19. An electronic device comprising: a laminated device, the laminated device including a first substrate including a semiconductor layer having a first surface and a second surface opposite to each other and having a first functional element constituted by the semiconductor layer; a second substrate laminated on the first substrate opposite the second surface of the semiconductor layer; and an alignment mark provided on the first substrate on the side of the second surface of the semiconductor layer and formed by a conductive film that is transparent to visible light.

20. A method for manufacturing a stacked device, comprising: forming a semiconductor layer on a growth substrate by epitaxial growth; depositing a conductive film that is transparent to visible light on the semiconductor layer to form an alignment mark; dicing the semiconductor layer into multiple pieces; transferring the multiple diced semiconductor layers to a support substrate; processing each of the multiple semiconductor layers to form multiple first functional elements; and hybrid-bonding and bonding the first substrate having the multiple first functional elements to a second substrate.

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