Three-dimensional monolithic complementary transistor using channel all around structure

Abstract

A three-dimensional monolithic complementary transistor is provided. The three-dimensional monolithic complementary transistor may comprise: a gate electrode extending in a normal direction of an upper surface of a substrate; a first channel layer of a first type disposed below the gate electrode; a second channel layer of a second type surrounding one region of an upper surface and a side surface of the gate electrode; a drain electrode disposed on the substrate so as to be in contact with the first channel layer and the second channel layer; a first source electrode disposed on the substrate so as to be in contact with only the first channel layer among the first channel layer and the second channel layer; and a second source electrode disposed on the second channel layer so as to be in contact with only the second channel layer among the first channel layer and the second channel layer.

Description

3D monolithic complementary transistor with channel all-around structure

[0001] The present invention relates to a three-dimensional monolithic complementary transistor, and more particularly, to a three-dimensional monolithic complementary transistor employing a channel all-around structure.

[0002] In addition, the present invention was derived through the support of the research project below.

[0003] [Research Project Name] [Application 1 - Gyeonggi-do] Development of CVD-based dielectric thin film process technology

[0004] [Research Project Number] S-2023-1650-005

[0005] [Ministry Name] Gyeonggi Provincial Government

[0006] [Host Organization] Gyeonggi Province

[0007] [Contribution rate] 50%

[0008] [Research Project Name] Gyeonggi-do Regional Cooperation Research Center (GRRC) Project

[0009] [Research Management Specialist Organization] Gyeonggi Regional Research Center (GRRC)

[0010] Research Period: July 1, 2023 - June 30, 2024

[0011] For decades, the semiconductor industry has experienced countless advancements driven by the development of transistor hardware. In particular, the recent advancements in various IT industries, such as IoT, communications, and multimedia, have been largely driven by the development of transistor technology, which handles computation. This transistor technology has achieved rapid performance improvements through continuous miniaturization (scaling), and currently utilizes FinFETs, an evolution of planar transistors, as its primary technology. Samsung, Intel, and TSMC are currently developing and experimenting with innovative gate-all-around (GAA) processes to achieve even finer transistors. Standard cells, composed of one or more transistors, are the core logic circuits in digital semiconductor chip design. Among these, the most fundamental CMOS circuits are comprised of NMOS and PMOS. Because these standard cells comprise a significant portion of the chip area, efficient chip area utilization is directly linked to the size of the standard cells. Recently, CFET technology, which reduces the footprint of a standard cell by half by vertically arranging the current planar PMOS+NMOS structure to implement a more detailed structure, has been proposed as one of the future innovative hardware technologies.

[0012] The technical problem to be solved by the present invention is to provide a three-dimensional monolithic complementary transistor using a channel all-around structure.

[0013] Another technical problem to be solved by the present invention is to provide a three-dimensional monolithic complementary transistor that can be easily integrated into a three-dimensional structure.

[0014] Another technical challenge to be solved by the present invention is to provide a three-dimensional monolithic complementary transistor capable of forming a channel through a low-temperature process.

[0015] Another technical problem to be solved by the present invention is to provide a three-dimensional monolithic complementary transistor in which parasitic capacitance can be reduced.

[0016] Another technical problem to be solved by the present invention is to provide a three-dimensional monolithic complementary transistor that can minimize problems such as the short channel effect that occurs in transistors of general planar structures when devices are miniaturized in the future (e.g., channel length is reduced) by maintaining high gate controllability for the channel.

[0017] The technical problems to be solved by the present invention are not limited to those described above.

[0018] To solve the above-described technical problems, the present invention provides a three-dimensional monolithic complementary transistor.

[0019] According to one embodiment, the three-dimensional monolithic complementary transistor may include a gate electrode extending in a normal direction to an upper surface of a substrate, a first type of first channel layer disposed below the gate electrode, a second type of second channel layer surrounding an area of ​​an upper surface and a side surface of the gate electrode, a drain electrode disposed on the substrate so as to be in contact with the first channel layer and the second channel layer, a first source electrode disposed on the substrate so as to be in contact only with the first channel layer among the first channel layer and the second channel layer, and a second source electrode disposed on the second channel layer so as to be in contact only with the second channel layer among the first channel layer and the second channel layer.

[0020] According to one embodiment, the second source electrode and the drain electrode may include non-overlapping portions in the direction in which the gate electrode extends.

[0021] According to one embodiment, the first source electrode and the drain electrode may overlap in a direction in which the gate electrode extends.

[0022] According to one embodiment, the first type may include a P type, and the second type may include an N type.

[0023] According to one embodiment, the first channel layer may include silicon (Si).

[0024] According to one embodiment, the second channel layer may include any one of an oxide semiconductor and a two-dimensional material.

[0025] According to one embodiment, the gate electrode, the first channel layer, the drain electrode, and the first source electrode may be defined as a first transistor, and the gate electrode, the second channel layer, the drain electrode, and the second source electrode may be defined as a second transistor.

[0026] According to another embodiment, the three-dimensional monolithic complementary transistor may include a gate electrode extending in a normal direction to an upper surface of a substrate, a plurality of first type first channel layers arranged to be spaced apart from each other along a direction in which the gate electrode extends, a second type second channel layer surrounding an area of ​​an upper surface and a side surface of the gate electrode, a drain electrode arranged on the substrate so as to be in contact with the plurality of first channel layers and the second channel layer, a first source electrode arranged on the substrate so as to be in contact only with the first channel layer among the first channel layer and the second channel layer, and a second source electrode arranged on the second channel layer so as to be in contact only with the second channel layer among the first channel layer and the second channel layer.

[0027] According to another embodiment, the plurality of first channel layers may include those surrounded by the gate electrode.

[0028] According to another embodiment, the drain electrode may be in contact with all one end portions of each of the plurality of first channel layers.

[0029] In another embodiment, the first source electrode may be in contact with all of the other ends of each of the plurality of first channel layers.

[0030] In another embodiment, the second source electrode and the drain electrode may include non-overlapping portions in the direction in which the gate electrode extends.

[0031] According to another embodiment, the first source electrode and the drain electrode may overlap in the direction in which the gate electrode extends.

[0032] According to another embodiment, the first type may include a P type, and the second type may include an N type.

[0033] According to another embodiment, the first channel layer may include silicon (Si), and the second channel layer may include any one of an oxide semiconductor and a two-dimensional material.

[0034] A three-dimensional monolithic complementary transistor according to an embodiment of the present invention has a structure in which an N-type transistor having a CAA (Channel-All-Around) structure is stacked on top of a P-type transistor having a planar structure or a GAA (Gate-All-Around) structure, wherein silicon is used as the channel of the P-type transistor, and either an oxide semiconductor or a two-dimensional material can be used as the channel of the N-type transistor.

[0035] Accordingly, channel formation through an atomic layer deposition (ALD) process can be achieved, facilitating integration into three-dimensional structures. Furthermore, since channel formation is possible through a low-temperature process, degradation of the underlying stack due to high-temperature heat treatment can be prevented. Furthermore, high gate controllability for the channel is maintained, minimizing problems such as the short channel effect that occurs in conventional planar-structure transistors during future device miniaturization (e.g., reduced channel length).

[0036] FIG. 1 is a drawing for explaining a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention.

[0037] Figure 2 is an enlarged view of part A of Figure 1.

[0038] FIG. 3 is a drawing for explaining step S101 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention.

[0039] FIG. 4 is a drawing for explaining step S102 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention.

[0040] FIG. 5 is a drawing for explaining step S103 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention.

[0041] FIG. 6 is a drawing for explaining step S104 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention.

[0042] FIG. 7 is a drawing for explaining step S105 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention.

[0043] FIG. 8 is a drawing for explaining step S106 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention.

[0044] FIG. 9 is a drawing for explaining step S107 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention.

[0045] FIG. 10 is a drawing for explaining step S108 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention.

[0046] FIG. 11 is a drawing for explaining step S109 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention.

[0047] FIG. 12 is a drawing for explaining step S110 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention.

[0048] FIG. 13 is a drawing for explaining step S111 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention.

[0049] FIG. 14 is a drawing for explaining step S112 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention.

[0050] FIG. 15 and FIG. 16 are drawings for explaining step S113 of a method for manufacturing a three-dimensional monolithic complementary transistor according to the first embodiment of the present invention.

[0051] FIG. 17 is a drawing for explaining step S114 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention.

[0052] FIG. 18 is a drawing for explaining step S115 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention.

[0053] FIG. 19 is a drawing for explaining step S116 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention.

[0054] FIG. 20 is a drawing for explaining a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0055] FIG. 21 is a drawing for explaining step S201 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0056] FIG. 22 is a drawing for explaining step S202 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0057] FIG. 23 is a drawing for explaining step S203 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0058] FIG. 24 is a drawing for explaining step S204 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0059] FIG. 25 is a drawing for explaining step S205 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0060] FIG. 26 is a drawing for explaining step S206 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0061] FIG. 27 is a drawing for explaining step S207 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0062] FIG. 28 is a drawing for explaining step S208 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0063] FIG. 29 is a drawing for explaining step S209 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0064] FIG. 30 is a drawing for explaining step S210 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0065] FIG. 31 is a drawing for explaining step S211 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0066] FIG. 32 is a drawing for explaining step S212 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0067] FIG. 33 is a drawing for explaining step S213 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0068] FIG. 34 is a drawing for explaining step S214 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0069] FIG. 35 is a drawing for explaining step S215 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0070] FIG. 36 is a drawing for explaining step S216 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0071] FIG. 37 is a drawing for explaining step S217 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0072] FIG. 38 is a drawing for explaining step S218 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0073] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed content is thorough and complete and to sufficiently convey the spirit of the present invention to those skilled in the art.

[0074] In this specification, when a component is referred to as being on another component, it means that it can be formed directly on the other component, or a third component may be interposed between them. In addition, in the drawings, the thicknesses of films and regions are exaggerated for the purpose of effectively explaining the technical contents.

[0075] Also, although terms such as first, second, and third have been used to describe various components in various embodiments of this specification, these components should not be limited by these terms. These terms are only used to distinguish one component from another. Thus, what is referred to as a first component in one embodiment may be referred to as a second component in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiments. Also, the term "and / or" has been used herein to mean including at least one of the components listed before and after.

[0076] In the specification, singular expressions include plural expressions unless the context clearly dictates otherwise. In addition, terms such as "comprise" or "have" are intended to specify the presence of a feature, number, step, component, or combination thereof described in the specification, and should not be construed as excluding the presence or addition of one or more other features, numbers, steps, components, or combinations thereof. In addition, the term "connection" is used in the present specification to mean both indirectly connecting multiple components and directly connecting them.

[0077] In addition, when describing the present invention below, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

[0078]

[0079] FIG. 1 is a drawing for explaining a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention, and FIG. 2 is an enlarged drawing of part A of FIG. 1.

[0080] Referring to FIG. 1, the three-dimensional monolithic complementary transistor according to the first embodiment may include a substrate (10), a gate electrode (G), a first channel layer (C1), a second channel layer (C2), a first gate insulating layer (GI1), a second gate insulating layer (GI2), a first source electrode (S1), a second source electrode (S2), a drain electrode (D), a first interlayer insulating layer (ILD1), and a second interlayer insulating layer (ILD2). Each configuration is described below.

[0081] The substrate (10) is intended to support each component of the three-dimensional monolithic complementary transistor according to the first embodiment, and may be a silicon semiconductor substrate according to one embodiment. Alternatively, according to another embodiment, the substrate (10) may be any one of a compound semiconductor substrate, a glass substrate, or a plastic substrate. The type of the substrate (S) is not limited.

[0082] The first channel layer (C1) may be disposed on the substrate (10) or formed within a region of the substrate (10). According to one embodiment, the first channel layer (C1) may have a first type. For example, the first channel layer (C1) may have a P type. According to one embodiment, the first channel layer (C1) may include P type silicon.

[0083] The first gate insulating layer (GI1) may be disposed on the first channel layer (C1). The first gate insulating layer (GI1) is for electrical insulation between the first channel layer (C1) and a gate electrode (G) described below, and according to one embodiment, may include silicon oxide (SiO2). Alternatively, according to another embodiment, the first gate insulating layer (GI1) may include any one of hafnium oxide (HfO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2).

[0084] The gate electrode (G) may be disposed on the first gate insulating layer (GI1) and may extend in a normal direction of the upper surface of the substrate (10) (for example, the Y-axis direction of FIG. 1). That is, the gate electrode (G) may have a shape extending in a vertical direction of the substrate (10). According to one embodiment, the gate electrode (G) may include a metal. Alternatively, according to another embodiment, the gate electrode (G) may include polycrystalline silicon (poly-Si). The type of material that may be used as the gate electrode (G) is not limited. According to one embodiment, the gate electrode (G) may be a V of the complementary transistor according to the embodiment. in can be used as

[0085] The first source electrode (S1) may be disposed on the first channel layer (C1), and may be disposed so as to be in contact with one side of the first gate insulating layer (GI1). According to one embodiment, the first source electrode (S1) may also extend in the normal direction of the upper surface of the substrate (10) (for example, the Y-axis direction of FIG. 1), and the extended length may be shorter than the gate electrode (G). According to one embodiment, the first source electrode (S1) may be a V of the complementary transistor according to the embodiment. DD can be used as

[0086] The drain electrode (D) may be disposed on the first channel layer (C1), such that a lower region of the drain electrode (D) is in contact with the other side of the first gate insulating layer (GI1), and an upper region of the drain electrode (D) may be disposed to surround a second channel layer (C2) and a second gate insulating layer (GI2) to be described later.

[0087] That is, the first source electrode (S1) may be arranged to contact only the first channel layer (C1) among the first channel layer (C1) and the second channel layer (C2) described later, while the drain electrode (D) may be arranged to contact both the first channel layer (C1) and the second channel layer (C2) described later. In addition, a region of the drain electrode (D) surrounding the second channel layer (C2) and the second gate insulating layer (GI2) described later may overlap the first source electrode (S1) in the direction in which the gate electrode extends (for example, the Y-axis direction of FIG. 1).

[0088] According to one embodiment, the drain electrode (D) may be arranged to be spaced apart from the first source electrode (S1) with the gate electrode (G) therebetween. According to one embodiment, the drain electrode (D) may also extend in the normal direction of the upper surface of the substrate (10) (for example, the Y-axis direction of FIG. 1), but the extended length may be shorter than the gate electrode (G) and longer than the first source electrode (S1). According to one embodiment, the drain electrode (D) may be V of the complementary transistor according to the embodiment. out can be used as

[0089] The second gate insulating layer (GI2) may be arranged to surround an upper surface and a side surface region of the gate electrode (G). That is, the second gate insulating layer (GI2) may be arranged to conformally cover an upper region of the gate electrode (G) along a surface profile. The second gate insulating layer (GI2) is for electrical insulation between the gate electrode (G) and a second channel layer (C2) to be described later, and according to one embodiment, may include silicon oxide (SiO2). Alternatively, according to another embodiment, the second gate insulating layer (GI2) may include any one of hafnium oxide (HfO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2).

[0090] The second channel layer (C2) may be disposed on the second gate insulating layer (GI2). More specifically, the second channel layer (C2) may be disposed along the surface profile of the second gate insulating layer (GI2). Accordingly, the second channel layer (C2) may also surround a region of the upper surface and side surface of the gate electrode (G). According to an embodiment, the second channel layer (C2) may have a second type. For example, the second channel layer (C2) may have an N type. According to an embodiment, the second channel layer (C2) may include any one of an oxide semiconductor and a two-dimensional material having N type characteristics. As described above, when the second channel layer (C2) is composed of any one of an oxide semiconductor and a two-dimensional material, channel formation may be performed through an atomic layer deposition (ALD) process, so that integration into a three-dimensional structure may be easily performed. In addition, since channel formation is possible through a low-temperature process, deterioration of the lower stack due to high-temperature heat treatment can be prevented.

[0091] The second source electrode (S2) may be disposed on the second channel layer (C2) so as to contact only the second channel layer (C2) among the first channel layer (C1) and the second channel layer (C2). In addition, as illustrated in FIGS. 1 and 2, the second source electrode (S2) may be disposed so as not to overlap the drain electrode (D) in the direction in which the gate electrode (G) extends (for example, the Y-axis direction of FIG. 1). Accordingly, the parasitic capacitance may be reduced, thereby improving the electrical characteristics of the complementary transistor. Conversely, when the second source electrode (S2) and the drain electrode (D) are disposed so as to overlap, a problem may arise in which the electrical characteristics of the complementary transistor deteriorate due to an increase in parasitic capacitance. According to one embodiment, the second source electrode (S2) may be used as a ground of the complementary transistor according to the embodiment.

[0092] The first interlayer insulating layer (ILD1) may be disposed between the drain electrode (D) surrounding the upper region of the gate electrode (G) and the substrate (10) to electrically insulate between the gate electrode (G), the first source electrode (S1), and the drain electrode (D). In contrast, the second interlayer insulating layer (ILD2) may be disposed between the drain electrode (D) surrounding the upper region of the gate electrode (G) and the second source electrode (S2), to electrically insulate between the gate electrode (G), the second source electrode (S2), and the drain electrode (D).

[0093] The gate electrode (G), the first channel layer (C1), the first source electrode (S1), and the drain electrode (D) may be defined as a first transistor (TR1). Alternatively, the gate electrode (G), the second channel layer (C2), the second source electrode (S2), and the drain electrode (D) may be defined as a second transistor (TR2).

[0094] The first transistor (TR1) may have a planar structure in which the gate electrode (G), the first channel layer (C1), the first source electrode (S1), and the drain electrode (D) are arranged in a plane. In contrast, the second transistor (TR2) may have a Channel-All-Around (CAA) structure in which the second channel layer (C2) surrounds the gate electrode (G). In addition, the second transistor (TR2) may have a structure in which it is stacked on top of the first transistor (TR1) along a normal direction of the upper surface of the substrate (10).

[0095] As a result, the three-dimensional monolithic complementary transistor according to the first embodiment has a structure in which an N-type transistor of a CAA structure is stacked on top of a P-type transistor of a planar structure, and can share the gate electrode (G) and the drain electrode (D).

[0096] Above, a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention has been described. Hereinafter, a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention will be described.

[0097] FIG. 3 is a drawing for explaining step S101 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention, FIG. 4 is a drawing for explaining step S102 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention, FIG. 5 is a drawing for explaining step S103 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention, FIG. 6 is a drawing for explaining step S104 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention, FIG. 7 is a drawing for explaining step S105 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention, FIG. 8 is a drawing for explaining step S106 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention, and FIG. 9 is a drawing for explaining step S106 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention. FIG. 10 is a drawing for explaining step S107 of a method for manufacturing a complementary transistor, FIG. 10 is a drawing for explaining step S108 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention, FIG. 11 is a drawing for explaining step S109 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention, FIG. 12 is a drawing for explaining step S110 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention, FIG. 13 is a drawing for explaining step S111 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention, FIG. 14 is a drawing for explaining step S112 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention, and FIGS. 15 and 16 are drawings for explaining step S113 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention. This is a drawing for explanation,FIG. 17 is a drawing for explaining step S114 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention, FIG. 18 is a drawing for explaining step S115 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention, and FIG. 19 is a drawing for explaining step S116 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention.

[0098] Referring to FIG. 3, a substrate (10) having a first channel layer (C1) formed thereon may be prepared (S101). According to one embodiment, the first channel layer (C1) may be formed by doping a region of the upper surface of the substrate (10). For example, the substrate (10) may include silicon (Si), and the first channel layer (C1) may be formed by doping a region of the upper surface of the substrate (10) with an impurity to form a P-type doping layer.

[0099] Referring to FIGS. 4 and 5, a first source electrode (S1) and a first drain electrode (D1) may be formed on the first channel layer (C1) to be spaced apart from each other (S102), and a first gate insulating layer (GI1) may be formed on the first channel layer (C1) exposed between the first source electrode (S1) and the first drain electrode (D1) (S103).

[0100] Referring to FIGS. 6 and 7, a first gate electrode (G1) may be formed on the first gate insulating layer (GI1) so as to extend in the normal direction of the upper surface of the substrate (10) (e.g., the Y-axis direction of FIG. 6) (S104), and a first interlayer insulating layer (ILD1) may be formed on the substrate (10) so as to cover the first source electrode (S1), the first drain electrode (D1), the first gate insulating layer (GI1), and the first gate electrode (G1) (S105).

[0101] Referring to FIGS. 8 and 9, a first hole (H1) is formed by etching a region of the first interlayer insulating layer (ILD1) so that a region of the first gate electrode (G1) is exposed (S106), and a second gate electrode (G2) can be formed on the exposed first gate electrode (G1), that is, so as to extend along the direction in which the first gate electrode (G1) extends within the first hole (H1) (S107). In addition, the second gate electrode (G2) can be formed so as to be exposed to the outside of the first interlayer insulating layer (ILD1). According to one embodiment, the first gate electrode (G1) and the second gate electrode (G2) can include the same material, and the first gate electrode (G1) and the second gate electrode (G2) can form the gate electrode (G) described with reference to FIGS. 1 and 2.

[0102] Referring to FIGS. 10 to 12, a second gate insulating layer (GI2) is formed to conformally cover the upper surface of the first interlayer insulating layer (ILD1) and the exposed gate electrode (G) (S108), a second channel layer (C2) can be formed on the second gate insulating layer (GI2) along the surface profile of the second gate insulating layer (GI2) (S109), and the second channel layer (C2) and the second gate insulating layer (GI2) can be etched so that one area of ​​the upper surface of the first interlayer insulating layer (ILD1) is exposed (S110).

[0103] Referring to FIGS. 13 to 16, a second hole (H2) is formed by etching a region of the first interlayer insulating layer (ILD1) so that a region of the first drain electrode (D1) is exposed (S111), the inside of the second hole (H2) is filled with a metal (M) (S112), and a second drain electrode (D2) can be formed on the first interlayer insulating layer (ILD1) so as to surround the second gate insulating layer (GI2) and the second channel layer (C2) (S113). The first drain electrode (D1), the metal filling the inside of the second hole (H2), and the second drain electrode (D2) may include the same material, and the first drain electrode (D1), the metal filling the inside of the second hole (H2), and the second drain electrode (D2) may form the drain electrode (D) described with reference to FIGS. 1 and 2.

[0104] Referring to FIGS. 17 to 19, a second interlayer insulating layer (ILD2) is formed on the first interlayer insulating layer (ILD1) to cover the drain electrode (D) and the second channel layer (C2) (S114), a region of the second interlayer insulating layer (ILD2) is etched to expose the second channel layer (C2) to form a third hole (H3) (S115), and a second source electrode (S2) is formed on the exposed second channel layer (C2), that is, within the third hole (H3) (S116), and the second source electrode (S2) may be formed so as not to overlap the drain electrode (D) in the direction in which the gate electrode (G) extends. Accordingly, a three-dimensional monolithic complementary transistor according to the first embodiment can be manufactured.

[0105]

[0106] Above, a method for manufacturing a three-dimensional monolithic complementary transistor according to a first embodiment of the present invention has been described. Hereinafter, a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention will be described.

[0107] FIG. 20 is a drawing for explaining a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0108] Referring to FIG. 20, the three-dimensional monolithic complementary transistor according to the second embodiment may include a substrate (10), a gate electrode (G), a plurality of first channel layers (C1), a second channel layer (C2), a first gate insulating layer (GI1), a second gate insulating layer (GI2), a first source electrode (S1), a second source electrode (S2), a drain electrode (D), a first interlayer insulating layer (ILD1), and a second interlayer insulating layer (ILD2). Each configuration is described below.

[0109] The substrate (10) is intended to support each component of the three-dimensional monolithic complementary transistor according to the second embodiment, and may be a silicon semiconductor substrate according to one embodiment. Alternatively, according to another embodiment, the substrate (10) may be any one of a compound semiconductor substrate, a glass substrate, or a plastic substrate. The type of the substrate (S) is not limited.

[0110] A plurality of the first channel layers (C1) may be spaced apart from each other along the direction in which the gate electrode (G) extends and may be disposed on the substrate (10) so as to be adjacent to a lower region of the gate electrode (G). According to one embodiment, the first channel layer (C1) may have a first type. For example, the first channel layer (C1) may have a P type. According to one embodiment, the first channel layer (C1) may include P type silicon.

[0111] The first gate insulating layer (GI1) may be arranged to surround a plurality of the first channel layers (C1). The first gate insulating layer (GI1) is for electrical insulation between the first channel layer (C1) and a gate electrode (G) described below, and according to one embodiment, may include silicon oxide (SiO2). Alternatively, according to another embodiment, the first gate insulating layer (GI1) may include any one of hafnium oxide (HfO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2).

[0112] The gate electrode (G) may be disposed on the substrate (10) and may extend in a normal direction to the upper surface of the substrate (10). That is, the gate electrode (G) may have a shape extending in a vertical direction of the substrate (10). In addition, the gate electrode (G) may surround a plurality of the first channel layers (C1). According to one embodiment, the gate electrode (G) may include a metal. Alternatively, according to another embodiment, the gate electrode (G) may include polycrystalline silicon (poly-Si). The type of material that may be used as the gate electrode (G) is not limited. According to one embodiment, the gate electrode (G) may be a V of the complementary transistor according to the embodiment. in can be used as

[0113] The first source electrode (S1) may be arranged on the substrate (10) so as to be in contact with all other ends of each of the plurality of first channel layers (C1). According to one embodiment, the first source electrode (S1) may also extend in the normal direction of the upper surface of the substrate (10), but the extended length may be shorter than the gate electrode (G). According to one embodiment, the first source electrode (S1) may be V of the complementary transistor according to the embodiment. DD can be used as

[0114] The drain electrode (D) may be disposed on the substrate (10), and the lower region of the drain electrode (D) may be in contact with one end of each of the plurality of first channel layers (C1), and the upper region of the drain electrode (D) may be disposed to surround the second channel layer (C2) and the second gate insulating layer (GI2) described below.

[0115] That is, the first source electrode (S1) may be arranged to contact only the first channel layer (C1) among the first channel layer (C1) and the second channel layer (C2) described below, while the drain electrode (D) may be arranged to contact both the first channel layer (C1) and the second channel layer (C2) described below. In addition, a region of the drain electrode (D) surrounding the second channel layer (C2) and the second gate insulating layer (GI2) described below may overlap the first source electrode (S1) in the direction in which the gate electrode extends.

[0116] According to one embodiment, the drain electrode (D) may be arranged to be spaced apart from the first source electrode (S1) with the gate electrode (G) therebetween. According to one embodiment, the drain electrode (D) may also extend in the normal direction of the upper surface of the substrate (10), but the extended length may be shorter than the gate electrode (G) and longer than the first source electrode (S1). According to one embodiment, the drain electrode (D) may be V of the complementary transistor according to the embodiment. out can be used as

[0117] The second gate insulating layer (GI2) may be arranged to surround an upper surface and a side surface region of the gate electrode (G). That is, the second gate insulating layer (GI2) may be arranged to conformally cover an upper region of the gate electrode (G) along a surface profile. The second gate insulating layer (GI2) is for electrical insulation between the gate electrode (G) and a second channel layer (C2) to be described later, and according to one embodiment, may include silicon oxide (SiO2). Alternatively, according to another embodiment, the second gate insulating layer (GI2) may include any one of hafnium oxide (HfO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2).

[0118] The second channel layer (C2) may be disposed on the second gate insulating layer (GI2). More specifically, the second channel layer (C2) may be disposed along the surface profile of the second gate insulating layer (GI2). Accordingly, the second channel layer (C2) may also surround a region of the upper surface and side surface of the gate electrode (G). According to an embodiment, the second channel layer (C2) may have a second type. For example, the second channel layer (C2) may have an N type. According to an embodiment, the second channel layer (C2) may include any one of an oxide semiconductor and a two-dimensional material having N type characteristics. As described above, when the second channel layer (C2) is composed of any one of an oxide semiconductor and a two-dimensional material, channel formation may be performed through an atomic layer deposition (ALD) process, so that integration into a three-dimensional structure may be easily performed. In addition, since channel formation is possible through a low-temperature process, deterioration of the lower stack due to high-temperature heat treatment can be prevented.

[0119] The second source electrode (S2) may be disposed on the second channel layer (C2) so as to contact only the second channel layer (C2) among the first channel layer (C1) and the second channel layer (C2). In addition, as illustrated in FIG. 20, the second source electrode (S2) may be disposed so as not to overlap the drain electrode (D) in the direction in which the gate electrode (G) extends. Accordingly, parasitic capacitance may be reduced, thereby improving the electrical characteristics of the complementary transistor. Conversely, when the second source electrode (S2) and the drain electrode (D) are disposed so as to overlap, a problem may arise in which the electrical characteristics of the complementary transistor deteriorate due to an increase in parasitic capacitance. According to one embodiment, the second source electrode (S2) may be used as a ground of the complementary transistor according to the embodiment.

[0120] The first interlayer insulating layer (ILD1) may be disposed between the drain electrode (D) surrounding the upper region of the gate electrode (G) and the substrate (10) to electrically insulate between the gate electrode (G), the first source electrode (S1), and the drain electrode (D). In contrast, the second interlayer insulating layer (ILD2) may be disposed between the drain electrode (D) surrounding the upper region of the gate electrode (G) and the second source electrode (S2), to electrically insulate between the gate electrode (G), the second source electrode (S2), and the drain electrode (D).

[0121] The gate electrode (G), the plurality of first channel layers (C1), the first source electrode (S1), and the drain electrode (D) may be defined as a first transistor (TR1). Alternatively, the gate electrode (G), the second channel layer (C2), the second source electrode (S2), and the drain electrode (D) may be defined as a second transistor (TR2).

[0122] The first transistor (TR1) may have a Gate-All-Around (GAA) structure in which a plurality of the first channel layers (C1) are surrounded by the gate electrode (G). In contrast, the second transistor (TR2) may have a Channel-All-Around (CAA) structure in which the second channel layers (C2) surround the gate electrode (G). In addition, the second transistor (TR2) may have a structure in which it is stacked on top of the first transistor (TR1) along a normal direction of the upper surface of the substrate (10).

[0123] As a result, the three-dimensional monolithic complementary transistor according to the second embodiment has a structure in which an N-type transistor of a CAA structure is stacked on top of a P-type transistor of a GAA structure, and can share the gate electrode (G) and the drain electrode (D).

[0124] Above, a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention has been described. Hereinafter, a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention will be described.

[0125] FIG. 21 is a drawing for explaining step S201 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention, FIG. 22 is a drawing for explaining step S202 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention, FIG. 23 is a drawing for explaining step S203 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention, FIG. 24 is a drawing for explaining step S204 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention, FIG. 25 is a drawing for explaining step S205 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention, FIG. 26 is a drawing for explaining step S206 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention, and FIG. 27 is a drawing for explaining step S206 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention. This is a drawing for explaining step S207 of a method for manufacturing a three-dimensional monolithic complementary transistor, FIG. 28 is a drawing for explaining step S208 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention, FIG. 29 is a drawing for explaining step S209 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention, FIG. 30 is a drawing for explaining step S210 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention, FIG. 31 is a drawing for explaining step S211 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention, FIG. 32 is a drawing for explaining step S212 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention, and FIG. 33 is a drawing for explaining step S211 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention, This is a drawing to explain step S213,FIG. 34 is a drawing for explaining step S214 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention, FIG. 35 is a drawing for explaining step S215 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention, FIG. 36 is a drawing for explaining step S216 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention, FIG. 37 is a drawing for explaining step S217 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention, and FIG. 38 is a drawing for explaining step S218 of a method for manufacturing a three-dimensional monolithic complementary transistor according to a second embodiment of the present invention.

[0126] Referring to FIG. 21, a stack structure in which a sacrificial layer (SL) and a first channel layer (C1) are alternately and repeatedly laminated on a substrate (10) can be formed (S201). According to one embodiment, the sacrificial layer (SL) can include silicon and germanium (SiGe), and the first channel layer (C1) can include P-type silicon.

[0127] Referring to FIGS. 22 and 23, the stack structure can be etched so that one area of ​​the substrate (10) is exposed (S202), and a first source electrode (S1) and a first drain electrode (D1) can be formed to contact one side and the other side of the etched stack structure, respectively (S203).

[0128] Referring to FIGS. 24 to 26, the sacrificial layer (SL) is removed to form an empty space between the adjacent first channel layers (C1) (S204), and a plurality of first gate insulating layers (GI1) are formed to surround the first channel layers (C1) within the formed empty space (S205), and then a first gate electrode (G1) can be formed on the substrate (10) so as to extend in the normal direction of the upper surface of the substrate (10) (S206). According to one embodiment, the first gate electrode (G1) can be formed to surround the plurality of first channel layers (C1) and the first gate insulating layers (GI1).

[0129] Referring to FIGS. 27 to 29, a first interlayer insulating layer (ILD1) may be formed on the substrate (10) to cover a plurality of the first channel layers (C1), the first source electrode (S1), the first drain electrode (D1), the first gate insulating layer (GI1), and the first gate electrode (G1) (S207), a first hole (H1) may be formed by etching a region of the first interlayer insulating layer (ILD1) so that a region of the first gate electrode (G1) is exposed (S208), and a second gate electrode (G2) may be formed on the exposed first gate electrode (G1), that is, so as to extend along the direction in which the first gate electrode (G1) extends within the first hole (H1) (S209). In addition, the second gate electrode (G2) may be formed so as to be exposed to the outside of the first interlayer insulating layer (ILD1). According to one embodiment, the first gate electrode (G1) and the second gate electrode (G2) may include the same material, and the first gate electrode (G1) and the second gate electrode (G2) may form the gate electrode (G) described with reference to FIG. 20.

[0130] Referring to FIGS. 30 to 32, a second gate insulating layer (GI2) is formed to conformally cover the upper surface of the first interlayer insulating layer (ILD1) and the exposed gate electrode (G) (S210), a second channel layer (C2) can be formed on the second gate insulating layer (GI2) along the surface profile of the second gate insulating layer (GI2) (S211), and the second channel layer (C2) and the second gate insulating layer (GI2) can be etched so that one area of ​​the upper surface of the first interlayer insulating layer (ILD1) is exposed (S212).

[0131] Referring to FIGS. 33 to 35, a second hole (H2) may be formed by etching a region of the first interlayer insulating layer (ILD1) so that a region of the first drain electrode (D1) is exposed (S213), the interior of the second hole (H2) may be filled with a metal (M) (S214), and a second drain electrode (D2) may be formed on the first interlayer insulating layer (ILD1) so as to surround the second gate insulating layer (GI2) and the second channel layer (C2) (S215). The first drain electrode (D1), the metal filling the interior of the second hole (H2), and the second drain electrode (D2) may include the same material, and the first drain electrode (D1), the metal filling the interior of the second hole (H2), and the second drain electrode (D2) may form the drain electrode (D) described with reference to FIG. 20.

[0132] Referring to FIGS. 36 to 38, a second interlayer insulating layer (ILD2) is formed on the first interlayer insulating layer (ILD1) to cover the drain electrode (D) and the second channel layer (C2) (S216), a region of the second interlayer insulating layer (ILD2) is etched to expose the second channel layer (C2) to form a third hole (H3) (S217), and a second source electrode (S2) is formed on the exposed second channel layer (C2), that is, within the third hole (H3) (S218), and the second source electrode (S2) may be formed so as not to overlap the drain electrode (D) in the direction in which the gate electrode (G) extends. Accordingly, a three-dimensional monolithic complementary transistor according to the second embodiment can be manufactured.

[0133]

[0134] While the present invention has been described in detail using preferred embodiments, the scope of the present invention is not limited to the specific embodiments described above, and should be interpreted in accordance with the appended claims. Furthermore, those skilled in the art will appreciate that numerous modifications and variations are possible without departing from the scope of the present invention.

[0135] The present invention can be used in the semiconductor industry.

Claims

1. A gate electrode extending in the normal direction of the upper surface of the substrate; A first type first channel layer disposed under the gate electrode; A second type of second channel layer surrounding an area of ​​the upper surface and side surfaces of the gate electrode; A drain electrode disposed on the substrate so as to be in contact with the first channel layer and the second channel layer; A first source electrode disposed on the substrate so as to contact only the first channel layer among the first channel layer and the second channel layer; and A three-dimensional monolithic complementary transistor comprising a second source electrode disposed on the second channel layer so as to contact only the second channel layer among the first channel layer and the second channel layer.

2. In paragraph 1, A three-dimensional monolithic complementary transistor, wherein the second source electrode and the drain electrode do not overlap in the direction in which the gate electrode extends.

3. In paragraph 1, A three-dimensional monolithic complementary transistor, wherein the first source electrode and the drain electrode overlap in the direction in which the gate electrode extends.

4. In paragraph 1, A three-dimensional monolithic complementary transistor, wherein the first type comprises a P type and the second type comprises an N type.

5. In paragraph 1, A three-dimensional monolithic complementary transistor wherein the first channel layer comprises silicon (Si).

6. In paragraph 1, A three-dimensional monolithic complementary transistor wherein the second channel layer comprises one of an oxide semiconductor and a two-dimensional material.

7. In paragraph 1, The gate electrode, the first channel layer, the drain electrode, and the first source electrode are defined as a first transistor, A three-dimensional monolithic complementary transistor comprising the gate electrode, the second channel layer, the drain electrode, and the second source electrode, which are defined as a second transistor.

8. A gate electrode extending in the normal direction of the upper surface of the substrate; A plurality of first type first channel layers arranged on the substrate so as to be spaced apart from each other along the direction in which the gate electrode extends and adjacent to a lower region of the gate electrode; A second type of second channel layer surrounding an area of ​​the upper surface and side surfaces of the gate electrode; A drain electrode disposed on the substrate so as to be in contact with a plurality of the first channel layers and the second channel layer; A first source electrode disposed on the substrate so as to contact only the first channel layer among the first channel layer and the second channel layer; and A three-dimensional monolithic complementary transistor comprising a second source electrode disposed on the second channel layer so as to contact only the second channel layer among the first channel layer and the second channel layer.

9. In paragraph 8, A three-dimensional monolithic complementary transistor comprising a plurality of said first channel layers surrounded by said gate electrode.

10. In paragraph 8, A three-dimensional monolithic complementary transistor, wherein the drain electrode is in contact with one end of each of the plurality of first channel layers.

11. In paragraph 8, A three-dimensional monolithic complementary transistor, wherein the first source electrode is in contact with the other end of each of the plurality of first channel layers.

12. In paragraph 8, A three-dimensional monolithic complementary transistor, wherein the second source electrode and the drain electrode do not overlap in the direction in which the gate electrode extends.

13. In paragraph 8, A three-dimensional monolithic complementary transistor, wherein the first type comprises a P type and the second type comprises an N type.

14. In paragraph 8, A three-dimensional monolithic complementary transistor, wherein the first channel layer comprises silicon (Si) and the second channel layer comprises one of an oxide semiconductor and a two-dimensional material.

Images