Stacked chip and manufacturing method therefor, manufacturing method for circuit unit, and stacked substrate

Abstract

A stacked chip and a manufacturing method therefor, a manufacturing method for a circuit unit, and a stacked substrate, relating to the technical field of stacked chips. The manufacturing method for a stacked chip comprises: providing a first substrate, wherein a plurality of first circuit units are formed on the first substrate, and each first circuit unit comprises a first circuit and a first pad of the first circuit; providing a second substrate, wherein a plurality of second circuit units and a plurality of clearance parts are formed on the second substrate; stacking the first substrate and the second substrate to form a stacked assembly, wherein one second circuit unit is arranged corresponding to one first circuit unit, one clearance part is arranged corresponding to at least one first pad, and the first pad is not covered by the second substrate by means of the corresponding clearance part; and slicing the stacked assembly to obtain a plurality of stacked chips, wherein one stacked chip comprises a first circuit unit and a second circuit unit. The present application can improve the production efficiency of stacked chips.

Description

Laminated chip and manufacturing method thereof, manufacturing method of circuit unit, and laminated substrate Technical Field

[0001] The present invention relates to the technical field of stacked chips, and in particular to a stacked chip and a manufacturing method thereof, a manufacturing method of a circuit unit, and a stacked substrate. Background Art

[0002] 3D stacked chips (also known as three-dimensional integrated circuits) are an advanced integrated circuit technology that stacks electronic devices between multiple crystalline silicon layers or other insulating layers. Compared to traditional 2D planar integrated circuits, 3D stacking technology can increase integration density, reduce circuit size, lower power consumption, and improve performance.

[0003] In the field of 3D stacked chip technology, at least two chips need to be stacked and then packaged. The current stacked chip manufacturing method is to stack and package multiple chips one by one, which has low production efficiency and wastes a lot of manpower and material resources.

[0004] Summary of the Invention

[0005] The main technical problem solved by the present invention is that the existing manufacturing method of stacked chips has low production efficiency.

[0006] According to the first aspect, an embodiment provides a method for manufacturing a stacked chip, comprising:

[0007] Providing a first substrate, on which a plurality of first circuit units are formed, wherein the first circuit units include a first circuit and a first pad of the first circuit;

[0008] Providing a second substrate, on which a plurality of second circuit units and a plurality of relief portions are formed;

[0009] The first substrate and the second substrate are stacked to form a stacked assembly, wherein one second circuit unit is corresponding to one first circuit unit, one recess is corresponding to at least one first pad, and the first pad is not covered by the second substrate through the recess;

[0010] The stacked assembly is sliced ​​to obtain a plurality of stacked chips, wherein one stacked chip includes a first circuit unit, a second circuit unit and a first bonding pad.

[0011] According to the second aspect, an embodiment provides a method for manufacturing a stacked chip, comprising:

[0012] Providing a first substrate, on which a plurality of first circuit units are formed, wherein the first circuit units include a first circuit and a first pad of the first circuit;

[0013] Providing a second substrate, wherein a plurality of paving portions are formed on the second substrate, and the paving portions are through holes;

[0014] The first substrate and the second substrate are stacked, and a clearance portion is provided corresponding to at least one first pad, and the first pad is not covered by the second substrate through the clearance portion;

[0015] A plurality of second circuit units and a plurality of conductors are formed on the second substrate, wherein one second circuit unit is provided corresponding to one first circuit unit, and the conductors are filled in the recesses and electrically connected to the first pads to obtain a laminated assembly;

[0016] The stacked assembly is sliced ​​to obtain a plurality of stacked chips, wherein one stacked chip includes a first circuit unit, a second circuit unit and a first bonding pad.

[0017] According to a third aspect, an embodiment provides a stacked chip, comprising:

[0018] A first chip includes a first substrate having a first surface and a first circuit unit formed on the first surface, the first circuit unit including a first conductive coil having two ends and two first pads, the two first pads being connected to the two ends or located at the two ends respectively;

[0019] The second chip is provided on the first chip, and the second chip includes a second substrate having a second surface and a second conductive coil formed on the second surface. The second substrate has a recessed portion, and the recessed portion is provided corresponding to the two first pads, so that the first pads are connected to the external circuit through the recessed portion; wherein,

[0020] The projection of the second conductive coil on the first surface covers at least 80% of the projection of the first conductive coil on the first surface.

[0021] According to a fourth aspect, an embodiment provides a stacked chip, comprising:

[0022] A first chip includes a first substrate having a first surface and a first circuit unit formed on the first surface, wherein the first circuit unit includes a first electrode plate and a first pad connected to the first electrode plate;

[0023] The second chip is provided on the first chip, the second chip includes a second substrate having a second surface and a second circuit unit formed on the second surface, the second circuit unit includes a second electrode plate, the second substrate has a relief portion, the relief portion is provided on the second substrate corresponding to the first pad, so that the projection of the second chip on the first surface does not cover the first pad, wherein,

[0024] The projection of the second electrode plate on the first surface covers the projection of the first electrode plate on the first surface.

[0025] According to a fifth aspect, an embodiment provides a laminated substrate, comprising:

[0026] A first substrate assembly includes a first substrate and a plurality of first circuit units formed on the first substrate, wherein the first circuit unit includes a first circuit and a first pad of the first circuit;

[0027] The second substrate assembly includes a second substrate, and a plurality of second circuit units and a plurality of relief portions formed on the second substrate, wherein:

[0028] The first substrate and the second substrate are stacked to form a stacked assembly, a second circuit unit is arranged corresponding to a first circuit unit, a recess is arranged corresponding to at least one first pad, the first pad is used to connect to an external circuit through the recess, and the stacked substrate is used to be cut into multiple stacked chips, and a stacked chip includes a first circuit unit, a second circuit unit and a first pad.

[0029] According to the sixth aspect, an embodiment provides a stacked chip manufactured using the manufacturing method described in the first aspect or the second aspect.

[0030] According to a seventh aspect, an embodiment provides a method for manufacturing a circuit unit, including:

[0031] forming a first conductive layer on a substrate, and patterning the first conductive layer to form a plurality of connecting lines;

[0032] forming a first insulating layer on the substrate, wherein the first insulating layer at least covers the connecting wire;

[0033] forming a plurality of first openings on the first insulating layer, each first opening exposing one end of a connecting wire;

[0034] forming a second conductive layer on the first insulating layer, wherein the second conductive layer is further filled in the first opening to be connected to the connecting line;

[0035] The second conductive layer is patterned to form a plurality of circuits and pads connecting the circuits. At least one pad is disposed corresponding to a first opening. A circuit unit includes a circuit and a corresponding pad.

[0036] According to the stacked chip and its manufacturing method, the circuit unit manufacturing method, and the stacked substrate of the above-mentioned embodiment, by forming multiple first circuit units on the first substrate, forming multiple second circuit units on the second substrate, and providing a clearance portion on the second substrate, it can be ensured that the first solder pad is not covered after the first substrate and the second substrate are stacked, and cutting can be performed after stacking to obtain multiple stacked chips, thereby greatly improving the production efficiency of the stacked chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] FIG1 is a flow chart of a method for manufacturing a stacked chip according to an embodiment of the present application;

[0038] FIG2 is a schematic structural diagram of a first substrate and a first circuit unit provided in one embodiment of the present application;

[0039] FIG3 is a schematic structural diagram of a second substrate and a second circuit unit provided in one embodiment of the present application;

[0040] FIG4 a is a schematic structural diagram of a second substrate and a second circuit unit provided in another embodiment of the present application;

[0041] FIG4 b is a schematic structural diagram of a second substrate and a second circuit unit provided in another embodiment of the present application;

[0042] FIG5 is a schematic diagram of a process of manufacturing a stacked chip according to an embodiment of the present application;

[0043] FIG6 is a schematic diagram of a process for manufacturing a stacked chip according to another embodiment of the present application;

[0044] FIG7 a is a schematic structural diagram of a stacked chip provided in one embodiment of the present application;

[0045] FIG7 b is a schematic structural diagram of a stacked chip provided in another embodiment of the present application;

[0046] FIG7 c is a schematic structural diagram of a stacked chip provided in another embodiment of the present application;

[0047] FIG7 d is a schematic structural diagram of a stacked chip provided in another embodiment of the present application;

[0048] FIG7e is a schematic structural diagram of a stacked chip provided in another embodiment of the present application;

[0049] FIG8 is a schematic structural diagram of a stacked chip provided in another embodiment of the present application;

[0050] FIG9 is a schematic structural diagram of a first chip provided by an embodiment of the present application;

[0051] FIG10 is a schematic structural diagram of a second chip provided by an embodiment of the present application;

[0052] FIG11 is a flow chart of a method for manufacturing a circuit unit according to an embodiment of the present application;

[0053] FIG12 is a schematic diagram (I) of a process of manufacturing a circuit unit provided by an embodiment of the present application;

[0054] FIG13 is a schematic diagram (II) of a process of manufacturing a circuit unit provided by an embodiment of the present application;

[0055] FIG14 is a schematic diagram (III) of a process of manufacturing a circuit unit provided by an embodiment of the present application;

[0056] FIG15 is a schematic diagram (IV) of a process of a method for manufacturing a circuit unit provided by an embodiment of the present application;

[0057] FIG16 is a schematic diagram (V) of a process of manufacturing a circuit unit provided by an embodiment of the present application;

[0058] FIG17 is a schematic diagram (VI) of a method for manufacturing a circuit unit according to an embodiment of the present application;

[0059] FIG18 is a top view of a circuit unit provided in one embodiment of the present application;

[0060] FIG19 is a schematic structural diagram of a laminated substrate provided in one embodiment of the present application;

[0061] FIG20 is a schematic structural diagram of a laminated substrate provided in another embodiment of the present application.

[0062] Figure markings: 100-first substrate; 110-first circuit unit; 101-first circuit; 102-first solder pad; 103-first connecting line; 120-conductive adhesive layer; 130-insulating adhesive layer; 1000-first chip; 1100-first substrate assembly; 200-second substrate; 210-second circuit unit; 201-second circuit; 202-yield portion; 203-second solder pad; 204-second connecting line; 220-conductor; 221-first bridging solder pad; 222-second bridging solder pad; 223-bridging solder pad; 2000-second chip; 2100-second substrate assembly; 10-substrate; 11-connecting line; 12-first insulating layer; 121-first opening; 13-second conductive layer; 141-solder pad; 142-circuit; 143-inner end; 15-second insulating layer; 151-second opening. DETAILED DESCRIPTION

[0063] The present invention will be further described in detail below by means of specific embodiments in conjunction with the accompanying drawings. Similar elements in different embodiments are numbered with associated similar elements. In the following embodiments, many detailed descriptions are provided to enable the present application to be better understood. However, those skilled in the art will readily appreciate that some of the features may be omitted in different circumstances, or may be replaced by other elements, materials, or methods. In some cases, some operations related to the present application are not shown or described in the specification. This is to avoid the core portion of the present application being overwhelmed by excessive descriptions, and for those skilled in the art, it is not necessary to describe these related operations in detail. They will fully understand the related operations based on the description in the specification and the general technical knowledge in the art.

[0064] In addition, the features, operations, or characteristics described in the specification may be combined in any appropriate manner to form various embodiments. Furthermore, the steps or actions in the method description may be reordered or adjusted in a manner readily apparent to those skilled in the art. Therefore, the various sequences in the specification and drawings are provided solely for the purpose of clearly describing a particular embodiment and are not intended to be mandatory, unless otherwise specified.

[0065] The serial numbers assigned to components herein, such as "first," "second," etc., are used solely to distinguish the objects being described and do not convey any sequential or technical meaning. References to "connection" and "coupling" herein, unless otherwise specified, include both direct and indirect connections (couplings).

[0066] To address the low production efficiency of existing stacked chip manufacturing methods, this application proposes a manufacturing method that manufactures multiple first circuit units on a first substrate, and correspondingly manufactures multiple second circuit units on a second substrate. The two substrates are then stacked together in a single sheet. After slicing, multiple stacked chips are obtained, significantly improving production efficiency. It should be noted that when a third type of chip is present, multiple third circuit units are correspondingly formed on the third substrate. When a fourth type of chip is present, multiple fourth circuit units are correspondingly formed on the fourth substrate, and so on.

[0067] In this application, unless otherwise specified, a circuit unit refers to the collective term for the circuits, connecting wires, and pads on an independent chip. The circuit may include an inductor (such as a coil as shown in Figures 7a-7d), a capacitor (such as a plate as shown in Figure 8), a resistor, etc. Generally speaking, an independent chip includes at least one circuit unit, or multiple circuit units. Due to the space limitations between the two independent chips in a stacked chip, in order to facilitate subsequent wiring, there are differences between the two independent chips, specifically differences in substrates, sizes, shapes, and layouts of pads and circuits.

[0068] Example 1

[0069] As shown in FIG1 and FIG5 , an embodiment of the present application provides a method for manufacturing a stacked chip, which may include:

[0070] Step 1: As shown in FIG. 2 , a first substrate 100 is provided. A plurality of first circuit units 110 are formed on the first substrate 100 . The first circuit units 110 may include a first circuit 101 and a first pad 102 of the first circuit 101 .

[0071] It is understandable that the first pad 102 is electrically connected to the first circuit 101 , and is an endpoint pad on the chip that connects the first circuit 101 to other circuits, for example, an endpoint pad that is bridged to an external pin of the chip.

[0072] Step 2, as shown in FIG3 and FIG4b, provides a second substrate 200, on which a plurality of second circuit units 210 and a plurality of relief portions 202 are formed. The relief portions 202 can be formed on the second substrate 200 before or after the second circuit units 210 are manufactured.

[0073] For example, the first circuit unit 110 can be prefabricated on the first substrate 100, and the second circuit unit 210 can be prefabricated on the second substrate 200. When batch manufacturing stacked chips, using substrates with prefabricated circuit units can greatly improve production efficiency.

[0074] In some embodiments, as shown in Figures 7a to 10, the first circuit unit 110 may include a first circuit 101, a first pad 102, and a first connection line 103 connecting the first circuit 101 and the first pad 102; the second circuit unit 210 may include a second circuit 201, a second pad 203, and a second connection line 204 connecting the second circuit 201 and the second pad 203. The first circuit 101 may be the first conductive coil shown in Figure 7a or the first electrode plate shown in Figure 8, and the second circuit 201 may be the second conductive coil shown in Figure 7a or the second electrode plate shown in Figure 8.

[0075] Step 3, as shown in Figure 5, the first substrate 100 and the second substrate 200 are stacked to form a stacked component, as shown in Figures 7a and 8, wherein one second circuit unit 210 is set corresponding to one first circuit unit 110, specifically one second circuit 201 is set corresponding to one first circuit 101; one yield portion 202 is set corresponding to at least one first solder pad 102, and the first solder pad 102 is not covered by the second substrate 200 through the yield portion 202.

[0076] For example, the thickness of each of the first substrate 100 and the second substrate 200 may be in the range of 50 micrometers to 300 micrometers, preferably 100 micrometers, 200 micrometers, or 250 micrometers.

[0077] In the present application, the two substrates are thin and large in area, and a vacuum bonding method can be used for bonding. Specifically, a first adsorption device is used to adsorb the first substrate 100 from below, and a second adsorption device is used to adsorb the second substrate 200 from above. Both the first adsorption device and the second adsorption device include horizontal shaping plates, which are bonded to the first substrate 100 and the second substrate 200 respectively during adsorption to prevent the glass substrate from warping when the two substrates are combined.

[0078] Step 4, as shown in FIG5 , the stacked assembly is sliced ​​to obtain a plurality of stacked chips, each of which may include a first circuit unit 110, a second circuit unit 210, and a first pad 102. For example, laser cutting, wire cutting, or blade cutting is used.

[0079] As shown in Figures 5 and 6, the cut stacked chip also has a clearance portion 202. The cut portion bypasses the clearance hole or is located exactly where the strip hole is. As shown in Figure 5, there is residual material on both sides of the strip groove on the second substrate 200. The residual material on the left or right side of the strip groove after cutting may have peeled off during the production process or been peeled off with a tool.

[0080] In some embodiments, in the above step 3, in order to improve the alignment degree between the first circuit unit 110 and the second circuit unit 210 in the stacked chip, an alignment portion can be provided, wherein the first substrate 100 can have a first alignment portion and the second substrate 200 correspondingly has a second alignment portion.

[0081] For example, before stacking the first substrate 100 and the second substrate 200 to form a stacked assembly, the following steps may also be included:

[0082] Step 300: Align the second alignment portion with the first alignment portion.

[0083] For example, as shown in FIG5 , the first substrate 100 and the second substrate 200 have the same dimensions and can both be square substrates. Alignment is achieved by using corner stoppers. In this case, the first alignment portion can be an edge or corner of the first substrate 100, and the second alignment portion can be an edge or corner of the second substrate 200. Alternatively, the two alignment portions can be positioning holes pre-set on the first substrate 100 and the second substrate 200.

[0084] In some embodiments, in step 3, stacking the first substrate 100 and the second substrate 200 to form a stacked assembly may include:

[0085] Step 310 : forming a connection layer on the first substrate 100 ; for example, the connection layer may be implemented by adopting an insulating adhesive layer.

[0086] Step 320 , stacking the second substrate 200 on the first substrate 100 ; wherein the second substrate 200 is aligned with the first substrate 100 , and one second circuit unit 210 is aligned with one first circuit unit 110 ; fixing the second substrate 200 on the first substrate 100 through a connecting layer.

[0087] In some embodiments, as shown in FIG. 3 , the relief portion 202 may include a plurality of through holes.

[0088] In the above step 2, the clearance portion 202 may be in the form of a through hole. Forming a plurality of clearance portions 202 on the second substrate 200 may include:

[0089] Step 210 : forming a plurality of through holes on the second substrate 200 , wherein each through hole is used to allow a first solder pad 102 to be uncovered by the second substrate 200 .

[0090] Step 220 : forming a plurality of second circuit units 210 on the second substrate 200 .

[0091] In the present application, a through hole is first formed on the second substrate 200, for example, by chemical etching. Forming the through hole first can prevent the chemical from corroding the second circuit unit. Of course, the second circuit unit 210 can also be formed first and then the through hole is formed, using mask etching or laser etching to form the through hole.

[0092] In some embodiments, the second substrate 200 may be a glass substrate, and a through-hole (TGV) is located on the glass substrate. This through-hole is also known as a TGV (Through Glass Via) hole, which is a vertical electrical interconnection hole that passes through the glass substrate. This corresponds to TSV (Through Silicon Via), a material that may replace silicon substrates and is considered a key technology for next-generation 3D integration.

[0093] In some embodiments, the second circuit 201 may include a second conductive coil; corresponding to steps 10 to 70 in the third embodiment, the following steps may be used to form a plurality of second circuit units 210 on the second substrate 200:

[0094] Step 2000 : forming a first conductive layer on the second substrate 200 , and patterning the first conductive layer to form a plurality of second connection lines 204 .

[0095] The second connecting wires 204 serve to connect the solder joints in the second circuit 201 to the edges of the second circuit 201 to facilitate connection with subsequent chip pins.

[0096] Step 2100 : forming a second insulating layer covering the second connecting line 204 on the second substrate 200 .

[0097] Step 2200 : forming a plurality of first openings on the second insulating layer, wherein each first opening exposes one end of the second connecting line 204 .

[0098] Step 2300: Form a second conductive layer on the first insulating layer. The second conductive layer also fills the first opening to connect to the second connection line 204. The second conductive layer also covers the first opening to lead the inner end to the second pad position, facilitating connection of the conductive coil to the external circuit.

[0099] Step 2400 , patterning the second conductive layer to form a plurality of second conductive coils and a plurality of second pads 203 , each second conductive coil may include an inner end and an outer end, and each second conductive coil is connected to two second pads 203 respectively, and the inner end is connected to the second connection line 204 through the first opening.

[0100] Step 2500 : forming a second insulating layer covering the second conductive coil and the second pad 203 .

[0101] Step 2600: Form a second opening on the second insulating layer, where the second opening is used to expose the second pad 203 to achieve connection with an external circuit.

[0102] In some embodiments, as shown in FIG7b , the second circuit unit 210 includes multiple conductive elements, which may include a second connecting line 204, a second pad 203, a second circuit 201, a first bridge pad 221, a second bridge pad 222, and a conductor 220. For example, the conductor 220 is formed in the same process as at least one of the multiple conductive elements. Alternatively, at least two conductive elements are formed in the same process, for example, the second connecting line 204 and the first bridge pad 221 can be formed in the same process, and the second pad 203 and the second bridge pad 222 can be formed in the same process.

[0103] In some embodiments, as shown in Figures 7a and 7b, an endpoint pad in the second circuit 201 (located in the middle, not at the edge of the second circuit, not shown) is connected to the second pad 203 via a second connecting wire 204, extending inward along the thickness of the first insulating layer. In other words, the endpoint pad is not directly connected to the second pad 203, but rather connects to the second pad 203 by bypassing components in the second circuit 201 in the longitudinal direction. Compared to placing the second connecting wire 204 above the second conductive layer, this can avoid the phenomenon of poor contact with the endpoint pad in the second circuit 201 caused by the connecting wire climbing.

[0104] In some embodiments, the step 210 of forming a plurality of through holes on the second substrate 200 may further include:

[0105] Step 211 , as shown in FIG. 7 b , a conductor 220 is formed at the through hole (such as the clearance portion 202 shown in FIG. 7 a ).

[0106] The step 220 of forming a plurality of second circuit units 210 on the second substrate 220 may further include:

[0107] Step 221, as shown in Figure 7b, in step 2000, the first conductive layer also covers the through-hole. After the first conductive layer is patterned, the first conductive layer forms a conductor 220 at the location of the through-hole, and the conductor 220 at least partially fills the through-hole. For example, at least part of step 211 and step 221 can be performed simultaneously in the same process. When the first conductive layer is formed, the first conductive layer simultaneously fills the through-hole and forms the conductor 220. The conductor 220 can also protrude from a portion of the surface of the second substrate 200, flush with or substantially flush with the second connecting line 204.

[0108] Step 222, as shown in Figure 7b, in step 2300, the second conductive layer also covers the conductor 220. After the second conductive layer is patterned, the second conductive layer forms a bridging pad 223 at the position of the conductor 220. The bridging pad 223 is stacked on the conductor 220 and connected to the first pad 102 of the first substrate 100 through the conductor 220.

[0109] In some embodiments, the conductive body 220 may be formed first with the second circuit unit 210 , and a bridge pad may be formed on the conductive body 220 during the formation process of the second circuit unit 210 .

[0110] After step 211, step 220 of forming a plurality of second circuit units 210 on the second substrate 220 may further include:

[0111] Step 223 , as shown in FIG. 7 c , in step 2000 , the first conductive layer also covers the conductor 220 . After the first conductive layer is patterned, the first conductive layer forms a first bridging pad 221 at the location of the through hole.

[0112] Step 224, as shown in Figure 7c, in step 2300, the second conductive layer also covers the first bridging pad 221. After the second conductive layer is patterned, the second conductive layer forms a second bridging pad 222 at the position of the first bridging pad 221. The second bridging pad 222 is stacked on the first bridging pad 221 and connected to the first pad 102 of the first substrate 100 through the conductor 220.

[0113] When patterning the second conductive layer or the second conductive layer, the less blank area (that is, the area where the excess part is etched away) is left, the better. If there is too much blank area, the patterning time will be long, resulting in low patterning efficiency. The patterning process includes processes such as photolithography, exposure, development, and drying, and the development process is generally achieved by immersing the product in a developer. The more blank areas are left, the more developer is used, and the longer the development time and drying time are, which is not conducive to improving efficiency. Therefore, the first conductive layer (corresponding to the first bridging pad 221) and the second conductive layer (corresponding to the second bridging pad 222) on the first pad 102 corresponding to the position of the second circuit unit 210 are retained. The places where insulation is required between other circuits are etched away to form blank areas, which is not only conducive to improving efficiency, but also does not hinder the electrical connection between the conductor 220 and each pad.

[0114] Through the above steps, the second connecting wires 204 are formed below the second insulating layer / second circuit 201 and above the second substrate 200. This wiring method helps avoid obstruction caused by the connecting wires above the second circuit 201, facilitating soldering. Of course, for the manufacturing method of the stacked chip, whether the connecting wires are above or below the second circuit 201 does not affect the production efficiency of the stacked chip. The same applies to the first connecting wires 103.

[0115] For another example, the second circuit unit 210 may be formed on one side or both sides of the second substrate 200 . The second circuit unit 210 may also be formed on the second substrate 200 in a stacked manner.

[0116] Of course, the same steps can be used to form a plurality of first circuit units 110 on the first substrate 100 , which will not be described again here.

[0117] Steps 2000 to 2600 of the second circuit unit 210 may refer to steps 10 to 70 of the third embodiment. The second circuit 201, the second connecting line 204, the second conductive layer, the first insulating layer, the second insulating layer, the first opening, and the second opening may respectively correspond to the description of the circuit 142, the connecting line 11, the second conductive layer 13, the first insulating layer 12, the second insulating layer 15, the first opening 121, and the second opening 151 of the third embodiment. Similarly, the first circuit unit 110 also corresponds to the description thereof and will not be repeated here.

[0118] In some embodiments, before step 3 of laminating the first substrate 100 and the second substrate 200 to form a laminated assembly, the process further includes:

[0119] Step 3000, as shown in FIG7b, a conductive adhesive layer 120 is coated on the first pad 102 of the first substrate 100. The first circuit unit 110 is insulated from the conductive adhesive layer 120 to prevent the circuit unit from short-circuiting.

[0120] Step 3100: Apply an insulating adhesive layer 130 to the side of the second substrate 200 away from the second circuit unit 210. The insulating adhesive layer 130 does not cover the area of ​​the through-hole. The insulating adhesive layer 130 is used to bond the first substrate 100 and the second substrate 200 after they are stacked. The conductive adhesive layer 120 is used to electrically connect the first pad 102 and the conductor 220 after the first substrate 100 and the second substrate 200 are stacked. The conductive adhesive layer 120 and the insulating adhesive layer 130 are applied to the two substrates separately, and the two adhesive coating processes do not interfere with each other.

[0121] In some embodiments, the step 3000 of coating the conductive adhesive layer 120 on the first pad 102 of the first substrate 100 may include:

[0122] Step 3001: Provide a first preset template having a plurality of first hollow areas and non-hollow areas. The first preset template can prevent the conductive adhesive from being applied to the area of ​​the circuit unit and causing an impact on the circuit unit.

[0123] Step 3002: Place the first preset template on the first substrate 100, with the plurality of first hollow areas corresponding to and exposing the plurality of first pads 102. The non-hollow areas correspond to the plurality of first circuits to shield the first circuits and prevent the conductive adhesive layer 120 from being applied above the first circuits in step 3003.

[0124] Step 3003 : Under the masking of the first preset module, apply a conductive adhesive layer 120 on the exposed first pad 102 .

[0125] In some embodiments, step 3100 of coating the insulating adhesive layer 130 on the side of the second substrate 200 away from the second circuit unit 210 may include:

[0126] Step 3101: Provide a second preset template, wherein the second preset template has a second hollow area and a non-hollow area.

[0127] In step 3102, a second preset template is placed on the back of the second substrate 200 to shield the plurality of conductors 220. The non-hollowed areas correspond to the plurality of conductors 220 to shield the conductors 220 and prevent the insulating adhesive layer 130 from being coated below the conductors 220 in step 3103.

[0128] Step 3103 : Under the mask of the second preset template, an insulating adhesive layer 130 is applied to the exposed area on the back surface of the second substrate 200 except for the conductive body 220 .

[0129] The first preset template and the second preset module may be masks cut by laser.

[0130] In some embodiments, as shown in FIG2 , multiple first circuit units 110 are arranged in an array, and multiple first solder pads 102 are arranged in an array, such as the horizontal and vertical array arrangement shown in FIG2 . As shown in FIG4 a , the clearance portion 202 may include multiple strip-shaped holes, each of which is shorter than the width of the first circuit 101 in the direction of the strip-shaped hole length. Each strip-shaped hole is used to clear the multiple first solder pads 102 so that the first solder pads 102 are not covered by the second substrate 200 . As shown in FIG4 b , the clearance portion 202 may include multiple arrays of strip-shaped holes equal to the number of second circuit units 210, with each row having multiple strip-shaped holes. Compared to the implementation shown in FIG4 a , the multiple strip-shaped holes shown in FIG4 b can prevent large substrates from cracking due to insufficient strength of the second substrate 200.

[0131] It should be noted that, as shown in Figures 3 to 4b, the relief portion 202 can be implemented as a through hole or a bar hole, and the present application does not limit the possible implementation methods, such as square holes, special-shaped holes, special-shaped grooves, etc.

[0132] In some embodiments, in step 4, slicing the stacked component may include:

[0133] Step 410: Set a predetermined cutting line on the second substrate 200. The predetermined cutting line is located on a side of the clearance portion 202 that is different from the second circuit unit 210 (for each second circuit unit 210 on the cut chip). The predetermined cutting line divides the second substrate 200 into sections, each section corresponding to a second circuit unit 210 and a clearance portion 202 corresponding to the first solder pad 102.

[0134] Step 420: Slice the laminated component based on the preset cutting lines.

[0135] In summary, the manufacturing method provided in the first embodiment of the present application can form multiple small stacked chips by laminating two large substrates and then cutting them, which can greatly improve the production efficiency of the stacked chips.

[0136] A conductor 220 can also be formed in the yield portion 202, and a first bridging pad 221, a second bridging pad 222 or a bridging pad 223 can be formed on the conductor 220. On the one hand, it is beneficial for the second pad 203, the second bridging pad 222 or the bridging pad 223 on the first substrate 100 or the second substrate 200 to be at the same height or substantially at the same height, which is beneficial for the production of the second pad 203, the second bridging pad 222 or the bridging pad 223. On the other hand, raising the connection point of the first pad 102 is beneficial for improving the convenience of welding with the external circuit.

[0137] For example, when the stacked chip is connected to an external circuit, such as a PCB, the pads have the same height, making it easier to solder the stacked chip to the PCB using tinning.

[0138] Example 2

[0139] As shown in FIG. 2 and FIG. 6 , an embodiment of the present application further provides a method for manufacturing a stacked chip, which may include:

[0140] Step 5: As shown in FIG. 2 , a first substrate 100 is provided. A plurality of first circuit units 110 are formed on the first substrate 100 . The first circuit units 110 include first circuits 101 and first pads 102 of the first circuits 101 .

[0141] Step 6: As shown in FIG6 , a second substrate 200 is provided. A plurality of clearance portions 202 are formed on the second substrate 200 . The clearance portions 202 are through holes. In the second embodiment, the clearance portions 202 are formed in the second substrate 200 before the second circuit unit 210 .

[0142] Step 7: As shown in FIG. 6 , the first substrate 100 and the second substrate 200 are stacked, and a clearance portion 202 is provided corresponding to at least one first pad 102 . The first pad 102 is not covered by the second substrate 200 due to the clearance portion 202 .

[0143] Step 8, as shown in FIG6 , a plurality of second circuit units 210 and a plurality of conductors 220 are formed on the second substrate 200 , one second circuit unit 210 is arranged corresponding to one first circuit unit 110 , the conductors 220 are filled in the paving portion 202 and electrically connected to the first pads 102 to obtain a laminated component.

[0144] Step 9: As shown in FIG. 6 , the stacked assembly is sliced ​​to obtain a plurality of stacked chips. One stacked chip includes a first circuit unit 110 , a second circuit unit 210 and a first pad 102 .

[0145] The difference between the manufacturing method provided in Example 1 and the manufacturing method provided in Example 1 is that, in the manufacturing method provided in Example 2, the second circuit unit 210 is not prefabricated on the second substrate 200. The second circuit unit 210 is formed on the surface of the second substrate 200 after the second substrate 200 is stacked on the first substrate 100, and the conductor 220 is formed in the yield portion 202 at the same time.

[0146] As shown in Figures 7d and 7e, the conductor 220 can be directly formed on the first pad 102, so that the first substrate 100 and the second substrate 200 form a mechanical connection and an electrical connection. Compared with the chip shown in Figure 7b, there is no need to use step 3000 and its sub-steps described in Example 1 to form the conductive adhesive layer 120, which can save process steps.

[0147] Apart from the above differences, other process methods for each structure of the stacked chip can refer to the relevant steps in the first embodiment.

[0148] For example, the method for forming the second circuit unit 210 may refer to step 220 and steps 2000 to 2600 in the first embodiment; a first bridge pad 221 and a second bridge pad 222 may also be formed on the conductor 220 , which may refer to steps 221 to 222 in the first embodiment.

[0149] In some embodiments, in step 8, a plurality of second circuit units 210 may be formed on the second substrate 200 by using the following steps:

[0150] Step 2000 : forming a first conductive layer on the second substrate 200 , and patterning the first conductive layer to form a plurality of second connection lines 204 .

[0151] Step 2100 : forming a second insulating layer covering the second connecting line 204 on the second substrate 200 .

[0152] Step 2200 : forming a plurality of first openings on the second insulating layer, wherein each first opening exposes one end of the second connecting line 204 .

[0153] Step 2300: Form a second conductive layer on the first insulating layer. The second conductive layer also fills the first opening to connect to the second connection line 204. The second conductive layer also covers the first opening to lead the inner end to the second pad position, facilitating connection of the conductive coil to the external circuit.

[0154] Step 2400 , patterning the second conductive layer to form a plurality of second conductive coils and a plurality of second pads 203 , each second conductive coil may include an inner end and an outer end, and each second conductive coil is connected to two second pads 203 respectively, and the inner end is connected to the second connection line 204 through the first opening.

[0155] Step 2500 : forming a second insulating layer covering the second conductive coil and the second pad 203 .

[0156] Step 2600: Form a second opening on the second insulating layer, where the second opening is used to expose the second pad 203 to achieve connection with an external circuit.

[0157] In some embodiments, as shown in FIG7 d , the second circuit unit 210 includes multiple conductive elements, which may include a second connecting line 204, a second pad 203, a second circuit 201, a first bridge pad 221, a second bridge pad 222, and a conductor 220. For example, the conductor 220 is formed in the same process as at least one of the multiple conductive elements. Alternatively, at least two conductive elements are formed in the same process, for example, the second connecting line 204 and the first bridge pad 221 can be formed in the same process, and the second pad 203 and the second bridge pad 222 can be formed in the same process.

[0158] In some embodiments, the step 210 of forming a plurality of through holes on the second substrate 200 may further include:

[0159] Step 211, as shown in FIG7d, a conductor 220 is formed in the through hole (the clearance portion 202 shown in FIG7a). The conductor 220 is filled in the through hole and directly formed on the first pad 102 to achieve electrical connection.

[0160] Step 8 of forming a plurality of second circuit units 210 on the second substrate 220 may further include:

[0161] Step 221, as shown in FIG7d, in step 2000, the first conductive layer also covers the conductor 220 in the through-hole. After the first conductive layer is patterned, the first conductive layer forms a first bridging pad 221 at the location of the through-hole. For example, steps 211 and 221 can be performed simultaneously in the same process. When forming the first conductive layer, the first conductive layer simultaneously fills the through-hole and forms the conductor 220. The conductor 220 is directly formed on the first pad 102.

[0162] Step 222, as shown in Figure 7d, in step 2300, the second conductive layer also covers the first bridging pad 221. After the second conductive layer is patterned, the second conductive layer forms a second bridging pad 222 at the position of the first bridging pad 221. The second bridging pad 222 is stacked on the first bridging pad 221 and connected to the first pad 102 of the first substrate 100 through the conductor 220.

[0163] In some embodiments, the portion of the conductor 220 corresponding to the first bridge pad 221 may be formed simultaneously, and the step 220 of forming a plurality of second circuit units 210 on the second substrate 220 may further include:

[0164] Step 223, as shown in FIG7e, in step 2000, the first conductive layer also covers the through-hole. After the first conductive layer is patterned, the first conductive layer forms a conductor 220 at the location of the through-hole. Conductor 220 at least partially fills the through-hole. Conductor 220 may also protrude from a portion of the surface of second substrate 200 and be flush with or substantially flush with second connecting line 204.

[0165] Step 224, as shown in Figure 7e, in step 2300, the second conductive layer also covers the conductor 220. After the second conductive layer is patterned, the second conductive layer forms a bridging pad 223 at the position of the conductor 220. The bridging pad 223 is stacked on the conductor 220 and connected to the first pad 102 of the first substrate 100 through the conductor 220.

[0166] In some embodiments, the conductor 220 is first formed with the second circuit unit 210, and during the manufacturing process of the second circuit unit 210, a bridge pad is formed on the conductor 220. In some embodiments, before step 8 of laminating the first substrate 100 and the second substrate 200 to form a laminated assembly, the following steps may be further included:

[0167] Step 8100: Coat an insulating adhesive layer 130 on the side of the second substrate 200 away from the second circuit unit 210, wherein the insulating adhesive layer 130 does not cover the area of ​​the through hole. The insulating adhesive layer 130 is used to combine the first substrate 100 and the second substrate 200 after the first substrate 100 and the second substrate 200 are stacked.

[0168] In some embodiments, step 8100 of coating the insulating adhesive layer 130 on the side of the second substrate 200 away from the second circuit unit 210 may include:

[0169] Step 8101: Provide a second preset template, wherein the second preset template has a second hollow area and a non-hollow area.

[0170] In step 8102, a second preset template is placed on the back of the second substrate 200. The second preset template covers the plurality of conductors 220. The non-hollowed areas correspond to the plurality of conductors 220 to cover the conductors 220 and prevent the insulating adhesive layer 130 from being coated below the conductors 220 in step 3103.

[0171] Step 8103 : Under the mask of the second preset template, apply an insulating adhesive layer 130 to the exposed area of ​​the back surface of the second substrate 200 except the clearance portion 202 .

[0172] Example 3

[0173] As shown in FIG11 , an embodiment of the present application provides a method for manufacturing a circuit unit. The method can be used to manufacture the first circuit unit 110 and the second circuit unit 210 in the first embodiment. The method may include:

[0174] Step 10, as shown in FIG12 , forms a first conductive layer on the substrate 10 and patterns the first conductive layer to form a plurality of connecting lines 11. For example, the first conductive layer can be formed using a sputtering process such as electroplating, printing, magnetron sputtering, or a thin film process such as PVD. Alternatively, the first conductive layer can be patterned using photolithography and etching to form the first conductive layer on the substrate 10 according to the desired shape of the connecting lines 11.

[0175] The first conductive layer may be a single layer of conductive material or a multilayer conductive material, for example, formed of one or more materials selected from titanium, titanium carbide, copper, aluminum, silver or gold.

[0176] Corresponding to the first embodiment, the substrate 10 corresponds to the first substrate 100 or the second substrate 200 , and the connecting wires 11 correspond to the first connecting wires 103 or the second connecting wires 204 .

[0177] Step 20, as shown in FIG12 , forms a first insulating layer 12 on the substrate 10, the first insulating layer 12 at least covering the connecting wires 11. For example, the first insulating layer 12 is formed on the first conductive layer by using a sputtering process such as printing, magnetron sputtering, or a thin film process such as PVD.

[0178] Step 30 : forming a plurality of first openings 121 on the first insulating layer 12 , wherein each first opening 121 exposes one end of the connecting line 11 .

[0179] For example, the first insulating layer 12 can be patterned by photolithography and etching according to the positions where the pads 141 and the circuits 142 are connected to the connecting wires 11, respectively, to form a first opening 121, thereby exposing the connection positions. The rest of the connecting wires 11 are covered by the first insulating layer 12 to achieve insulation.

[0180] Step 40: As shown in FIG13 , a second conductive layer 13 is formed on the first insulating layer 12. The second conductive layer 13 also fills the first opening 121 to connect to the first connecting line 11. For example, the first conductive layer can be formed using a sputtering process such as electroplating, printing, magnetron sputtering, or a thin film process such as PVD. The second conductive layer 13 can be a single layer of conductive material or a multilayer conductive material, such as one or more materials selected from titanium, titanium carbide, copper, aluminum, silver, or gold.

[0181] Step 50, as shown in Figures 14 and 15, pattern the second conductive layer 13 to form multiple circuits 142 and pads 141 connecting the circuits 142; a pad 141 is set corresponding to a first opening 121, and a circuit unit may include a circuit 142 and a corresponding pad 141. The circuit may include a conductive coil shown in Figure 14 or a plate shown in Figure 15.

[0182] Corresponding to the first embodiment, the circuit 142 corresponds to the first circuit 101 or the second circuit 201 , and the pad 141 corresponds to the first pad 102 or the second pad 203 .

[0183] For example, according to the required shape of the circuit 142 , the second conductive layer 13 is patterned by photolithography and etching.

[0184] For example, as shown in Figures 14 and 18, the circuit 142 can be a conductive coil, each conductive coil can include an inner end 143 and an outer end, and each conductive coil is connected to two solder pads 141 respectively, and the inner end 143 is connected to the connecting line 11 through the first opening 121; for another example, as shown in Figure 15, the circuit 142 can be a conductive electrode, and at least one solder pad 141 is connected to a conductive electrode.

[0185] It should be noted that, in Figures 12 to 17, the first solder pad 141 connected to the connecting wire 11 and the inner end 142 is illustrated, and the first solder pad 141 corresponding to the outer end is not shown. The first solder pad 141 corresponding to the outer end can be shown in Figure 18.

[0186] Corresponding to the first embodiment, the conductive coil corresponds to the first conductive coil or the second conductive coil, and the conductive electrode plate corresponds to the first electrode plate or the second electrode plate.

[0187] Step 60: As shown in FIG16 , a second insulating layer 15 is formed covering the circuit 142 and the pad 141. The material of the second insulating layer 15 can be the same as or different from that of the first insulating layer 12. Generally, to ensure connectivity between the structural layers, the same material is used in this application, such as photosensitive polyimide (PSPI). Other insulating materials, such as acrylonitrile-butadiene-styrene copolymer (ABS), polystyrene (PS), silicon dioxide, silicon nitride, etc., can also be used.

[0188] 17 , a second opening 151 is formed on the second insulating layer 15. The second opening 151 is used to connect the pad 141 to an external circuit 142. For example, the second insulating layer 15 is patterned using photolithography and etching according to the position and desired shape of the pad 141.

[0189] In summary, the circuit unit manufacturing method of the third embodiment can be used to manufacture circuit units on a substrate 10. It can be used to manufacture the first circuit unit 110 on the first substrate 100 and the second circuit unit 210 on the second substrate 200 in the first embodiment. The connection line 11 can be arranged below the circuit 142 (with the substrate 10 as the bottom as the reference direction). The connection line 11 will not block the circuit 142, which can facilitate soldering to the pad 141, and the overall manufacturing process is convenient.

[0190] For example, the pads of some circuits may be inside the circuit, but for standard chips, the pins are located at the ends of the chip, and the pads inside the circuit cannot be directly led to the ends. Therefore, internal connecting wires are used to bypass other conductive parts of the circuit to prevent short circuits with other parts of the circuit caused by directly leading connecting wires from the internal pads.

[0191] Example 4

[0192] As shown in FIG. 7 a to FIG. 7 e , an embodiment of the present application provides a stacked chip, which may include a first chip 1000 and a second chip 2000 .

[0193] As shown in Figure 9, the first chip 1000 may include a first substrate 100 having a first surface (such as the upper surface of the first substrate 100 in Figure 9) and a first circuit unit 110 formed on the first surface. The first circuit unit 110 may include a first conductive coil having two ends (corresponding to the first circuit 101 in Example 1) and two first solder pads 102. The two first solder pads 102 are respectively connected to the two ends or located at the two ends.

[0194] As shown in Figure 10, the second chip 2000 is arranged on the first chip 1000. The second chip 2000 may include a second substrate 200 having a second surface (such as the upper surface of the second substrate 200 in Figure 10) and a second conductive coil formed on the second surface (corresponding to the second circuit 201 in Example 1). The second substrate 200 has a yield portion 202, and the yield portion 202 is arranged corresponding to the two first solder pads 102, so that the first solder pads 102 are connected to the external circuit through the yield portion 202.

[0195] The projection of the second conductive coil on the first surface covers at least 80% of the projection of the first conductive coil on the first surface. Overlapping the two coils maximizes energy or signal transmission efficiency; staggered placement results in greater energy or signal loss. As shown in Figures 3, 4a, 4b, and 18, the coil layer spirally forms multiple turns. The projection of the two conductive coils refers to the area of ​​the shape (e.g., a circle or rectangle) enclosed by the outermost turns, which define the area of ​​the coils. The at least 80% coverage refers to the projection ratio of the area defined by the outermost turns of the two coils. As shown in Figure 7a, to ensure convenient soldering of the pads to external leads and overlap of the two conductive coils, the first pad 102 and the second pad 203 are located on opposite sides of the stacked chip (left and right as shown in Figure 7a). In some embodiments, the second chip 2000 may include a second substrate 200 and a second circuit unit 210 formed on the second surface. The second circuit unit 210 may include a second conductive coil having two ends and two second pads 203, with the two second pads 203 connected to or located at the two ends.

[0196] As shown in Figures 2 through 4, the first and second pads 102 and 203 can be arranged on opposite sides of the stacked chip. As shown in Figure 2, the first pad 102 is located below the first conductive coil, while as shown in Figures 3 and 4, the second pad 203 is located above the second conductive coil. As shown in Figure 7a, the first pad 102 is exposed by the relief portion 202, enabling front-side soldering.

[0197] In some embodiments, the first substrate 100 may be a glass substrate or a composite substrate containing glass, and / or the second substrate 200 may be a glass substrate or a composite substrate containing glass. The glass may be a silicate-based glass (e.g., lithium silicate, borosilicate, aluminum silicate, etc.), a soda-lime glass, or a glass made of fused quartz. The dimensions of the glass substrate or composite substrate may be 510 mm by 515 mm, 600 mm by 600 mm, 730 mm by 920 mm, or other sizes.

[0198] In some embodiments, the clearance portion 202 may be a clearance hole / through hole filled with a conductor 220. A bridge pad is provided on a side of the clearance hole that is different from the first substrate 100. The bridge pad is electrically connected to the first pad 102 via the conductor 220. The bridge pad is used to connect to an external circuit. For example, the external circuit may be a pin on a control chip or a circuit board.

[0199] As shown in Figures 7b to 7e, the clearance portion 202 may be a through hole / clearance hole, the size of which may correspond to the size of the first pad 102. The stacked chip may further include a conductor 220, which is filled in the clearance portion 202. As shown in Figures 7d and 7e, the conductor 220 may be formed directly on the first pad 102; as shown in Figure 7b, the conductor 220 may also be electrically connected to the first pad 102 via a conductive adhesive layer 120.

[0200] As shown in Figures 7b to 7e, the conductor 220 or the bridge pad is disposed on the same layer as at least part of the second circuit unit 210. For example, the first bridge pad 221 can be disposed on the same layer as the second connection line 204, and the second bridge pad 222 / bridge pad 223 can be disposed on the same layer as the second pad 203. As shown in Figures 7b and 7d, the conductor 220 can be disposed on the same layer as the second connection line 204.

[0201] For another example, the stacked chip may further include a bridge pad connected to the conductor 220. The top surface of the bridge pad may be flush with the top surface of the second pad 203. The bridge pad is used to connect to an external circuit to achieve an electrical connection between the external circuit and the first pad 102. The bridge pad may include a first bridge pad 221, a second bridge pad 222, or a bridge pad 223. The stacked chip may be an inductive stacked chip and may be used to manufacture a magnetically coupled digital isolator or a transformer (such as a DC-DC transformer).

[0202] The stacked chip in the fourth embodiment can be manufactured using the stacked chip manufacturing method described in the first or second embodiment.

[0203] The first circuit unit 110 or the second circuit unit 210 in the fourth embodiment can be manufactured using the circuit unit manufacturing method described in the third embodiment.

[0204] Example 5

[0205] As shown in FIG. 8 , an embodiment of the present application provides a stacked chip, which may include a first chip 1000 and a second chip 2000 .

[0206] The first chip 1000 may include a first substrate 100 having a first surface (such as the upper surface of the first substrate 100 in Figure 8) and a first circuit unit 110 formed on the first surface. The first circuit unit 110 may include a first electrode (corresponding to the first circuit 101 in Example 1) and a first solder pad 102 connected to the first electrode.

[0207] The second chip 2000 is disposed on the first chip 1000. The second chip 2000 may include a second substrate 200 having a second surface (such as the upper surface of the second substrate 200 in FIG8 ) and a second circuit unit 210 formed on the second surface. The second circuit unit 210 may include a second electrode plate (corresponding to the second circuit 201 in the first embodiment). The second substrate 200 has a relief portion 202. The relief portion 202 is disposed on the second substrate 200 corresponding to the first solder pad 102 so that the projection of the second chip 2000 on the first surface does not cover the first solder pad 102. The projection of the second electrode plate on the first surface covers the projection of the first electrode plate on the first surface. When the two electrode plates overlap, the energy transmission efficiency or signal transmission efficiency is maximized; if they are staggered, the energy and signal loss is large.

[0208] As shown in FIG8 , in order to ensure convenient soldering between the pads and external leads and to ensure overlap between the two plates, the first pads 102 and the second pads 203 are located on both sides of the stacked chip (left and right sides as shown in FIG8 ).

[0209] In some embodiments, as shown in FIG. 7b and FIG. 7d , in the stacked chip provided in this embodiment, the clearance portion 202 may be a through-hole, the size of which corresponds to the size of the first pad 102. The stacked chip may further include a conductor 220, which is filled in the clearance portion 202. As shown in FIG. 7d , the conductor 220 may be formed directly on the first pad 102; as shown in FIG. 7b , the conductor 220 may also be electrically connected to the first pad 102 via a conductive adhesive layer 120.

[0210] For another example, the stacked chip may further include a bridge pad connected to the conductor 220. The top surface of the bridge pad may be flush with the top surface of the second pad 203. The bridge pad is used to connect to an external circuit to achieve an electrical connection between the external circuit and the first pad 102. The bridge pad may include a first bridge pad 221 and a second bridge pad 222 or a bridge pad 223.

[0211] The above-mentioned stacked chip can be a capacitive stacked chip, which can be used to manufacture capacitor devices, filter devices, energy storage devices, isolated DC devices, resonant devices, etc.

[0212] The stacked chip in the fifth embodiment can be manufactured using the manufacturing method of the stacked chip described in the first or second embodiment, thereby obtaining the stacked chip as shown in FIG. 7 a to FIG. 8 .

[0213] The first circuit unit 110 or the second circuit unit 210 in the fifth embodiment can be manufactured using the circuit unit manufacturing method described in the third embodiment.

[0214] Example 6

[0215] As shown in FIG. 19 and FIG. 20 , an embodiment of the present application further provides a laminated substrate, which may include: a first substrate assembly 1100 and a second substrate assembly 2100 .

[0216] The first substrate assembly 1100 may include a first substrate 100 , and a plurality of first circuit units 110 formed on the first substrate 100 . The first circuit unit 110 may include a first circuit 101 and a first pad 102 of the first circuit 101 .

[0217] The second substrate assembly 2100 may include a second substrate 200 , and a plurality of second circuit units 210 and a plurality of relief portions 202 formed on the second substrate 200 .

[0218] Among them, the first substrate 100 and the second substrate 200 are stacked to form a stacked component, a second circuit unit 210 is set corresponding to a first circuit unit 110, a recess 202 is set corresponding to at least one first solder pad 102, and the first solder pad 102 is used to connect to the external circuit through the recess 202. The stacked substrate is used to be cut into multiple stacked chips, and a stacked chip includes a first circuit unit 110, a second circuit unit 210 and a first solder pad 102.

[0219] As shown in Figure 19 , the first circuit 101 may include a first conductive coil, and the second circuit 201 may include a second conductive coil. As shown in Figure 20 , the first circuit 101 may include a first electrode plate, and the second circuit 201 may include a second electrode plate. When the clearance portion 202 is a through hole / clearance hole, referring to Figures 7b to 7e , the second substrate assembly 2100 may further include a conductor 220 , which is formed at the through hole and may have a bridging pad formed thereon. The conductor 220 may be formed directly on the surface of the first pad 102, or the conductor 220 may be electrically connected to the first pad 102 via a conductive adhesive layer 120 .

[0220] The laminated substrate can be cut to obtain multiple laminated chips. Users can cut according to actual needs. A single chip can be shown in Figures 7a to 7e. Users can cut to form two, three, or more laminated chips as a whole.

[0221] As shown in Figures 19 and 20, there can be three stacked chips. The three stacked chips can be connected to the first pads 102 and the second pads 203 via wires, enabling series or parallel connection of the multiple stacked chips, or a combination thereof, to form a chipset with more electrical functions. Alternatively, multiple independent stacked chips can be stacked in 3D and connected in series or parallel via their respective pads to achieve more complex electrical functions.

[0222] In summary, the laminated chips, laminated substrates, and their manufacturing methods provided by this application, taking an inductive laminated chip as an example, are currently produced and packaged in the following manner: first, two coils of different sizes are produced on the same glass substrate, then the coils are cut, and then the cut coils are laminated and stacked one by one, which wastes a lot of time and labor costs. In this application, however, a glass substrate has only one coil size, and then the coils to be stacked are laminated as a whole. After lamination, the upper and lower substrates are cut and packaged together, which greatly saves time and labor, and the procedure is simpler than the previous method.

[0223] Alternatively, based on the second substrate with through holes, the second substrate can be first bonded to the first substrate, and then a second circuit unit and a conductor can be formed on the second substrate. The conductor can improve the convenience of connecting the first pad to the external circuit, and can also improve production efficiency.

[0224] The present invention utilizes a technique for stacking two glass substrates to form chips, which can be referred to as panel-to-panel stacking, panel-level stacking packaging, or panel-level packaging. This technology is used in the field of electronic packaging, and through this panel-level packaging technology, higher-density, more compact electronic components can be mass-produced.

[0225] In this application, glass substrates are used as the first substrate and the second substrate. In the traditional chip manufacturing process, organic materials such as semiconductor materials such as silicon are used as substrates to make chips. Glass, as an inorganic non-metallic material, has different physical and chemical properties from semiconductor materials. Glass substrates have good thermal stability and can remain stable in high temperature environments. During the packaging process, they can withstand higher temperatures better than silicon substrates, thereby avoiding distortion or errors in the signal transmission process and reducing warping and deformation. In addition, the flatness of the glass substrate is high, which can ensure the accuracy of the signal transmission path. Although glass is relatively brittle, due to the small size of the chip in this application, it is not affected during the chip production and subsequent use. In addition, glass has the characteristics of low interference to electromagnetic waves and good high-voltage resistance (tens of thousands of volts), making it a microelectronic device with broad application prospects.

[0226] The stacked chip provided by the present application is not limited to inductive stacked chips or capacitive stacked chips. This application takes inductors (coils) or capacitors (plates) as examples to describe how the manufacturing method of the stacked chip provided by the present application improves the production efficiency of the stacked chip. The stacked chip has at least two independent chips, which can be three or four or more, forming a 3D stacked chip. In this application, a substrate is formed with only one specification of circuit unit, and then the multiple substrates to be stacked are first bonded together as a whole board. After bonding, the upper and lower multiple substrates are cut and packaged together, which greatly saves time and manpower, and the procedure is simpler than the previous method.

[0227] This document is described with reference to various exemplary embodiments. However, those skilled in the art will recognize that changes and modifications may be made to the exemplary embodiments without departing from the scope of this document. For example, the various operational steps and components used to perform the operational steps may be implemented in different ways (e.g., one or more steps may be deleted, modified, or incorporated into other steps) depending on the specific application or considering any number of cost functions associated with the operation of the system.

[0228] In addition, in this application, "electrically connected" includes the situation where components are connected together through an element having some electrical function. The electrical connection can be a direct connection or an indirect connection through a third or more electronic components.

[0229] In this application, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0230] In this application, "A and B are arranged in the same layer" means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A.

[0231] Although the principles of this invention have been shown in various embodiments, many modifications of structure, arrangement, proportion, elements, materials and components that are particularly suitable for specific environments and operational requirements can be used without departing from the principles and scope of this invention. The above modifications and other changes or amendments are intended to be included within the scope of this invention.

[0232] The foregoing detailed description has been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of this disclosure. Therefore, the present disclosure will be considered in an illustrative rather than a restrictive sense, and all such modifications will be included within its scope. Similarly, the advantages, other advantages and solutions to the problems of the various embodiments have been described above. However, the benefits, advantages, solutions to the problems and any elements that can produce these, or make them more specific, should not be interpreted as critical, required or necessary. The term "comprising" and any other variants used in this article are all non-exclusive inclusions, so that a process, method, article or device that includes a list of elements includes not only these elements, but also other elements that are not explicitly listed or do not belong to the process, method, system, article or device. In addition, the term "coupled" and any other variants used in this article refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections and / or any other connections.

[0233] Those skilled in the art will recognize that many changes can be made to the details of the above embodiments without departing from the basic principles of the invention. Therefore, the scope of the present invention should be determined solely by the claims.

Claims

1. A method for manufacturing a stacked chip, characterized in that: include: Providing a first substrate, wherein a plurality of first circuit units are formed on the first substrate, wherein the first circuit units include a first circuit and a first pad of the first circuit; Providing a second substrate, wherein a plurality of second circuit units and a plurality of relief portions are formed on the second substrate; The first substrate and the second substrate are stacked to form a stacked assembly, wherein one second circuit unit is corresponding to one first circuit unit, one recess is corresponding to at least one first pad, and the first pad is not covered by the second substrate through the recess; The stacked assembly is sliced ​​to obtain a plurality of stacked chips, wherein one stacked chip includes one first circuit unit, one second circuit unit and the first bonding pad.

2. The manufacturing method according to claim 1, wherein The relief portion includes a plurality of through holes, The step of forming a plurality of second circuit units and a plurality of relief portions on the second substrate includes: forming the plurality of through holes on the second substrate, each of the through holes being used to allow a first pad to be positioned so that the first pad is not covered by the second substrate; A plurality of second circuit units are formed on the second substrate.

3. The manufacturing method according to claim 1, wherein: Multiple first circuit units are arranged in an array, multiple first solder pads are arranged in an array, the making way portion includes multiple strip holes, the strip holes are located between two adjacent second circuit units, and each of the strip holes is used to make way for multiple first solder pads so that the first solder pads are not covered by the second substrate.

4. The manufacturing method according to claim 1, wherein: The first substrate and the second substrate are stacked to form a stacked assembly, comprising: forming a connection layer on the first substrate; stacking the second substrate on the first substrate; wherein the second substrate is aligned with the first substrate, and one second circuit unit is aligned with one first circuit unit; The second substrate is fixed on the first substrate through the connection layer.

5. The manufacturing method according to claim 2, wherein: The second circuit unit includes a second conductive coil; The method of forming a plurality of second circuit units on the second substrate includes: forming a first conductive layer on the second substrate, and patterning the first conductive layer to form a plurality of connecting lines; forming an insulating layer covering the connecting wire on the second substrate; forming a plurality of first openings on the insulating layer, each first opening exposing one end of the connecting wire; A second conductive layer is formed on the insulating layer, and the second conductive layer is also filled in the first opening to connect with the connecting Wiring electrical connections; The second conductive layer is patterned to form a plurality of second conductive coils and a plurality of second pads. Each second conductive coil includes an inner end and an outer end. The inner end is connected to the connecting line through the first opening, and the outer end is connected to the second pad.

6. The manufacturing method according to claim 5, wherein: The step of forming the plurality of through holes on the second substrate further includes: forming a conductor at the through holes, the second circuit unit including a plurality of conductive elements, wherein the conductor is formed in the same process as at least one of the plurality of conductive elements.

7. The manufacturing method according to claim 6, wherein the step of forming the plurality of through holes on the second substrate further comprises: forming a conductor at the through hole; The step of forming a plurality of second circuit units on the second substrate further includes: The first conductive layer also covers the through hole. After the first conductive layer is patterned, the first conductive layer forms the conductor at the position of the through hole, and the conductor at least partially fills the through hole. The second conductive layer also covers the conductor. After the second conductive layer is patterned, the second conductive layer forms a bridge pad at the position of the conductor. The bridge pad is stacked on the conductor and connected to the first pad through the conductor.

8. The manufacturing method according to claim 6, wherein: Before the step of stacking the first substrate and the second substrate to form a stacked assembly, the method further includes: Coating a conductive adhesive layer on the area of ​​the first pad of the first substrate; An insulating adhesive layer is coated on a side of the second substrate away from the second circuit unit, wherein the insulating adhesive layer does not cover the area of ​​the through hole, the insulating adhesive layer is used to combine the first substrate and the second substrate after the first substrate and the second substrate are stacked, and the conductive adhesive layer is used to electrically connect the first pad and the conductor after the first substrate and the second substrate are stacked.

9. The manufacturing method according to claim 8, wherein: Coating a conductive adhesive layer on the region of the first pad of the first substrate includes: Providing a first preset template, wherein the first preset template has a plurality of first hollow areas; Placing the first preset template on the first substrate, wherein the plurality of first hollow areas correspond to and expose the plurality of first pads; Under the cover of the first preset module, a conductive adhesive layer is coated on the exposed first pad.

10. A method for manufacturing a stacked chip, characterized in that: include: Providing a first substrate, wherein a plurality of first circuit units are formed on the first substrate, wherein the first circuit units include a first circuit and a first pad of the first circuit; Providing a second substrate, wherein a plurality of paving portions are formed on the second substrate, and the paving portions are through holes; The first substrate and the second substrate are stacked, one of the clearance portions is provided corresponding to at least one of the first pads, and the first pads are not covered by the second substrate through the clearance portion; A plurality of second circuit units and a plurality of conductors are formed on the second substrate, wherein one second circuit unit is provided corresponding to one first circuit unit, and the conductors are filled in the recessed portions and electrically connected to the first pads to obtain a stacked assembly; The stacked assembly is sliced ​​to obtain a plurality of stacked chips, wherein one stacked chip includes one first circuit unit, one second circuit unit and the first bonding pad.

11. A stacked chip, characterized in that: include: A first chip includes a first substrate having a first surface and a first circuit unit formed on the first surface, wherein the first circuit unit includes a first conductive coil having two ends and two first pads, wherein the two first pads are respectively connected to or located at the two ends; A second chip is provided on the first chip, the second chip including a second substrate having a second surface and a second conductive coil formed on the second surface, the second substrate having a relief portion, the relief portion being provided corresponding to the two first pads so that the first pads are connected to an external circuit through the relief portion; wherein, The projection of the second conductive coil on the first surface covers at least 80% of the projection of the first conductive coil on the first surface.

12. The stacked chip according to claim 11, wherein: The first substrate is a glass substrate or a composite substrate containing glass material. And / or, the second substrate is a glass substrate or a composite substrate containing glass material.

13. The stacked chip according to claim 11, wherein: The second chip includes the second substrate and a second circuit unit formed on the second surface. The second circuit unit includes the second conductive coil having two end portions and two second pads. The two second pads are respectively connected to the two end portions or located at the two end portions.

14. The stacked chip according to claim 11, wherein: The evacuation portion is a evacuation hole filled with a conductor. A bridging pad is provided on a side of the evacuation hole different from the first substrate. The bridging pad is electrically connected to the first pad through the conductor and is used to connect to an external circuit.

15. The stacked chip according to claim 14, wherein: The conductor or the bridge pad is provided in the same layer as at least a portion of the second circuit unit.

16. A stacked chip, characterized in that: include: A first chip includes a first substrate having a first surface and a first circuit unit formed on the first surface, wherein the first circuit unit includes a first plate and a first pad connected to the first plate; A second chip is provided on the first chip, the second chip includes a second substrate having a second surface and a second circuit unit formed on the second surface, the second circuit unit includes a second electrode plate, the second substrate has a relief portion, the relief portion is provided on the second substrate corresponding to the first pad, so that the projection of the second chip on the first surface does not cover the first pad, wherein, The projection of the second electrode plate on the first surface covers the projection of the first electrode plate on the first surface.

17. A laminated substrate, characterized in that: include: A first substrate assembly includes a first substrate and a plurality of first circuit units formed on the first substrate, wherein the first circuit units include a first circuit and a first pad of the first circuit; The second substrate assembly includes the second substrate, and a plurality of second circuit units and a plurality of relief portions formed on the second substrate, wherein: The first substrate and the second substrate are stacked to form a stacked assembly, one second circuit unit is arranged corresponding to one first circuit unit, one said yield portion is arranged corresponding to at least one first solder pad, the first solder pad is used to connect to the external circuit through the yield portion, the stacked substrate is used to be cut into multiple stacked chips, and one said stacked chip includes one first circuit unit, one second circuit unit and the first solder pad.

18. A stacked chip, characterized in that: The method is manufactured by any one of claims 1 to 10.

19. A method for manufacturing a circuit unit, characterized in that: include: forming a first conductive layer on a substrate, and patterning the first conductive layer to form a plurality of connecting lines; forming a first insulating layer on the substrate, wherein the first insulating layer at least covers the connecting wire; forming a plurality of first openings on the first insulating layer, each first opening exposing one end of the connecting wire; forming a second conductive layer on the first insulating layer, wherein the second conductive layer is further filled in the first opening to be connected to the connecting line; The second conductive layer is patterned to form a plurality of circuits and pads connected to the circuits, at least one pad is disposed corresponding to one of the first openings, and one circuit unit includes one circuit and the corresponding pad.

20. The manufacturing method according to claim 19, wherein: Also includes: forming a second insulating layer covering the circuit and the pad; A second opening is formed on the second insulating layer, and the second opening is used to connect the pad to an external circuit.

21. The manufacturing method according to claim 19, wherein: The circuit is a conductive coil, each conductive coil includes an inner end and an outer end, and each conductive coil is connected to the two pads respectively, and the inner end is connected to the connecting line through the first opening; Alternatively, the circuit is a conductive electrode plate, and at least one of the pads is connected to one of the conductive electrode plates.

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