Chip grading method and related apparatus

Abstract

The embodiments of the present disclosure relate to the technical field of integrated circuits. Disclosed are a chip grading method and a related apparatus, which can improve the accuracy of chip grading and effectively reduce resource waste. The method comprises: determining a mapping relationship between a first parameter, a second parameter and a third parameter of a chip sample, so as to obtain a grading assistance function, wherein the first parameter and the second parameter are obtained by performing wafer testing on the chip sample, and the third parameter is obtained by performing post-packaging testing on the chip sample; and acquiring a parameter value of the first parameter and a parameter value of the second parameter of a chip to be graded, and grading said chip on the basis of the parameter value of the first parameter, the parameter value of the second parameter, the grading assistance function, and grading description information of said chip, wherein the grading description information is used for describing correlations between different grades of the chip and the value range of the third parameter. The present disclosure is applicable to grading various chips.

Description

Chip grading method and related device

[0001] This application claims priority to Chinese Patent Application No. 202410389320.4 filed on April 1, 2024, the entire text of which is incorporated herein by reference as a part of this application. Technical Field

[0002] The present disclosure relates to a chip grading method and related devices. Background Art

[0003] A wafer is a thin, circular sheet of semiconductor material that forms the basis of integrated circuit manufacturing. Thousands of integrated circuit dies can be manufactured on each wafer, and each is diced into individual dies. These individual dies can then be packaged to create corresponding chip products.

[0004] Due to inevitable process deviations during semiconductor processing, the performance of different chips may vary. In practice, chips are generally divided into different grades based on certain performance parameters (such as the maximum operating frequency of the die, static leakage current, etc.) measured before chip packaging (such as wafer testing). Then, chips of different grades are packaged using packaging specifications that match the grade (such as packaging process, packaging materials, etc.). For example, for chips with better performance and higher grades, higher-level packaging specifications can be used to provide better support and protection for the chips with excellent performance, while lower-level packaging specifications can be used for chips with poorer performance and lower grades, thereby effectively reducing costs while meeting application requirements.

[0005] However, because the chip hasn't yet been packaged, many of its operating parameters are unknown. Consequently, it's common for some operating parameters to exceed specified ranges (e.g., power consumption) when the chip is packaged and running. This can cause a mismatch between the chip's packaging specifications and its actual performance, leading to wasted resources. For example, a chip with good performance but high power consumption might use a higher-specification package, wasting packaging resources. Alternatively, a chip with good performance and low power consumption might use a lower-specification package, degrading the chip and creating waste.

[0006] Regarding the problem of how to accurately classify chips to reduce resource waste, there is no effective solution in the relevant technology.

[0007] Summary of the Invention

[0008] In view of this, embodiments of the present disclosure provide a chip grading method and related apparatus, which can improve the accuracy of chip grading and effectively reduce resource waste.

[0009] In a first aspect, an embodiment of the present disclosure provides a chip grading method, comprising: determining a mapping relationship between a first parameter, a second parameter, and a third parameter of a chip sample to obtain a grading auxiliary function, wherein the first parameter and the second parameter are obtained by performing wafer testing on the chip sample, and the third parameter is obtained by performing post-packaging testing on the chip sample; obtaining parameter values ​​of the first parameter and the second parameter of the chip to be graded, and grading the chip to be graded according to the parameter value of the first parameter, the parameter value of the second parameter, the grading auxiliary function, and grading description information of the chip to be graded, wherein the grading description information is used to describe the correspondence between different grades of chips and the value range of the third parameter.

[0010] In one embodiment, determining the mapping relationship between the first parameter, the second parameter, and the third parameter of the chip sample to obtain the hierarchical auxiliary function includes: determining the adaptive dynamic voltage regulation mechanism of the chip sample, the adaptive dynamic voltage regulation mechanism being used to represent the functional relationship between the operating voltage of the chip and the operating frequency of the chip; based on the adaptive dynamic voltage regulation mechanism, determining the mapping relationship between the first parameter, the second parameter, and the third parameter to obtain the hierarchical auxiliary function.

[0011] In one embodiment, determining the adaptive dynamic voltage regulation mechanism of the chip sample includes: performing wafer testing on the chip sample to obtain multiple operating frequency values ​​and power supply monitoring (PSM) values ​​at each operating frequency value; performing curve fitting on the multiple operating frequency values ​​and the PSM values ​​at each operating frequency value to obtain a first curve; performing post-package operation testing on the chip sample to obtain multiple operating voltage values ​​and the PSM values ​​at each operating voltage value; performing curve fitting on the multiple operating voltage values ​​and the PSM values ​​at each operating voltage value to obtain a second curve; and determining the adaptive dynamic voltage regulation mechanism of the chip sample based on the first curve and the second curve.

[0012] In one embodiment, determining the adaptive dynamic voltage regulation mechanism of the chip sample includes: performing an operation test on the chip sample after packaging, recording multiple operating voltage values ​​of the chip sample, and the operating frequency value corresponding to each of the operating voltage values; and obtaining the adaptive dynamic voltage regulation mechanism of the chip sample by curve fitting the operating voltage values ​​and the operating frequency values.

[0013] In one embodiment, the mapping relationship between the first parameter, the second parameter and the third parameter is determined based on the adaptive dynamic voltage regulation mechanism to obtain the hierarchical auxiliary function, including: respectively determining the first relationship between the first parameter and the operating frequency, the second relationship between the dynamic power consumption of the chip sample and the operating voltage, the third relationship between the second parameter and the static power consumption of the chip sample, and the fourth relationship between the third parameter and the dynamic power consumption and the static power consumption; substituting the first relationship and the second relationship into the adaptive dynamic voltage regulation mechanism to obtain the fifth relationship between the first parameter and the dynamic power consumption; determining the mapping relationship between the first parameter, the second parameter and the third parameter according to the fifth relationship, the third relationship and the fourth relationship to obtain the hierarchical auxiliary function.

[0014] In one embodiment, the obtaining of the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded, and grading the chip to be graded according to the parameter value of the first parameter, the parameter value of the second parameter, the grading auxiliary function and the grading description information of the chip to be graded includes: obtaining the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded, and determining the predicted value of the third parameter of the chip to be graded according to the parameter value of the first parameter, the parameter value of the second parameter and the grading auxiliary function; determining the value interval to which the predicted value of the third parameter belongs according to the grading description information, and obtaining a target interval; and grading the chip to be graded according to the level corresponding to the target interval.

[0015] In one embodiment, the hierarchical description information is also used to describe the correspondence between different levels of the chip and the value range of the first parameter; determining the value range to which the predicted value of the third parameter belongs based on the hierarchical description information, and obtaining the target range includes: determining the first value range to which the predicted value of the third parameter belongs, and the second value range to which the parameter value of the first parameter belongs based on the hierarchical description information; determining the target range based on the common part of the first value range and the second value range.

[0016] In one embodiment, the obtaining of the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded, and grading the chip to be graded according to the parameter value of the first parameter, the parameter value of the second parameter, the grading auxiliary function and the grading description information of the chip to be graded includes: substituting the interval boundary values ​​of each value interval of the third parameter into the grading auxiliary function respectively to obtain the boundary correspondence between the interval boundary values ​​of the value interval of the first parameter and the interval boundary values ​​of the value interval of the second parameter; establishing a coordinate system with the first parameter and the second parameter as two mutually perpendicular coordinate axes, plotting the boundary correspondence in the coordinate system, and obtaining a corresponding boundary constraint curve; obtaining the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded, and determining the position of a target point in the coordinate system according to the parameter value of the first parameter and the parameter value of the second parameter, wherein the target point is a two-dimensional coordinate with the parameter value of the first parameter and the parameter value of the second parameter; grading the chip to be graded according to the relative position relationship between the target point and the boundary constraint curve in the coordinate system.

[0017] In one embodiment, the grading description information is also used to describe the correspondence between different grades of the chip and the value range of the first parameter; establishing a coordinate system with the first parameter and the second parameter as two mutually perpendicular coordinate axes, drawing the boundary correspondence in the coordinate system, and obtaining a corresponding boundary constraint curve includes: establishing a coordinate system with the first parameter and the second parameter as two mutually perpendicular coordinate axes, drawing the boundary correspondence in the coordinate system, obtaining a first constraint curve, and drawing the interval boundary of the value range of the first parameter in the coordinate system, obtaining a second constraint curve; grading the chip to be graded according to the relative position relationship between the target point and the boundary constraint curve in the coordinate system includes: grading the chip to be graded according to the relative position relationship between the target point and the first constraint curve and the second constraint curve in the coordinate system.

[0018] In one embodiment, there is at least one type of the first parameter, at least one type of the second parameter, and at least one type of the third parameter, and each of the third parameters corresponds to one of the first parameters and one of the second parameters.

[0019] In one embodiment, the third parameter includes the total core power consumption of the chip to be classified; the second parameter includes static leakage current; the first parameter includes any one of the following: capacitive load, operating voltage, operating frequency; or, the third parameter includes the total core power consumption of the chip to be classified; the second parameter includes operating voltage; the first parameter includes any one of the following: capacitive load, operating frequency; or, the third parameter includes the dynamic power consumption of the chip to be classified; the first parameter and the second parameter respectively include any one of the following: capacitive load, operating voltage, operating frequency; the first parameter is different from the second parameter.

[0020] In the second aspect, an embodiment of the present disclosure also provides a chip grading device, including: a determination unit, used to determine the mapping relationship between the first parameter, the second parameter and the third parameter of the chip sample, and obtain a grading auxiliary function, wherein the first parameter and the second parameter are obtained by performing wafer testing on the chip sample, and the third parameter is obtained by performing post-packaging testing on the chip sample; a grading unit, used to obtain the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded, and grade the chip to be graded according to the parameter value of the first parameter, the parameter value of the second parameter, the grading auxiliary function and the grading description information of the chip to be graded, wherein the grading description information is used to describe the correspondence between different grades of chips and the value range of the third parameter.

[0021] In one embodiment, the determination unit includes: a first determination module, used to determine the adaptive dynamic voltage regulation mechanism of the chip sample, wherein the adaptive dynamic voltage regulation mechanism is used to represent the functional relationship between the operating voltage of the chip and the operating frequency of the chip; a second determination module, used to determine the mapping relationship between the first parameter, the second parameter and the third parameter based on the adaptive dynamic voltage regulation mechanism, and obtain the hierarchical auxiliary function.

[0022] In one embodiment, the first determination module is specifically used to: perform wafer testing on the chip sample to obtain multiple operating frequency values ​​and PSM values ​​at each operating frequency value; perform curve fitting on the multiple operating frequency values ​​and the PSM values ​​at each operating frequency value to obtain a first curve; perform post-package operation testing on the chip sample to obtain multiple operating voltage values ​​and the PSM values ​​at each operating voltage value; perform curve fitting on the multiple operating voltage values ​​and the PSM values ​​at each operating voltage value to obtain a second curve; and determine the adaptive dynamic voltage regulation mechanism of the chip sample based on the first curve and the second curve.

[0023] In one embodiment, the first determination module is specifically used to: perform an operation test on the chip sample after packaging, record multiple operating voltage values ​​of the chip sample, and the operating frequency value corresponding to each of the operating voltage values; and obtain an adaptive dynamic voltage regulation mechanism of the chip sample by curve fitting the operating voltage values ​​and the operating frequency values.

[0024] In one embodiment, the second determination module includes: a first determination submodule, used to respectively determine the first relationship between the first parameter and the operating frequency, the second relationship between the dynamic power consumption of the chip sample and the operating voltage, the third relationship between the second parameter and the static power consumption of the chip sample, and the fourth relationship between the third parameter and the dynamic power consumption and the static power consumption; a substitution submodule, used to substitute the first relationship and the second relationship into the adaptive dynamic voltage regulation mechanism to obtain a fifth relationship between the first parameter and the dynamic power consumption; a second determination submodule, used to determine the mapping relationship between the first parameter, the second parameter, and the third parameter based on the fifth relationship, the third relationship, and the fourth relationship to obtain the hierarchical auxiliary function.

[0025] In one embodiment, the grading unit includes: a third determination module, used to obtain the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded, and determine the predicted value of the third parameter of the chip to be graded based on the parameter value of the first parameter, the parameter value of the second parameter and the grading auxiliary function; a fourth determination module, used to determine the value interval to which the predicted value of the third parameter belongs based on the grading description information, and obtain the target interval; a first grading module, used to grade the chip to be graded according to the level corresponding to the target interval.

[0026] In one embodiment, the hierarchical description information is also used to describe the correspondence between different levels of the chip and the value range of the first parameter; the fourth determination module is specifically used to: determine the first value range to which the predicted value of the third parameter belongs, and the second value range to which the parameter value of the first parameter belongs based on the hierarchical description information; determine the target range based on the common part of the first value range and the second value range.

[0027] In one embodiment, the grading unit includes: a substitution module for substituting the interval boundary values ​​of each value interval of the third parameter into the grading auxiliary function respectively to obtain the boundary correspondence between the interval boundary values ​​of the value interval of the first parameter and the interval boundary values ​​of the value interval of the second parameter; an establishment module for establishing a coordinate system with the first parameter and the second parameter as two mutually perpendicular coordinate axes, plotting the boundary correspondence in the coordinate system, and obtaining a corresponding boundary constraint curve; a fifth determination module for obtaining the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded, and determining the position of the target point in the coordinate system according to the parameter value of the first parameter and the parameter value of the second parameter, wherein the target point is a two-dimensional coordinate with the parameter value of the first parameter and the parameter value of the second parameter; a second grading module for grading the chip to be graded according to the relative position relationship between the target point and the boundary constraint curve in the coordinate system.

[0028] In one embodiment, the grading description information is also used to describe the correspondence between different grades of the chip and the value range of the first parameter; the establishment module is specifically used to: establish a coordinate system with the first parameter and the second parameter as two mutually perpendicular coordinate axes, draw the boundary correspondence in the coordinate system to obtain a first constraint curve, and draw the interval boundary of the value range of the first parameter in the coordinate system to obtain a second constraint curve; the second grading module is specifically used to: grade the chip to be graded according to the relative position relationship between the target point and the first constraint curve and the second constraint curve in the coordinate system.

[0029] In one embodiment, there is at least one type of the first parameter, at least one type of the second parameter, and at least one type of the third parameter, and each of the third parameters corresponds to one of the first parameters and one of the second parameters.

[0030] In one embodiment, the third parameter includes the total core power consumption of the chip to be classified; the second parameter includes static leakage current; the first parameter includes any one of the following: capacitive load, operating voltage, operating frequency; or, the third parameter includes the total core power consumption of the chip to be classified; the second parameter includes operating voltage; the first parameter includes any one of the following: capacitive load, operating frequency; or, the third parameter includes the dynamic power consumption of the chip to be classified; the first parameter and the second parameter respectively include any one of the following: capacitive load, operating voltage, operating frequency; the first parameter is different from the second parameter.

[0031] In a third aspect, an embodiment of the present disclosure further provides an electronic device, comprising: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to various circuits or devices of the above-mentioned electronic device; the memory for storing executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the chip grading method provided in any embodiment of the present disclosure.

[0032] In a fourth aspect, an embodiment of the present disclosure further provides a computer-readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement the chip grading method provided in any embodiment of the present disclosure.

[0033] The chip grading method and related device provided by the embodiments of the present disclosure can determine the mapping relationship between the first parameter, the second parameter and the third parameter of the chip sample, obtain the grading auxiliary function, obtain the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded, and grade the chip to be graded according to the parameter value of the first parameter, the parameter value of the second parameter, the grading auxiliary function and the grading description information of the chip to be graded. Since the grading description information of the chip to be graded is used to describe the correspondence between the different grades of the chip and the value range of the third parameter, the grade division of the chip is closely related to the third parameter. Since the grading auxiliary function can establish a connection between the first parameter, the second parameter and the third parameter of the chip to be graded, through the grading auxiliary function, it is possible to establish a connection between the parameter value of the first parameter, the parameter value of the second parameter and the grading description information of the chip to be graded, so that the first parameter and the second parameter of the chip to be graded can be used to grade the chip to be graded. Since the first parameter and the second parameter are obtained by wafer testing of the chip sample, and the third parameter is obtained by post-packaging testing of the chip sample, it is possible to estimate the performance of the chip to be graded in the post-packaging test during the wafer testing stage of the chip to be graded and grade it accordingly, thereby greatly reducing the situation where the test results of the chip post-packaging test do not match the chip grade. Therefore, it can effectively improve the accuracy of chip grading and greatly reduce resource waste. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0035] FIG1 is a flow chart of a chip classification method provided by an embodiment of the present disclosure;

[0036] FIG2 is a schematic diagram of a curve fitting of frequency parameters and PSM values ​​in an embodiment of the present disclosure;

[0037] FIG3 is a schematic diagram of a curve fitting of PSM values ​​and chip voltage parameters in an embodiment of the present disclosure;

[0038] FIG4 is a schematic diagram of a curve fitting of frequency parameters and chip voltage parameters in an embodiment of the present disclosure;

[0039] FIG5 is a schematic diagram of a curve fitting of chip voltage parameters and dynamic power consumption in an embodiment of the present disclosure;

[0040] FIG6 is a schematic diagram of a curve fitting of chip frequency parameters and dynamic power consumption in an embodiment of the present disclosure;

[0041] FIG7 is a schematic diagram of a curve fitting of a chip static current parameter and static power consumption in an embodiment of the present disclosure;

[0042] FIG8 is a schematic diagram of a curve fitting of frequency parameters and chip voltage parameters in an embodiment of the present disclosure;

[0043] FIG9 is a schematic diagram of chip level division in an embodiment of the present disclosure;

[0044] FIG10 is another schematic diagram of chip level division in an embodiment of the present disclosure;

[0045] FIG11 is a schematic diagram of chip classification;

[0046] FIG12 is a schematic diagram comparing the chip level division effect in the embodiment of the present disclosure with the chip level division effect in FIG11 ;

[0047] FIG13 is a detailed flow chart of a chip classification method provided in an embodiment of the present disclosure;

[0048] FIG14 is a schematic structural diagram of a chip grading device provided in an embodiment of the present disclosure;

[0049] FIG15 is a schematic structural diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0051] It should be clear that the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0052] In a first aspect, embodiments of the present disclosure provide a chip grading method, which can improve the accuracy of chip grading and effectively reduce resource waste.

[0053] As shown in FIG1 , an embodiment of the present disclosure provides a chip grading method, including:

[0054] S11, determining a mapping relationship between a first parameter, a second parameter, and a third parameter of a chip sample to obtain a hierarchical auxiliary function, wherein the first parameter and the second parameter are obtained by performing wafer testing on the chip sample, and the third parameter is obtained by performing post-packaging testing on the chip sample;

[0055] In an embodiment of the present disclosure, a chip sample may refer to a chip obtained by wafer testing and packaging. The chip sample may be wafer tested (CP test, Chip Probing) before packaging to obtain corresponding wafer test data. Furthermore, according to the needs of chip grading, one or more of the wafer test data may be selected as the first parameter, and one or more wafer test data different from the first parameter may be selected as the second parameter. For example, in one embodiment of the present disclosure, the wafer test data may include the main frequency, turbo frequency, maximum operating frequency, static leakage current, capacitive load, etc. of the chip, the first parameter may include the main frequency, and the second parameter may include the static leakage current, etc.

[0056] After wafer testing, chip samples can be packaged and further tested after packaging, such as through FT testing (pre-shipment testing), to obtain corresponding test data. Furthermore, based on the needs of chip grading, one or more data points can be selected from the post-packaging test data as a third parameter. In one embodiment of the present disclosure, the third parameter may include, for example, total core power consumption, dynamic power consumption, and other power-related parameters of the chip.

[0057] In an embodiment of the present disclosure, after obtaining the first parameter, the second parameter and the third parameter of the chip sample, the mapping relationship between the first parameter, the second parameter and the third parameter can be obtained based on statistics and data analysis of a large number of chip samples, that is, a hierarchical auxiliary function. In order to make the obtained hierarchical auxiliary function more accurately characterize the mapping relationship between the first parameter, the second parameter and the third parameter, in one embodiment of the present disclosure, chips from multiple batches and multiple process angles under the same process conditions can be selected as chip samples. Since chip samples produced under different process conditions may have large differences, in another embodiment of the present disclosure, the mapping relationship between the first parameter, the second parameter and the third parameter can also be determined for chip samples produced under different process conditions, and the corresponding hierarchical auxiliary function for each process condition can be obtained. Of course, when the chip samples obtained under different process conditions are not much different, the same hierarchical auxiliary function can also be established for chip samples produced under multiple different process conditions. The embodiments of the present disclosure are not limited to this.

[0058] It should be noted that in this step, the mapping relationship between the first parameter, the second parameter and the third parameter of the chip sample can be obtained by testing and processing the chip sample, or can be provided based on the historical test data of the chip, for example, provided by the manufacturer based on the historical test data of the chip.

[0059] S12, obtaining the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded, and grading the chip to be graded according to the parameter value of the first parameter, the parameter value of the second parameter, the grading auxiliary function and the grading description information of the chip to be graded, wherein the grading description information is used to describe the correspondence between different grades of the chip and the value range of the third parameter.

[0060] The chip to be graded may refer to a bare chip (or die) that has completed the semiconductor manufacturing process of the chip but has not yet been packaged and needs to be graded, so that it can be packaged using the corresponding packaging process according to the chip grading result. In one embodiment of the present disclosure, the chip to be graded may have the same structure as the chip sample and be processed based on the same process. Since it has not yet been packaged, the chip to be graded can be wafer tested by testing equipment such as a probe station, but it is not yet possible to perform post-package operation testing. In other words, for the chip to be graded, the parameter value of the first parameter and the parameter value of the second parameter can be obtained through wafer testing, but since the third parameter needs to be packaged before it can be tested, the third packaging parameter of the chip to be graded cannot be obtained through testing.

[0061] In embodiments of the present disclosure, a grading auxiliary function can establish a mapping relationship between a first parameter, a second parameter, and a third parameter using a chip sample. Because the chip to be graded and the chip sample have the same structure and are manufactured using the same process, the mapping relationship between the first parameter, the second parameter, and the third parameter in the grading auxiliary function can also be applied to the chip to be graded.

[0062] Specifically, the classification of the chips to be classified can be based on certain classification rules, and the classification description information can be used to describe the classification rules of the chips. In one example, the classification description information can be used to describe the correspondence between the different levels of the chips and the value range of the third parameter. For example, for chips at level 1, the value range of the third parameter is [a1, a2); for chips at level 2, the value range of the third parameter is [a2, a3); for chips at level 3, the value range of the third parameter is [a3, a4); and so on.

[0063] The chip grading method provided by the embodiment of the present disclosure can determine the mapping relationship between the first parameter, the second parameter and the third parameter of the chip sample, obtain the grading auxiliary function, obtain the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded, and grade the chip to be graded according to the parameter value of the first parameter, the parameter value of the second parameter, the grading auxiliary function and the grading description information of the chip to be graded. Since the grading description information of the chip to be graded is used to describe the correspondence between the different grades of the chip and the value range of the third parameter, the grade division of the chip is closely related to the third parameter. Since the grading auxiliary function can establish a connection between the first parameter, the second parameter and the third parameter of the chip to be graded, through the grading auxiliary function, it is possible to establish a connection between the parameter value of the first parameter, the parameter value of the second parameter and the grading description information of the chip to be graded, so that the first parameter and the second parameter of the chip to be graded can be used to grade the chip to be graded. Since the first parameter and the second parameter are obtained by wafer testing of the chip sample, and the third parameter is obtained by post-packaging testing of the chip sample, it is possible to estimate the performance of the chip to be graded in the post-packaging test during the wafer testing stage of the chip to be graded and grade it accordingly, thereby greatly reducing the situation where the test results of the chip post-packaging test do not match the chip grade. Therefore, it can effectively improve the accuracy of chip grading and greatly reduce resource waste.

[0064] Specifically, in an embodiment of the present disclosure, the relationships between voltage, current, power consumption, frequency, etc. during chip operation are very complex. To this end, a portion of chips can be selected from a large number of chips as chip samples. Wafer testing and post-package operation testing can be performed first. These complex relationships can be fitted using the test data of the chip samples, thereby achieving modeling of a hierarchical auxiliary function. For example, some chips can dynamically adjust the chip's operating voltage, thereby changing the chip's operating frequency. In order to characterize the changing relationship between the operating frequency and the operating voltage in the hierarchical auxiliary function, in one embodiment of the present disclosure, step S11 determines the mapping relationship between the first parameter, the second parameter, and the third parameter of the chip sample. Obtaining the hierarchical auxiliary function can specifically include: determining an adaptive dynamic voltage regulation mechanism for the chip sample, the adaptive dynamic voltage regulation mechanism being used to represent the functional relationship between the chip's operating voltage and the chip's operating frequency; and determining the mapping relationship between the first parameter, the second parameter, and the third parameter based on the adaptive dynamic voltage regulation mechanism to obtain the hierarchical auxiliary function. In this way, the hierarchical auxiliary function can reflect the changing relationship between the chip's operating frequency and the operating voltage, thereby more accurately and objectively characterizing the mapping relationship between the first parameter, the second parameter, and the third parameter.

[0065] In specific implementation, in one example, determining the adaptive dynamic voltage regulation mechanism of the chip sample may include: performing wafer testing on the chip sample to obtain multiple operating frequency values ​​and PSM values ​​at each operating frequency value; performing curve fitting on the multiple operating frequency values ​​and the PSM values ​​at each operating frequency value to obtain a first curve; performing post-package operation testing on the chip sample to obtain multiple operating voltage values ​​and the PSM values ​​at each operating voltage value; performing curve fitting on the multiple operating voltage values ​​and the PSM values ​​at each operating voltage value to obtain a second curve; and determining the adaptive dynamic voltage regulation mechanism of the chip sample based on the first curve and the second curve.

[0066] Among them, the PSM circuit is a circuit in the chip used for power supply regulation. It can adjust the output power of the power supply by controlling whether the switch tube works within a cycle. Different output powers correspond to different PSM values. In the embodiment of the present disclosure, on the one hand, the PSM values ​​at different operating frequencies can be recorded respectively, and the corresponding relationship between the operating frequency and PSM can be fitted into a first curve. On the other hand, the operating voltages corresponding to different PSM values ​​can be recorded respectively, and the corresponding relationship between the operating voltage and PSM can be fitted into a second curve. Then, using the PSM value as a bridge, combining the first curve and the second curve, the mapping relationship between the operating frequency and the operating voltage is obtained, that is, the adaptive dynamic voltage regulation mechanism of the chip sample is obtained.

[0067] In this embodiment, the adaptive dynamic voltage regulation mechanism of the chip sample is obtained by using the PSM value as a bridge, but the embodiments of the present disclosure are not limited thereto. In other embodiments of the present disclosure, the adaptive dynamic voltage regulation mechanism can also be obtained by other means. For example, in another embodiment of the present disclosure, determining the adaptive dynamic voltage regulation mechanism of the chip sample may include: performing a post-package operation test on the chip sample, recording multiple operating voltage values ​​of the chip sample, and the operating frequency values ​​corresponding to each of the operating voltage values; and obtaining the adaptive dynamic voltage regulation mechanism of the chip sample by curve fitting the operating voltage values ​​and the operating frequency values. In other words, the operating voltage values ​​and the operating frequency values ​​can also be directly curve fitted to obtain the adaptive dynamic voltage regulation mechanism of the chip sample.

[0068] After obtaining the adaptive dynamic voltage regulation mechanism, the mapping relationship between the first parameter, the second parameter, and the third parameter can be determined based on the adaptive dynamic voltage regulation mechanism to obtain a hierarchical auxiliary function. Specifically, in one embodiment of the present disclosure, based on the adaptive dynamic voltage regulation mechanism, determining the mapping relationship between the first parameter, the second parameter, and the third parameter to obtain the hierarchical auxiliary function may include:

[0069] respectively determining a first relationship between the first parameter and the operating frequency, a second relationship between the dynamic power consumption of the chip sample and the operating voltage, a third relationship between the second parameter and the static power consumption of the chip sample, and a fourth relationship between the third parameter and the dynamic power consumption and the static power consumption;

[0070] Substituting the first relationship and the second relationship into the adaptive dynamic voltage regulation mechanism to obtain a fifth relationship between the first parameter and the dynamic power consumption;

[0071] According to the fifth relationship, the third relationship and the fourth relationship, a mapping relationship among the first parameter, the second parameter and the third parameter is determined to obtain the hierarchical auxiliary function.

[0072] In the embodiment of the present disclosure, since the adaptive dynamic voltage regulation mechanism involves the correspondence between the operating voltage and the operating frequency of the chip sample, when determining the mapping relationship between the first parameter, the second parameter and the third parameter based on the adaptive dynamic voltage regulation mechanism, the first parameter, the second parameter and the third parameter are also related to the operating voltage and the operating frequency of the chip sample, that is, the first parameter, the second parameter and the third parameter are linked through the connection between the operating voltage and the operating frequency.

[0073] Specifically, a first relationship exists between the first parameter and the operating frequency. For example, the first parameter may be the operating frequency, or the first parameter may be a preset multiple of the operating frequency, or there may be another functional relationship between the first parameter and the operating frequency. Because a second relationship exists between dynamic power consumption and operating voltage, and the operating voltage and operating frequency are linked via the adaptive dynamic voltage regulation mechanism, substituting the first and second relationships into the adaptive dynamic voltage regulation mechanism yields a fifth relationship between the first parameter and dynamic power consumption.

[0074] There is a third relationship between the second parameter and the static power consumption of the chip sample. For example, the second parameter can be static leakage current, and the third relationship can be the relationship between static leakage current and static power consumption. The third parameter is related to the dynamic power consumption and static power consumption of the chip. In one example, the third parameter can be the total core power consumption of the chip sample, and the fourth relationship between the third parameter and the dynamic power consumption and static power consumption can be total core power consumption = dynamic power consumption + static power consumption. Substituting the above fifth relationship and the third relationship into the fourth relationship respectively, the relationship between the total core power consumption (corresponding to the third parameter) and the operating frequency (corresponding to the first parameter) and the static leakage current (corresponding to the second parameter) can be obtained, that is, the hierarchical auxiliary function is obtained.

[0075] For example, in one embodiment of the present disclosure, the first parameter may be the frequency parameter of the chip (such as the main frequency or turbo frequency), the second parameter may be the static current parameter of the chip (such as the static leakage current), and the third parameter may be the total core power consumption of the chip. In order to obtain a hierarchical auxiliary function, modeling can be performed from three aspects: modeling between frequency parameters and dynamic power consumption, modeling between static current parameters and static power consumption, and modeling between total core power consumption and dynamic power consumption and static power consumption. These are explained below respectively.

[0076] Modeling between frequency parameters and dynamic power consumption:

[0077] As shown in Figure 2, by testing and fitting data on a large number of chip samples, it can be obtained that the frequency parameter (Freq) and the PSM test value fitting curve satisfy the relationship: PSM=a1*Freq^2+b1*Freq+c1 (1)

[0078] Among them, a1, b1, and c1 are all real numbers.

[0079] As shown in Figure 3, by testing and fitting data on a large number of chip samples, it can be obtained that the PSM test value and the chip voltage parameter (DieVoltage) fitting curve satisfy the relationship: DieVoltage=a2*PSM^2+b2*PSM+c2 (2)

[0080] Among them, a2, b2, and c2 are all real numbers.

[0081] Substituting formula (1) into formula (2), as shown in Figure 4, we can obtain that the frequency parameter Freq and the voltage parameter DieVoltage satisfy: DieVoltage=a3*Freq^4+b3*Freq^3+c3*Freq^2+d3*Freq+e3 (3)

[0082] Among them, a3, b3, c3, d3, and e3 are all real numbers.

[0083] As shown in FIG5 , the chip voltage parameter DieVoltage is fitted with the dynamic power consumption parameter Dynamic_Power to obtain: Dynamic_Power=a4*DieVoltage^3+b4*DieVoltage^2 (4)

[0084] Among them, a4 and b4 are both real numbers.

[0085] As shown in Figure 6, by substituting formula (3) into formula (4), we can obtain the relationship between the frequency parameter Freq and the dynamic power consumption Dynamic_Power, which satisfies: Dynamic_Power=f*(a5*x^4+b5*x^3+c5*x^2+d5*x+e5)^3+g*(a5*x^4+b5*x^3+c5*x^2+d5*x+e5)^2 (5)

[0086] Where x=Freq, and a5, b5, c5, d5, and e5 are all real numbers.

[0087] Modeling between static current parameter Sidd and static power consumption:

[0088] As shown in FIG7 , by testing and data fitting a large number of chip samples, the static current parameter Sidd and the static power consumption Static_Power satisfy the following relationship: Static_Power=a6*Sidd+b6 (6)

[0089] Among them, a6 and b6 are both real numbers.

[0090] Modeling between the core total power consumption Total_Power and the dynamic power consumption Dynamic_Power and static power consumption Static_Power:

[0091] By adding equations (5) and (6), we can get the relationship between the total power consumption of the chip core Total_Power (i.e., the third parameter) and the frequency parameter (i.e., the first parameter) and the static power parameter (i.e., the second parameter): Total_Power=Dynamic_Power+Static_Power=f*(a5*x^4+b5*x^3+c5*x^2+d5*x+e5)^3+g*(a5*x^4+b5* x^3+c5*x^2+d5*x+e5)^2+a6*y+b6 (7)

[0092] Where x = Freq, y = Sidd

[0093] Then, formula (7) is the hierarchical auxiliary function.

[0094] After obtaining the grading auxiliary function, the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded can be obtained in step S12, and the chip to be graded can be graded according to the parameter value of the first parameter, the parameter value of the second parameter, the grading auxiliary function and the grading description information of the chip to be graded.

[0095] Optionally, in one embodiment, obtaining the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded, and grading the chip to be graded according to the parameter value of the first parameter, the parameter value of the second parameter, the grading auxiliary function and the grading description information of the chip to be graded may specifically include: obtaining the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded, and determining the predicted value of the third parameter of the chip to be graded according to the parameter value of the first parameter, the parameter value of the second parameter and the grading auxiliary function; determining the value range to which the predicted value of the third parameter belongs according to the grading description information, and obtaining the target range; and grading the chip to be graded according to the level corresponding to the target range.

[0096] In this embodiment, the grading auxiliary function can be used to estimate the value of the third parameter corresponding to the first parameter and the second parameter to obtain a predicted value of the third parameter, and then detect which value range of the third parameter in the grading description information the predicted value falls into to obtain a target range, and then determine the grade of the chip to be graded according to the grade corresponding to the target range. For example, in one example, the first parameter of the chip to be graded is 3GHz, and the second parameter is 0.1 microamperes. The predicted value of the third parameter of the chip to be graded obtained according to the grading auxiliary function is 15 watts. It is known that in the grading description information, the value range of the third parameter corresponding to grade 1 is 0 to 10 watts, the value range of the third parameter corresponding to grade 2 is 10 to 20 watts, and the value range of the third parameter corresponding to grade 3 is 20 to 35 watts. Since 15 watts is between 10 watts and 20 watts, that is, it falls into the value range of the third parameter corresponding to grade 2, the chip to be graded can be classified into grade 2.

[0097] In this embodiment, the hierarchical description information is used to describe the correspondence between the different levels of the chip and the value range of the third parameter, but the embodiments of the present disclosure are not limited to this. The hierarchical description information may also include other information required for grading, thereby providing a more refined grading of the chip. For example, in one embodiment of the present disclosure, the hierarchical description information may also be used to describe the correspondence between the different levels of the chip and the value range of the first parameter; based on this, according to the hierarchical description information, the value range to which the predicted value of the third parameter belongs is determined, and obtaining the target range may specifically include: according to the hierarchical description information, determining the first value range to which the predicted value of the third parameter belongs, and the second value range to which the parameter value of the first parameter belongs; and determining the target range based on the common part of the first value range and the second value range.

[0098] Specifically, although all chips to be graded have the same structure and are manufactured using the same process, due to the inevitable process non-uniformity in semiconductor manufacturing, parameters such as performance and power consumption may vary from chip to chip. Generally, under the same applied voltage conditions, chips with higher frequency parameters can be assigned to higher levels, such as Level 1, and chips with lower frequency parameters can be assigned to lower levels, such as Level 3 or Level 4.

[0099] In the embodiments of the present disclosure, there is an adaptive dynamic voltage regulation mechanism between the frequency parameters and voltage parameters of the chip. As shown in FIG8 , for a chip with good performance (such as the chip represented by the point in the lower right corner of FIG8 ), a smaller voltage can be applied to achieve a higher frequency, while for a chip with poor performance (such as the chip represented by the point in the upper left corner of FIG8 ), even if a larger voltage is applied, a very high frequency cannot be achieved. Therefore, the frequency value range corresponding to the chip of each level can be determined based on the voltage value range specified for the chip of that level. For example, for a chip of level 2, a minimum voltage of 1.1V is required, and the corresponding frequency is 4GHz. For a chip of level 3, a minimum voltage of 1.5V is required, and the corresponding frequency is 3.5GHz, etc.

[0100] Continuing with the example where the first parameter is 3 GHz and the predicted value of the third parameter is 15 watts, if in the grading description information, the value range of the third parameter corresponding to level 1 is 0 to 10 watts, and the value range of the first parameter corresponding to level 1 is 3.2 GHz to 3.5 GHz, the value range of the third parameter corresponding to level 2 is 10 to 20 watts, and the value range of the first parameter corresponding to level 2 is 3.2 GHz to 3.5 GHz, the value range of the third parameter corresponding to level 3 is 0 to 10 watts, and the value range of the first parameter corresponding to level 3 is 2.5 GHz to 3.2 GHz, the value range of the third parameter corresponding to level 4 is 10 to 20 watts, and the value range of the first parameter corresponding to level 4 is 2.5 GHz to 3.2 GHz, then since the first parameter of the chip to be graded is 3 GHz and the predicted value of the third parameter is 15 watts, the common part of the value ranges of the first and third parameters falls into the interval corresponding to level 4, then it can be determined that the chip to be graded can be classified into level 4.

[0101] Furthermore, in addition to estimating the predicted value of the third parameter using the grading auxiliary function, in the embodiments of the present disclosure, the chips to be graded may also be graded in other ways. For example, in one embodiment, the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded are obtained, and according to the parameter value of the first parameter, the parameter value of the second parameter, the grading auxiliary function and the grading description information of the chip to be graded, grading the chip to be graded may specifically include: substituting the interval boundary values ​​of each value interval of the third parameter into the grading auxiliary function respectively to obtain the boundary correspondence between the interval boundary values ​​of the value interval of the first parameter and the interval boundary values ​​of the value interval of the second parameter; establishing a coordinate system with the first parameter and the second parameter as two mutually perpendicular coordinate axes, plotting the boundary correspondence in the coordinate system, and obtaining a corresponding boundary constraint curve; obtaining the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded, and determining the position of the target point in the coordinate system according to the parameter value of the first parameter and the parameter value of the second parameter, wherein the target point is a two-dimensional coordinate with the parameter value of the first parameter and the parameter value of the second parameter; grading the chip to be graded according to the relative position relationship between the target point and the boundary constraint curve in the coordinate system.

[0102] For example, as shown in FIG9 , in one example, the first parameter is the frequency parameter (e.g., main frequency) of the chip to be classified, the second parameter is the static leakage current of the chip to be classified, and the third parameter is the total core power consumption of the chip. Then, a coordinate system can be established with the first parameter as the horizontal axis and the second parameter as the vertical axis. The interval boundaries of each value interval of the third parameter in the classification description information are substituted into the classification auxiliary function. For example, the value interval of the third parameter corresponding to level 2 is 10 to 25 watts. Then, 10 and 25 watts can be substituted into formula (7) respectively to obtain the boundary correspondence between the interval boundary value of the value interval of the first parameter corresponding to level 1 and the interval boundary value of the value interval of the second parameter. The boundary correspondence is plotted in the aforementioned coordinate system to obtain the corresponding boundary constraint curve, i.e., the curves spec1 (corresponding to the third parameter of 10 watts) and spec2 (corresponding to the third parameter of 25 watts) in FIG9 . In this way, the target point can be determined based on the first and second parameters of the chip to be classified, and the relative position relationship with the boundary constraint curve can be used to classify the chip to be classified. For example, if the target point determined by the first parameter and the second parameter of the chip to be graded is between spec1 and spec2, the chip to be graded may be determined to be grade 2.

[0103] In this embodiment, the hierarchical description information is used to describe the correspondence between different levels of the chip and the value range of the third parameter, but the embodiments of the present disclosure are not limited thereto. The hierarchical description information may also include other information required for grading, thereby providing a more refined grading of the chip. For example, in one embodiment of the present disclosure, the hierarchical description information is also used to describe the correspondence between different levels of the chip and the value range of the first parameter; based on this, a coordinate system is established with the first parameter and the second parameter as two mutually perpendicular coordinate axes, and the boundary correspondence is plotted in the coordinate system to obtain the corresponding boundary constraint curve. Specifically, the following may be included: establishing a coordinate system with the first parameter and the second parameter as two mutually perpendicular coordinate axes, plotting the boundary correspondence in the coordinate system to obtain a first constraint curve, and plotting the interval boundary of the value range of the first parameter in the coordinate system to obtain a second constraint curve; accordingly, grading the chip to be graded according to the relative positional relationship between the target point and the boundary constraint curve in the coordinate system may specifically include: grading the chip to be graded according to the relative positional relationship between the target point and the first constraint curve and the second constraint curve in the coordinate system.

[0104] Illustratively, the first constraint curve and the second constraint curve may be as shown in FIG. 10 .

[0105] Figure 11 is a schematic diagram of chip grading according to a chip grading method, and Figure 12 is a schematic diagram comparing the chip grading effect in an embodiment of the present disclosure with the chip grading effect in Figure 11. As can be seen from the comparison, compared with the chip grading method in Figure 11, the chip grading method provided by the embodiment of the present disclosure primarily performs chip grading based on a boundary constraint curve. The boundary constraint curve is not a simple straight line, but rather a curve with rich fluctuations formed based on the mapping relationship between the first parameter, the second parameter, and the third parameter, as well as the constraints on the value range of the third function in the grading description information.

[0106] As shown in Figure 12, curve G1 represents a grading line formed by the static current parameter in the chip grading method of Figure 11. According to the chip grading method of Figure 11, when grading chips based on data obtained during wafer testing, the chips represented by points below curve G1 are classified as Level 2 due to their lower static current parameters, while the chips represented by points above curve G1 are classified as Level 3 due to their higher static current parameters. However, if the chips are packaged and tested post-package, it will be found that the power consumption of some chips originally classified as Level 2 (such as the chips in the area shown in part 1) exceeds the power consumption limit of Level 2. Therefore, these chips should actually be classified as Level 3. Similarly, the actual power consumption of some chips classified as Level 3 (such as the chips in the area shown in part 2) is relatively low, below the power consumption limit of Level 2. Therefore, these chips should originally be classified as Level 2. It can be seen that chip grading based on curve G1 is not very accurate, and some chips may be incorrectly graded, resulting in resource waste.

[0107] In contrast to curve G1, curve G2 represents three boundary constraint curves, spec1, spec2, and spec3, formed according to the chip grading method provided in accordance with an embodiment of the present disclosure. The chips represented by the points below spec2 of curve G2 can be classified into level 2, while the chips represented by the points above spec2 of curve G2 can be classified into level 3. It can be seen that when grading chips according to curve G2, the chips in the area shown in part1 can be accurately classified into level 3, thereby effectively reducing the degradation of chips due to excessive power consumption after packaging testing and reducing the waste of packaging resources, while the chips in the area shown in part2 can be accurately classified into level 2, thereby returning the chips originally classified into level 3 to level 2, thereby making better use of chip resources.

[0108] In the aforementioned embodiment, the chip frequency parameter is used as the first parameter, the chip quiescent current parameter is used as the second parameter, and the chip core total power consumption is used as the third parameter to classify the chips to be classified, but the embodiments of the present disclosure are not limited thereto. In other embodiments of the present disclosure, the first parameter may also be other chip parameters, and the first parameter may be of one or more types, the second parameter may also be other chip parameters, and the second parameter may also be of one or more types, and the third parameter may also be other chip parameters, and the third parameter may also be of one or more types, wherein each third parameter may correspond to one of the first parameters and one of the second parameters.

[0109] In one embodiment of the present disclosure, when there are multiple first parameters, multiple second parameters, and multiple third parameters, the chip grading method of any of the aforementioned embodiments can be used to grade the chips using each set of first parameters, second parameters, and third parameters, and then the final grading result can be determined by combining the grading results of each set. For example, if the grading results determined by each set of parameters are the same, then that grading result can be determined as the final grading result. If the grading results determined by each set of parameters are different, then the grading result with the highest hit rate can be used as the final grading result. If the hit rates of the grading results are the same, then, according to a preset rule, one grading result can be selected from each grading result as the final grading result.

[0110] Since the selection of the first parameter, the second parameter and the third parameter is very flexible, there are also various chip grading methods, and the chips can be accurately and flexibly graded according to different needs.

[0111] For example, in one example, the third parameter may include the total core power consumption of the chip to be classified; the second parameter includes static leakage current; and the first parameter includes any one of the following: capacitive load, operating voltage, and operating frequency.

[0112] In another example, the third parameter may include the total core power consumption of the chip to be graded; the second parameter includes the operating voltage; and the first parameter includes any one of the following: capacitive load, operating frequency.

[0113] In another example, the third parameter may include the dynamic power consumption of the chip to be graded; the first parameter and the second parameter respectively include any one of the following: capacitive load, operating voltage, operating frequency; the first parameter is different from the second parameter.

[0114] The chip grading method provided by the embodiments of the present disclosure is described in detail below through specific examples.

[0115] As shown in FIG13 , the chip classification method provided by the embodiment of the present disclosure may include:

[0116] S201 , performing an operation test on a chip sample after packaging, and recording a plurality of operating voltage values ​​of the chip sample and an operating frequency value corresponding to each of the operating voltage values.

[0117] S202 : Obtain an adaptive dynamic voltage regulation mechanism of the chip sample by performing curve fitting on the operating voltage value and the operating frequency value.

[0118] S203. Determine respectively a first relationship between the first parameter and the operating frequency, a second relationship between the dynamic power consumption of the chip sample and the operating voltage, a third relationship between the second parameter and the static power consumption of the chip sample, and a fourth relationship between the third parameter and the dynamic power consumption and the static power consumption.

[0119] S204 : Substitute the first relationship and the second relationship into the adaptive dynamic voltage regulation mechanism to obtain a fifth relationship between the first parameter and the dynamic power consumption.

[0120] S205: Determine a mapping relationship among the first parameter, the second parameter, and the third parameter according to the fifth relationship, the third relationship, and the fourth relationship, and obtain the hierarchical auxiliary function.

[0121] S206 , obtaining parameter values ​​of a first parameter and a second parameter of the chip to be graded, and determining a predicted value of a third parameter of the chip to be graded based on the parameter value of the first parameter, the parameter value of the second parameter and the grading auxiliary function.

[0122] S207: Determine the value interval to which the predicted value of the third parameter belongs according to the hierarchical description information, and obtain a target interval.

[0123] S208: Classify the chips to be classified according to the level corresponding to the target interval.

[0124] In a second aspect, embodiments of the present disclosure provide a chip grading device that can improve the accuracy of chip grading and effectively reduce resource waste.

[0125] As shown in FIG14 , the chip grading device provided by the embodiment of the present disclosure may include:

[0126] a determining unit 31, configured to determine a mapping relationship between a first parameter, a second parameter, and a third parameter of a chip sample to obtain a hierarchical auxiliary function, wherein the first parameter and the second parameter are obtained by performing wafer testing on the chip sample, and the third parameter is obtained by performing post-packaging testing on the chip sample;

[0127] The grading unit 32 is used to obtain the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded, and grade the chip to be graded according to the parameter value of the first parameter, the parameter value of the second parameter, the grading auxiliary function and the grading description information of the chip to be graded, wherein the grading description information is used to describe the correspondence between different grades of the chip and the value range of the third parameter.

[0128] The chip grading device provided by the embodiment of the present disclosure is capable of determining the mapping relationship between the first parameter, the second parameter and the third parameter of the chip sample, obtaining a grading auxiliary function, obtaining the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded, and grading the chip to be graded according to the parameter value of the first parameter, the parameter value of the second parameter, the grading auxiliary function and the grading description information of the chip to be graded. Since the grading description information of the chip to be graded is used to describe the correspondence between the different grades of the chip and the value range of the third parameter, the grade division of the chip is closely related to the third parameter. Since the grading auxiliary function can establish a connection between the first parameter, the second parameter and the third parameter of the chip to be graded, the grading auxiliary function can establish a connection between the parameter value of the first parameter, the parameter value of the second parameter and the grading description information of the chip to be graded, so that the first parameter and the second parameter of the chip to be graded can be used to grade the chip to be graded. Since the first parameter and the second parameter are obtained by wafer testing of the chip sample, and the third parameter is obtained by post-packaging testing of the chip sample, it is possible to estimate the performance of the chip to be graded in the post-packaging test during the wafer testing stage of the chip to be graded and grade it accordingly, thereby greatly reducing the situation where the test results of the chip post-packaging test do not match the chip grade. Therefore, it can effectively improve the accuracy of chip grading and greatly reduce resource waste.

[0129] In one embodiment, the determining unit 31 may include:

[0130] A first determining module is configured to determine an adaptive dynamic voltage regulation mechanism for the chip sample, where the adaptive dynamic voltage regulation mechanism is used to represent a functional relationship between an operating voltage of the chip and an operating frequency of the chip;

[0131] The second determining module is configured to determine a mapping relationship among the first parameter, the second parameter and the third parameter based on the adaptive dynamic voltage regulation mechanism, and obtain the hierarchical auxiliary function.

[0132] In one embodiment, the first determining module may be specifically configured to:

[0133] Performing wafer testing on the chip sample to obtain a plurality of operating frequency values ​​and a PSM value at each of the operating frequency values;

[0134] Performing curve fitting on a plurality of operating frequency values ​​and the PSM values ​​at each of the operating frequency values ​​to obtain a first curve;

[0135] Performing a post-package operation test on the chip sample to obtain a plurality of operating voltage values ​​and a PSM value at each of the operating voltage values;

[0136] Performing curve fitting on a plurality of operating voltage values ​​and the PSM values ​​at each of the operating voltage values ​​to obtain a second curve;

[0137] An adaptive dynamic voltage regulation mechanism of the chip sample is determined according to the first curve and the second curve.

[0138] In one embodiment, the first determining module is specifically configured to:

[0139] Performing an operation test on the chip sample after packaging, and recording a plurality of operating voltage values ​​of the chip sample and an operating frequency value corresponding to each of the operating voltage values;

[0140] By performing curve fitting on the operating voltage value and the operating frequency value, an adaptive dynamic voltage regulation mechanism of the chip sample is obtained.

[0141] In one embodiment, the second determining module includes:

[0142] a first determining submodule, configured to respectively determine a first relationship between the first parameter and the operating frequency, a second relationship between the dynamic power consumption of the chip sample and the operating voltage, a third relationship between the second parameter and the static power consumption of the chip sample, and a fourth relationship between the third parameter and the dynamic power consumption and the static power consumption;

[0143] a substitution submodule, configured to substitute the first relationship and the second relationship into the adaptive dynamic voltage regulation mechanism to obtain a fifth relationship between the first parameter and the dynamic power consumption;

[0144] The second determining submodule is configured to determine a mapping relationship among the first parameter, the second parameter, and the third parameter according to the fifth relationship, the third relationship, and the fourth relationship, to obtain the hierarchical auxiliary function.

[0145] In one embodiment, the classification unit 32 includes:

[0146] a third determination module, configured to obtain a parameter value of a first parameter and a parameter value of a second parameter of the chip to be classified, and determine a predicted value of a third parameter of the chip to be classified based on the parameter value of the first parameter, the parameter value of the second parameter, and the classification auxiliary function;

[0147] a fourth determining module, configured to determine, based on the hierarchical description information, a value interval to which the predicted value of the third parameter belongs, to obtain a target interval;

[0148] The first grading module is configured to grade the chips to be graded according to the grade corresponding to the target interval.

[0149] In one embodiment, the hierarchical description information is also used to describe the correspondence between different levels of the chip and the value range of the first parameter; the fourth determination module is specifically used to: determine the first value range to which the predicted value of the third parameter belongs, and the second value range to which the parameter value of the first parameter belongs based on the hierarchical description information; determine the target range based on the common part of the first value range and the second value range.

[0150] In one embodiment, the classification unit 32 includes:

[0151] a substitution module, configured to substitute the interval boundary values ​​of each value interval of the third parameter into the hierarchical auxiliary function, respectively, to obtain a boundary correspondence between the interval boundary values ​​of the value interval of the first parameter and the interval boundary values ​​of the value interval of the second parameter;

[0152] An establishment module, configured to establish a coordinate system using the first parameter and the second parameter as two mutually perpendicular coordinate axes, and plot the boundary correspondence in the coordinate system to obtain a corresponding boundary constraint curve;

[0153] a fifth determining module, configured to obtain a parameter value of a first parameter and a parameter value of a second parameter of the chip to be graded, and determine a position of a target point in the coordinate system based on the parameter value of the first parameter and the parameter value of the second parameter, wherein the target point has two-dimensional coordinates based on the parameter value of the first parameter and the parameter value of the second parameter;

[0154] The second grading module is configured to grade the chips to be graded according to the relative positional relationship between the target point and the boundary constraint curve in the coordinate system.

[0155] In one embodiment, the hierarchical description information is further used to describe the correspondence between different levels of the chip and the value range of the first parameter;

[0156] The establishing module is specifically configured to establish a coordinate system using the first parameter and the second parameter as two mutually perpendicular coordinate axes, plot the boundary correspondence in the coordinate system to obtain a first constraint curve, and plot the interval boundary of the value interval of the first parameter in the coordinate system to obtain a second constraint curve;

[0157] The second grading module is specifically configured to grade the chips to be graded according to the relative positional relationship between the target point and the first constraint curve and the second constraint curve in the coordinate system.

[0158] In one embodiment, there is at least one type of the first parameter, at least one type of the second parameter, and at least one type of the third parameter, and each of the third parameters corresponds to one of the first parameters and one of the second parameters.

[0159] In one embodiment, the third parameter includes the total core power consumption of the chip to be classified; the second parameter includes static leakage current; the first parameter includes any one of the following: capacitive load, operating voltage, operating frequency;

[0160] or

[0161] The third parameter includes the total core power consumption of the chip to be classified; the second parameter includes the operating voltage; the first parameter includes any one of the following: capacitive load, operating frequency;

[0162] or

[0163] The third parameter includes the dynamic power consumption of the chip to be graded; the first parameter and the second parameter respectively include any one of the following: capacitive load, operating voltage, operating frequency; the first parameter is different from the second parameter.

[0164] On the third aspect, an embodiment of the present disclosure further provides an electronic device that can improve the accuracy of chip grading and effectively reduce resource waste.

[0165] As shown in Figure 15, the electronic device provided by the embodiment of the present disclosure may include: a shell 51, a processor 52, a memory 53, a circuit board 54 and a power supply circuit 55, wherein the circuit board 54 is placed inside the space enclosed by the shell 51, and the processor 52 and the memory 53 are set on the circuit board 54; the power supply circuit 55 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 53 is used to store executable program code; the processor 52 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 53, so as to execute the chip grading method provided by any of the aforementioned embodiments.

[0166] The specific execution process of the above steps by the processor 52 and the steps further executed by the processor 52 by running the executable program code can be found in the description of the above embodiment and will not be repeated here.

[0167] Fourthly, an embodiment of the present disclosure further provides a computer-readable storage medium, which stores one or more programs. The one or more programs can be executed by one or more processors to implement any chip grading method provided in the aforementioned embodiments, thereby also achieving the corresponding technical effects, which have been described in detail above and will not be repeated here.

[0168] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0169] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0170] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0171] For the convenience of description, the above device is described as being divided into various units / modules based on their functions. Of course, when implementing the present disclosure, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0172] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing related hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above-described method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0173] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A chip grading method, comprising: Determine a mapping relationship between a first parameter, a second parameter, and a third parameter of a chip sample to obtain a hierarchical auxiliary function, wherein the first parameter and the second parameter are obtained by performing wafer testing on the chip sample, and the third parameter is obtained by performing post-packaging testing on the chip sample; Obtain the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded, and grade the chip to be graded according to the parameter value of the first parameter, the parameter value of the second parameter, the grading auxiliary function and the grading description information of the chip to be graded, wherein the grading description information is used to describe the correspondence between different grades of the chip and the value range of the third parameter.

2. The method according to claim 1, wherein Determining the mapping relationship among the first parameter, the second parameter, and the third parameter of the chip sample to obtain a grading auxiliary function includes: Determining an adaptive dynamic voltage regulation mechanism for the chip sample, where the adaptive dynamic voltage regulation mechanism is used to represent a functional relationship between an operating voltage of the chip and an operating frequency of the chip; Based on the adaptive dynamic voltage regulation mechanism, a mapping relationship among the first parameter, the second parameter and the third parameter is determined to obtain the hierarchical auxiliary function.

3. The method according to claim 2, wherein: Determining the adaptive dynamic voltage regulation mechanism of the chip sample includes: Performing wafer testing on the chip sample to obtain a plurality of operating frequency values ​​and a power supply monitoring value at each of the operating frequency values; Performing curve fitting on a plurality of operating frequency values ​​and power supply monitoring values ​​at each of the operating frequency values ​​to obtain a first curve; Performing a post-package operation test on the chip sample to obtain a plurality of operating voltage values ​​and a power supply monitoring value at each of the operating voltage values; Performing curve fitting on a plurality of operating voltage values ​​and the power supply monitoring value at each of the operating voltage values ​​to obtain a second curve; An adaptive dynamic voltage regulation mechanism of the chip sample is determined according to the first curve and the second curve.

4. The method according to claim 2, wherein: Determining the adaptive dynamic voltage regulation mechanism of the chip sample includes: Performing an operation test on the chip sample after packaging, and recording a plurality of operating voltage values ​​of the chip sample and an operating frequency value corresponding to each of the operating voltage values; By performing curve fitting on the operating voltage value and the operating frequency value, an adaptive dynamic voltage regulation mechanism of the chip sample is obtained.

5. The method according to any one of claims 2 to 4, wherein: The determining, based on the adaptive dynamic voltage regulation mechanism, a mapping relationship among the first parameter, the second parameter, and the third parameter to obtain the hierarchical auxiliary function includes: respectively determining a first relationship between the first parameter and the operating frequency, a second relationship between the dynamic power consumption of the chip sample and the operating voltage, a third relationship between the second parameter and the static power consumption of the chip sample, and a fourth relationship between the third parameter and the dynamic power consumption and the static power consumption; Substituting the first relationship and the second relationship into the adaptive dynamic voltage regulation mechanism to obtain a fifth relationship between the first parameter and the dynamic power consumption; According to the fifth relationship, the third relationship and the fourth relationship, a mapping relationship among the first parameter, the second parameter and the third parameter is determined to obtain the hierarchical auxiliary function.

6. The method according to any one of claims 1 to 5, wherein: The obtaining of the parameter value of the first parameter and the parameter value of the second parameter of the chip to be classified, and grading the chip to be classified according to the parameter value of the first parameter, the parameter value of the second parameter, the grading auxiliary function, and the grading description information of the chip to be classified includes: Obtaining a parameter value of a first parameter and a parameter value of a second parameter of the chip to be classified, and determining a predicted value of a third parameter of the chip to be classified based on the parameter value of the first parameter, the parameter value of the second parameter and the classification auxiliary function; Determining, based on the hierarchical description information, a value interval to which the predicted value of the third parameter belongs, and obtaining a target interval; The chips to be graded are graded according to the grade corresponding to the target interval.

7. The method according to claim 6, wherein: The hierarchical description information is further used to describe the correspondence between different levels of the chip and the value range of the first parameter; Determining, based on the hierarchical description information, a value interval to which the predicted value of the third parameter belongs, and obtaining a target interval includes: Determine the first value range to which the predicted value of the third parameter belongs according to the hierarchical description information and a second value interval to which the parameter value of the first parameter belongs; The target interval is determined according to a common portion of the first value interval and the second value interval.

8. The method according to any one of claims 1 to 5, wherein: The obtaining of the parameter value of the first parameter and the parameter value of the second parameter of the chip to be classified, and grading the chip to be classified according to the parameter value of the first parameter, the parameter value of the second parameter, the grading auxiliary function, and the grading description information of the chip to be classified includes: Substituting the interval boundary values ​​of each value interval of the third parameter into the hierarchical auxiliary function respectively, to obtain the boundary correspondence between the interval boundary values ​​of the value interval of the first parameter and the interval boundary values ​​of the value interval of the second parameter; Establishing a coordinate system with the first parameter and the second parameter as two mutually perpendicular coordinate axes, plotting the boundary correspondence in the coordinate system to obtain a corresponding boundary constraint curve; Obtaining a parameter value of a first parameter and a parameter value of a second parameter of the chip to be graded, and determining a position of a target point in the coordinate system according to the parameter value of the first parameter and the parameter value of the second parameter, wherein the target point has two-dimensional coordinates based on the parameter value of the first parameter and the parameter value of the second parameter; The chips to be graded are graded according to the relative positional relationship between the target point and the boundary constraint curve in the coordinate system.

9. The method according to claim 8, wherein The hierarchical description information is further used to describe the correspondence between different levels of the chip and the value range of the first parameter; The step of establishing a coordinate system with the first parameter and the second parameter as two mutually perpendicular coordinate axes, and plotting the boundary correspondence in the coordinate system to obtain a corresponding boundary constraint curve includes: Establishing a coordinate system with the first parameter and the second parameter as two mutually perpendicular coordinate axes, plotting the boundary correspondence in the coordinate system to obtain a first constraint curve, and plotting the interval boundary of the value interval of the first parameter in the coordinate system to obtain a second constraint curve; Classifying the chips to be classified according to the relative positional relationship between the target point and the boundary constraint curve in the coordinate system includes: The chips to be graded are graded according to the relative positional relationship between the target point and the first constraint curve and the second constraint curve in the coordinate system.

10. The method according to any one of claims 1 to 9, wherein: There is at least one type of the first parameter, at least one type of the second parameter, and at least one type of the third parameter. Each of the third parameters corresponds to one of the first parameters and one of the second parameters.

11. The method according to any one of claims 1 to 10, wherein: The third parameter includes the total core power consumption of the chip to be classified; the second parameter includes static leakage current; the first parameter includes any one of the following: capacitive load, operating voltage, operating frequency; or The third parameter includes the total core power consumption of the chip to be classified; the second parameter includes the operating voltage; the first parameter includes any one of the following: capacitive load, operating frequency; or The third parameter includes the dynamic power consumption of the chip to be graded; the first parameter and the second parameter respectively include any one of the following: capacitive load, operating voltage, operating frequency; the first parameter is different from the second parameter.

12. A chip grading device, comprising: a determining unit, configured to determine a mapping relationship between a first parameter, a second parameter, and a third parameter of a chip sample to obtain a hierarchical auxiliary function, wherein the first parameter and the second parameter are obtained by performing wafer testing on the chip sample, and the third parameter is obtained by performing post-packaging testing on the chip sample; A grading unit is used to obtain the parameter value of the first parameter and the parameter value of the second parameter of the chip to be graded, and grade the chip to be graded according to the parameter value of the first parameter, the parameter value of the second parameter, the grading auxiliary function and the grading description information of the chip to be graded, wherein the grading description information is used to describe the correspondence between different grades of the chip and the value range of the third parameter.

13. The device according to claim 12, wherein The determining unit includes: A first determining module is configured to determine an adaptive dynamic voltage regulation mechanism for the chip sample, where the adaptive dynamic voltage regulation mechanism is used to represent a functional relationship between an operating voltage of the chip and an operating frequency of the chip; The second determining module is configured to determine a mapping relationship among the first parameter, the second parameter and the third parameter based on the adaptive dynamic voltage regulation mechanism, and obtain the hierarchical auxiliary function.

14. The device according to claim 13, wherein The first determining module is specifically configured to: Performing wafer testing on the chip sample to obtain a plurality of operating frequency values ​​and a power supply monitoring value at each of the operating frequency values; Performing curve fitting on a plurality of operating frequency values ​​and power supply monitoring values ​​at each of the operating frequency values ​​to obtain a first curve; Performing a post-package operation test on the chip sample to obtain a plurality of operating voltage values ​​and a power supply monitoring value at each of the operating voltage values; Performing curve fitting on a plurality of operating voltage values ​​and the power supply monitoring value at each of the operating voltage values ​​to obtain a second curve; An adaptive dynamic voltage regulation mechanism of the chip sample is determined according to the first curve and the second curve.

15. The device according to claim 13, wherein The first determining module is specifically configured to: Performing an operation test on the chip sample after packaging, and recording a plurality of operating voltage values ​​of the chip sample and an operating frequency value corresponding to each of the operating voltage values; By performing curve fitting on the operating voltage value and the operating frequency value, an adaptive dynamic voltage regulation mechanism of the chip sample is obtained.

16. The device according to any one of claims 13 to 15, wherein: The second determining module includes: a first determining submodule, configured to respectively determine a first relationship between the first parameter and the operating frequency, a second relationship between the dynamic power consumption of the chip sample and the operating voltage, a third relationship between the second parameter and the static power consumption of the chip sample, and a fourth relationship between the third parameter and the dynamic power consumption and the static power consumption; a substitution submodule, configured to substitute the first relationship and the second relationship into the adaptive dynamic voltage regulation mechanism to obtain a fifth relationship between the first parameter and the dynamic power consumption; The second determining submodule is configured to determine a mapping relationship among the first parameter, the second parameter, and the third parameter according to the fifth relationship, the third relationship, and the fourth relationship, to obtain the hierarchical auxiliary function.

17. The device according to any one of claims 12 to 16, wherein: The grading unit comprises: a third determination module, configured to obtain a parameter value of a first parameter and a parameter value of a second parameter of the chip to be classified, and determine a predicted value of a third parameter of the chip to be classified based on the parameter value of the first parameter, the parameter value of the second parameter, and the classification auxiliary function; a fourth determining module, configured to determine, based on the hierarchical description information, a value interval to which the predicted value of the third parameter belongs, to obtain a target interval; The first grading module is configured to grade the chips to be graded according to the grade corresponding to the target interval.

18. The device according to claim 17, wherein The hierarchical description information is further used to describe the correspondence between different levels of the chip and the value range of the first parameter; The fourth determining module is specifically configured to: Determining, according to the hierarchical description information, a first value interval to which the predicted value of the third parameter belongs, and a second value interval to which the parameter value of the first parameter belongs; The target interval is determined according to a common portion of the first value interval and the second value interval.

19. The device according to any one of claims 12 to 16, wherein: The grading unit comprises: a substitution module, configured to substitute the interval boundary values ​​of each value interval of the third parameter into the hierarchical auxiliary function, respectively, to obtain a boundary correspondence between the interval boundary values ​​of the value interval of the first parameter and the interval boundary values ​​of the value interval of the second parameter; An establishment module, configured to establish a coordinate system using the first parameter and the second parameter as two mutually perpendicular coordinate axes, and plot the boundary correspondence in the coordinate system to obtain a corresponding boundary constraint curve; a fifth determining module, configured to obtain a parameter value of a first parameter and a parameter value of a second parameter of the chip to be graded, and determine a position of a target point in the coordinate system based on the parameter value of the first parameter and the parameter value of the second parameter, wherein the target point has two-dimensional coordinates based on the parameter value of the first parameter and the parameter value of the second parameter; The second grading module is configured to grade the chips to be graded according to the relative positional relationship between the target point and the boundary constraint curve in the coordinate system.

20. The device according to claim 19, wherein The hierarchical description information is further used to describe the correspondence between different levels of the chip and the value range of the first parameter; The establishment module is specifically used to: Establishing a coordinate system with the first parameter and the second parameter as two mutually perpendicular coordinate axes, plotting the boundary correspondence in the coordinate system to obtain a first constraint curve, and plotting the interval boundary of the value interval of the first parameter in the coordinate system to obtain a second constraint curve; The second grading module is specifically used to: The chips to be graded are graded according to the relative positional relationship between the target point and the first constraint curve and the second constraint curve in the coordinate system.

21. The device according to any one of claims 12 to 20, wherein: There is at least one type of the first parameter, at least one type of the second parameter, and at least one type of the third parameter. Each of the third parameters corresponds to one of the first parameters and one of the second parameters.

22. The device according to any one of claims 12 to 21, wherein: The third parameter includes the total core power consumption of the chip to be classified; the second parameter includes static leakage current; the first parameter includes any one of the following: capacitive load, operating voltage, operating frequency; or The third parameter includes the total core power consumption of the chip to be classified; the second parameter includes the operating voltage; the first parameter includes any one of the following: capacitive load, operating frequency; or The third parameter includes the dynamic power consumption of the chip to be graded; the first parameter and the second parameter respectively include any one of the following: capacitive load, operating voltage, operating frequency; the first parameter is different from the second parameter.

23. An electronic device comprising: A housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, and is used to execute the chip grading method according to any one of the preceding claims 1 to 11.

24. A computer-readable storage medium, wherein: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the chip hierarchical method according to any one of claims 1 to 11.

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