Packaging structure of light-emitting chip and forming method for packaging structure

Abstract

A packaging structure of a light-emitting chip and a forming method for the packaging structure. The packaging structure comprises: a substrate, the substrate comprising a functional region and a non-functional region; a light-emitting diode array, the light-emitting diode array being located on a first surface of the substrate in the functional region, and the light-emitting diode array comprising a plurality of light-emitting diodes arranged in an array; electrode structures located on the first surface of the substrate in the non-functional region; conductive plugs passing through the non-functional region, the conductive plugs being electrically connected to the electrode structures; and first solder balls electrically connected to the conductive plug, the first solder balls being located on a second surface of the non-functional region. The conductive plugs passing through the non-functional region of the substrate and the first solder balls are connected to an external circuit, and compared with the electrode structures being connected to the external circuit by means of bonding wires, the area occupied by bonding wires in a direction parallel to the surface of the substrate is saved, thereby reducing the size of the packaging structure of a light-emitting chip.

Description

Packaging structure of light-emitting chip and forming method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on April 2, 2024, with application number 2024103975416 and invention name “Packaging structure of light-emitting chip and its formation method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to a semiconductor manufacturing process, and in particular to a packaging structure of a light-emitting chip and a forming method thereof. Background Art

[0003] Inorganic micro-pixel light-emitting diodes, also known as micro light-emitting diodes (Micro LEDs or μ-LEDs), are used in self-luminous micro-displays, visible light communications, optogenetics, and other fields. Compared with traditional light-emitting diodes, micro-LEDs have better strain relaxation, better light extraction efficiency, more uniform current diffusion, and higher output performance. Micro-LEDs also have the advantages of improved thermal effects, faster response speed, a wider operating temperature range, higher resolution, a wider color gamut, higher contrast, lower power consumption, and higher current density.

[0004] At present, the micro-LED packaging structure is packaged on an integrated circuit board. The micro-LED array composed of micro-LED units is packaged in the functional area on the front of the integrated circuit board to form a light-emitting area. At the same time, the electrode structure is packaged in the non-functional area on the front of the integrated circuit board to form an input / output port (IO) for transmitting voltage and signals.

[0005] However, the packaging structure of the micro light emitting diode and the micro light emitting diode still have the problem of being large in size.

[0006] Summary of the Invention

[0007] The technical problem solved by the present invention is how to reduce the size of the packaging structure of the light-emitting chip and the size of the light-emitting chip.

[0008] To solve the above technical problems, an embodiment of the present invention provides a packaging structure for a light-emitting chip, comprising: a substrate, the substrate comprising: a functional area and a non-functional area; a light-emitting diode array, the light-emitting diode array being located on the first surface of the substrate in the functional area, the light-emitting diode array comprising a plurality of light-emitting diodes arranged in an array; an electrode structure located on the first surface of the substrate in the non-functional area; a conductive plug penetrating the non-functional area, the conductive plug being electrically connected to the electrode structure; and a first solder ball electrically connected to the conductive plug, the first solder ball being located on the second surface of the non-functional area.

[0009] Optionally, the method further includes: a second solder ball electrically connecting the substrate to an external circuit, wherein the second solder ball is located on the second surface of the functional area.

[0010] Optionally, the distance between the electrode structure and the light-emitting diode array in a direction parallel to the substrate surface is greater than 100 microns.

[0011] Optionally, the height-to-width ratio of the conductive plug is in a range of 3:1 to 10:1.

[0012] Optionally, the method further includes: a wiring layer located on the second surface, wherein the wiring layer includes a dielectric layer and a conductive layer located within the dielectric layer.

[0013] Optionally, the method further includes: a solder pad located on the conductive layer, wherein the solder pad is electrically connected to the first solder ball.

[0014] Optionally, the light emitting diode array is a Micro-LED array.

[0015] Optionally, the material of the substrate includes silicon.

[0016] Correspondingly, the technical solution of the present invention also provides a method for forming a packaging structure of a light-emitting chip, comprising: providing a substrate, the substrate comprising: a functional area and a non-functional area; forming a light-emitting diode array and an electrode structure on a first surface of the substrate, the light-emitting diode array being located on the substrate of the functional area, the light-emitting diode array comprising a plurality of light-emitting diodes arranged in an array, the electrode structure being located on the substrate of the non-functional area; forming a conductive plug penetrating the non-functional area on the second surface of the substrate, the conductive plug being electrically connected to the electrode structure; forming a first solder ball electrically connected to the conductive plug, the first solder ball being located on the second surface of the non-functional area.

[0017] Optionally, the step of forming the conductive plug includes: etching the substrate in a direction from the second surface to the first surface, forming an opening penetrating the substrate in a non-functional area of ​​the substrate, wherein the opening exposes the electrode structure; pre-treating the opening to form a first conductive layer on the surface of the opening; and forming a conductive plug filling the opening in the opening with the first conductive layer formed on the surface.

[0018] Optionally, the step of forming the opening includes: forming a first mask layer on the second surface of the substrate, the first mask layer exposing a portion of the surface of the second surface of the substrate; and etching the substrate using the first mask layer as a mask to form an opening passing through the substrate.

[0019] Optionally, the etching method includes: dry etching and wet etching.

[0020] Optionally, the step of forming the opening further comprises: laser drilling the substrate along the second surface in a direction pointing toward the first surface, thereby forming an opening penetrating the substrate within a non-functional region of the substrate, wherein the opening exposes the electrode structure. Optionally, after forming the conductive plug, the second surface of the substrate is planarized to expose the conductive plug.

[0021] Optionally, the process for forming the first conductive layer includes physical vapor deposition; and the process for forming a conductive plug filling the opening formed with the first conductive layer on the surface includes electroplating.

[0022] Optionally, before forming the first solder balls and after planarizing the second surface of the substrate, the method further includes: forming a wiring layer on the second surface.

[0023] Optionally, the step of forming the wiring layer includes: forming a wiring layer on the second surface of the substrate after planarization, wherein the wiring layer includes a dielectric layer and a second conductive layer located in the dielectric layer.

[0024] Optionally, the method further includes: forming a solder pad on the second conductive layer, wherein the solder pad is electrically connected to the first solder ball.

[0025] Optionally, the step of forming a first solder ball electrically connected to the conductive plug includes: providing a prefabricated solder ball; forming an auxiliary solder material, and fixing the prefabricated solder ball on the solder pad through the auxiliary solder material; performing a reflow process to form the first solder ball; and cleaning the solder pad after the reflow process.

[0026] Optionally, after forming the conductive plug, the method further includes: forming a second solder ball on the second surface of the substrate to electrically connect the substrate to an external circuit, wherein the second solder ball is located in the functional area.

[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0028] In the packaging structure of the light-emitting chip of the technical solution of the present invention, the conductive plug penetrating the non-functional area of ​​the substrate electrically connects the electrode structure located on the first surface with the first solder ball located on the second surface in a direction perpendicular to the substrate surface. The first solder ball is connected to an external circuit. Compared with the connection of the electrode structure to the external circuit through wire bonding, the structure in which the conductive plug and the first solder ball cooperate saves the area occupied in the direction parallel to the substrate surface, thereby reducing the size of the packaging structure of the light-emitting chip.

[0029] An optional embodiment of the present invention further includes a second solder ball electrically connecting the substrate to an external circuit, the second solder ball being located on the second surface of the functional area. The first solder ball connects the electrode structure to the external circuit and the substrate to the external circuit, while the second solder ball connects the substrate to the external circuit. This eliminates the need for a flexible printed circuit board (FPCB), saving wiring space on the FPCB and reducing the size of the light-emitting chip.

[0030] In the method for forming the packaging structure of the light-emitting chip of the technical solution of the present invention, the conductive plug and the first solder ball are formed on the second surface of the substrate, penetrating the non-functional area of ​​the substrate, and the electrode structure located on the first surface is electrically connected to the first solder ball located on the second surface in a direction perpendicular to the surface of the substrate. The first solder ball is connected to an external circuit. Compared with connecting the electrode structure to the external circuit through wire bonding, the conductive plug saves the area occupied by wire bonding in a direction parallel to the surface of the substrate, thereby reducing the size of the packaging structure of the light-emitting chip.

[0031] In an optional embodiment of the present invention, after forming the conductive plug, the method further includes forming a second solder ball on the second surface of the functional region of the substrate, the second solder ball electrically connecting the substrate to an external circuit. The first solder ball connects the electrode structure to the external circuit and the substrate to the external circuit, while the second solder ball connects the substrate to the external circuit. This eliminates the need for a flexible circuit board (FPCB), saving wiring space on the FPCB and reducing the size of the light-emitting chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] 1 to 9 are structural schematic diagrams of various steps of a method for forming a packaging structure of a light-emitting chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] As described in the background art, the packaging structure of the micro light emitting diode and the micro light emitting diode still have the problem of being large in size.

[0034] In an embodiment of a packaging structure of a light-emitting chip, the packaging structure of the light-emitting chip includes: a substrate; a base, the substrate is located on the substrate, the base includes: a functional area and a non-functional area; a light-emitting diode array, the light-emitting diode array is located on the base of the functional area, the light-emitting diode array includes a plurality of light-emitting diodes arranged in an array; an electrode structure located on the base of the non-functional area; bonding wires, the bonding wires electrically connecting the electrode structure and the substrate; and a flexible circuit board, the flexible circuit board electrically connecting the base and the substrate.

[0035] The bonding wires occupy a large space in a direction parallel to the substrate surface, resulting in a larger size of the micro-LED packaging structure. In addition, the flexible circuit board requires a large wiring space, resulting in a larger micro-LED product.

[0036] To solve the above technical problems, the technical solution of the present invention provides a method for forming a packaging structure of a light-emitting chip, comprising: providing a substrate, the substrate comprising: a functional area and a non-functional area; forming a light-emitting diode array and an electrode structure on a first surface of the substrate, the light-emitting diode array being located on the substrate of the functional area, the light-emitting diode array comprising a plurality of light-emitting diodes arranged in an array, and the electrode structure being located on the substrate of the non-functional area; forming a conductive plug penetrating the non-functional area on the second surface of the substrate, the conductive plug being electrically connected to the electrode structure; and forming a first solder ball electrically connected to the conductive plug, the first solder ball being located on the second surface of the non-functional area.

[0037] In the method for forming a light-emitting chip package structure according to the technical solution of the present invention, the conductive plug extending through the non-functional area of ​​the substrate electrically connects the electrode structure on the first surface to the first solder ball on the second surface in a direction perpendicular to the substrate surface. The first solder ball is connected to an external circuit. Compared to connecting the electrode structure to the external circuit via wire bonding, the coordinated structure of the conductive plug and the first solder ball saves area parallel to the substrate surface, thereby reducing the size of the light-emitting chip package structure. The first solder ball connects the electrode structure to the external circuit and the substrate to the external circuit, while the second solder ball connects the substrate to the external circuit. This connection between the substrate and the external circuit can be achieved without the need for a flexible printed circuit board, saving the space required for wiring on the flexible printed circuit board and reducing the size of the light-emitting chip.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] 1 to 9 are schematic structural diagrams of various steps of a method for forming a packaging structure of a light-emitting chip according to an embodiment of the present invention.

[0040] Please refer to FIG. 1 , a substrate 101 is provided, and the substrate 101 includes a functional area I and a non-functional area II.

[0041] The substrate 101 is made of silicon. In some embodiments, the substrate 101 may be a silicon substrate.

[0042] The functional area I provides a structural basis for forming the light emitting diode array 102 , and the non-functional area II provides a structural basis for forming the electrode structure 103 .

[0043] Please refer to Figures 2 and 3. Figure 3 is a cross-sectional view of Figure 2 at position A1A2. A light-emitting diode array 102 and an electrode structure 103 are formed on the first surface of the substrate 101. The light-emitting diode array 102 is located on the substrate 101 of the functional area I. The light-emitting diode array 102 includes a plurality of light-emitting diodes arranged in an array. The electrode structure 103 is located on the substrate 101 of the non-functional area II.

[0044] The distance between the electrode structure 103 and the LED array 102 in a direction parallel to the surface of the substrate 101 is greater than 100 micrometers.

[0045] Specifically, in this embodiment, the light-emitting diode array is a Micro-LED array. In the step of forming the light-emitting diode array 102 and the electrode structure 103 on the first surface of the substrate 101, a Micro-LED wafer process is completed on the substrate 101 to form the light-emitting diode array 102.

[0046] In the LED array 102, the LEDs may be arranged in a format of 320×240, 640×480, 1600×1200, 1920×1080, or 2560×1440. The size of a single LED is between 100 nm and 100 μm. In some embodiments, the size of a single LED is between 150 nm and 15 μm. In some embodiments, the size of a single LED can be less than 10 μm.

[0047] 4 and 5 , a conductive plug 105 penetrating the non-functional area II is formed on the second surface of the substrate 101 . The conductive plug 105 is electrically connected to the electrode structure 103 .

[0048] The conductive plugs 105 are arranged in a one-to-one correspondence with the electrode structures 103. The conductive plugs 105, which extend through the non-functional region II of the substrate 101, are electrically connected to the electrode structures 103. Subsequently formed first solder balls 110 are electrically connected to the conductive plugs 105. The conductive plugs 105 electrically connect the electrode structures 103 on the first surface to the first solder balls 110 on the second surface in a direction perpendicular to the surface of the substrate 101. The first solder balls 110 are connected to external circuits. Compared to connecting the electrode structures 103 to external circuits via wire bonding, the conductive plugs 105 save area occupied by wire bonding in a direction parallel to the surface of the substrate 101, thereby reducing the size of the light-emitting chip package structure.

[0049] After completing the Micro-LED manufacturing process on the substrate 101, a drilling operation is performed on the substrate 101 and the opening 104 formed by the drilling operation is metallized. Specifically, the steps of forming the conductive plug 105 include: as shown in FIG4 , etching the substrate 101 in a direction from the second surface to the first surface, forming an opening 104 penetrating the substrate 101 in the non-functional region II of the substrate 101, the opening 104 exposing the electrode structure 103; as shown in FIG5 , pre-treating the opening 104 to form a first conductive layer (not shown) on the surface of the opening 104; and forming a conductive plug 105 in the opening 104 with the first conductive layer formed on the surface, so as to fill the opening 104.

[0050] In one embodiment, the step of forming the opening 104 includes: forming a first mask layer on the second surface of the substrate 101, wherein the first mask layer exposes a portion of the surface of the second surface of the substrate 101; and etching the substrate 101 using the first mask layer as a mask to form the opening 104 passing through the substrate 101.

[0051] The etching method includes dry etching and wet etching.

[0052] In other embodiments, the step of forming the opening further includes: laser drilling the substrate in a direction from the second surface to the first surface, forming an opening penetrating the substrate in a non-functional area of ​​the substrate, wherein the opening exposes the electrode structure. After the drilling operation is performed on the substrate 101, the formed opening 104 is metallized using through silicon via (TSV) technology. Specifically, the process of forming the first conductive layer includes: physical vapor deposition; the process of forming the conductive plug 105 filling the opening 104 in the opening 104 with the first conductive layer formed on the surface includes: electroplating.

[0053] The conductive plug 105 is made of copper.

[0054] In some embodiments, the depth-to-width ratio of the opening 104 is in a range of 3:1 to 10:1, and the height-to-width ratio of the conductive plug 105 is in a range of 3:1 to 10:1.

[0055] The purpose of pre-treating the opening 104 is that the substrate 101 is made of silicon, which has poor conductivity and cannot be electroplated with copper within the opening 104. Therefore, a first conductive layer is first formed on the surface of the opening 104 to make the portion of the substrate 101 exposed by the opening 104 conductive. Then, a conductive plug 105 is formed within the opening 104 with the first conductive layer formed on the surface, filling the opening 104. This method combines physical vapor deposition with electroplating, saving process time and improving production efficiency compared to forming the conductive plug 105 within the opening 104 by physical vapor deposition.

[0056] After the conductive plug 105 is formed, the second surface of the substrate 101 is planarized to expose the conductive plug 105 .

[0057] The planarization process provides a basis for forming a wiring layer. The planarization process methods include mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing.

[0058] It should be noted that the planarization treatment of the second surface of the substrate 101 can not only expose the conductive plug 105 but also remove excess material on the substrate 101 , such as an excess silicon layer on the silicon substrate.

[0059] Referring to FIG. 6 , after the second surface of the substrate 101 is planarized, the process further includes forming a wiring layer on the second surface.

[0060] The step of forming the wiring layer includes forming a wiring layer on the second surface of the substrate 101 after planarization, wherein the wiring layer includes a dielectric layer 106 and a second conductive layer 107 located in the dielectric layer 106 .

[0061] After forming the second conductive layer 107 , the method further includes forming a pad 108 on the second conductive layer 107 , wherein the pad 108 is electrically connected to a first solder ball 110 formed subsequently. The pad 108 is also electrically connected to a second solder ball 111 formed subsequently.

[0062] Please refer to Figures 7 to 9. Figure 9 is a top view of the second surface of the substrate 101 in Figure 8. Figure 9 only shows the first solder ball 110, the second solder ball 111, and the substrate 101. The first solder ball 110 is formed to be electrically connected to the conductive plug 105. The first solder ball 110 is located on the second surface of the non-functional area II.

[0063] Specifically, in this embodiment, after forming the conductive plug 105 , the method further includes forming a second solder ball 111 on the second surface of the substrate 101 to electrically connect the substrate 101 to an external circuit, wherein the second solder ball 111 is located in the functional area I.

[0064] The first solder balls 110 connect the electrode structure 103 and the substrate 101 to the external circuit, while the second solder balls 111 connect the substrate 101 to the external circuit. This eliminates the need for a flexible printed circuit board (FPCB), saving wiring space on the FPCB and reducing the size of the light-emitting chip.

[0065] In some embodiments, the step of forming a first solder ball 110 electrically connected to the conductive plug 105 and the step of forming a second solder ball 111 on the second surface of the functional area I of the substrate 101 can be performed in the same process, that is, the first solder ball 110 and the second solder ball 111 are formed, the first solder ball 110 is located on the second surface of the substrate 101 in the non-functional area II, and the second solder ball 111 is located on the second surface of the substrate 101 in the functional area I.

[0066] The steps of forming the first solder ball 110 and the second solder ball 111 include: providing a prefabricated solder ball 109 as shown in FIG7 ; forming an auxiliary solder material; fixing the prefabricated solder ball 109 on the solder pad 108 by the auxiliary solder material as shown in FIG8 ; performing a reflow process to form the first solder ball 110 and the second solder ball 111; and cleaning the solder pad 108 after the reflow process.

[0067] The prefabricated solder balls 109 provide a basis for forming the first solder balls 110 and the second solder balls 111. For example, the prefabricated solder balls 109 may be lead-free SAC305 solder balls. The prefabricated solder balls 109 may be placed on the corresponding solder pads 108 using a stencil.

[0068] The auxiliary solder material includes at least one of a flux and a solder paste. The flux is a high-viscosity flux that can perform both bonding and soldering functions, ensuring a clear, non-overflowing auxiliary solder material pattern. The solder paste's material composition matches that of the prefabricated solder balls 109. For example, the solder paste comprises a tin-lead alloy with a weight ratio of 63% tin to 37% lead.

[0069] The step of forming the auxiliary solder material is performed by printing a dedicated ball grid array (BGA) stencil. The thickness and opening size of the stencil used in the step of forming the auxiliary solder material are determined based on the size of the prefabricated solder balls 109 and the spacing between adjacent prefabricated solder balls 109.

[0070] It should be noted that after forming the auxiliary solder material and before performing the reflow process, the step of forming the first solder ball 110 and the second solder ball 111 further includes: performing a quality inspection on the formed auxiliary solder material. If the quality inspection fails, the step of forming the auxiliary solder material must be performed again after cleaning.

[0071] The size of the prefabricated solder ball 109 is adapted to the size of the auxiliary solder material. In some embodiments, when the auxiliary solder material is a high-viscosity solder flux, the size of the prefabricated solder ball 109 is the same as the size of the first solder ball 110 and the second solder ball 111 to be formed; when the auxiliary solder material is solder paste, the size of the prefabricated solder ball 109 is smaller than the size of the first solder ball 110 and the second solder ball 111 to be formed.

[0072] After the auxiliary solder material is formed, the prefabricated solder balls 109 are mounted on the corresponding solder pads 108 through the auxiliary solder material. Specifically, the prefabricated solder balls 109 are mounted using a ball planter: a ball planting template that matches the distribution of the solder pads is provided, the leak size of the ball planting template being slightly larger than the diameter of the prefabricated solder balls 109 (for example, the leak size of the ball planting template is larger than the diameter of the prefabricated solder balls 109 by 0.05 mm to 0.1 mm); the prefabricated solder balls 109 are evenly dispersed on the ball planting template, and the ball planting template is shaken so that one prefabricated solder ball 109 is retained in each leak on the surface of the ball planting template, and the excess prefabricated solder balls are collected in the solder ball collecting groove of the ball planting template; thereafter, the substrate 101 with the auxiliary solder material formed on the second surface is sucked onto the suction nozzle, the formed auxiliary solder material is aligned with the prefabricated solder balls 109, and the prefabricated solder balls 109 are mounted on the corresponding solder pads 108 through the viscosity of the auxiliary solder material.

[0073] The first solder ball 110 is made of tin. The second solder ball 111 is made of tin.

[0074] Afterwards, a reflow process is performed. During the reflow process, the auxiliary solder balls 109 and the auxiliary solder material are heated to form a first solder ball 110 and a second solder ball fixed on the solder pad 108 .

[0075] After the reflow process is completed, the pad 108 is cleaned to make the surface of the pad 108 smooth. The cleaning method includes: using a soldering iron to clean the residual solder on the pad 108 or using a desoldering braid and a flat spatula-shaped soldering iron tip to clean the pad 108.

[0076] The first solder ball 110 and the second solder ball 111 both have a height and are located between the substrate 101 and the external circuit, so that there is a gap between the substrate 101 and the external circuit, which is beneficial to heat dissipation between the substrate 101 and the external circuit.

[0077] Correspondingly, an embodiment of the present invention further provides a packaging structure for a light-emitting chip, please continue to refer to Figure 8, including: a substrate 101, the substrate 101 including: a functional area I and a non-functional area II; a light-emitting diode array 102, the light-emitting diode array 102 is located on the first surface of the substrate 101 in the functional area I, and the light-emitting diode array 102 includes a plurality of light-emitting diodes arranged in an array; an electrode structure 103 is located on the first surface of the substrate 101 in the non-functional area II; a conductive plug 105 passing through the non-functional area II, the conductive plug 105 is electrically connected to the electrode structure 103; a first solder ball 110 electrically connected to the conductive plug 105, and the first solder ball 110 is located on the second surface of the non-functional area II.

[0078] The conductive plug 105, which extends through the non-functional area II of the substrate 101, electrically connects the electrode structure 103 on the first surface to the first solder ball 110 on the second surface, perpendicular to the surface of the substrate 101. The first solder ball 110 is connected to an external circuit. Compared to connecting the electrode structure 103 to the external circuit via wire bonding, the combined structure of the conductive plug 105 and the first solder ball 110 saves area parallel to the surface of the substrate 101, reducing the size of the light-emitting chip package. The first solder ball 110 connects the electrode structure 103 and the substrate 101 to the external circuit, while the second solder ball 111 connects the substrate 101 to the external circuit. This connection between the substrate 101 and the external circuit is achieved without the need for a flexible printed circuit board (FPCB), saving the space required for wiring on the FPCB and reducing the size of the light-emitting chip.

[0079] The packaging structure of the light-emitting chip includes a substrate 101 , and the substrate 101 includes a functional area I and a non-functional area II.

[0080] The substrate 101 is made of silicon. In some embodiments, the substrate 101 may be a silicon substrate.

[0081] The packaging structure of the light-emitting chip includes: a light-emitting diode array 102, wherein the light-emitting diode array 102 is located on the first surface of the substrate 101 of the functional area I, and the light-emitting diode array 102 includes a plurality of light-emitting diodes arranged in an array.

[0082] Specifically, in this embodiment, the light emitting diode array 102 is a Micro-LED array.

[0083] In the LED array 102, the LEDs may be arranged in a format of 320×240, 640×480, 1600×1200, 1920×1080, or 2560×1440. The size of a single LED is between 100 nm and 100 μm. In some embodiments, the size of a single LED is between 150 nm and 15 μm. In some embodiments, the size of a single LED can be less than 10 μm.

[0084] The packaging structure of the light-emitting chip includes: an electrode structure 103 located on the first surface of the substrate 101 in the non-functional area II.

[0085] The distance between the electrode structure 103 and the LED array 102 in a direction parallel to the surface of the substrate 101 is greater than 100 micrometers.

[0086] The packaging structure of the light-emitting chip includes a conductive plug 105 penetrating the non-functional area II, and the conductive plug 105 is electrically connected to the electrode structure 103 .

[0087] The height-to-width ratio of the conductive plug 105 ranges from 3:1 to 10:1. The conductive plug 105 is made of copper.

[0088] The packaging structure of the light emitting chip includes: a first solder ball 110 electrically connected to the conductive plug 105, the first solder ball 110 being located on the second surface of the non-functional area II. The material of the first solder ball 110 includes tin.

[0089] The packaging structure of the light-emitting chip includes a second solder ball 111 electrically connecting the substrate 101 to an external circuit, and the second solder ball 111 is located on the second surface of the functional area I. The material of the second solder ball 111 includes tin.

[0090] The packaging structure of the light-emitting chip includes: a wiring layer located on the second surface, wherein the wiring layer includes a dielectric layer 106 and a conductive layer 107 located within the dielectric layer 106 .

[0091] The packaging structure of the light emitting chip includes a solder pad 108 located on the conductive layer 107 , wherein the solder pad 108 is electrically connected to the first solder ball 110 and the second solder ball 111 .

[0092] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A packaging structure of a light-emitting chip, characterized in that: include: A substrate, the substrate comprising: a functional area and a non-functional area; A light emitting diode array, the light emitting diode array being located on the first surface of the substrate of the functional area, the light emitting diode array comprising a plurality of light emitting diodes arranged in an array; an electrode structure located on the first surface of the substrate in the non-functional area; a conductive plug penetrating the non-functional area, the conductive plug being electrically connected to the electrode structure; A first solder ball electrically connected to the conductive plug, wherein the first solder ball is located on the second surface of the non-functional area.

2. The light emitting chip packaging structure according to claim 1, wherein: Also includes: A second solder ball electrically connects the substrate to an external circuit, wherein the second solder ball is located on the second surface of the functional area.

3. The light emitting chip packaging structure according to claim 1, wherein: The distance between the electrode structure and the light emitting diode array in a direction parallel to the substrate surface is greater than 100 micrometers.

4. The light emitting chip packaging structure according to claim 1, wherein: The height-to-width ratio of the conductive plug is in a range of 3:1 to 10:

1.

5. The light emitting chip packaging structure according to claim 1, wherein: Also includes: A wiring layer located on the second surface includes a dielectric layer and a conductive layer located within the dielectric layer.

6. The light emitting chip packaging structure according to claim 5, wherein: Also includes: A solder pad is located on the conductive layer, and is electrically connected to the first solder ball.

7. The light emitting chip packaging structure according to claim 1, wherein: The light emitting diode array is a Micro-LED array.

8. The light emitting chip packaging structure according to claim 1, wherein: The material of the substrate includes silicon.

9. A method for forming a packaging structure of a light-emitting chip, characterized in that: include: Providing a substrate, the substrate comprising: a functional area and a non-functional area; forming a light-emitting diode array and an electrode structure on the first surface of the substrate, wherein the light-emitting diode array is located on the substrate of the functional area and includes a plurality of light-emitting diodes arranged in an array, and the electrode structure is located on the substrate of the non-functional area; forming a conductive plug penetrating the non-functional area on the second surface of the substrate, wherein the conductive plug is electrically connected to the electrode structure; A first solder ball electrically connected to the conductive plug is formed, and the first solder ball is located on the second surface of the non-functional area.

10. The method for forming a light emitting chip packaging structure according to claim 9, wherein: The steps of forming the conductive plug include: etching the substrate in a direction from the second surface to the first surface, forming an opening penetrating the substrate in a non-functional area of ​​the substrate, wherein the opening exposes the electrode structure; pre-treating the opening to form a first conductive layer on the surface of the opening; and forming a conductive plug filling the opening in the opening with the first conductive layer formed on the surface.

11. The method for forming a light emitting chip packaging structure according to claim 10, wherein: The step of forming the opening includes: forming a first mask layer on the second surface of the substrate, wherein the first mask layer exposes a portion of the surface of the second surface of the substrate; and etching the substrate using the first mask layer as a mask to form an opening penetrating the substrate.

12. The method for forming a light emitting chip package structure according to claim 11, wherein: The etching method includes dry etching and wet etching.

13. The method for forming a light emitting chip package structure according to claim 10, wherein: The step of forming the opening further includes: performing laser drilling on the substrate along a direction from the second surface to the first surface, forming an opening penetrating the substrate in a non-functional area of ​​the substrate, wherein the opening exposes the electrode structure.

14. The method for forming a light emitting chip packaging structure according to claim 10, wherein: After forming the conductive plug, the second surface of the substrate is planarized to expose the conductive plug.

15. The method for forming a light emitting chip packaging structure according to claim 10, wherein: The process of forming the first conductive layer includes physical vapor deposition; and the process of forming a conductive plug filling the opening formed with the first conductive layer on the surface includes electroplating.

16. The method for forming a light emitting chip packaging structure according to claim 14, wherein: Before forming the first solder balls, after performing a planarization process on the second surface of the substrate, the method further includes: forming a wiring layer on the second surface.

17. The method for forming a light emitting chip packaging structure according to claim 16, wherein: The step of forming the wiring layer includes: forming a wiring layer on the second surface of the substrate after planarization, wherein the wiring layer includes a dielectric layer and a second conductive layer located in the dielectric layer.

18. The method for forming a light emitting chip package structure according to claim 17, wherein: Also includes: A solder pad is formed on the second conductive layer, wherein the solder pad is electrically connected to the first solder ball.

19. The method for forming a light emitting chip package structure according to claim 18, wherein: The step of forming a first solder ball electrically connected to the conductive plug includes: providing a prefabricated solder ball; forming an auxiliary solder material, and fixing the prefabricated solder ball on the pad through the auxiliary solder material; performing a reflow process to form the first solder ball; and cleaning the pad after the reflow process.

20. The method for forming a light emitting chip package structure according to claim 9, wherein: After forming the conductive plug, the method further includes forming a second solder ball on the second surface of the substrate to electrically connect the substrate to an external circuit, wherein the second solder ball is located in the functional area.

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