High-speed counter device using phase shift and method thereof

Abstract

The present invention relates to a high-speed counter using phase shift, comprising: a divide-by-2 circuit that generates a frequency-divided-by-2 clock signal from an input clock signal; a phase shifter that receives the frequency-divided-by-2 clock signal generated by the divide-by-2 circuit and generates a clock signal having a phase delayed by 180 degrees; a first counter that operates with the frequency-divided-by-2 clock signal; a second counter that operates with the frequency-divided-by-2 clock signal having a phase delayed by 180 degrees; a logic circuit that, when a target number N is given, operates the first counter if the remainder of N divided by 2 is 0, operates the second counter if the remainder of N divided by 2 is 1, and sets, as a new target number, a number M obtained by dividing the target number by 2 after excluding the least significant bit (LSB) of the target number; and a compare logic circuit that compares an output from either the first counter or the second counter with M and outputs the result.

Description

High-speed counter device and method using phase shift

[0001] The present invention relates to a high-speed counter, and more particularly, to a high-speed counter device and method using phase shift.

[0002] Recent electronic devices increasingly demand both high-speed operation and low power consumption. High-speed operation means faster data processing speeds, while low power consumption focuses on reducing device power consumption and extending battery life.

[0003] Conventional low-power design methods, in particular, limit the switching speed of semiconductor devices, leading to performance degradation. Slower switching speeds reduce data throughput, which in turn reduces processing speed. Furthermore, technologies such as high-performance computing, wireless communications, and high-speed data transmission require high switching speeds, making low-power design methods insufficient for this purpose.

[0004] To address these challenges, a new type of counter design is needed that can simultaneously achieve high-speed operation and low power consumption. The development of a counter that overcomes the limitations of existing low-power processes and can operate without performance degradation even when the operating clock frequency increases is required.

[0005] An object of the present invention is to provide a counter that minimizes power consumption.

[0006] Another object of the present invention is to provide a counter capable of high-speed operation that overcomes the limitation of counters that cannot respond to high input clock frequencies.

[0007] However, the technical task that this embodiment seeks to achieve is not limited to the technical task described above, and other technical tasks may exist.

[0008] A high-speed counter using a phase shift according to one embodiment of the present invention may include a 2-divider circuit that generates a 2-divided clock signal from an input clock signal, a phase shifter that receives the 2-divided clock signal generated from the 2-divided circuit and generates a clock signal whose phase is 180 degrees behind, a first counter that operates with the 2-divided clock signal, a second counter that operates with the 2-divided clock signal and whose phase is 180 degrees behind, a logic circuit that operates the first counter when a remainder when N is divided by 2 is 0 when a target number N is given, and operates the second counter when the remainder when N is divided by 2 is 1, and sets a number M divided by 2 excluding the least significant bit (LSB) of the target number as a new target number, and a comparison logic circuit that compares an output from either the first counter or the second counter with M and outputs an output.

[0009] According to one embodiment, when the first counter is operating, the second counter may be turned OFF, and when the second counter is operating, the first counter may be turned OFF.

[0010] According to one embodiment, the circuit may further include a summation logic circuit that compares the output from either the first counter or the second counter with M and outputs an output pulse or flag signal as a result.

[0011] A high-speed counter using a phase shift according to another embodiment of the present invention comprises: a 4-divider circuit for generating a 4-divided clock signal from an input clock signal; a phase shifter for receiving the 4-divided clock signal generated from the 4-divider circuit and generating clock signals with a phase that is 90 degrees, 180 degrees, and 270 degrees slower; a first counter operating with a 4-divided clock signal; a second counter operating with a 4-divided clock signal that is 90 degrees slower in phase; a third counter operating with a 4-divided clock signal that is 180 degrees slower in phase; a fourth counter operating with a 4-divided clock signal that is 270 degrees slower in phase; when a target number N is given, if the remainder when N is divided by 4 is 0, the first counter is operated; if the remainder when N is divided by 4 is 1, the second counter is operated; if the remainder when N is divided by 4 is 2, the third counter is operated; and if the remainder when N is divided by 4 is 3, the fourth counter is operated. It may include a logic circuit that operates a counter and sets a new target number, M, which is a number divided by 4 excluding the least significant two bits of the target number, and a comparison logic circuit that compares the output from any one of the first counter, the second counter, the third counter, or the fourth counter and outputs the result.

[0012] In one embodiment, when the first counter operates, the second counter, the third counter, and the fourth counter may be turned OFF, when the second counter operates, the first counter, the third counter, and the fourth counter may be turned OFF, when the third counter operates, the first counter, the second counter, and the fourth counter may be turned OFF, and when the fourth counter operates, the first counter, the second counter, and the third counter may be turned OFF.

[0013] In one embodiment, the circuit may further include a summation logic circuit that compares an output from any one of the first counter, the second counter, the third counter, or the fourth counter with M and outputs an output pulse or flag signal as a result.

[0014] According to the present invention, a counter can be provided that minimizes power consumption by operating a counter that is 2 or 4 times slower and turning off all counters other than the corresponding counter.

[0015] In addition, according to the present invention, a counter capable of high-speed operation that responds to a high input clock frequency can be provided in a manner that can respond to a counter of a clock slower than the input clock.

[0016] FIG. 1 is a block diagram showing a high-speed counter (100) using phase shift according to one embodiment of the present invention.

[0017] Figure 2 is a flowchart showing a counting sequence using a conventional counter.

[0018] Figure 3 is a flowchart showing a counting sequence using a high-speed counter according to the present invention.

[0019] Figure 4 is a block diagram showing a method of operating the first counter and the second counter.

[0020] FIG. 5 is a timing diagram illustrating the operation of a high-speed counter according to one embodiment of the present invention.

[0021] Figure 6 is a block diagram showing a high-speed counter according to another embodiment of the present invention.

[0022] Figure 7 is a flowchart showing the operation of a high-speed counter according to another embodiment of the present invention.

[0023] Figure 8 is a timing diagram showing the operation of a high-speed counter when N=8.

[0024] Figure 9 is a timing diagram showing the operation of a high-speed counter when N=9.

[0025] Figure 10 is a timing diagram showing the operation of a high-speed counter when N=10.

[0026] Figure 11 is a timing diagram showing the operation of a high-speed counter when N=11.

[0027] Below, with reference to the attached drawings, embodiments of the present invention are described in detail so that those skilled in the art can easily implement them. The present invention is susceptible to various modifications and embodiments, and specific embodiments are illustrated in the drawings and specifically described in the detailed description. However, this is not intended to limit the present invention to specific embodiments, but rather to encompass all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention.

[0028] To clearly explain the present invention, parts irrelevant to the description have been omitted from the drawings, and similar parts have been designated with similar drawing reference numerals throughout the specification. In addition, when describing with reference to the drawings, even if components are indicated by the same name, the drawing numbers may vary depending on the drawing. The drawing numbers are described merely for the convenience of explanation, and the concept, feature, function, or effect of each component is not limited by the drawing numbers.

[0029] In describing each drawing, similar reference numerals are used to refer to similar components. Terms such as first, second, etc. may be used to describe various components, but the components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, a first component could be referred to as a second component, and similarly, a second component could also be referred to as a first component, without departing from the scope of the present invention. The term "and / or" includes any combination of multiple related listed items or any one of multiple related listed items.

[0030] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs.

[0031] Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense unless expressly defined in this application.

[0032] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case where it is "directly connected" but also the case where it is "electrically connected" with another element in between. Furthermore, when a part is said to "include" a component, this should be understood to mean that it may include other components rather than excluding other components unless specifically stated to the contrary, and does not preclude the presence or possibility of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0033] The present invention relates to a counter, a crucial component of digital circuit design, and particularly aims to provide an innovative improvement in counter design techniques that enable high-speed operation while minimizing power consumption. Conventional counters can be classified into two types: synchronous and asynchronous. These are used to count the number of bits of data and are configured by appropriately arranging flip-flops according to the required number of bits. In a synchronous counter, all flip-flops are triggered simultaneously by a common clock signal, whereas in an asynchronous counter, flip-flops are connected in a chain such that the output of the previous flip-flop serves as the clock input for the next flip-flop.

[0034] The present invention departs from conventional methods by not directly using the clock signal input to the counter, but by modulating it to make it slower. For example, by generating and using a clock that is slowed down to two or four times the original clock speed, the clock frequency is effectively divided. This slowed clock is synchronized with the original input clock and used to change its phase. In this process, the phase difference of the clock signal is utilized to group flip-flops, thereby enabling each part of the counter to operate efficiently.

[0035] The present invention activates and operates only flip-flop groups that meet operating conditions, while deactivating groups that are not involved, thereby reducing unnecessary power consumption. This approach maximizes the power efficiency of the counter while increasing its operating frequency. By slowly adjusting the operating frequency of the flip-flops, the counter can operate effectively even with lower power consumption. This ultimately increases the maximum operating frequency of the counter and improves overall operating performance.

[0036] Hereinafter, a high-speed counter device and method using phase shift according to the present invention will be described in detail with reference to the attached drawings.

[0037] FIG. 1 is a block diagram showing a high-speed counter (100) using phase shift according to one embodiment of the present invention.

[0038] Referring to FIG. 1, a high-speed counter (100) includes a 2-timer circuit (110) that reduces an input clock frequency by half, a phase shifter (120) that adjusts the phase of the clock, a first counter (130) that performs counting in response to an adjusted clock signal, a second counter (131) that performs counting in response to a signal that is phase-delayed from the adjusted clock signal, a logic circuit (140) that determines a counter to be operated, and a comparison logic circuit (150) that compares an output from the counter with an updated target number M and outputs the result.

[0039] Specifically, the divide-by-2 circuit (110) generates a clock that operates at half the input clock frequency. For example, a clock_x2 signal that halves the frequency of the input clock signal is generated so that the counter operates at a lower frequency than before. For example, if the basic clock signal is 100 MHz, the divide-by-2 circuit (110) generates a clock signal of 50 MHz.

[0040] The phase shifter (120) generates a clock signal with the same frequency as clock_x2 but with a phase delay of 180 degrees. It generates a clock signal that is delayed in time by half a cycle of the basic clock signal. For example, it generates a clock_x2_180shift signal.

[0041] The first counter (130) is a counter that operates by the clock_x2 signal. The first counter (130) performs counting in response to a clock signal that is twice as slow.

[0042] The second counter (131) is a counter that operates by the clock_x2_180shift signal. The second counter (131) performs counting in response to a signal whose phase is delayed by 180 degrees from a clock signal that is twice as slow.

[0043] In the present invention, each counter is configured to synchronize to a different clock signal, thereby efficiently distributing and managing power. Specifically, the present invention groups flip-flops according to the phase difference of the clock signal and operates them accordingly. As needed, only specific groups are selectively activated, thereby suppressing power consumption in the remaining groups.

[0044] The logic circuit (140) selectively operates either the first counter (130) or the second counter (131) according to a given target number N. When a target number N is given, if the remainder when N is divided by 2 is O, the first counter is operated, and if the remainder when N is divided by 2 is 1, the second counter is operated. For example, if N is n bits, N = N[n:0], and if N %2 = 0, the first counter (130) is operated, and if N %2 = 1, the second counter (131) is operated. In addition, a number M divided by 2, excluding the least significant bit (LSB) of the target number, is set as a new target number.

[0045] The comparison logic circuit (150) compares the output from either the first counter (130) or the second counter (131) with a new target number M and outputs the result. In this way, power consumption can be reduced by dividing the cases where the target number N %2 = 0 and 1 and turning off either the first counter (130) or the second counter (131).

[0046] Figure 2 is a flowchart showing a counting sequence using a conventional counter.

[0047] Referring to Fig. 2, first, a target number N is set in step S210. In step S220, a counter operates to perform counting, and in step S230, the output of the counter is compared with the target number N. When counting is completed in step S240, a flag is raised or a pulse synchronized to the corresponding clock is output. Since the conventional technology uses the same clock signal as input to the counter, it is difficult to realize low power and high-speed counter.

[0048] Figure 3 is a flowchart showing a counting sequence using a high-speed counter according to the present invention.

[0049] In step S310, a target number N is set. In step S320, a value divided by 2 excluding the target number N[0] bit, i.e., N[m:1]=M[n-1;0], is set to M.

[0050] In step S330, it is determined whether the target number N is even or odd. If it is determined in step S330 that N is even, Counter_0 is performed in step S340, and if N is odd, Counter_1 is performed in step S341. In other words, when the target number N is given, if the remainder when N is divided by 2 is O, Counter_0 is operated, and if the remainder when N is divided by 2 is 1, Counter_1 is operated. For example, if N is n bits, and N = N[n:0], and N %2 = 0, that is, N[0]=0, Counter_0 is operated, and if N %2 = 1, that is, N[0]=1, Counter_1 is operated.

[0051] In step S350, the output of counter_0 is compared with M, in step S351, the output of counter_1 is compared with M, and in step S360, the counter result is transmitted. That is, the output from either counter_0 or counter_1 is compared with the new target number M and outputted. In this way, power consumption can be reduced by dividing the cases where the target number N %2 = 0 and 1 and turning off either counter_0 or counter_1.

[0052] Figure 4 is a block diagram showing a method of operating a first counter (430) and a second counter (431).

[0053] Referring to Fig. 4, the 2-timer circuit (410) is a circuit that outputs a clock with twice the input clock cycle. For example, when the input signal of the 2-timer circuit (410) is a clock, the output signal becomes clock_x2 with a cycle twice that of the input signal (clock). Thereafter, the first counter (430) operates by the clock_x2 signal, and the second counter (431) operates by the clock_x2_180shift signal, which is delayed by 180 degrees from the clock_x2 signal.

[0054] The number of registers used in the counter of the prior art and the sum of the registers used in the first counter (430) and the second counter (431) used in the present invention are the same. However, since either the first counter (430) or the second counter (431) is turned off depending on the result of dividing the target number N by 2 (%2), the power consumption of the entire circuit can be reduced.

[0055] If the target number N has n bits, N can be expressed as N[n:0]. At this time, N[n:1] excluding N[0] is set to the number M. In this case, M=M[n-1:0]. Afterwards, the first comparison logic circuit (440) outputs the value obtained by comparing Counter_0 and M or the second comparison logic circuit (441) outputs the result obtained by comparing Counter_1 and M. The output result is transmitted to the summation logic circuit (450) to output PLU_CNT, which is a pulse or flag signal.

[0056] FIG. 5 is a timing diagram illustrating the operation of a high-speed counter according to one embodiment of the present invention.

[0057] Referring to Figure 5, the clock signal is a signal that originally comes in through the counter, clock_x2 is a signal that slows down the clock signal by two times, and clock_x2_180shift is a signal that receives the clock_x2 signal, shifts it by 1 clock in synchronization with the clock signal, and as a result, phase-shifts the clock_x2 signal by 180.

[0058] The target number can be any number expressed by N[n:0], and in Fig. 5, for example, the cases (a) N=10 and (b) N=11 are used to explain.

[0059] First, when N=10, the first counter (COUNTER_0) operates. Referring again to Figure 1, ON_0 of the first counter=1 and ON_1 of the second counter=0. Next, M[n-1:0] set in the logic circuit becomes 5 when divided by 2, excluding N[0]. Therefore, PUL_CNT becomes 5.

[0060] Next, when N=11, the second counter (COUNTER_1) operates. Referring to Figure 1 again, ON_0 of the first counter=0 and ON_1 of the second counter=1. Next, M[n-1:0] set in the logic circuit becomes 5 when divided by 2 excluding N[0]. Therefore, PUL_CNT becomes 5.

[0061] Figure 6 is a block diagram showing a high-speed counter according to another embodiment of the present invention.

[0062] Referring to FIG. 6, a high-speed counter (600) representing another embodiment of the present invention may include a 4-phase divider circuit (610), a first phase shifter (620), a second phase shifter (621), a third phase shifter (622), a first counter (630), a second counter (631), a third counter (632), a fourth counter (633), and a summation logic circuit (640).

[0063] The 4-frequency circuit (610) outputs a clock signal four times the input clock cycle. That is, a clock signal is input and a clock_x4 signal is output to the first counter (630).

[0064] The first phase shifter (620) receives a clock signal, delays the phase by 90 degrees, and outputs a clock_x4_90shift signal with a phase shifted by 90 degrees to the second counter (631).

[0065] The second phase shifter (621) shifts the clock_x4_90shift signal, which is shifted by 90 degrees in phase by the first phase shifter (620), by 90 degrees again and outputs the clock_x4_180shift signal to the third counter (632).

[0066] The third phase shifter (622) shifts the 180-degree shifted clock_x4_180shift signal by 90 degrees again and outputs the clock_x4_270shift signal to the fourth counter (633).

[0067] When the target number N is divided by 4, depending on whether the remainder is 0, 1, 2, or 3, one of the first counter (630), the second counter (631), the third counter (632), and the fourth counter (633) operates.

[0068] For example, if the remainder when N is divided by 4 is 0, the first counter (630) operates, and at this time, the second counter (631), the third counter (632), and the fourth counter (633) are all turned OFF. If the remainder when N is divided by 4 is 1, the second counter (631) operates, and at this time, the first counter (630), the third counter (632), and the fourth counter (633) are all turned OFF. If the remainder when N is divided by 4 is 2, the third counter (632) operates, and at this time, the first counter (630), the second counter (631), and the fourth counter (633) are all turned OFF. If the remainder when N is divided by 4 is 3, the fourth counter (633) operates, and at this time, the first counter (630), the second counter (631), and the third counter (632) are all turned OFF.

[0069] Afterwards, the outputs of the first counter (630), the second counter (631), the third counter (632), and the fourth counter (633) are compared with M.

[0070] The target number M is set through the following process. Specifically, according to the target number N, N[n:2]=M[n-2;0] is set to M by dividing the value by 4, excluding the target number N[1:0] bits (setting them to fix 00). For example, the two least significant bits (LSBs) of the target number are set to '0'. This means 'clearing' the bits. Bit masking or bit clearing operations can be used to perform this task. For example, if the target number is 1011 in binary (11 in decimal), setting the two least significant bits to 0 will make it 1000 (8 in decimal). Next, the target number modified in the previous step is divided by 4. Since the LSBs are set to 0, this number is already a multiple of 4. Therefore, the result of dividing this number by 4 will always be an integer, and this integer is set as the new value M. For example, dividing 1000 (8 in decimal) by 4 gives 0010 (2 in decimal). This becomes the new value M.

[0071] Next, the outputs of M and the counter are compared with each other, and the PUL_CNT signal is output.

[0072] Figure 7 is a flowchart showing the operation of a high-speed counter according to another embodiment of the present invention.

[0073] In step S710, a target number N is set. In step S720, the target number N[1:0] bit is set to fix 00, and a value divided by 4, i.e., N[n:2]=M[n-2;0] is set to M.

[0074] In step S730, the target number N is divided by 4 and the remainder is determined to be 0, 1, 2, or 3.

[0075] If N is 0 as determined in step S730, Counter_0 is performed in step S740. At this time, Counter_1, Counter_2, and Counter_3 all become OFF. If N is 1, Counter_1 is performed in step S741. At this time, Counter_0, Counter_2, and Counter_3 all become OFF. If N is 2, Counter_2 is performed in step S742. At this time, Counter_0, Counter_1, and Counter_3 all become OFF. If N is 3, Counter_3 is performed in step S743. At this time, Counter_0, Counter_1, and Counter_2 all become OFF.

[0076] In step S750, the output of counter_0 is compared with M, in step S751, the output of counter_1 is compared with M, in step S752, the output of counter_2 is compared with M, and in step S753, the output of counter_3 is compared with M.

[0077] The counter result is transmitted in step S760.

[0078] FIGS. 8 to 11 are timing diagrams showing the operation of a high-speed counter according to another embodiment of the present invention.

[0079] Referring to FIGS. 8 to 11, the clock signal is a signal originally coming through the counter, clock_x2 is a signal that slows down the clock signal by two times, and clock_x4 is a signal that slows down the clock signal by four times.

[0080] clock_x4_90shift is a signal that receives the clock_x4 signal, shifts it by 1 clock in synchronization with the clock signal, and as a result, shifts the clock_x4 signal by 90 degrees in phase.

[0081] clock_x4_180shift is a signal that receives the clock_x4 signal, shifts it by 2 clocks in synchronization with the clock signal, and as a result, shifts the clock_x4 signal by 180 degrees in phase.

[0082] clock_x4_270shift is a signal that receives the clock_x4 signal, shifts it by 3 clocks in synchronization with the clock signal, and as a result, the clock_x4 signal is phase-shifted by 270 degrees.

[0083] The target number can be any number represented by N[n:0], and FIGS. 8 and 9 show, as examples, the cases where N=8 and N=9.

[0084] Figure 8 is a timing diagram showing the operation of a high-speed counter when N=8.

[0085] Referring to Fig. 8, when N=8, 8%4 is 0, so the first counter (COUNTER_0) is used. Referring again to Fig. 6, the first counter (COUNTER_0) is ON, and the remaining second counter (COUNTER_1), third counter (COUNTER_2), and fourth counter (COUNTER_3) are OFF. Next, M[n-2:0] set in the logic circuit becomes 2 when divided by 4, excluding N[1:0]. Therefore, PUL_CNT becomes 2.

[0086] Figure 9 is a timing diagram showing the operation of a high-speed counter when N=9.

[0087] Referring to Fig. 9, when N=9, the second counter (COUNTER_1) is used. Referring again to Fig. 6, the second counter (COUNTER_1) is ON, and the remaining first counter (COUNTER_0), third counter (COUNTER_2), and fourth counter (COUNTER_3) are OFF. Next, M[n-2:0] set in the logic circuit becomes 2 when divided by 4, excluding N[1:0]. Therefore, PUL_CNT becomes 2.

[0088] Figure 10 is a timing diagram showing the operation of a high-speed counter when N=10.

[0089] Referring to Fig. 10, when N=10, the third counter (COUNTER_2) is used. Referring again to Fig. 6, the third counter (COUNTER_2) is ON, and the remaining first counter (COUNTER_0), second counter (COUNTER_1), and fourth counter (COUNTER_3) are OFF. Next, M[n-2:0] set in the logic circuit becomes 2 when divided by 4, excluding N[1:0]. Therefore, PUL_CNT becomes 2.

[0090] Figure 11 is a timing diagram showing the operation of a high-speed counter when N=11.

[0091] Referring to Fig. 11, when N=11, the fourth counter (COUNTER_3) is used. Referring again to Fig. 6, the fourth counter (COUNTER_3) is ON, and the remaining first counter (COUNTER_0), second counter (COUNTER_1), and third counter (COUNTER_2) are OFF. Next, M[n-2:0] set in the logic circuit becomes 2 when divided by 4, excluding N[1:0]. Therefore, PUL_CNT becomes 2.

[0092] In the above, it has been exemplified that the clock signal generates a signal that is 2 times or 4 times slower, but the embodiments of the present invention are not limited to the above examples, and it is not excluded that it is also possible to generate and use a signal that is 8 times, 16 times, or the like slower.

[0093] The embodiments of the present invention described above may also be implemented in the form of a recording medium containing computer-executable instructions, such as program modules executed by a computer. Computer-readable recording media may include computer storage media, and computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data.

[0094] Although the devices and methods of the present invention have been described with respect to specific embodiments, some or all of their components or operations may be implemented using a computer system having a general-purpose hardware architecture.

[0095] The foregoing description of the present invention is for illustrative purposes only, and those skilled in the art will readily appreciate that the present invention can be readily modified into other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single entity may be implemented in a distributed manner, and similarly, components described as distributed may be implemented in a combined manner.

[0096] The scope of the present invention is indicated by the claims described below rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention.

[0097] [Sasamungu]

[0098] (Korean) This project (outcome) is the result of a local government-university cooperation-based regional innovation project, supported by the National Research Foundation of Korea and funded by the Ministry of Education in 2024. (2023RIS-009)

[0099] (English) This research was supported by "Regional Innovation Strategy (RIS)" through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (MOE). (2023RIS-009)

[0100] [National Research and Development Project Supporting This Invention]

[0101] [Project ID] 1345370817

[0102] [Project Number] 2023RIS-009

[0103] [Ministry Name] Ministry of Education

[0104] [Project Management (Specialist) Agency Name] Jeju Regional Innovation Platform Green Energy Future Mobility Business Unit

[0105] [Research Project Name] Green Energy and Future Mobility Core Company Growth Bridge Project

[0106] [Research Project Name] Development of Regional Advanced Semiconductor Ecosystem Technology

[0107] [Name of the project performing organization] Meta C&I Co., Ltd.

[0108] [Research Period] March 1, 2024 - February 28, 2025

Claims

1. A divide-by-2 circuit that generates a clock signal divided by 2 from an input clock signal; A phase shifter that receives the divided-by-two clock signal generated from the divided-by-two circuit and generates a clock signal with a phase that is 180 degrees behind; A first counter operating with the above-mentioned two-time divided clock signal; A second counter operating on a clock signal divided by two and with a phase 180 degrees behind; A logic circuit that operates a first counter when a remainder of N divided by 2 is O when a target number N is given, operates a second counter when the remainder of N divided by 2 is 1, and sets a number M divided by 2 excluding the least significant bit (LSB) of the target number as a new target number; A comparison logic circuit including an output from either the first counter or the second counter and comparing the M to output, High-speed counter device using phase shift.

2. In paragraph 1, A high-speed counter device using phase shift, wherein when the first counter operates, the second counter is turned off, and when the second counter operates, the first counter is turned off.

3. In paragraph 1, A high-speed counter device using a phase shift, further comprising a summation logic circuit that compares the output from either the first counter or the second counter with the M and outputs an output pulse or flag signal as a result.

4. A high-speed counting method performed by a high-speed counter device, A step of generating a clock signal divided by two from an input clock signal; A step of receiving a divided-by-2 clock signal generated from a divided-by-2 circuit and generating a clock signal whose phase is 180 degrees behind; When a target number N is given, if the remainder when N is divided by 2 is O, a first counter operating with the divided-by-2 clock signal is operated, and if the remainder when N is divided by 2 is 1, a second counter operating with the divided-by-2 clock signal whose phase is 180 degrees behind is operated, and a number M divided by 2 excluding the least significant bit (LSB) of the target number is set as a new target number; A high-speed counting method using a phase shift, comprising a step of comparing the output from either the first counter or the second counter with the M and outputting the result.

5. In paragraph 4, A high-speed counting method using phase shift, wherein when the first counter operates, the second counter is turned off, and when the second counter operates, the first counter is turned off.

6. In paragraph 4, A high-speed counting method using a phase shift, further comprising a step of comparing the output from either the first counter or the second counter with the M and outputting an output pulse or flag signal as a result.

7. A 4-division circuit that generates a 4-division clock signal from an input clock signal; A phase shifter that receives the divided-by-four clock signal generated from the divided-by-four circuit and generates clock signals with phases that are 90 degrees, 180 degrees, and 270 degrees behind; A first counter operating with the above-mentioned 4-time divided clock signal; A second counter operating on a clock signal divided by four and with a phase lag of 90 degrees; A third counter operating on a clock signal divided by four and with a phase 180 degrees behind; A fourth counter operating on a clock signal divided by four and with a phase 270 degrees behind; A logic circuit that, when a target number N is given, operates a first counter if the remainder when N is divided by 4 is O, operates a second counter if the remainder when N is divided by 4 is 1, operates a third counter if the remainder when N is divided by 4 is 2, operates a fourth counter if the remainder when N is divided by 4 is 3, and sets a number M divided by 4 excluding the least significant 2 bits of the target number as a new target number; A comparison logic circuit that compares the output from any one of the first counter, the second counter, the third counter, or the fourth counter with the M and outputs the result. High-speed counter device using phase shift.

8. In paragraph 7, A high-speed counter device using a phase shift, wherein when the first counter operates, the second counter, the third counter, and the fourth counter are turned off, when the second counter operates, the first counter, the third counter, and the fourth counter are turned off, when the third counter operates, the first counter, the second counter, and the fourth counter are turned off, and when the fourth counter operates, the first counter, the second counter, and the third counter are turned off.

9. In paragraph 7, A high-speed counter device using a phase shift, further comprising a summation logic circuit that compares the output from any one of the first counter, the second counter, the third counter, or the fourth counter with the M and outputs an output pulse or flag signal as a result.

10. A high-speed counting method performed by a high-speed counter device, A step of generating a clock signal divided by four from an input clock signal; A step of receiving the above-mentioned 4-phase clock signal and generating clock signals whose phases are 90 degrees, 180 degrees, and 270 degrees behind; When a target number N is given, if the remainder when N is divided by 4 is O, a first counter operating with the clock signal divided by 4 is operated, if the remainder when N is divided by 4 is 1, a second counter operating with the clock signal divided by 4 and having a phase that is 90 degrees slower than the first counter, if the remainder when N is divided by 4 is 2, a third counter operating with the clock signal divided by 4 and having a phase that is 180 degrees slower than the first counter, if the remainder when N is divided by 4 is 3, a fourth counter operating with the clock signal divided by 4 and having a phase that is 270 degrees slower than the first counter, and setting a number M divided by 4, excluding the least significant 2 bits of the target number, as a new target number; Comprising a step of comparing the output from any one of the first counter, the second counter, the third counter, or the fourth counter with the M and outputting the result. High-speed counting method using phase shift.

11. In paragraph 10, A high-speed counting method using a phase shift, wherein when the first counter operates, the second counter, the third counter, and the fourth counter are turned off, when the second counter operates, the first counter, the third counter, and the fourth counter are turned off, when the third counter operates, the first counter, the second counter, and the fourth counter are turned off, and when the fourth counter operates, the first counter, the second counter, and the third counter are turned off.

12. In paragraph 10, A high-speed counting method using a phase shift, further comprising a step of comparing the output from any one of the first counter, the second counter, the third counter, or the fourth counter with the M and outputting an output pulse or flag signal as a result.

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