Capacitor and manufacturing method therefor, and memory array, memory and electronic device

Abstract

Provided in the present application are a capacitor and a manufacturing method therefor, and a memory array, a memory and an electronic device. The capacitor comprises: a first electrode, a second electrode, and a ferroelectric layer located between the first electrode and the second electrode, wherein the ferroelectric layer comprises an undoped layer and a doped layer. The present application can improve the resistance for breakdown field strength, thereby improving the durability of a capacitor and prolonging the service life of the capacitor.

Description

Capacitor, method of manufacturing the same, memory array, memory, and electronic device TECHNICAL FIELD

[0001] The present application relates to the technical field of information storage, and in particular to a capacitor, a method of manufacturing the same, a memory array, a memory, and an electronic device. BACKGROUND

[0002] Most electronic devices are currently equipped with a memory. The memory can be used to perform write and / or read operations to achieve storage and / or reading of information. In order to filter out power supply noise in the memory, a capacitor can be usually included in the memory.

[0003] The capacitor includes a first electrode, a ferroelectric layer, and a second electrode, and the material of the ferroelectric layer is a ferroelectric material. In use, the ferroelectric layer will undergo multiple ferroelectric polarization flips, and the continuous ferroelectric polarization flips will cause the concentration of oxygen vacancies in the ferroelectric layer to rise, thereby causing the capacitor to break down. Therefore, the durability and service life of the capacitor in the related art are low. SUMMARY

[0004] To solve the above technical problems, the present application provides a capacitor, a method of manufacturing the same, a memory array, a memory, and an electronic device, which can improve the breakdown electric field resistance and thereby improve the durability and service life of the capacitor.

[0005] In a first aspect, the present application provides a capacitor, comprising: a first electrode, a second electrode, and a ferroelectric layer between the first electrode and the second electrode, the ferroelectric layer comprising a doped layer and a non-doped layer, and the doped layer and the non-doped layer each comprising ferroelectric grains. That is, the doped elements of the doped layer are incorporated into the ferroelectric grains. Moreover, the doped elements can occupy the sites of the ferroelectric grains and form bonds with oxygen, thereby effectively inhibiting the generation of charged oxygen vacancies, which is conducive to the stability of the ferroelectric domains, and thereby improving the stability of the ferroelectric grains. Moreover, the doped layer elements do not cut off the integrity of the ferroelectric grains.

[0006] Moreover, since the doped elements have a pinning effect on the oxygen vacancies in the ferroelectric layer, the migration of the oxygen vacancies under the action of the electric field during the ferroelectric domain flip is effectively controlled and cannot move at will, thereby improving the breakdown electric field and thereby improving the breakdown electric field resistance. Moreover, fatigue that occurs during continuous flipping can be alleviated, thereby further improving the durability. In addition, when the breakdown electric field resistance is improved, the service life of the capacitor can also be improved.

[0007] In some embodiments of the present application, the ferroelectric layer comprises at least two undoped layers and at least one doped layer, each doped layer being located between each adjacent two undoped layers. That is, there is at least one undoped layer between each doped layer and the first electrode, and there is at least one undoped layer between each doped layer and the second electrode, so that the direct contact between the doped layer and the first electrode or the second electrode does not affect the normal use of the capacitor.

[0008] For the structure of the capacitor, in one possible embodiment, the first electrode and the second electrode are stacked, and at least two undoped layers and at least one doped layer are stacked between the first electrode and the second electrode. In one example, the stacking direction of the first electrode, the ferroelectric layer and the second electrode is the thickness direction of the memory. In another example, the stacking direction of the first electrode, the ferroelectric layer and the second electrode is the length or width direction of the memory.

[0009] For the structure of the capacitor, in another possible embodiment, the second electrode surrounds the first electrode, and at least two undoped layers and at least one doped layer are arranged between the first electrode and the second electrode. In one example, the first electrode, the ferroelectric layer and the second electrode can all be in a ring-shaped quadrilateral structure. In another example, the first electrode, the ferroelectric layer and the second electrode can all be in a circular ring shape.

[0010] In some embodiments of the present application, the capacitor has a symmetrical structure about a center plane, the distance between the center plane and the surface of the first electrode away from the second electrode is the same as the distance between the center plane and the surface of the second electrode away from the first electrode. In this way, the absolute values of the positive coercive field strength and the negative coercive field strength are the same, that is, the positive coercive field strength and the negative coercive field strength are symmetrical, so that the situation of uneven flipping does not occur, thereby alleviating the situation that the single-sided storage state cannot be maintained due to uneven flipping. A larger imprint effect will cause the ferroelectric polarization curve to shift at high temperature, thereby causing the storage window to decrease, the storage information to be lost, and the rewriting to be difficult. Therefore, when the imprint effect of the present application is alleviated, the shift amount of the ferroelectric polarization curve at high temperature can be reduced, thereby not causing the storage window to decrease, improving the storage retention, and reducing the difficulty of rewriting.

[0011] Further, the ferroelectric layer comprises a first doped layer and a second doped layer respectively located on two sides of the center plane, and the distance between the first doped layer and the center plane is the same as the distance between the second doped layer and the center plane. That is, the first doped layer and the second doped layer are in a symmetric structure about the center plane. The thickness of the undoped layer between the first doped layer and the second doped layer ranges from 3 nm to 5 nm. For example, 3 nm, 4 nm or 5 nm, etc. When the thickness of the undoped layer is less than 3 nm, it indicates that the first doped layer and the second doped layer are closer to the center plane, in which case, the current density is larger and the imprint effect is smaller. As can be seen, the closer the first doped layer and the second doped layer to the center plane, the more the imprint effect can be alleviated. However, this will lead to poor domain continuity of the undoped layer, increased crystallization difficulty, and a large decrease in remanent polarization. Moreover, the lack of control of oxygen vacancies near the interface between the first electrode and the undoped layer increases the depolarization field, which is not conducive to the retention of the storage state. When the thickness is greater than 5 nm, it indicates that the doped layer is far away from the center plane, which is conducive to the retention of the storage state, but the effect of alleviating the imprint effect is poor. Therefore, when the thickness ranges from 3 nm to 5 nm, the retention of the storage state and the effect of alleviating the imprint effect can be considered at the same time.

[0012] In other possible embodiments, the first doped layer and the second doped layer are in a non-symmetric structure about the center plane. For example, the first doped layer and the second doped layer are located on the same side of the center plane; or the first doped layer and the second doped layer are respectively located on two sides of the center plane, and the distance between the first doped layer and the center plane is greater than the distance between the second doped layer and the center plane.

[0013] In some embodiments of the present application, the projection of the doped layer on the first electrode is the same as the projection of the undoped layer on the first electrode.

[0014] In some embodiments of the present application, the material of the undoped layer comprises hafnium oxide or hafnium zirconium oxide, and the doping element of the doped layer comprises titanium, tantalum or niobium. Since titanium, tantalum or niobium is an element of the same group or adjacent subgroup as hafnium, its ionic radius is close to that of hafnium and zirconium, and therefore it can better occupy the lattice sites, interstitial sites and grain boundary defects of hafnium oxide or hafnium zirconium oxide.

[0015] In some embodiments of the present application, the capacitor further comprises a first conductive layer and a second conductive layer, the first conductive layer is located between the first electrode and the ferroelectric layer, and the second conductive layer is located between the second electrode and the ferroelectric layer.

[0016] In a second aspect of the present application, a storage array is provided, comprising a switching tube and a capacitor of any of the above embodiments, the switching tube being electrically connected to the capacitor. The storage array can realize all the effects of the capacitor.

[0017] In a third aspect of the present application, a memory is provided, comprising a controller and the memory array as described above, wherein the controller is electrically connected with the memory array. The memory can realize all the effects of the memory array.

[0018] In a fourth aspect of the present application, an electronic device is provided, comprising a circuit board and the memory as described above, wherein the circuit board is electrically connected with the memory. The electronic device can realize all the effects of the memory.

[0019] In a fifth aspect of the present application, a method for manufacturing a capacitor is provided, comprising: manufacturing a first electrode; manufacturing an initial ferroelectric layer on the first electrode, the initial ferroelectric layer comprising an initial undoped layer and an initial doped layer stacked, the initial undoped layer comprising ferroelectric grains, and the initial doped layer comprising a doping element; manufacturing a second electrode on the initial ferroelectric layer; and performing a crystallization treatment on the initial ferroelectric layer to obtain a ferroelectric layer, the ferroelectric layer comprising an undoped layer and a doped layer, both the undoped layer and the doped layer comprising ferroelectric grains, and the doped layer comprising a doping element. That is, the doping element in the doped layer is incorporated into the ferroelectric grains, and can occupy the sites of the ferroelectric grains and form bonds with oxygen, thereby effectively inhibiting the generation of charged oxygen vacancies, which is conducive to the stability of ferroelectric domains, and further improves the stability of the ferroelectric grains. Moreover, the elements in the doped layer do not cut off the integrity of the ferroelectric grains.

[0020] Moreover, since the doping element has a pinning effect on the oxygen vacancies in the ferroelectric layer, the migration of the oxygen vacancies under the action of the electric field in the process of the ferroelectric domain flipping is effectively controlled and cannot move at will, thereby improving the breakdown electric field, which improves the anti-breakdown electric field capability, so that the endurance of the ferroelectric material is improved at the same working voltage. Moreover, fatigue that occurs in the process of continuous flipping can also be slowed down, thereby further improving the endurance. In addition, when the anti-breakdown electric field capability is improved, the service life of the capacitor can also be improved.

[0021] In some embodiments of the present application, the spacing between the initial doped layer closest to the first electrode and the first electrode ranges from 0.1 nm to 10 nm. If the spacing between the two is less than 0.1 nm, the spacing between the two is too small, which causes the doping element in the initial doped layer to diffuse to the first electrode during the subsequent crystallization treatment, thereby affecting the normal use of the capacitor. If the spacing between the two is greater than 10 nm, the spacing between the two is too large, which causes the thickness of the capacitor to be too large, thereby increasing the volume of the capacitor and reducing the power density of the capacitor. Therefore, when the spacing between the two ranges from 0.1 nm to 10 nm, the normal use of the capacitor can be ensured, and the power density of the capacitor can be improved.

[0022] Further, the spacing between the initial doped layer closest to the second electrode and the second electrode ranges from 0.1 nm to 10 nm. In this way, the capacitor can be used normally and the power density of the capacitor can be improved when the spacing between the two ranges from 0.1 nm to 10 nm.

[0023] In some embodiments of the present application, the initial ferroelectric layer includes at least two layers of stacked and spaced initial undoped layers, and the spacing between the two adjacent initial undoped layers ranges from 0.1 nm to 20 nm. If the spacing between the two is less than 0.1 nm, the spacing between the two is too small, thereby causing the thickness of the initial doped layer between the two adjacent initial undoped layers to be too small to effectively control the migration of oxygen vacancies. If the spacing between the two is greater than 20 nm, the spacing between the two is too large, thereby causing the thickness of the capacitor to be too large, which in turn increases the volume of the capacitor and reduces the power density of the capacitor. Therefore, when the spacing between the two ranges from 0.1 nm to 20 nm, the migration of oxygen vacancies can be effectively controlled, and the power density of the capacitor can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the description of the embodiments of the present application will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0025] FIG. 1 is a schematic diagram of the three-dimensional structure of a capacitor in the related art;

[0026] FIG. 2 is a schematic diagram of the cross-sectional structure of the capacitor shown in FIG. 1;

[0027] FIG. 3 is a durability cycle curve of the capacitor shown in FIG. 1;

[0028] FIG. 4 is a ferroelectric polarization curve of the capacitor shown in FIG. 1;

[0029] FIG. 5 is a ferroelectric polarization curve of the capacitor shown in FIG. 1 at different temperatures;

[0030] FIG. 6 is a schematic diagram of the imprint effect of the capacitor shown in FIG. 1;

[0031] FIG. 7 is a durability curve of the capacitor shown in FIG. 1 at different temperatures;

[0032] FIG. 8 is another durability curve of the capacitor shown in FIG. 1 at 450°C;

[0033] FIG. 9 is another durability curve of the capacitor shown in FIG. 1 at 500°C;

[0034] Fig. 10 is a perspective view of a capacitor according to a first embodiment of the present application;

[0035] Fig. 11 is a cross-sectional view of the capacitor shown in Fig. 1;

[0036] Fig. 12 is a durability curve of the capacitor shown in Fig. 10 at a working voltage of 2V;

[0037] Fig. 13 is a durability curve of the capacitor shown in Fig. 10 at a working voltage of 1.6V;

[0038] Fig. 14 is a rewriting difficulty curve of the related art shown in Fig. 1 and the embodiment shown in Fig. 10;

[0039] Fig. 15 is a storage retention curve of the related art shown in Fig. 1 and the embodiment shown in Fig. 10;

[0040] Fig. 16 is a ferroelectric polarization curve of the related art shown in Fig. 1 and the embodiment shown in Fig. 10 under one condition;

[0041] Fig. 17 is a ferroelectric polarization curve of the related art shown in Fig. 1 and the embodiment shown in Fig. 10 under another condition;

[0042] Fig. 18 is a comparison of ferroelectric polarization curves of the related art shown in Fig. 1 before and after heating at 400°C for 3 hours;

[0043] Fig. 19 is a comparison of ferroelectric polarization curves of the embodiment shown in Fig. 10 before and after heating at 400°C for 3 hours;

[0044] Fig. 20 is a comparison of ferroelectric polarization curves of an asymmetrically structured capacitor and a symmetrically structured capacitor;

[0045] Fig. 21 is a comparison of current density curves of a capacitor when a doped layer is at three different positions;

[0046] Fig. 22 is a comparison of durability curves of a capacitor when a doped layer is at three different positions;

[0047] Fig. 23 is a cross-sectional view of a capacitor according to a second embodiment of the present application;

[0048] Fig. 24 is a perspective view of a capacitor according to a third embodiment of the present application;

[0049] Fig. 25 is a cross-sectional view of a capacitor according to a fourth embodiment of the present application;

[0050] Fig. 26 is a cross-sectional view of a capacitor according to a fifth embodiment of the present application;

[0051] Fig. 27 is a cross-sectional view of a capacitor according to a sixth embodiment of the present application;

[0052] Fig. 28 is a schematic diagram of a perspective view of a capacitor according to a seventh embodiment of the present application;

[0053] Fig. 29 is a schematic diagram of a manufacturing process of the capacitor shown in Fig. 10;

[0054] Fig. 30 is a schematic diagram of a detailed process of the manufacturing method shown in Fig. 29.

[0055] Fig. 30 is a schematic diagram of a detailed process of the manufacturing method shown in Fig. 29. DETAILED DESCRIPTION

[0056] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without any creative work fall within the scope of the present application.

[0057] The term “and / or” in the present application is only used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that there are three cases of A alone, A and B together, and B alone, where A and B can be singular or plural. The character “ / ” generally represents an “or” relationship between the associated objects before and after it. “At least one” means one or more, and “multiple” means two or more. “At least one of the following” or the like means any combination of these items, including any combination of single item or multiple items. For example, at least one of a, b or c can mean a, b, c, “a and b”, “a and c”, “b and c”, or “a and b and c”, where a, b, and c can be single or multiple.

[0058] The terms “first” and “second” and the like in the specification and claims of the embodiments of the present application are used to distinguish different objects, and are not used to describe the specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, and are not used to describe the specific order of the target objects.

[0059] Terms such as “connected” and “linked” are used to express the interconnection or interaction between different components, which may include direct connection or indirect connection through other components. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses. Terms such as “upper,” “lower,” “left,” and “right” are used only relative to the orientation of components in the accompanying drawings. These directional terms are relative concepts used for relative description and clarification, and may vary accordingly depending on the orientation of the components in the drawings.

[0060] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0061] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0062] With the massive growth of data, new requirements have been placed on memory, such as non-volatility, low power consumption, high reliability, and high density. Embedded non-volatile memory (eNVM), as a core and indispensable system-on-chip (SoC) technology, is required in microcontroller units (MCUs), automotive chips, and 5G-related chips to meet the explosive growth in demand from fields such as the Internet of Things (IoT) and autonomous driving.

[0063] Currently, eNVM, based on traditional embedded flash memory (eFlash) technology, requires higher voltages for reading and writing, making it difficult to miniaturize and unable to support further evolution to process nodes below 28nm.

[0064] The memory can be applied to an electronic device, and the electronic device further includes a circuit board, and the memory can be electrically connected with the circuit board. The electronic device can be, for example, a server, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, and the like, and the embodiments of the present application do not limit this. Illustratively, the above-mentioned consumer electronic product can be a mobile phone, a tablet computer, a notebook computer, a personal computer (PC), a personal digital assistant (PDA), a smart wearable product (for example, a smart watch, a smart bracelet, and the like), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a drone, and the like. The home electronic product can be a smart door lock, a television, a smart sound box, a refrigerator, a sweeping robot, and the like. The vehicle-mounted electronic product can be a vehicle-mounted navigator, a vehicle-mounted display, and the like. The financial terminal product can be an automated teller machine (ATM), an electronic device for self-service business, and the like. The communication electronic product can be a server, a memory, a radar, a base station, and the like.

[0065] The memory can include a controller and a storage array, and the storage array can include a capacitor and a switching tube. The capacitor is used for reading information, and the switching tube is used for gating the capacitor. As a kind of memory, the ferroelectric random access memory (FeRAM) is a metal-insulator-metal (MIM) capacitor composed of a metal-ferroelectric material-metal (MFM).

[0066] The principle of the capacitor 1 is to utilize the physical phenomenon that the orientation of the polarization of the ferroelectric material can be changed by an external electric field. Inside the ferroelectric material, the positive and negative charge centers are asymmetric, resulting in the appearance of an electric dipole, generating the spontaneous polarization direction of the ferroelectric material. Under the action of an applied electric field, the polarization direction is rewritten as two directions of up and down. Under the action of a detection amplifier, it can be identified as the state of storing information "0" or "1". Since the polarization state of the FeRAM can be maintained after the applied electric field is removed, the FeRAM has the characteristic of non-volatility. In addition, the main source of ferroelectric polarization reversal is the reversal of the electric dipole, and since the reversal speed is fast and the Joule heat generated is small, the FeRAM also has the advantages of fast read-write speed and low power consumption.

[0067] In a related technology, the ferroelectric material is a perovskite structure material such as lead zirconium titanate (Pb(Zr,Ti)O3, PZT), which cannot be compatible with advanced process size miniaturization because it can only exhibit stable ferroelectricity above a critical thickness. To solve this problem, in another related technology, the ferroelectric material is a hafnium oxide (HfO2) based material doped with other elements, such as zirconium (Zr) element doped in hafnium oxide to obtain hafnium zirconium oxide (HZO). Since this material has good complementary metal oxide semiconductor (CMOS) process compatibility, the ferroelectric layer 20 can be made by thin film deposition using atomic layer deposition (ALD), so that the ferroelectric layer 20 has a lower crystallization temperature, and the size of the memory can be miniaturized to below 5 nm, and non-volatility, low power consumption, high reliability and high density can be achieved.

[0068] The ferroelectric material can have an imprint effect, that is, the storage state of the ferroelectric layer 20 can have an imprint effect after experiencing high temperature. Specifically, as shown in FIG. 3, charges are accumulated at the interface between the ferroelectric layer 20 and the second electrode 30.

[0069] Retention is a reliability indicator of the capacitor in a high temperature working environment. When the capacitor 1 is in a high temperature working environment, the imprint effect can cause the ferroelectric polarization-voltage (PV) curve to shift at high temperature, resulting in a decrease in the storage window and a decrease in retention. The decrease in retention specifically manifests as loss of stored information and difficulty in rewriting. As shown in FIG. 4, which shows the ferroelectric polarization curve of the capacitor under the influence of high temperature imprint effect, it can be seen from FIG. 4 that the ferroelectric polarization curve shifts to the right along the direction of the arrow.

[0070] The ferroelectric layer 20 of the capacitor 1 shown in FIG. 2 has no doping, the first electrode 10 is in contact with the ferroelectric layer 20, and the second electrode 30 is in contact with the ferroelectric layer 20. When the capacitor 1 is made, the first electrode 10, the ferroelectric layer 20 and the second electrode 30 can be subjected to rapid thermal annealing (RTA) treatment, also known as crystallization treatment, which uses the effective stress of the first electrode 10 or the second electrode 30 on the ferroelectric layer 20 to generate O phase in the ferroelectric layer 20. The ferroelectric polarization curve of the capacitor 1 after crystallization treatment is shown in FIG. 5. The coercive field strength E CAs an index reflecting the difficulty of ferroelectric polarization flipping, the reverse electric field strength required for the polarization strength of the ferroelectric layer 20 to recover to zero should be appropriately reduced to reduce the working voltage. As shown in FIG. 5, the current coercive field strength is about 1.6 MV / cm, which will limit the further reduction of the working voltage of the capacitor 1. Moreover, since the continuous ferroelectric polarization flipping will cause the concentration of oxygen vacancies in the ferroelectric layer 20 to rise, and these charged defects will cause the capacitor 1 to break down after being connected.

[0071] Endurance is a performance of the capacitor 1, which determines the service life of the capacitor 1. As shown in FIG. 6, the endurance cycle of the capacitor 1 usually goes through the pristine, wake-up and fatigue periods, until breakdown or fatigue. When the capacitor 1 breaks down prematurely, it indicates that the endurance of the capacitor 1 is lower.

[0072] In most cases, oxygen vacancies will gradually accumulate at the interface between the first electrode 10 and the ferroelectric layer 20 and the interface between the second electrode 30 and the ferroelectric layer 20. When the oxygen vacancies accumulate too much, the ferroelectric polarization flipping will appear fatigue, causing the polarization to decrease and the storage window to drop, as shown in FIG. 7. The capacitor 1 first experiences the wake-up stage, and after 10 6 seconds, the fatigue phenomenon appears after the life stack point, and the storage window begins to drop. It can be understood that the storage window can be calculated by the difference between the remanent polarization strengths of the two curves at the same temperature in FIG. 7 at 10 6 seconds.

[0073] As shown in FIGS. 8 and 9, the imprint effect of the ferroelectric material will also cause the normalized polarization curve to shift, making it difficult to rewrite the storage state and causing the storage window to drop. After the capacitor 1 experiences high temperature, the imprint effect is more significant due to insufficient crystallization, and it is difficult for the capacitor 1 to maintain the storage window unchanged after 85°C and 105°C.

[0074] Based on this, as shown in FIG. 10, an embodiment of the present application provides a capacitor 1. The capacitor 1 includes a first electrode 10, a second electrode 30 and a ferroelectric layer 20 which are sequentially stacked, and the stacking direction is the Z direction, that is, the thickness direction of the capacitor 1, that is, the thickness direction of the capacitor 1.

[0075] The material of the first electrode 10 and the second electrode 30 shown in FIG. 10 can be a conductive material, such as tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), and the like. Moreover, the material of the first electrode 10 can be the same as the material of the second electrode 30, or the material of the first electrode 10 can be different from the material of the second electrode 30. That is, in the present embodiment, the capacitor 1 can be an MFM structure. In other embodiments, the capacitor 1 can be a metal-ferroelectric-semiconductor (MFS) structure.

[0076] As shown in FIG. 10, the first electrode 10 and the second electrode 30 can have the same size, for example, the first electrode 10 and the second electrode 30 can have the same size along the X direction, the first electrode 10 and the second electrode 30 can have the same size along the Y direction, and the first electrode 10 and the second electrode 30 can have the same size along the Z direction. For example, the size of the first electrode 10 and the second electrode 30 along the Z direction can range from 5 nm to 100 nm.

[0077] As shown in FIG. 10, the ferroelectric layer 20 includes a doped layer 21 and an undoped layer 22. Moreover, the ferroelectric layer 20 includes at least two undoped layers 22 and at least one doped layer 21, and each doped layer 21 is located between each adjacent two undoped layers 22. For example, as shown in FIG. 10, in the present embodiment, the ferroelectric layer 20 includes three undoped layers 22 and two doped layers 21, and each doped layer 21 is located between each adjacent two undoped layers 22. That is, the doped layer 21 closest to the first electrode 10 has a spacing with the first electrode 10, which can range from 0.1 nm to 10 nm, for example; the doped layer 21 closest to the second electrode 30 also has a spacing with the second electrode 30, which can range from 0.1 nm to 10 nm, for example; and the spacing between each adjacent two doped layers 21 can range from 0.1 nm to 20 nm, for example.

[0078] As shown in FIG. 10, the projection of the doped layer 21 on the first electrode 10 is the same as the projection of the undoped layer 22 on the first electrode 10. For example, the size of the doped layer 21 along the X direction is the same as the size of the undoped layer 22 along the X direction, and the size of the doped layer 21 along the Y direction is the same as the size of the undoped layer 22 along the Y direction.

[0079] The size of each doped layer 21 along the Z direction can be the same, for example, the size of each doped layer 21 along the Z direction can range from 0.1 nm to 5 nm, and the size of the ferroelectric layer 20 along the Z direction can range from 3 nm to 20 nm.

[0080] The ferroelectric grains are included in both the doped layer 21 and the non-doped layer 22. The material of the ferroelectric grains is a ferroelectric material, and in this embodiment, the ferroelectric material can be hafnium oxide (HfO2) or hafnium zirconium oxide (HfZrO), etc.

[0081] The doped layer 21 includes a doped element, and the doped element of the doped layer 21 can include titanium (Ti), tantalum (Ta) or niobium (Nb) which are in the same group or adjacent subgroup of hafnium. Moreover, the doped element can exist in the form of a multi-valence metal element. Since the ionic radius of these doped elements is close to that of hafnium and zirconium, the doped elements can occupy the lattice sites, interstitial sites and grain boundary defects of hafnium oxide or hafnium zirconium oxide. Alternatively, the doped elements can also exist in the form of oxides, such as titanium oxide (TiO), tantalum oxide (Ta2O5), mononibium oxide, diniobium oxide, di-niobium trioxide or di-niobium pentoxide, etc.

[0082] The doping concentration of the doped layer 21 can range from 0.1% to 30%, for example, 0.1%, 10%, 20% or 30%.

[0083] Since the ferroelectric grains are included in both the doped layer 21 and the non-doped layer 22, and the doped element is included in the doped layer 21, the doped element can be incorporated into the ferroelectric grains, and can occupy the sites of the ferroelectric grains and form bonds with oxygen, thereby effectively inhibiting the generation of charged oxygen vacancies, stabilizing the oxygen vacancies, and thus being conducive to the stability of the ferroelectric domains, the ferroelectric polarization, the promotion of the O phase, the improvement of the ferroelectric crystalline quality, and the improvement of the stability of the ferroelectric grains. Moreover, the doped element does not cut off the integrity of the ferroelectric grains.

[0084] The relevant performance parameters of the related art and the capacitor 1 of this embodiment are calculated to obtain the performance parameter comparison table shown in Table 1.

[0085] Table 1

[0086] Since the doped element has a pinning effect on the oxygen vacancies in the ferroelectric layer 20, the migration of the oxygen vacancies under the action of the electric field during the flipping of the ferroelectric domains is effectively controlled and cannot move at will, thereby improving the breakdown electric field E BD , for example, as shown in Table 1, compared with the related art, the breakdown electric field E BD of this embodiment is increased from 3.6 MV / cm to 6.27 MV / cm, thereby improving the breakdown electric field capacity, and thus improving the durability of the ferroelectric material under the same working voltage. Moreover, when the breakdown electric field capacity is improved, the service life of the capacitor 1 can also be improved.

[0087] In addition, as can be seen from Table 1, compared with the related art, the coercive field strength E Cfrom 1.6 MV / cm to 0.9 MV / cm, while the coercive field strength E C is positively correlated with the working voltage of the capacitor 1 and the device loss, so the working voltage and the device power consumption can be greatly reduced.

[0088] In addition, the breakdown probability of the capacitor 1 is positively correlated with the coercive field strength E C / E BD , and when the coercive field strength E C is reduced and the breakdown field E BD is increased, the breakdown field E BD can be appropriately reduced, and the breakdown probability is also reduced, for example, as shown in Table 1, the breakdown probability of the capacitor 1 of the embodiment is reduced from 44% to 25% compared with the related art. Thus, higher durability can be obtained. For example, as shown in Table 1, the durability of the capacitor 1 of the embodiment is improved from 10 9 times of breakdown to 10 11 times of no breakdown compared with the related art.

[0089] In addition, since the migration of oxygen vacancies under the action of the electric field is effectively controlled and cannot be moved at will, fatigue that occurs in the process of continuous flipping can be slowed down, thereby further improving the durability. The durability of the capacitor 1 of the related art and the embodiment is tested, and the durability curves shown in FIG. 12 and FIG. 13 are obtained. FIG. 12 is a durability curve of the capacitor 1 of the embodiment, and the working voltage is 2V. FIG. 13 is a durability curve of the capacitor 1 of the embodiment, and the working voltage is 1.6V. As can be seen from FIG. 12 and FIG. 13, the capacitor 1 of the related art has fatigue at 10 9 times, and the capacitor 1 of the embodiment has not yet had fatigue at 10 10 times.

[0090] In addition, the embodiment can also effectively improve the storage retention of the ferroelectric material and inhibit the imprint effect. The storage performance of the capacitor 1 of the related art and the embodiment shown in FIG. 1 is tested under the working condition of 105°C, and the storage performance comparison graphs of FIG. 14, FIG. 15, FIG. 16 and FIG. 17 are obtained. FIG. 14 shows the rewriting difficulty curves of the capacitor 1 of the related art and the embodiment at 105°C. Among them, OS represents rewriting from 0 to 1, and the earlier the OS+ curve and the OS- curve cross, the more difficult the rewriting is. As can be seen from FIG. 14, the OS+ curve and the OS- curve of the related art cross earlier, thereby indicating that the capacitor 1 of the related art is more difficult to rewrite. Moreover, the related art cannot support ten years at 105°C, while the remaining polarization of the SS+ of the capacitor 1 of the embodiment after ten years is 10.42uC / cm 2 , the remaining polarization of the SS- after ten years is -9.62uC / cm 2 , and the remaining polarization after ten years is still 10.42-(-9.62)≈20uC / cm 2 .

[0091] Figure 15 shows the storage retention curves of the capacitor 1 of the related art and the present embodiment at 105°C. In Figure 15, SS indicates the initial storage 0, and after ten years, it is still 0. Moreover, the related art SS+ remains polarized at 10.25 μC / cm 2 after ten years, and SS- remains polarized at -11.74 μC / cm 2 , and the storage window is 10.25 - (-11.74) = 21.99 μC / cm 2 . However, the present embodiment SS+ remains polarized at 20.99 μC / cm 2 after ten years, and SS- remains polarized at -19.38 μC / cm 2 , and the storage window is 20.99 - (-19.38) = 40.37 μC / cm 2 . It can be seen that the SS+ and SS- of the present embodiment remain polarized after ten years, both of which are greater than those of the related art. It can be seen that the storage retention of the present embodiment is higher. Moreover, the storage window of the present embodiment is greater than that of the related art, which can also be seen from Table 1.

[0092] Figure 16 shows the ferroelectric polarization curves of the related art and the present embodiment. Figure 16(a) is the ferroelectric polarization curve of the related art, and Figure 16(b) is the ferroelectric polarization curve of the present embodiment. As can be seen from Figure 16(a), the coercive field strength E C of the related art has a shift of -0.69 MV / cm. As can be seen from Figure 16(b), the coercive field strength E C of the present embodiment has a shift of -0.31 MV / cm.

[0093] Figure 17 shows the ferroelectric polarization curves of the related art and the present embodiment. Figure 17(a) is the ferroelectric polarization curve of the related art, and Figure 17(b) is the ferroelectric polarization curve of the present embodiment. As can be seen from Figure 17(a), the coercive field strength E C of the related art has a shift of -0.31 MV / cm. As can be seen from Figure 17(b), the coercive field strength E C of the present embodiment has a shift of -0.19 MV / cm. It should be noted that the ferroelectric polarization curves of Figure 17 and the ferroelectric polarization curves of Figure 16 are measured at different initial storage states. The temperature is 105°C. Figure 16 is the coercive field strength E C shift after storing "0", and Figure 17 is the coercive field strength E C shift after storing "1".

[0094] As can be seen from Figure 16 and Figure 17, the coercive field strength E CThe offset is smaller, that is, the ferroelectric polarization is lost less, and the effective storage window is larger. Moreover, it can also be shown that the capacitor 1 has stronger high-temperature resistance, better storage retention, and better stability at high temperature (industry level and automotive level, 85°C / 125°C).

[0095] In the process of manufacturing the capacitor 1 shown in FIG. 10, the first electrode 10, the initial ferroelectric layer 201, and the second electrode 30 can be sequentially manufactured, and then the initial ferroelectric layer 201 is subjected to a crystallization treatment to obtain the ferroelectric layer 20. The crystallization treatment is specifically that the first electrode 10, the initial ferroelectric layer 201, and the second electrode 30 are placed in a high-temperature environment for a certain time and then rapidly annealed. In the crystallization treatment process, the capacitor 1 can be caused to have poor thermal stability, resulting in changes in the storage window and the coercive field strength E C Therefore, the capacitor 1 of the related art can be subjected to a thermal stability test to obtain the ferroelectric polarization curves shown in FIG. 18. In FIG. 18, (a) is the initial ferroelectric polarization curve of the capacitor 1 of the related art, and (b) is the ferroelectric polarization curve of the capacitor 1 of the related art after being heated at 400°C for 3 hours. The capacitor 1 of the present embodiment is subjected to a thermal stability test to obtain the ferroelectric polarization curves shown in FIG. 19. In FIG. 19, (a) is the initial ferroelectric polarization curve of the capacitor 1 of the present embodiment, and (b) is the ferroelectric polarization curve of the capacitor 1 of the present embodiment after being heated at 400°C for 3 hours.

[0096] From the ferroelectric polarization curves in FIGS. 18 and 19, the results in Table 2 can be obtained.

[0097] Table 2

[0098] As can be seen from Table 2, after three hours at 400°C, the storage window 2Pr of the present embodiment has a larger remanent polarization, a smaller loss ratio of the storage window, and an effective storage window that can be maintained. Moreover, the coercive field strength change is also small and can be ignored. That is, the coercive field strength E C remains unchanged, and thus the capacitor 1 of the present embodiment has better thermal stability.

[0099] As shown in FIG. 11, the capacitor 1 has a symmetrical structure about the center surface 101, and the distance between the center surface 101 and the surface 11 of the first electrode 10 away from the second electrode 30 is the same as the distance between the center surface 101 and the surface 31 of the second electrode 30 away from the first electrode 10. Moreover, the two doped layers 21 (the first doped layer and the second doped layer) are respectively located on the two sides of the center surface 101.

[0100] As shown in Fig. 20(a), the ferroelectric polarization curve of the capacitor 1 in the asymmetric structure, it can be seen from Fig. 20(a) that +Ec is 1.33 MV / cm, -Ec is -0.61 MV / cm, the absolute values of +Ec and -Ec are different, that is, +Ec and -Ec are asymmetric, and the difference between the absolute values of +Ec and -Ec is 0.72 MV / cm. It can be seen that if the capacitor 1 is in an asymmetric structure about the center plane 101, the asymmetry of +Ec and -Ec is often caused, and thus when the positive and negative working voltages with the same absolute value are applied to the capacitor 1, the situation of uneven flipping is caused, and the situation that the storage state on one side is easy to maintain while the storage state on the other side is difficult to maintain is easily induced.

[0101] As shown in Fig. 20(b), the ferroelectric polarization curve of the capacitor 1 in the symmetric structure shown in Fig. 11. As can be seen from Fig. 20(b), +Ec is 0.96 MV / cm, -Ec is -0.96 MV / cm, the absolute values of +Ec and -Ec are the same, that is, +Ec and -Ec are symmetric. That is, the symmetry of +Ec and -Ec can be realized in the embodiment, thereby relieving the situation that the storage state on one side is difficult to maintain due to uneven flipping.

[0102] It can be understood that in actual design, the doping concentration of the doping layer 21 can be adjusted according to the position of the ferroelectric polarization curve. For example, when the ferroelectric polarization curve is right-biased, the doping concentration of the doping layer 21 close to the first electrode 10 can be increased; when the ferroelectric polarization curve is left-biased, the doping concentration of the doping layer 21 close to the second electrode 30 can be increased, thereby effectively improving the asymmetry of +Ec and -Ec.

[0103] The position of each doping layer 21 in the capacitor 1 affects the storage retention and current density (leakage) of the capacitor 1. The storage retention and current density of the capacitor 1 with three different doping layer 21 positions are tested, and the current density curve shown in Fig. 21 and the storage retention curve shown in Fig. 22 are obtained.

[0104] As shown in Fig. 11, it is assumed that the thickness of the undoped layer 22 closest to the first electrode 10 is d1, the thickness of the undoped layer 22 in the middle is d2, and the thickness of the undoped layer 22 closest to the second electrode 30 is d3. As shown in Fig. 21(a) and Fig. 22(a), d1 and d3 are both 1 nm, and d2 is 6 nm. As shown in Fig. 21(b) and Fig. 22(b), d1 and d3 are both 2 nm, and d2 is 4 nm. As shown in Fig. 23(c) and Fig. 23(c), d1 and d3 are both 3 nm, and d2 is 2 nm. It can be seen that the doping layer 21 in the capacitor 1 corresponding to Fig. 21(a) is farthest from the center plane 101, and the doping layer 21 in the capacitor 1 corresponding to Fig. 21(c) is closest to the center plane 101.

[0105] As can be seen from FIG. 21 (a), when d1 and d3 are both 1 nm and d2 is 6 nm, the current density is 1.05 A / m 2 After experiencing ten years at 105°C, the remaining storage window is 78%. As can be seen from FIG. 21 (b), when d1 and d3 are both 2 nm and d2 is 4 nm, the current density is 143.06 A / m 2 After experiencing ten years at 105°C, the remaining storage window is 84%. As can be seen from FIG. 21 (c), when d1 and d3 are both 3 nm and d2 is 2 nm, the current density is 1297.44 A / m 2 After experiencing ten years at 105°C, the remaining storage window is 71%. As can be seen from FIG. 21 (c), the closer the doping layer 21 is to the center plane 101, the greater the current density and the smaller the imprint effect, which shows that the closer the doping layer 21 is to the center plane 101, the better the imprint effect can be alleviated. As can be seen from FIG. 21 (a), the farther the doping layer 21 is from the center plane 101, the worse the effect of alleviating the imprint effect.

[0106] As can be seen from FIG. 22 (a), the remaining polarization after SS+ ten years is 18.68 uC / cm 2 , the remaining polarization after SS- ten years is -20.04 uC / cm 2 . As can be seen from FIG. 22 (a), the remaining polarization after SS+ ten years is 11.34 uC / cm 2 , the remaining polarization after SS- ten years is -14.97 uC / cm 2 . As can be seen from FIG. 22 (c), the remaining polarization after SS+ ten years is 5.99 uC / cm 2 , the remaining polarization after SS- ten years is -9.86 uC / cm 2 . As can be seen from FIG. 22 (c), the closer the doping layer 21 is to the center plane 101, the worse the domain continuity of the undoped layer 22, the greater the difficulty of crystallization, and the greater the reduction of the remaining polarization. Moreover, the lack of control of oxygen vacancies near the interface between the first electrode 10 and the undoped layer 22 increases the depolarization field, which is not conducive to the retention of the storage state. As can be seen from FIG. 22 (a), the farther the doping layer 21 is from the center plane 101, the more conducive to the retention of the storage state.

[0107] Therefore, when the thickness of the undoped layer 22 between the two doping layers 21 is moderate, for example, 3 nm-5 nm, specifically 4 nm, the retention of the storage state and the alleviation of the imprint effect can be simultaneously considered.

[0108] In other embodiments of the present application, as shown in FIG. 23, the difference between the embodiment shown in FIG. 23 and the embodiment shown in FIG. 10 is that the capacitor 1 of the embodiment shown in FIG. 23 is asymmetric about the center plane 101. Specifically, as shown in FIG. 23, in the embodiment shown in FIG. 23, the distance between the doped layer 21 closest to the first electrode 10 and the surface 11 is greater than the distance between the doped layer 21 closest to the second electrode 30 and the surface 31. In other embodiments, the two doped layers 21 can be located on the same side of the center plane 101.

[0109] In other embodiments of the present application, as shown in FIG. 24, the difference between the embodiment shown in FIG. 24 and the embodiment shown in FIG. 10 is that the number of layers of the doped layer 21 and the undoped layer 22 in the ferroelectric layer 20 is different. Specifically, in the embodiment shown in FIG. 24, the ferroelectric layer 20 includes two undoped layers 22 and one doped layer 21, and the doped layer 21 is located between the two undoped layers 22.

[0110] In other embodiments of the present application, as shown in FIG. 25, the difference between the embodiment shown in FIG. 25 and the embodiment shown in FIG. 10 is that the stacking direction of the first electrode 10, the ferroelectric layer 20 and the second electrode 30 is different. Specifically, in the embodiment shown in FIG. 25, as shown in FIG. 26, the first electrode 10, the ferroelectric layer 20 and the second electrode 30 are stacked along the X direction, i.e., stacked along the length or width direction of the memory.

[0111] In other embodiments of the present application, as shown in FIG. 26, the difference between the embodiment shown in FIG. 26 and the embodiment shown in FIG. 10 is that the structure of the embodiment shown in FIG. 26 is different. Specifically, in the embodiment shown in FIG. 26, as shown in FIG. 26, the second electrode 30 is arranged around the first electrode 10, and three undoped layers 22 and two doped layers 21 are arranged around the first electrode 10 and the second electrode 30. Moreover, the first electrode 10, the ferroelectric layer 20 and the second electrode 30 all form a ring-shaped quadrilateral.

[0112] In other embodiments of the present application, as shown in FIG. 27, the difference between the embodiment shown in FIG. 27 and the embodiment shown in FIG. 28 is that the shape of the embodiment shown in FIG. 27 is different. Specifically, as shown in FIG. 27, the first electrode 10, the ferroelectric layer 20 and the second electrode 30 all form a circular ring shape.

[0113] In other embodiments of the present application, as shown in FIG. 28, the difference between the embodiment shown in FIG. 28 and the embodiment shown in FIG. 10 is that the embodiment shown in FIG. 28 adds a first conductive layer 40 and a second conductive layer 50 to the embodiment shown in FIG. 10. The first conductive layer 40 is located between the first electrode 10 and the ferroelectric layer 20, and the second conductive layer 50 is located between the second electrode 30 and the ferroelectric layer 20. Moreover, the thickness of the first conductive layer 40 and the second conductive layer 50 can be the same, and the material of the first conductive layer 40 and the second conductive layer 50 can be Nb2O5, Ta2O5 or V2O5, etc.

[0114] The embodiment of the present application further provides a manufacturing method of the capacitor 1, which can be applied to the capacitor 1 shown in FIG. 10. As shown in FIG. 29, the manufacturing method can include the following steps.

[0115] S61, manufacturing the first electrode.

[0116] The first electrode 10 shown in FIG. 30(a) can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) and the like.

[0117] S62, manufacturing the initial ferroelectric layer on the first electrode.

[0118] As shown in FIG. 30(b), the initial ferroelectric layer 201 includes two initial doping layers 210 and three initial undoped layers 220. The initial undoped layer 220 includes ferroelectric grains, and the material of the ferroelectric grains is ferroelectric material. Specifically, in the embodiment, the ferroelectric material can be hafnium oxide (HfO2) or hafnium zirconium oxide (HfZrO) and the like.

[0119] The initial doping layer 210 includes doping elements, and the doping elements of the initial doping layer 210 can include titanium (Ti), tantalum (Ta) or niobium (Nb) which are in the same group or adjacent subgroup of hafnium.

[0120] The spacing between the initial doping layer 210 closest to the first electrode 10 and the first electrode 10 ranges from 0.1 nm to 10 nm. If the spacing between the two is less than 0.1 nm, the spacing between the two is too small, which causes the doping elements in the initial doping layer 210 to diffuse to the first electrode 10 during subsequent crystallization processing, thereby affecting the normal use of the capacitor 1. If the spacing between the two is greater than 10 nm, the spacing between the two is too large, which causes the thickness of the capacitor 1 to be too large, thereby increasing the volume of the capacitor 1 and reducing the power density of the capacitor 1. Therefore, when the spacing between the two ranges from 0.1 nm to 10 nm, the normal use of the capacitor 1 can be ensured, and the power density of the capacitor 1 can be improved.

[0121] The interval between the two adjacent initial undoped layers 220 ranges from 0.1 nm to 20 nm. If the interval between the two is less than 0.1 nm, the interval between the two is too small, thus resulting in that the thickness of the initial doped layer 210 between the two adjacent initial undoped layers 220 is too small to effectively control the migration of oxygen vacancies. If the interval between the two is greater than 20 nm, the interval between the two is too large, thus resulting in that the thickness of the capacitor 1 is too large, which in turn increases the volume of the capacitor 1 and reduces the power density of the capacitor 1. Therefore, when the interval between the two ranges from 0.1 nm to 20 nm, the migration of oxygen vacancies can be effectively controlled, and the power density of the capacitor 1 can be improved.

[0122] S63, a second electrode is made on the initial ferroelectric layer.

[0123] As shown in (c) of FIG. 30, a second electrode 30 is made on the initial undoped layer 220 of the initial ferroelectric layer 201 farthest from the first electrode 10. The interval between the initial doped layer 210 closest to the second electrode 30 and the second electrode 30 ranges from 0.1 nm to 10 nm. If the interval between the two is less than 0.1 nm, the interval between the two is too small, thus resulting in that, during the subsequent crystallization process, the doped elements in the initial doped layer 210 diffuse to the first electrode 10, which affects the normal use of the capacitor 1. If the interval between the two is greater than 10 nm, the interval between the two is too large, thus resulting in that the thickness of the capacitor 1 is too large, which in turn increases the volume of the capacitor 1 and reduces the power density of the capacitor 1. Therefore, when the interval between the two ranges from 0.1 nm to 10 nm, the normal use of the capacitor 1 can be ensured, and the power density of the capacitor 1 can be improved.

[0124] S64, the initial ferroelectric layer is subjected to a crystallization process to obtain a ferroelectric layer.

[0125] As shown in (d) of FIG. 30, after the initial ferroelectric layer 201 is subjected to the crystallization process, the doped elements in the initial doped layer (the dashed area shown in (d) of FIG. 30) diffuse into the initial undoped layer 220, that is, the thickness of the doped layer 21 obtained after the initial doped layer is subjected to the crystallization process is greater than the thickness of the initial doped layer 210. The ferroelectric grains in the initial undoped layer also diffuse into the initial doped layer after the crystallization process, thus spreading throughout the entire ferroelectric layer 20.

[0126] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the specific embodiments described above, which are only illustrative but not restrictive, and a person of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope protected by the claims.

Claims

1. A capacitor characterized by, The capacitor comprises: a first electrode, a second electrode, and a ferroelectric layer between the first electrode and the second electrode, the ferroelectric layer comprising a doped layer and a non-doped layer, and each of the doped layer and the non-doped layer comprising ferroelectric grains.

2. The capacitor of claim 1, wherein The ferroelectric layer comprises at least two layers of the non-doped layer and at least one layer of the doped layer, and each layer of the doped layer is between each two adjacent layers of the non-doped layer.

3. The capacitor of claim 2, wherein The first electrode and the second electrode are stacked, and at least two layers of the non-doped layer and at least one layer of the doped layer are stacked between the first electrode and the second electrode.

4. The capacitor of claim 2, wherein The second electrode surrounds the first electrode, and at least two layers of the non-doped layer and at least one layer of the doped layer are stacked between the first electrode and the second electrode.

5. The capacitor according to any one of claims 2 to 4, wherein The capacitor has a symmetric structure with respect to a center plane, and the distance between the center plane and the surface of the first electrode away from the second electrode is the same as the distance between the center plane and the surface of the second electrode away from the first electrode.

6. The capacitor of claim 5, wherein The ferroelectric layer comprises a first doped layer and a second doped layer on both sides of the center plane, and the thickness of the non-doped layer between the first doped layer and the second doped layer ranges from 3 nm to 5 nm.

7. The capacitor of any one of claims 2-4, wherein, The ferroelectric layer comprises a first doped layer and a second doped layer, and the first doped layer and the second doped layer have an asymmetric structure with respect to a center plane.

8. The capacitor of any one of claims 1-7, wherein, The projection of the doped layer on the first electrode is the same as the projection of the non-doped layer on the first electrode.

9. The capacitor of any one of claims 1-8, wherein, The material of the non-doped layer comprises hafnium oxide or hafnium zirconium oxide, and the doping element of the doped layer comprises titanium, tantalum, or niobium.

10. The capacitor of any one of claims 1-9, wherein, The capacitor further comprises a first conductive layer between the first electrode and the ferroelectric layer, and a second conductive layer between the second electrode and the ferroelectric layer.

11. A memory array comprising: The capacitor comprises a switch tube and any one of claims 1-10, and the switch tube is electrically connected to the capacitor.

12. A memory, comprising: The storage array comprises a controller and claim 11, and the controller is electrically connected to the storage array.

13. An electronic device, comprising: The memory comprises a circuit board and claim 12, and the circuit board is electrically connected to the memory.

14. A method of fabricating a capacitor, comprising: The manufacturing method comprises: manufacturing a first electrode; manufacturing an initial ferroelectric layer on the first electrode, the initial ferroelectric layer comprising an initial non-doped layer and an initial doped layer stacked, the initial non-doped layer comprising ferroelectric grains, and the initial doped layer comprising a doping element; manufacturing a second electrode on the initial ferroelectric layer; performing crystallization treatment on the initial ferroelectric layer to obtain a ferroelectric layer, the ferroelectric layer comprising a non-doped layer and a doped layer, each of the non-doped layer and the doped layer comprising ferroelectric grains, and the doped layer comprising a doping element.

15. The method of manufacturing according to claim 14, wherein, The distance between the initial doped layer closest to the first electrode and the first electrode ranges from 0.1 nm to 10 nm, and the distance between the initial doped layer closest to the second electrode and the second electrode ranges from 0.1 nm to 10 nm.

16. The production method according to claim 14 or 15, characterized by, The initial ferroelectric layer comprises at least two layers of the initial undoped layers stacked and spaced, and the spacing between two adjacent initial undoped layers ranges from 0.1 nm to 20 nm.

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