Optimized configuration for output power maximization of thermoelectric generator arrays

Abstract

An optimized static configuration approach can reallocate thermoelectric generator (TEG) modules without exchanging electrical connections to maintain a constant temperature gradient between strings. For example, a method can involve arranging an array of TEGs in an initial state. The method can further include assigning, for each TEG in the array of TEGs, a number based on a location of the TEG within the array. Additionally, the method can involve determining an arrangement of the array of TEGs. The rearrangement can be consistent with constraints of a combinatorial number placement procedure. The rearrangement can reduce a nonuniformity of a temperature distribution associated with the array of TEGs. The method can involve reconfiguring the array to match the rearrangement. Each of rows and each of columns of the reconfigured array can include TEGs with unique assigned numbers within each row or each column.

Description

OPTIMIZED CONFIGURATION FOR OUTPUT POWER MAXIMIZATION OF THERMOELECTRIC GENERATOR ARRAYSCROSS-REFERENCES TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Patent ApplicationNo. 63 / 631,034, filed April 8, 2024, the entire contents of which are hereby incorporated by reference for all purposes in its entirety.BACKGROUND OF THE INVENTION

[0002] An interest in reaching lower Greenhouse Gas (GHG) emissions can spur innovation of numerous green energy sources. Among these sources, a thermoelectric generator (TEG) device can be an environment friendly innovative solution. TEG devices can directly generate electric power via wasted heat without any chemical reaction or emission. Hence, employing the TEG can become notable in waste heat recovery applications such as automotive, hybrid solar-hydrogen, and geothermal-hydrogen-based systems to use generated electricity to run electrolyzers. Nevertheless, in practical applications, a TEG system can suffer from poor conversion efficiency due to an exposure to nonuniform temperature distributions (NUTDs) in many applications.

[0003] To maximize an output power of TEG arrays, several of maximum power point (MPP) tracking approaches have been developed. For example, approaches such as perturb and observe (P&O), Incremental conductance (IC), open-circuit voltage (OCV), and a set of stochastic-based techniques exist. An instantaneous linear extrapolation (ILE) MPP tracking technique can be used to identify a voltage at the MPP. An advanced MPP tracking controller based on a non-linear sliding mode variable structure control approach can be adopted. A linear extrapolation of two measurable points can identify the OCV and short circuit current (SCC) and then determine a duty cycle at the MPP. However, these proposed MPP tracking approaches can show an efficient performance under uniform temperature distribution; resultant multi-peaks on the TEG array characteristics under NUTD can easily drive the multipeaks into a local MPP. Some approaches, such as a dynamic array reconfiguration approach, can re-configure TEG modules to maintain consistent temperature distribution over the array.

[0004] The dynamic array reconfiguration approach developed for TEG arrays can dynamically alert electric connections of modules of the array through a set of switches without changing physical locations to enhance an overall generated power. For example, a methodology incorporating an improved immune genetic algorithm can promote produced power of the TEG array via reconfiguring array architecture dynamically with a change in temperature distribution profiles. Another approach can tailor an improved cooperation search algorithm to dynamically reconfigure the TEG array by using two switch matrices to mitigate negative effects of a heterogeneous heat distribution. Furthermore, a particle swarm optimization can be applied for some dynamic reconfiguration approaches. An adaptive coordinated seeker can enhance TEG array harvested energy under NUTD. A Lagrange multiplier optimization method can be employed to evaluate sizes of switches in a switch matrix used with a reconfigured TEG array such that an array generated power can be maximized. A jellyfish search algorithm can be adopted to dynamically determine an optimal layout of the TEG array with temperature distribution changes.

[0005] Dynamic reconfiguration of TEG arrays may be the most common technique utilized to maximize output power of TEG under NUTD. The dynamic reconfiguration of TEG arrays, however, may face serious implementation challenges when TEG arrays are scaled up. In particular, costs and complexity of dynamic reconfiguration for TEG arrays may increase with an increase of TEG modules and / or arrays as a large number of switches and sensors may need to be installed and dynamically reconfigured. Further, excessive switching actions may occur in applications at which a temperature distribution changes sporadically. The excessive switching actions can, in turn, cause wear and tear of switches. Moreover, installed switches and sensors can be in close contact with a TEG array zone and hence the switches and sensors may be often exposed to high-temperature levels, which can lead to exhausting maintenance requirements. To alleviate drawbacks of dynamic reconfiguration, there may be a need to optimize a static configuration of TEGs exposed to different temperature distribution profiles.BRIEF SUMMARY OF THE INVENTION

[0006] An optimized static configuration (OSC) approach can reallocate thermoelectric generator (TEG) modules without exchanging electrical connections to maintain a constant temperature gradient between strings. For example, a method described herein can involve arranging an array of TEGs in an initial state. The array can include M rows and N columns.The method can further include assigning, for each TEG in the array of TEGs, a number based on a location of the TEG within the array. Additionally, the method can involve determining an arrangement of the array of TEGs. The rearrangement can be consistent with constraints of a combinatorial number placement procedure. The rearrangement can reduce a nonuniformity of a temperature distribution associated with the array of TEGs. The method can involve reconfiguring the array to match the rearrangement. Each of the M rows and each of the N columns of the reconfigured array can include TEGs with unique assigned numbers within each row or each column.

[0007] In another example, a system described herein can include an array of thermoelectric generators (TEGs). The array can include M rows and N columns. The array can be reconfigured to match a rearrangement consistent with constraints of a combinatorial number placement procedure. The rearrangement can reduce a nonuniformity of a temperature distribution associated with the array of TEGs. The system can further include a computing device. The computing device can include a processor and a memory. The memory can include instructions executable by the processor for causing the processor to perform operations. The operations can include assigning, for each TEG in an initial state of the array of TEGs, a number based on a location of each TEG within the array. The operations can further include determining the rearrangement of the array of TEGs. The rearrangement of the array can include TEGs with unique assigned numbers within each row or each column.

[0008] In another example, a non-transitory computer-readable medium described within can include instructions that are executable by a processor for causing the processor to perform operations. The operations can include assigning for each TEG in an initial state of an array of TEGs, a number based on a location of each TEG within the array. The array can include M rows and N columns. The operations can further include determining a rearrangement of the array of TEGs. The rearrangement can be consistent with constraints of a combinatorial number placement procedure. The rearrangement can reduce a nonuniformity of a temperature distribution associated with the array of TEGs. Each of the M rows and each of the N columns of the rearrangement can include TEGs with unique assigned numbers within each row or each column.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1A is a schematic of a hybrid solar-hydrogen system according to certain aspects of the present disclosure.

[0010] FIG. IB is an internal microimage of a TEG according to certain aspects of the present disclosure.

[0011] FIG. 1C is a schematic of a set of TEG modules connected in a series-parallel (SP) design according to certain aspects of the present disclosure.

[0012] FIG. ID is a schematic of an equivalent circuit for a single TEG module according to certain aspects of the present disclosure.

[0013] FIG. IE is a schematic of an equivalent circuit for a string of TEG modules connected in series according to certain aspects of the present disclosure.

[0014] FIG. IF is a schematic of an equivalent current source connected in parallel with a corresponding internal resistance according to certain aspects of the present disclosure.

[0015] FIG. 1G is a schematic of a circuit for a TEG array composed from N parallel strings with N series TEG modules according to certain aspects of the present disclosure.

[0016] FIG. 1H is a schematic of an equivalent circuit for a TEG array composed from N parallel strings with N series TEG modules according to certain aspects of the present disclosure.

[0017] FIG. 2A is a schematic of a Soduku puzzle layout for a 6 X 6 matrix array according to certain aspects of the present disclosure.

[0018] FIG. 2B is a schematic of a Soduku puzzle layout for a 9 X 9 matrix array according to certain aspects of the present disclosure.

[0019] FIG. 3A is a schematic of a series-parallel SP TEG array in an initial state according to certain aspects of the present disclosure.

[0020] FIG. 3B is a schematic of a TEG array with modules moved to locations consistent with a Soduku puzzle layout according to certain aspects of the present disclosure.

[0021] FIG. 3C is a schematic depicting physical relocations of two TEG modules of a TEG array consistent with a Soduku puzzle layout according to certain aspects of the present disclosure.

[0022] FIG. 3D is a schematic of a TEG array consistent with a Soduku puzzle layout with a modified temperature distribution according to certain aspects of the present disclosure.

[0023] FIG. 3E is an exemplary plot of voltage and power versus current characteristics for a SP TEG array in an initial state and a TEG after rearranged using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure.

[0024] FIG. 4 is a flow chart of a process for reconfiguring an array of TEGs consistent with an OSC approach according to certain aspects of the present disclosure.

[0025] FIG. 5 is a block diagram of a computing device for determining a rearrangement, consistent with an OSC approach, of an array of TEGs according to certain aspects of the present disclosure.

[0026] FIG. 6A is a schematic of a 6 X 6 TEG array in an initial state with a long narrow nonuniform temperature distribution (NUTD) according to certain aspects of the present disclosure.

[0027] FIG. 6B is a schematic of a 6 x 6 TEG array in an initial state with a long wide nonuniform temperature distribution (NUTD) according to certain aspects of the present disclosure.

[0028] FIG. 6C is a schematic of a 6 x 6 TEG array in an initial state with a non- homogenous nonuniform temperature distribution (NUTD) according to certain aspects of the present disclosure.

[0029] FIG. 6D is a schematic of a 6 X 6 TEG array with an initial long narrow nonuniform temperature distribution (NUTD) reconfigured using an OSC approach according to certain aspects of the present disclosure.

[0030] FIG. 6E is a schematic of a 6 X 6 TEG array with an initial long wide nonuniform temperature distribution (NUTD) reconfigured using an OSC approach according to certain aspects of the present disclosure.

[0031] FIG. 6F is a schematic of a 6 X 6 TEG array with an initial non-homogenous nonuniform temperature distribution (NUTD) reconfigured using an OSC approach according to certain aspects of the present disclosure.

[0032] FIG. 7A is an exemplary plot of voltage and power versus current characteristics for a 6 X 6 SP TEG array in an initial state with a long narrow NUTD and a corresponding TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure.

[0033] FIG. 7B is an exemplary plot of voltage and power versus current characteristics for a 6 x 6 SP TEG array in an initial state with a long wide NUTD and a corresponding TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure.

[0034] FIG. 7C is an exemplary plot of voltage and power versus current characteristics for a 6 X 6 SP TEG array in an initial state with a non-homogenous NUTD and a corresponding TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure.

[0035] FIG. 8A is a schematic of a 9 x 9 TEG array in an initial state with a NUTD across rows according to certain aspects of the present disclosure.

[0036] FIG. 8B is a schematic of a 9 x 9 TEG array in an initial state with a NUTD across columns according to certain aspects of the present disclosure.

[0037] FIG. 8C is a schematic of a 9 x 9 TEG array in an initial state with a short wide NUTD according to certain aspects of the present disclosure.

[0038] FIG. 8D is a schematic of a 9 x 9 TEG array in an initial state with a diagonal NUTD according to certain aspects of the present disclosure.

[0039] FIG. 8E is a schematic of a 9 X 9 TEG array in an initial state with an internal NUTD according to certain aspects of the present disclosure.

[0040] FIG. 8F is a schematic of a 9 X 9 TEG array in an initial state with a random NUTD according to certain aspects of the present disclosure.

[0041] FIG. 8G is a schematic of a 9 x 9 TEG array with an initial NUTD across rows reconfigured using an OSC approach according to certain aspects of the present disclosure.

[0042] FIG. 8H is a schematic of a 9 X 9 TEG array with an initial NUTD across columns reconfigured using an OSC approach according to certain aspects of the present disclosure.

[0043] FIG. 81 is a schematic of a 9 X 9 TEG array with an initial short wide NUTD reconfigured using an OSC approach according to certain aspects of the present disclosure.

[0044] FIG. 8J is a schematic of a 9 x 9 TEG array with an initial diagonal NUTD reconfigured using an OSC approach according to certain aspects of the present disclosure.

[0045] FIG. 8K is a schematic of a 9 X 9 TEG array with an initial internal NUTD reconfigured using an OSC approach according to certain aspects of the present disclosure.

[0046] FIG. 8L is a schematic of a 9 X 9 TEG array with an initial random NUTD reconfigured using an OSC approach according to certain aspects of the present disclosure.

[0047] FIG. 9A is an exemplary plot of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with a NUTD across rows and a corresponding TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure.

[0048] FIG. 9B is an exemplary plot of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with a NUTD across columns and a corresponding TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure.

[0049] FIG. 9C is an exemplary plot of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with a short wide NUTD and a corresponding TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure.

[0050] FIG. 9D is an exemplary plot of voltage and power versus current characteristics for a 9 x 9 SP TEG array in an initial state with a diagonal NUTD and a corresponding TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure.

[0051] FIG. 9E is an exemplary plot of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with an internal NUTD and a corresponding TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure.

[0052] FIG. 9F is an exemplary plot of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with a random NUTD and a corresponding TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure.

[0053] FIG. 10A is an exemplary plot of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with a NUTD across rows after rearrangement usingan optimized static configuration (OSC) approach and a dynamic reconfiguration approach according to certain aspects of the present disclosure.

[0054] FIG. 1 OB is an exemplary plot of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with a NUTD across columns after rearrangement using an optimized static configuration (OSC) approach and a dynamic reconfiguration approach according to certain aspects of the present disclosure.

[0055] FIG. 10C is an exemplary plot of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with a short wide NUTD after rearrangement using an optimized static configuration (OSC) approach and a dynamic reconfiguration approach according to certain aspects of the present disclosure.

[0056] FIG. 10D is an exemplary plot of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with a diagonal NUTD after rearrangement using an optimized static configuration (OSC) approach and a dynamic reconfiguration approach according to certain aspects of the present disclosure.

[0057] FIG. 10E is an exemplary plot of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with an internal NUTD after rearrangement using an optimized static configuration (OSC) approach and a reconfiguration approach according to certain aspects of the present disclosure.

[0058] FIG. 10F is an exemplary plot of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with a random NUTD after rearrangement using an optimized static configuration (OSC) approach and a dynamic reconfiguration approach according to certain aspects of the present disclosure.

[0059] FIG. 11 is a schematic of an experimental setup for a 4 x 4 TEG array according to certain aspects of the present disclosure.

[0060] FIG. 12A-12P are schematics of initial states and reconfigured states for a 4 x 4 TEG array subject to various initial NUTDs according to certain aspects of the present disclosure.

[0061] FIG. 13A-13H are exemplary plots of voltage and power versus current characteristics for a 4 x 4 SP TEG array in various initial NUTD states before and afterrearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure.DETAILED DESCRIPTION OF THE INVENTION

[0062] NomenclatureAbbreviationsTEG thermoelectric generatorMPP maximum power pointNUTD nonuniform temperature distributionGHG greenhouse gasIndices and Sets i. j indices for TEG array rows and columnsNotation| #max |maximumvalue of variable #Parameters and variablesM X N dimension of a TEG arrayAT temperature differenceVoc. . open circuit voltage of TEG module at ithrow and jthcolumn (V)RM.. internal resistance of TEG module at itflrow and jtflcolumn (fl)Itj output current of TEG module at itflrow and jtflcolumn (A)PM. ■ output power of TEG module at ithrow and jthcolumn (Id / )Thtemperature of TEG module hot side (°C) asSeebeck coefficient (— )Tctemperature of TEG module cold side (°C)P^^ maximum power of TEG module at ithrow and jthcolumn (IV)Vs. open circuit voltage of jthTEG string (V)Rs. total internal resistance of jtflTEG string (fl)RAtotal internal resistance of (M x N) TEG array (fl)VAopen circuit voltage of (M x N) TEG array (V)RLload resistance (fl) pmax maximum power of (M X N) TEG array (IV)Yya binary number that stands for a state of a series diode in a ythcolumnPij a binary number that stands for a state of a bypass diode in the Ithrow and jtflcolumnI total current of (M X N) TEG array Ij current source of the jtflTEG string

[0063] Certain aspects and examples of the present disclosure relate to an optimized static configuration (OSC) for TEG modules. The TEG modules in the OSC can be physically reallocated without exchanging electric connections in an original TEG array to maintain a constant temperature gradient between strings. An OSC approach can be formulated as a combinatorial number placement procedure, such as a Sudoku puzzle resolving procedure, to obtain a unique TEG array design that fits multiple NUTD. To evaluate an efficiency of the OSC approach, harvested power of two TEG arrays (with 6x6 and 9x9 sizes, as one illustrative example) can be modeled and compared with an output power of an original series-parallel (SP) TEG array design with several NUTD profiles. A percentage of power enhancements can be obtained through implementing the OSC approach can be computed as a validation metric. Recorded results can affirm significant enhancements of yielded output power using the OSC approach. Results of the OSC approach can be compared with results from a dynamic reconfiguration approach. A comparative analysis can highlight specific requirements for dynamic configuration such as switches, system complexity, a capacity to disperse a nonuniformity of temperature distribution, and, eventually, excessive running expenses.

[0064] The OSC approach provides many advantages / characteristics. For example, the OSC approach can lead to a designed TEG layout that can maximize array power output when exposed to different patterns of NUTDs. In an example, the combinatorial number placement procedure of the OSC approach for TEG arrays can be formalized as a procedure to resolve Soduku puzzle.

[0065] In the following description, various embodiments will be described. For purposes of explanation, specific configurations and details are set forth in order to provide a thorough understanding of the embodiments. However, it will also be apparent to one skilled in the art that the embodiments may be practiced without the specific details. Furthermore, well-known features may be omitted or simplified in order not to obscure the embodiment being described.

[0066] A TEG can be a semiconductor-based device that directly converts a temperature difference between two sides, named cold and hot sides, into electric energy through a phenomenon named a Seebeck effect. FIG. 1A is a schematic of a hybrid solar-hydrogensystem according to certain aspects of the present disclosure. The TEG can be integrated into several applications as a promising solution for converting waste heat to electricity, such as the hybrid solar-hydrogen system depicted shown in FIG. 1 A. As depicted in the figure, generated electricity can be employed to run an associated Proton Exchange Membrane Electrolyzer (PEME). FIG. IB is an internal microimage of a TEG according to certain aspects of the present disclosure. The inside of a TEG can include a group of thermoelectric couple units; each of the thermoelectric couple units can have two semiconductor pins (one doped N-type and another doped P-type). The thermoelectric couple units can be connected in series with conductive metal strips between each pair of thermoelectric couple units. An output power for TEGs can vary depending on i) how a TEG array is configured and ii) operating conditions associated with temperature, e.g., uniform temperature versus nonuniform temperature, etc. Therefore, generated power from one TEG module can be insufficient to run the PEME. FIG. 1C is a schematic of a set of TEG modules connected in a series-parallel (SP) design according to certain aspects of the present disclosure. The set of TEG modules can be used and modified to obtain certain voltage and power capacity levels. FIG. ID is a schematic of an equivalent circuit for a single TEG module according to certain aspects of the present disclosure. The single TEG module can be electrically modeled as a voltage source in series with an equivalent resistance. Using Kirchhoff Voltage law, voltage measured at a terminal of the TEG module can be given as:where Voc.. and RMijrefer to an open circuit voltage and an internal resistance for a TEG module located at an Ithrow and jthcolumn respectively. Note i = 1 and j = n for a highlighted module in FIG. 1C. Values of VocI. J . and RMI.J . can be temperature dependent.

[0067] The open circuit voltage can be proportional to a Seebeck coefficient, which can vary with a Thomass coefficient. Thus, a second-order polynomial curve fitting approach can describe a change of the open circuit voltage and the internal resistance with a temperature difference as given in (2) and (3), respectively:where asis the Seebeck coefficient and AT is a temperature difference between hot (Tft) and cold (Tc) sides of the TEG module. The coefficients (with units) a ,and f( ~) are constant coefficients that can vary for each TEG. Values of these coefficients can be found to be —7 x 10-5, 0.0649, —0.9553, —9 x 10-6, 0.0065, and 1.1734.

[0068] When a load (e.g., RLas in FIG. ID) is connected to terminals of a TEG array, current flowing through a TEG module and a corresponding produced power can be computed from (4) and (5) as follows:are the output current and power of the TEG module located at an Ithrow and jthcolumn respectively. An expressioncan be a convex quadratic function. The TEG can apply a maximum value of P^ when the load resistance equals the internal resistance, as concluded from maximizing Ptj in part by taking a derivative of (5) with respect to RL. The maximum value of the output power generated by the TEG module can be expressed as:

[0069] Voltage and current values of a set of TEG modules (e.g., the shaded set of TEG modules in FIG. 1C) connected in series to form a string can be computed from (7) and (8), as follows:where n is a total number of rows (series modules) of the TEG array shown in FIG 1c and pL-j is a binary number that defines a state of a bypass diode in the Ithrow and jthcolumn. FIG.IE is a schematic of an equivalent circuit for a string of TEG modules connected in series according to certain aspects of the present disclosure. FIG. IF is a schematic of an equivalent current source connected in parallel with a corresponding internal resistance according to certain aspects of the present disclosure. According to Thevenin’s theorem, each string of the TEG array can be represented with an equivalent current source connected in parallel with a corresponding internal resistance, thus the circuit depicted in FIG. IE is equivalent to the circuit depicted in FIG. IF. Using Eqs.7 and 8, a value of the equivalent current source of jth string is expressed as:

[0070] FIG. 1G is a schematic of a circuit for a TEG array composed from N parallel strings with N series TEG modules according to certain aspects of the present disclosure. FIG. 1H is a schematic of an equivalent circuit for a TEG array composed from N parallel strings with N series TEG modules according to certain aspects of the present disclosure. Based on previous relations and equivalent circuits, overall current and resistance values for an entire TEG array composed from N parallel strings with N series TEG modules (e.g., an IV x IV TEG array as shown in FIG.1 C) can be expressed by ( 10) and (11) and represented by the equivalent circuit ofFIG. 1G:where N is the total number of columns in the TEG array, y, is a binary number that can stanc for a state of a series diode (blocking diode) in the jthcolumn. Using Eqs. (10) and (11), an array voltage and a maximum generated output power by the TEG array can be computed as (12) and (13):where a product of I and RAcan represent a total terminal voltage VAof the TEG array.

[0071] Sudoku can be a logic-based number-placement puzzle. An IV x IV Sudoku layout can contain M number of n X m submatrices, and every row, column, and matrix can accommodate unique digits from 1 to M without repeating any number. FIG. 2A is a schematic of a Soduku puzzle layout for a 6 x 6 matrix array according to certain aspects of the present disclosure. The Sudoku puzzle layout can have six 2 X 3 submatrices, and every row, column, and submatrix can have unique digits from 1 to 6 without repeating any number. FIG. 2B is a schematic of a Soduku puzzle layout for a 9 x 9 matrix array according to certain aspects of the present disclosure. In FIG. 2B, the Soduku puzzle layout can have nine 3 x 3 submatrices. Every row, column, and submatrix of the 9 x 9 array can have unique values without repetition. Main steps and constraints associated with Soduku layouts can be summarized as: i) every marked submatrix shown in FIG. 2A and FIG. 2B can include a unique digit and ii) each cell in a row or column may only contain a unique digit from 1 to IV. Soduku layout constraints for an A x A matrix can be mathematically expressed as:

[0072] For the 6 X 6 matrix array of FIG. 2A, a following constraint is satisfied:

[0073] For the 9 X 9 matrix array of FIG. 2B, a following constraint is satisfied:

[0074] To illustrate a methodology of configuring an SP TEG array based on Sudoku layouts from FIG. 2A and FIG. 2B, a 6 x 6 array can be considered as an example for visualizing a Soduku layout approach, as illustrated in FIGs. 3A-3E. An electrical connection of TEG modules can remain in associated nodes as connected in an original SP array. However, a physical location of TEG modules can be changed. FIG. 3 A is a schematic of a series-parallel SP TEG array in an initial state according to certain aspects of the present disclosure. The SPTEG can include a regular order of TEG modules. A TEG module can have a number 6 in row 1 (Rl) to point to a location of the module in a sixth column (string) in a first row (a first module in a sixth string). Similarly, a TEG module with a number 1 in row 2 (R2) can refer to a TEG module location in a first string in a second row (a second module in a first string).

[0075] A temperature distribution associated with the SP TEG array can be non-uniform. Different strings of the SP TEG array can have different temperature profiles. For example, four of the TEG modules (e.g., a module at Rl and Cl, a module at Rl and C2, a module at R2 and Cl, and a module at R2 and C2) in the SP TEG array can each have a temperature of 95°C. Another four TEG modules (e.g., a module located at R3 and Cl, a module at R3 and C2, a module at R4 and Cl, and a module at R4 and C2) in the SP TEG array can each have a temperature of 125°C. Another set of four TEG modules (e.g., a module located at R5 and Cl, a module at R5 and C2, a module at R6 and Cl, and a module at R6 and C2) in the SP TEG array can each have a temperature of 105°C. Lastly, remaining modules (e.g., all modules in strings 3-6) in the SP TEG array can each have a temperature of 200°C.

[0076] FIG. 3B is a schematic of a TEG with modules moved to locations consistent with a Soduku puzzle layout according to certain aspects of the present disclosure. The TEG modules in FIG. 3B can be the same TEG modules from FIG. 3A in new locations. Based on a Suduoko layout from FIG. 2A, a TEG module originally with a number 6 in Rl can be moved physically to a second column (string) of a same row as illustrated in FIG. 3B without altering electric connections of a previous location. A second module in a first string (marked by 1 in R2) can change physical locations to a fourth string of the same row without changing electric connections in the previous location, as displayed in FIG. 3B.

[0077] FIG. 3C is a schematic depicting physical relocations of two TEG modules of a TEG array consistent with a Soduku puzzle layout according to certain aspects of the present disclosure. To clearly describe an approach of physical replacement without alerting the electrical connections, FIG. 3C provides a visual description for reallocating a first module initially with a number 6 in a first row and a second module initially with a number 1 in a second row. In FIG. 3C, a current location of the first and second module is highlighted by a box surrounding each module and a previous location does not have the box surrounding each number. A physical location of each of the modules can be changed while electric connections are still connected at the same nodes based on locations of each of the modes in the original SP array depicted in FIG. 3A. Following a same approach, TEG modules of the entire array canbe designed and relocated based on a new layout. Accordingly, the new array layout can help disperse nonuniformity of a temperature distribution throughout strings of the array to maintain consistent temperature distribution.

[0078] FIG. 3D is a schematic of a TEG array consistent with a Soduku puzzle layout with a modified temperature distribution according to certain aspects of the present disclosure. The TEG array reconfigured according to the Soduku puzzle layout can have a more even temperature distribution than an original state (e.g., as depicted in FIG. 3A) of the TEG array prior to reconfiguration. For example, in the original state depicted in FIG. 3 A, only two strings (or columns) in the TEG array may TEG modules with temperatures less than 200°C. After the reconfiguration according to the Soduku puzzle layout, each string in the TEG array can include two TEG modules with temperatures less than 200°C as depicted in FIG. 3D. With a more even temperature distribution, the reconfigured TEG array can harvest more power than the TEG array in the original state.

[0079] FIG. 3E is an exemplary plot 390 of voltage and power versus current characteristics for a SP TEG array in an initial state and a TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure. The initial state SP TEG array can be array 300 from FIG. 3 A and the rearranged TEG can be TEG 330 from FIG. 3D. The plot 390 includes a power versus current curve 312 for the SP TEG array in the initial state and a power versus current curve 314 for the TEG after rearrangement. Additionally, the plot 390 includes a voltage versus current curve 316 for the SP TEG array in the initial state and a voltage versus current curve 318 for the TEG after rearrangement. A comparison of curve 312 to 314 can show that the rearrangement of the TEG can increase a maximum power output. For example, the curve 312 has a maximum power output less than 215 Watts and curve 314 has a power output of about 220 Watts. The maximum power output can be due to a more even temperature distribution in the rearranged TEG compared to a temperature distribution of the SP array in the initial state.

[0080] FIG. 4 is a flow chart of a process 400 for reconfiguring an array of TEGs consistent with an OSC approach according to certain aspects of the present disclosure. Operations of processes may be performed by software, firmware, hardware, or a combination thereof. Other examples can involve more operations, fewer operations, different operations, or a different order of operations than shown in FIG. 4. The operations of the process 400 can begin at block 410.

[0081] At block 410, the process 400 involves arranging an array of TEGs in an initial state. The array can include M rows and N columns. The array in the initial state can be subjected to a nonuniform temperature distribution. TEG modules in the array can be electrically connected. For example, for each column in the array, each TEG in the column can be electrically connected in series with at least one other TEG in the column. At least one of the columns can be electrically connected in parallel with at least one other column in the array. In some examples, all of the columns can be electrically connected in parallel. The array of TEGs can be a series-parallel SP array. Alternatively or additionally, for each row in the array, each TEG in the row can be electrically connected in series with at least one other TEG in the row. At least one of the rows can be electrically connected in parallel with at least one other row. In some examples, all of the rows can be electrically connected in parallel.

[0082] At block 420, the process 400 involves assigning for each TEG in the array of TEGs, a number. The assigned number can be based on a location of the TEG within the array. For example, for a 6 x 6 array of TEGs, each TEG in a first column can be assigned a number ‘ 1’, each TEG in a second column, can be assigned a number ‘2’, each TEG in a sixth column can be assigned a number ‘6’, etc. In another example, each TEG in a first row can be assigned a number ‘ 1 ’, each TEG in a second row can be assigned a number ‘2’, etc. Assigning the number can be based in part on the nonuniform temperature distribution (NUTD) of the array in the initial state. For example, based on the NUTD, numbers in similar rows can be assigned a same number, numbers in similar columns can be assigned a same number, numbers along a diagonal can be assigned a same number, etc.

[0083] At block 430, the process 400 involves determining a rearrangement of the array of TEGs. The rearrangement can be consistent with constraints of a combinatorial number placement procedure, such as a Soduku puzzle. For example, a rearranged array can include rows where each TEG in each row has a different or unique assigned number compared to all other TEGs in the same row. The rearranged array can also include columns where each TEG in each column has a different or unique assigned number compared to all other TEGs in the same column. Additionally, the rearranged array can include submatrices. The submatrices can include m rows and n columns. Each submatrix can include TEGs where each TEG in the submatrix has a different or unique assigned number compared to all other TEGs in the submatrix.

[0084] A 6 x 6 matrix can be used as an example of the array of TEGs. For the 6 x 6 matrix M = N = 6. The 6 x 6 matrix with TEGs at each matrix element can originally be arranged in an initial state. While in the initial state, each TEG of the 6 x 6 matrix can be assigned a number and the number can be based on a location of the TEG within the 6 x 6 matrix. For example, each TEG in a first column can be assigned a number ‘ 1’, each TEG in a second column can be assigned a number ‘2’, each TEG in a third column can be assigned a number ‘3’, each TEG in a fourth column can be assigned a number ‘4’, each TEG in a fifth column can be assigned a number ‘5’, and each TEG in a sixth column can be assigned a number ‘6’. A rearrangement of the 6 x 6 matrix can be determined. The rearrangement of the 6 x 6 matrix can be another 6 x 6 matrix. The rearrangement can be divided into six submatrices with dimensions of 2 X 3, meaning that the submatrices can have two rows and three columns and m = 2 and n = 3. The determined rearrangement can satisfy the constraints of a Soduku puzzle. Specifically, each row, each column, and each submatrix of the rearranged 6 x 6 matrix can include six TEGs. The assigned numbers of the six TEGs can include each number from 1 to 6 without any of the numbers repeating.

[0085] At block 440, the process 400 involves reconfiguring the array of TEGs to match the rearrangement. Reconfiguring the array can involve moving TEGs to new positions in the array. Each of the M rows and each of the N columns of the reconfigured array comprises TEGs with unique assigned numbers within each row or each column. Additionally, each submatrix of the reconfigured array can include TEG elements with unique assigned numbers within the submatrix. Reconfiguring the array can involve moving TEGs of the array to new locations within the array. For example, a TEG located in a first row and a fourth column of the array in the initial state can be moved to a new location such as a position in the first row and a second column. In reconfiguring the array, at least two of the TEGs can be moved. Moving TEGs to new locations within the array can involve moving the TEGs while maintaining original electrical connections of the array. The reconfigured array can have a more uniform temperature distribution compared to the array in the initial state. With a more uniform temperature distribution, the reconfigured array can be more efficient and can output a larger maximum power than the array in the initial state.

[0086] FIG. 5 is a block diagram of a computing device 500 for determining a rearrangement, consistent with an OSC approach, of an array of TEGs according to certain aspects of the present disclosure. As shown, the computing device 500 includes a processor 502 communicatively coupled to memory 504. The processor 502 can include one processingdevice or multiple processing devices. Non-limiting examples of the processor 502 include a Field-Programmable Gate Array (FPGA), an application specific integrated circuit (ASIC), a microprocessor, or any combination of these. The processor 502 can execute instructions 510 stored in the memory 504 to perform operations, such as the operations of process 400 from FIG. 4. In some examples, the instructions 510 can include processor-specific instructions generated by a compiler or an interpreter from code written in any suitable computerprogramming language, such as C, C++, C#, Python, or Java.

[0087] The memory 504 can include one memory device or multiple memory devices. The memory 504 can be non-volatile and may include any type of memory device that retains stored information when powered off. Non-limiting examples of the memory 504 include electrically erasable and programmable read-only memory (EEPROM), flash memory, or any other type of non-volatile memory. At least some of the memory 504 can include a non-transitory computer-readable medium from which the processor 502 can read instructions 510. The non- transitory computer-readable medium can include electronic, optical, magnetic, or other storage devices capable of providing the processor 502 with the instructions 510 or other program code. Non-limiting examples of the non-transitory computer-readable medium include magnetic disk(s), memory chip(s), RAM, an ASIC, or any other medium from which a computer processor can read instructions 510.

[0088] The memory 504 can further include a list of assigned numbers 512, Soduku constraints 514, and a rearrangement of an array of TEGs 516. The processor 502 can assign the assigned numbers 512 to TEGs of an array of TEGs in an initial state. The assigned numbers 512 can be TEGs based on locations of the TEGs within the array of TEGs. Further, the processor 502 can determine the rearrangement of the array of TEGs 516. The determination can be based on or subject to the Soduku constraints 514. The determined rearrangement of the array of TEGs can improve a nonuniformity of a temperature distribution of the initial state of the array of TEGs.

[0089] Examples

[0090] An OSC approach has been applied on two TEG arrays (6 x 6 and 9 x 9) exposed to various NUTD profiles. The two studied TEG arrays have been configured in a form of an SP array. Maximum output power of the SP arrays based on an original layout and the OSC approach were recorded for comparison purposes. Moreover, to scrutinize an enhancementachieved using the OSC approach, the percentage of power enhancement (%PH) is computed using the following formula:where PGMPPSUC1and PcMPPspcnote maximum yielded power by the TEG array while using the OSC approach and the original layout, respectively. All models and case studies were executed and enforced in MAT-LAB / Simulink platform. The following subsections present an analysis and discussion of the studied TEG arrays.

[0091] Case study 1: 6 x 6 SP TEG array

[0092] In this subsection, a 6 x 6 SP TEG array exposed to three NUTD profdes is considered for validating the OSC approach for an array layout. In practical applications, the TEG array can usually be placed around a heat exchanger with a large temperature variation interval. Hence, the three NUTD profdes were generated based on possible changes in a temperature distribution on a hot side of the TEG modules. FIG. 6A is a schematic of a 6 x 6 TEG array 600 in an initial state with a long narrow nonuniform temperature distribution (NUTD) according to certain aspects of the present disclosure. Hot side temperature values are shown in FIG. 6A for each TEG module in the TEG array 600. A first two rows of first two columns have hot side temperatures at 95 °C. Third and fourth rows of the first two columns have hot side temperatures at 125 °C. Fifth and sixth rows of the first two columns have hot side temperatures at 105 °C. All other TEGs in the TEG array 600 in the initial state have hot side temperatures of 200 °C.

[0093] FIG. 6B is a schematic of a 6 x 6 TEG array 610 in an initial state with a long wide nonuniform temperature distribution (NUTD) according to certain aspects of the present disclosure. Hot side temperature values are shown in FIG. 6B for each TEG module in the TEG array 610. A first two rows the TEG array 610 have hot side temperatures at 100 °C. A last four rows of first and second columns have hot side temperatures at 125 °C. All other TEGs in the TEG array 610 in the initial state have hot side temperatures of 275 °C.

[0094] FIG. 6C is a schematic of a 6 X 6 TEG array 620 in an initial state with a non- homogenous nonuniform temperature distribution (NUTD) according to certain aspects of the present disclosure. Hot side temperature values are shown in FIG. 6C for each TEG module in the TEG array 620. TEGs in a first column of the TEG array 620 have hot side temperatures at55 °C. TEGs in a second column of the TEG array 620 have hot side temperatures at 75 °C. TEGs in a third column of the TEG array 620 have hot side temperatures at 175 °C. TEGs in a fourth column of the TEG array 620 have hot side temperatures at 150 °C. TEGs in a fifth column of the TEG array 620 have hot side temperatures at 98 °C. TEGs in a sixth column of the TEG array 620 have hot side temperatures at 87 °C.

[0095] A cold side of each of the TEG modules in the arrays of FIGs. 6A-6C can usually be set to an air ambient temperature via using a heat sink; as such, and without loss of generality, the temperature of the cold side is specified in this study at 20°C. A structure of an SP TEG array reconfiguration using the OSC approach for each of the initial state arrays of FIGs. 6A- 6C are shown in FIGs. 6D-6F.

[0096] FIG. 6D is a schematic of a 6 X 6 TEG array 630 with an initial long narrow nonuniform temperature distribution (NUTD) reconfigured using an OSC approach according to certain aspects of the present disclosure. The TEG array 630 can be a reconfigured version of TEG array 600 from FIG. 6A. A temperature distribution of the TEG array 630 is more uniform than the TEG array 600.

[0097] FIG. 6E is a schematic of a 6 X 6 TEG array 640 with an initial long wide nonuniform temperature distribution (NUTD) reconfigured using an OSC approach according to certain aspects of the present disclosure. The TEG array 640 can be a reconfigured version of TEG array 610 from FIG. 6B. A temperature distribution of the TEG array 630 is more uniform than the TEG array 610.

[0098] FIG. 6F is a schematic of a 6 X 6 TEG array 650 with an initial non-homogenous nonuniform temperature distribution (NUTD) reconfigured using an OSC approach according to certain aspects of the present disclosure. The TEG array 650 can be a reconfigured version of TEG array 620 from FIG. 6C. A temperature distribution of the TEG array 650 is more uniform than the TEG array 620.

[0099] FIG. 7A is an exemplary plot 700 of voltage and power versus current characteristics for a 6 X 6 SP TEG array in an initial state with a long narrow NUTD and a corresponding TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure. The TEG array in the initial state is 6 x 6 TEG array 600 from FIG. 6A and the corresponding TEG is 6 X 6 TEG array 630 from FIG. 6D. The plot 700 includes a power versus current curve 702 for the SP TEG array in the initial state and apower versus current curve 704 for the TEG after rearrangement. Additionally, the plot 700 includes a voltage versus current curve 706 for the SP TEG array in the initial state and a voltage versus current curve 708 for the TEG after rearrangement. A comparison of curve 702 to 704 can show that the rearrangement of the TEG can increase a maximum power output. For example, the curve 702 has a maximum power output less than 215 Watts and curve 704 has a power output of about 220 Watts. The maximum power output can be due to a more even temperature distribution in the rearranged TEG compared to a temperature distribution of the SP array in the initial state.

[0100] FIG. 7B is an exemplary plot 710 of voltage and power versus current characteristics for a 6 X 6 SP TEG array in an initial state with a long wide NUTD and a corresponding TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure. The TEG array in the initial state is 6 x 6 TEG array 610 from FIG. 6B and the corresponding TEG is 6 X 6 TEG array 640 from FIG. 6E. The plot 710 includes a power versus current curve 712 for the SP TEG array in the initial state and a power versus current curve 714 for the TEG after rearrangement. Additionally, the plot 710 includes a voltage versus current curve 716 for the SP TEG array in the initial state and a voltage versus current curve 718 for the TEG after rearrangement. A comparison of curve 712 to 714 can show that the rearrangement of the TEG can increase a maximum power output. For example, the curve 712 has a maximum power output less than 235 Watts and curve 714 has a power output of greater than 235 Watts. The maximum power output can be due to a more even temperature distribution in the rearranged TEG compared to a temperature distribution of the SP array in the initial state.

[0101] FIG. 7C is an exemplary plot 720 of voltage and power versus current characteristics for a 6 X 6 SP TEG array in an initial state with a non-homogenous NUTD and a corresponding TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure. The TEG array in the initial state is 6 x 6 TEG array 620 from FIG. 6C and the corresponding TEG is 6 X 6 TEG array 650 from FIG. 6F. The plot 720 includes a power versus current curve 722 for the SP TEG array in the initial state and a power versus current curve 724 for the TEG after rearrangement. Additionally, the plot 720 includes a voltage versus current curve 726 for the SP TEG array in the initial state and a voltage versus current curve 728 for the TEG after rearrangement. A comparison of curve 722 to 724 can show that the rearrangement of the TEG can increase a maximum power output. For example, the curve 722 has a maximum power output less than 81 Watts and curve 724 has apower output of greater than 82 Watts. The maximum power output can be due to a more even temperature distribution in the rearranged TEG compared to a temperature distribution of the SP array in the initial state.

[0102] Exhibited Power versus current curves in FIGs. 7A-7C can reveal a superiority of the OSC approach identified as an ‘Rec-SP’ (‘Rec-SP’ can stand for reconfigured SP array) curve in each figure in maximizing yielded output power from the TEG array for the three studied NUTD profiles. Moreover, one key observation is a detected smoothness enhancement in a characteristic of the TEG array based on the OSC approach (Rec - SP ) compared to the original SP arrays that feature having some local maximum power points. A reason for that enhancement can be that the OSC approach scatters the nonuniformity of the temperature distribution across entire array strings; hence a consistent temperature distribution can be acquired. As a result, the TEG array-based OSC approach can generate an open voltage higher than the original SP array; thus, output power can be boosted.Table I: Generated maximum power and %PH in a case study of a 6 x 6 TEG array based on an original array layout and a proposed OSC approach incorporating a Soduku puzzle layout.

[0103] Table I lists a maximum output power of TEG arrays based on an original SP layout and the proposed OSC approach. As per reported data, the OSC approach can significantly improve the maximum output power for the three studied NUTD profiles compared to the original SP. The Rec-SP can produce about 224 W of maximum power in a case of a long narrow NUTD; meanwhile, the SP produces less at about 213.7 W; consequently, the Rec - SP can enhance harvested power by 4.92%. Likewise, for long wide and non-homogenous NUTD profiles, the Rec-SP can promote an enhanced yielded power by 3.66% and 2.65%, respectively.

[0104] Case study 2: 9 x 9 SP TEG array

[0105] In this subsection, a 9x9 SP TEG array exposed to six NUTD profiles is studied to justify an efficiency of the proposed OSC approach. In practical applications, the TEG array is usually placed around the heat exchanger with a large temperature variation interval. Hence, the six NUTD profiles are generated based on possible changes in a temperature distribution on a hot side of the TEG modules. The NUTD profiles are classified as NUTD across rows, NUTD across columns, short-wise NUTD, diagonal NUTD, internal NUTD, and random NUTD, as displayed in FIGs. 8A-8F, respectively. FIG. 8A is a schematic of a 9 x 9 TEG array 800 in an initial state with a NUTD across rows according to certain aspects of the present disclosure. Hot side temperature values are shown in FIG. 8 A for each TEG module in the TEG array 800. TEG modules in a first five rows have hot side temperatures at 100 °C. TEG modules in a last four rows of a first two columns have hot side temperatures at 125 °C. TEG modules in a last four rows of third, fourth, and fifth columns have hot side temperatures at 55 °C. TEG modules in a last four rows of sixth and seventh columns have hot side temperatures at 60 °C. TEG modules in a last four rows of a last two columns have hot side temperatures at 158 °C.

[0106] FIG. 8B is a schematic of a 9 X 9 TEG array 810 in an initial state with a NUTD across columns according to certain aspects of the present disclosure. Hot side temperature values are shown in FIG. 8B for each TEG module in the TEG array 810. TEG modules in a first five columns have hot side temperatures at 100 °C. TEG modules in a first five rows of sixth and seventh columns have hot side temperatures at 80 °C. TEG modules in a last four rows of the sixth and seventh columns have hot side temperatures at 55 °C. TEG modules in a first five rows of eighth and ninth columns have hot side temperatures at 170 °C. TEG modules in a last four rows of the eighth and ninth columns have hot side temperatures at 153 °C.

[0107] FIG. 8C is a schematic of a 9 x 9 TEG array 820 in an initial state with a short wide NUTD according to certain aspects of the present disclosure. Hot side temperature values are shown in FIG. 8C for each TEG module in the TEG array 820. TEG modules in a first four rows, a last five columns of fifth and sixth rows, and a last two columns of a seventh row have hot side temperatures at 100 °C. TEG modules in a last five rows of a first two columns, and a fifth row of third and fourth columns have hot side temperatures at 50 °C. TEG modules in a last four rows of the third and fourth columns have hot side temperatures at 58 °C. TEG modules in a last three rows of fifth, sixth, and seventh columns have hot side temperatures at180 °C. TEG modules in a last two rows of the eighth and ninth columns have hot side temperatures at 165 °C.

[0108] FIG. 8D is a schematic of a 9 x 9 TEG array 830 in an initial state with a diagonal NUTD according to certain aspects of the present disclosure. Hot side temperature values are shown in FIG. 8D for each TEG module in the TEG array 830. TEG modules in a first three rows of first three columns have hot side temperatures at 180 °C. TEG modules in fifth, sixth and seventh rows of fourth and fifth columns have hot side temperatures at 50 °C. TEG modules in a second, third, fourth, and fifth rows of sixth and seventh columns have hot side temperatures at 53 °C. TEG modules in a last three rows of fifth, sixth, and seventh columns have hot side temperatures at 180 °C. TEG modules in a first three rows of the eighth and ninth columns have hot side temperatures at 60 °C. All other TEG modules in the TEG array 830 have hot side temperatures of 100 °C.

[0109] FIG. 8E is a schematic of a 9 X 9 TEG array 840 in an initial state with an internal NUTD according to certain aspects of the present disclosure. Hot side temperature values are shown in FIG. 8E for each TEG module in the TEG array 840. TEG modules in a first two rows of second, third, fourth, and fifth columns have hot side temperatures at 55 °C. TEG modules in fifth, sixth, seventh, and eighth rows of a second column have hot side temperatures at 63 °C. TEG modules in the fifth, sixth, seventh, and eighth rows of third, fourth, and fifth columns have hot side temperatures at 90 °C. TEG modules in third, fourth, fifth, sixth, seventh, and eighth rows of sixth, and seventh columns have hot side temperatures at 170 °C. All other TEG modules in the TEG array 840 have hot side temperatures of 100 °C.

[0110] FIG. 8F is a schematic of a 9 X 9 TEG array 850 in an initial state with a random NUTD according to certain aspects of the present disclosure. Hot side temperature values are shown in FIG. 8F for each TEG module in the TEG array 850. TEG modules in a last four rows of a first two columns have hot side temperatures at 55 °C. TEG modules in a first five rows of third, fourth, and fifth columns have hot side temperatures at 63 °C. TEG modules in a first five rows of sixth and seventh columns have hot side temperatures at 180 °C. TEG modules in last four rows of the sixth and seventh columns have hot side temperatures at 135 °C. All other TEG modules in the TEG array 850 have hot side temperatures of 100 °C.[oni] A cold side of each of the TEG modules in the arrays of FIGs. 8A-6F can usually be set to an air ambient temperature via using a heat sink; as such, and without loss of generality, the temperature of the cold side is specified in this study at 20°C. A structure of an SP TEGarray reconfiguration using the OSC approach for each of the initial state arrays of FIGs. 8A- 8F are shown in FIGs. 8G-8L.

[0112] FIG. 8G is a schematic of a 9 X 9 TEG array 860 with an initial NUTD across rows reconfigured using an OSC approach according to certain aspects of the present disclosure. The TEG array 860 can be a reconfigured version of TEG array 800 from FIG. 8A. A temperature distribution of the TEG array 860 is more uniform than the TEG array 800.

[0113] FIG. 8H is a schematic of a 9 X 9 TEG array 870 with an initial NUTD across columns reconfigured using an OSC approach according to certain aspects of the present disclosure. The TEG array 870 can be a reconfigured version of TEG array 810 from FIG. 8B. A temperature distribution of the TEG array 870 is more uniform than the TEG array 810.

[0114] FIG. 81 is a schematic of a 9 X 9 TEG array 880 with an initial short wide NUTD reconfigured using an OSC approach according to certain aspects of the present disclosure. The TEG array 880 can be a reconfigured version of TEG array 820 from FIG. 8C. A temperature distribution of the TEG array 880 is more uniform than the TEG array 820.

[0115] FIG. 8 J is a schematic of a 9 X 9 TEG array 890 with an initial diagonal NUTD reconfigured using an OSC approach according to certain aspects of the present disclosure. The TEG array 890 can be a reconfigured version of TEG array 830 from FIG. 8D. A temperature distribution of the TEG array 890 is more uniform than the TEG array 830.

[0116] FIG. 8K is a schematic of a 9 X 9 TEG array 895 with an initial internal NUTD reconfigured using an OSC approach according to certain aspects of the present disclosure. The TEG array 895 can be a reconfigured version of TEG array 840 from FIG. 8E. A temperature distribution of the TEG array 895 is more uniform than the TEG array 840.

[0117] FIG. 8L is a schematic of a 9 X 9 TEG array 896 with an initial random NUTD reconfigured using an OSC approach according to certain aspects of the present disclosure. The TEG array 896 can be a reconfigured version of TEG array 850 from FIG. 8F. A temperature distribution of the TEG array 896 is more uniform than the TEG array 850.

[0118] FIG. 9A is an exemplary plot 900 of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with a NUTD across rows and a corresponding TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure. The TEG array in the initial state is 9 x 9 TEG array 800 from FIG. 8A and the corresponding TEG is 9 X 9 TEG array 860 from FIG. 8G. The plot900 includes a power versus current curve 902 for the SP TEG array in the initial state and a power versus current curve 904 for the TEG after rearrangement. Additionally, the plot 900 includes a voltage versus current curve 906 for the SP TEG array in the initial state and a voltage versus current curve 908 for the TEG after rearrangement. A comparison of curve 902 to 904 can show that the rearrangement of the TEG can increase a maximum power output. For example, the curve 902 has a maximum power output less than 172 Watts and curve 904 has a power output of more than 178 Watts. The maximum power output can be due to a more even temperature distribution in the rearranged TEG compared to a temperature distribution of the SP array in the initial state.

[0119] FIG. 9B is an exemplary plot 910 of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with a NUTD across columns and a corresponding TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure. The TEG array in the initial state is 9 x 9 TEG array 810 from FIG. 8B and the corresponding TEG is 9 X 9 TEG array 870 from FIG. 8H. The plot 910 includes a power versus current curve 912 for the SP TEG array in the initial state and a power versus current curve 914 for the TEG after rearrangement. Additionally, the plot 910 includes a voltage versus current curve 916 for the SP TEG array in the initial state and a voltage versus current curve 918 for the TEG after rearrangement. A comparison of curve 912 to 914 can show that the rearrangement of the TEG can increase a maximum power output. For example, the curve 912 has a maximum power output less than 187 Watts and curve 914 has a power output of more than 195 Watts. The maximum power output can be due to a more even temperature distribution in the rearranged TEG compared to a temperature distribution of the SP array in the initial state.

[0120] FIG. 9C is an exemplary plot 920 of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with a short wide NUTD and a corresponding TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure. The TEG array in the initial state is 9 x 9 TEG array 820 from FIG. 8C and the corresponding TEG is 9 X 9 TEG array 880 from FIG. 81. The plot 920 includes a power versus current curve 922 for the SP TEG array in the initial state and a power versus current curve 924 for the TEG after rearrangement. Additionally, the plot 920 includes a voltage versus current curve 926 for the SP TEG array in the initial state and a voltage versus current curve 928 for the TEG after rearrangement. A comparison of curve 922 to 924 can show that the rearrangement of the TEG can increase a maximum power output. Forexample, the curve 922 has a maximum power output less than 158 Watts and curve 924 has a power output of about 165 Watts. The maximum power output can be due to a more even temperature distribution in the rearranged TEG compared to a temperature distribution of the SP array in the initial state.

[0121] FIG. 9D is an exemplary plot 930 of voltage and power versus current characteristics for a 9 x 9 SP TEG array in an initial state with a diagonal NUTD and a corresponding TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure. The TEG array in the initial state is 9 x 9 TEG array 830 from FIG. 8D and the corresponding TEG is 9 X 9 TEG array 890 from FIG. 8J. The plot 930 includes a power versus current curve 932 for the SP TEG array in the initial state and a power versus current curve 934 for the TEG after rearrangement. Additionally, the plot 930 includes a voltage versus current curve 936 for the SP TEG array in the initial state and a voltage versus current curve 938 for the TEG after rearrangement. A comparison of curve 932 to 934 can show that the rearrangement of the TEG can increase a maximum power output. For example, the curve 932 has a maximum power output less than 149 Watts and curve 934 has a power output of more than 152 Watts. The maximum power output can be due to a more even temperature distribution in the rearranged TEG compared to a temperature distribution of the SP array in the initial state.

[0122] FIG. 9E is an exemplary plot 940 of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with an internal NUTD and a corresponding TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure. The TEG array in the initial state is 9 x 9 TEG array 840 from FIG. 8E and the corresponding TEG is 9 X 9 TEG array 895 from FIG. 8K. The plot 940 includes a power versus current curve 942 for the SP TEG array in the initial state and a power versus current curve 944 for the TEG after rearrangement. Additionally, the plot 940 includes a voltage versus current curve 946 for the SP TEG array in the initial state and a voltage versus current curve 948 for the TEG after rearrangement. A comparison of curve 942 to 944 can show that the rearrangement of the TEG can increase a maximum power output. For example, the curve 942 has a maximum power output less than 170 Watts and curve 944 has a power output of more than 175 Watts. The maximum power output can be due to a more even temperature distribution in the rearranged TEG compared to a temperature distribution of the SP array in the initial state.

[0123] FIG. 9F is an exemplary plot 950 of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with a random NUTD and a corresponding TEG after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure. The TEG array in the initial state is 9 x 9 TEG array 850 from FIG. 8F and the corresponding TEG is 9 X 9 TEG array 896 from FIG. 8L. The plot 950 includes a power versus current curve 952 for the SP TEG array in the initial state and a power versus current curve 954 for the TEG after rearrangement. Additionally, the plot 950 includes a voltage versus current curve 956 for the SP TEG array in the initial state and a voltage versus current curve 958 for the TEG after rearrangement. A comparison of curve 952 to 954 can show that the rearrangement of the TEG can increase a maximum power output. For example, the curve 952 has a maximum power output less than 162 Watts and curve 954 has a power output of more than 171 Watts. The maximum power output can be due to a more even temperature distribution in the rearranged TEG compared to a temperature distribution of the SP array in the initial state.

[0124] Exhibited Power versus current curves in FIGs. 7A-7C can reveal a superiority of the OSC approach identified as an ‘Rec-SP’ (‘Rec-SP’ can stand for reconfigured SP array) curve in each figure in maximizing yielded output power from the TEG array for the six studied NUTD profiles in Case II. Moreover, one key observation is a detected smoothness enhancement in a characteristic of the TEG array based on the OSC approach (Rec - SP ) compared to the original SP arrays that feature having some local maximum power points. A reason for that enhancement can be that the OSC approach scatters the nonuniformity of the temperature distribution across entire array strings; hence a consistent temperature distribution can be acquired. As a result, the TEG array-based OSC approach can generate an open voltage higher than the original SP array; thus, output power can be boosted.Table II: Generated maximum power and %PH in a case study of a 9 x 9 TEG array baser on an original array layout and a proposed OSC approach incorporating a Soduku puzzle layout.

[0125] Table II reports maximum output power from TEG arrays based on the original SP layout and reconfigured arrays based on the proposed OSC. The reported data indicates that the reconfigured arrays significantly enhance the maximum output power for the six studied NUTD profiles compared to the original SP. The reconfigured arrays provide 178.65 W, 195.58 W, 165.48 W, 152.84 W, 175.79 W, and 171.35 W over the six NUTD profiles, respectively; meanwhile, the original SP offers 170.98 W, 186.217 W, 157.12 W, 148.03 W, 169.26 W, and 160.817 W; respectively. Accordingly, the reconfigured arrays enhance the harvested power by a range from 3.25% to 6.55%. Thus, implementing the proposed static configuration approach in dispersing the nonuniformity of the temperature can improve the array produced output power over various NUTD profiles.

[0126] Case study 3: Comparing the OSC approach to a dynamic reconfiguration approach.

[0127] This section gives a detailed comparative analysis between the proposed OSC based- Sudoku puzzle layout approach and a dynamic reconfiguration approach to demonstrate the effectiveness of the OSC approach. The analysis includes using switches, system complexity, a capacity to disperse a nonuniformity of temperature distribution, and, eventually, running expenses.

[0128] The dynamic reconfiguration approach can be established by a series of switches that can involve links, wirings, and a tricky switching matrix. Moreover, a scalable dimensional TEG array can increase a complexity of system structure for the dynamic reconfiguration approach. For example, the dynamic reconfiguration approach can involve 32 switches and 16 sensors for a 4 X 4 TEG array, 72 switches and 36 sensors for a 6 X 6 TEG array, or 162 switches and 81 sensors for a 9 x 9 TEG array. However, the proposed OSC approach can provide a single physical unique design; hence, the tricky switching matrix can be avoided.

[0129] Numerous studies have shown an applicability of the dynamic reconfiguration approach for harvesting TEG output power. Nevertheless, a quality of the dynamicreconfiguration approach can rely on properties, processing time, and customized settings of implemented algorithms. FIG. 10A is an exemplary plot 1000 of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with a NUTD across rows after rearrangement using an optimized static configuration (OSC) approach and a dynamic reconfiguration approach according to certain aspects of the present disclosure. The NUTD across rows can be seen in 9 X 9 TEG array 800 from FIG. 8A and the TEG formed by reconfiguration by the OSC approach is 9 X 9 TEG array 860 from FIG. 8G. The plot 1000 includes a power versus current curve 1002 for the TEG after rearrangement by the dynamic reconfiguration approach and a power versus current curve 1004 for the TEG after rearrangement by the OSC approach. Additionally, the plot 1000 includes a voltage versus current curve 1006 for the TEG array after rearrangement by the dynamic reconfiguration and a voltage versus current curve 1008 for the TEG after rearrangement by the OSC approach. A comparison of curve 1002 to 1004 can show that both rearrangements can have a similar maximum power output.

[0130] FIG. 10B is an exemplary plot 1010 of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with a NUTD across columns after rearrangement using an optimized static configuration (OSC) approach and a dynamic reconfiguration approach according to certain aspects of the present disclosure. The NUTD across columns can be seen in 9 X 9 TEG array 810 from FIG. 8B and the TEG formed by reconfiguration by the OSC approach is 9 X 9 TEG array 870 from FIG. 8H. The plot 1010 includes a power versus current curve 1012 for the TEG after rearrangement by the dynamic reconfiguration approach and a power versus current curve 1014 for the TEG after rearrangement by the OSC approach. Additionally, the plot 1010 includes a voltage versus current curve 1016 for the TEG array after rearrangement by the dynamic reconfiguration and a voltage versus current curve 1018 for the TEG after rearrangement by the OSC approach. A comparison of curve 1012 to 1014 can show that both rearrangements can have a similar maximum power output, with a higher maximum output for curve 1014.

[0131] FIG. 10C is an exemplary plot 1020 of voltage and power versus current characteristics for a 9 x 9 SP TEG array in an initial state with a short wide NUTD after rearrangement using an optimized static configuration (OSC) approach and a dynamic reconfiguration approach according to certain aspects of the present disclosure. The short wide NUTD can be seen in 9 X 9 TEG array 820 from FIG. 8C and the TEG formed by reconfiguration by the OSC approach is 9 X 9 TEG array 880 from FIG. 81. The plot 1020includes a power versus current curve 1022 for the TEG after rearrangement by the dynamic reconfiguration approach and a power versus current curve 1024 for the TEG after rearrangement by the OSC approach. Additionally, the plot 1020 includes a voltage versus current curve 1026 for the TEG array after rearrangement by the dynamic reconfiguration and a voltage versus current curve 1028 for the TEG after rearrangement by the OSC approach. A comparison of curve 1022 to 1024 can show that both rearrangements can have a similar maximum power output, with a higher maximum output for curve 1024.

[0132] FIG. 10D is an exemplary plot 1030 of voltage and power versus current characteristics for a 9 x 9 SP TEG array in an initial state with a diagonal NUTD after rearrangement using an optimized static configuration (OSC) approach and a dynamic reconfiguration approach according to certain aspects of the present disclosure. The NUTD across rows can be seen in 9 X 9 TEG array 830 from FIG. 8D and the TEG formed by reconfiguration is 9 X 9 TEG array 890 from FIG. 8J. The plot 1030 includes a power versus current curve 1032 for the TEG after rearrangement by the dynamic reconfiguration approach and a power versus current curve 1034 for the TEG after rearrangement by the OSC approach. Additionally, the plot 1030 includes a voltage versus current curve 1036 for the TEG array after rearrangement by the dynamic reconfiguration and a voltage versus current curve 1038 for the TEG after rearrangement by the OSC approach. A comparison of curve 1032 to 1034 can show that both rearrangements can have a similar maximum power output, with a higher maximum output for curve 1034.

[0133] FIG. 10E is an exemplary plot 1040 of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with an internal NUTD after rearrangement using an optimized static configuration (OSC) approach and a reconfiguration approach according to certain aspects of the present disclosure. The NUTD across rows can be seen in 9 X 9 TEG array 840 from FIG. 8E and the TEG formed by reconfiguration is 9 X 9 TEG array 895 from FIG. 8K. The plot 1040 includes a power versus current curve 1042 for the TEG after rearrangement by the dynamic reconfiguration approach and a power versus current curve 1044 for the TEG after rearrangement by the OSC approach. Additionally, the plot 1040 includes a voltage versus current curve 1046 for the TEG array after rearrangement by the dynamic reconfiguration and a voltage versus current curve 1048 for the TEG after rearrangement by the OSC approach. A comparison of curve 1042 to 1044 can show that both rearrangements can have a similar maximum power output, with a higher maximum output for curve 1044.

[0134] FIG. 10F is an exemplary plot 1050 of voltage and power versus current characteristics for a 9 X 9 SP TEG array in an initial state with a random NUTD after rearrangement using an optimized static configuration (OSC) approach and a dynamic reconfiguration approach according to certain aspects of the present disclosure. The NUTD across rows can be seen in 9 X 9 TEG array 850 from FIG. 8F and the TEG formed by reconfiguration is 9 X 9 TEG array 896 from FIG. 8L. The plot 1050 includes a power versus current curve 1052 for the TEG after rearrangement by the dynamic reconfiguration approach and a power versus current curve 1054 for the TEG after rearrangement by the OSC approach. Additionally, the plot 1050 includes a voltage versus current curve 1056 for the TEG array after rearrangement by the dynamic reconfiguration and a voltage versus current curve 1058 for the TEG after rearrangement by the OSC approach. A comparison of curve 1052 to 1054 can show that both rearrangements can have a similar maximum power output, with a higher maximum output for curve 1054. The proposed OSP approach shows a notable improvement of the TEG array power across the profiles of 2-6 by employing a simple fixed structure compared to the complex dynamic reconfiguration approach.

[0135] The dynamically based reconfiguration procedure during operation can necessitate ongoing sensor and switching matrix maintenance, incurring additional expenditures. In contrast, a static configuration approach-based on a Sudoku puzzle layout can provide just a unique TEG array layout that fits several NUTD profiles; thus, no maintenance expenditures for sensors or switching matrices may be necessary. When compared to the dynamic reconfiguration approach, results show that the proposed OSC approach can improving the output power of TEG arrays operating under NUTD with a simpler design and minimal expenditures. Further, the OSC approach can help maintain consistent temperature distributions over the entire TEG array; accordingly, a smooth uni -peak characteristic in power versus current data can be obtained.

[0136] FIG. 11 is a schematic of an experimental setup 1100 for a 4 x 4 TEG array 1103 according to certain aspects of the present disclosure. A TEG 12708T237 model TEG module was used for each TEG in the experimental setup 1100. Rectangular heaters can be employed in the setup 1100 to provide heat. Temperature control can be achieved through temperature controllers 1101 and relays (e.g., SELEC-type controllers and relays). In the setup 1100, which can include a load 1108, each TEG module was pasted between aluminum cooling fins 1104 and mild steel heat spreader plates using thermal paste. Cooling fans 1102 can ensure effective cooling on a cold side of each TEG. Both the heat spreader plates, and the cooling fans 1102can be equipped with thermocouples (e.g., K-type thermocouples) to monitor temperatures on the hot side or cold side of TEG modules. Temperature data can be recorded with a data logger 1106 (e.g., Agilent 34972A data logger).

[0137] FIG. 12A-12P are schematics of initial states and reconfigured states for a 4 x 4 TEG array subject to various initial NUTDs according to certain aspects of the present disclosure. The 4 x 4 TEG array was subjected to eight different NUTD initial state arrangements. The eight different initial state arrangements are illustrated in FIGs. 12A-12H. Each of the initial state arrangements were reconfigured according to a Soduku puzzle layout. The eight electrical array patterns for the 4 x 4 TEG arrays after rearrangement are illustrated in FIGs. 121- 12P. For example, FIG. 121 displays a rearranged array of the first NUTD initial state arrangement (e.g., pattern 1) illustrated in FIG. 12A. FIG. 12J shows the rearranged array of the second NUTD initial state arrangement (e.g., pattern 2) of FIG. 12B, and so on.

[0138] FIG. 13A-13H are exemplary plots of voltage and power versus current characteristics for a 4 x 4 TEG array in various initial NUTD states before and after rearrangement using an optimized static configuration (OSC) approach according to certain aspects of the present disclosure. Each of the plots (e.g., FIG. 13A-13H) is associated with one of the eight NUTD initial state arrangements described above. For example, FIG. 13A is associated with a first NUTD initial state arrangement and shows voltage and power versus current characteristics for 4 X 4 TEG array configurations described in FIG. 12A and FIG. 121. All of the plots (e.g., FIG. 13A-13H) demonstrate an ability of the OSC approach to enhance an output power of the 4 X 4 TEG array after rearrangement. A summary of the enhancements is shown in Table III.Table III: Generated maximum power and %PH in a case study of a 4 x 4 TEG array experimental setup based on an original array layout and a proposed OSC approach incorporating a Soduku puzzle layout.

[0139] While the present subject matter has been described in detail with respect to specific embodiments thereof, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing may readily produce alterations to, variations of, and equivalents to such embodiments. Accordingly, it should be understood that the present disclosure has been presented for purposes of example rather than limitation, and does not preclude inclusion of such modifications, variations, and / or additions to the present subject matter as would be readily apparent to one of ordinary skill in the art. Indeed, the methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the present disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the present disclosure.

[0140] Conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain examples include, while other examples do not include, certain features, elements, and / or steps. Thus, such conditional language is not generally intended to imply that features, elements and / or steps are in any way required for one or more examples or that one or more examples necessarily include logic for deciding, with or without author input or prompting, whether these features, elements and / or steps are included or are to be performed in any particular example.

[0141] Disjunctive language such as the phrase “at least one of X, Y, or Z,” unless specifically stated otherwise, is otherwise understood within the context as used in general to present that an item, term, etc., may be either X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, such disjunctive language is not generally intended to, and should not,imply that certain examples require at least one of X, at least one of Y, or at least one of Z to each be present.

[0142] Use herein of the word “or” is intended to cover inclusive and exclusive OR conditions. In other words, A or B or C includes any or all of the following alternative combinations as appropriate for a particular usage: A alone; B alone; C alone; A and B only; A and C only; B and C only; and all three of A and B and C.

[0143] The use of the terms “a” and “an” and “the” and similar referents in the context of describing the disclosed examples (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The terms “comprising,” “including,” “having,” and the like are synonymous and are used inclusively, in an open-ended fashion, and do not exclude additional elements, features, acts, operations, and so forth. Also, the term “or” is used in its inclusive sense (and not in its exclusive sense) so that when used, for example, to connect a list of elements, the term “or” means one, some, or all of the elements in the list. The use of “adapted to” or “configured to” herein is meant as open and inclusive language that does not foreclose devices adapted to or configured to perform additional tasks or steps. The term “connected” is to be construed as partly or wholly contained within, attached to, or joined together, even if there is something intervening. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. Additionally, the use of “based on” is meant to be open and inclusive, in that a process, step, calculation, or other action “based on” one or more recited conditions or values may, in practice, be based on additional conditions or values beyond those recited. Similarly, the use of “based at least in part on” is meant to be open and inclusive, in that a process, step, calculation, or other action “based at least in part on” one or more recited conditions or values may, in practice, be based on additional conditions or values beyond those recited. Headings, lists, and numbering included herein are for ease of explanation only and are not meant to be limiting.

[0144] The various features and processes described above may be used independently of one another or may be combined in various ways. All possible combinations and subcombinations are intended to fall within the scope of the present disclosure. In addition, certain method or process blocks may be omitted in some implementations. The methods andprocesses described herein are also not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences that are appropriate. For example, described blocks or states may be performed in an order other than that specifically disclosed, or multiple blocks or states may be combined in a single block or state. The example blocks or states may be performed in serial, in parallel, or in some other manner. Blocks or states may be added to or removed from the disclosed examples. Similarly, the example systems and components described herein may be configured differently than described. For example, elements may be added to, removed from, or rearranged compared to the disclosed examples.

[0145] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

Claims

WHAT IS CLAIMED IS:

1. A method comprising: arranging an array of thermoelectric generator (TEGs) in an initial state, wherein the array comprises M rows and N columns; assigning, for each TEG in the array of TEGs, a number based on a location of the TEG within the array; determining a rearrangement of the array of TEGs, the rearrangement consistent with constraints of a combinatorial number placement procedure and wherein the rearrangement reduces a nonuniformity of a temperature distribution associated with the array of TEGs; and reconfiguring the array of TEGs to match the rearrangement, wherein each of the M rows and each of the N columns of the reconfigured array comprises TEGs with unique assigned numbers within each row or each column.

2. The method of claim 1, wherein reconfiguring the array of TEGs comprises moving at least two TEGs of the array of TEGs to new positions in the array of TEGs.

3. The method of claim 1, wherein arranging the array of TEGs comprises electrically connecting each TEG in a column in series and electrically connecting at least one column in parallel with at least one other column of the TEG.

4. The method of claim 3, wherein reconfiguring the array of TEGs comprises moving at least two TEGs of the array of TEGs to new positions while maintaining original electrical connections in the array of TEGs.

5. The method of claim 1, wherein arranging an array of TEGs comprises electrically connecting each TEG in a row in series and electrically connecting at least one row in parallel with at least one other row of the TEG.

6. The method of claim 1, wherein assigning the number is based in part on a nonuniform temperature distribution of the initial state of the array.

7. The method claim 1, wherein the reconfigured array comprises submatrices with m rows and n columns, wherein each submatrix comprises TEGs with unique assigned numbers.

8. A system comprising: an array of thermoelectric generators (TEGs), wherein the array comprises M rows and N columns, the array configured to be reconfigured to match a rearrangement consistent with constraints of a combinatorial number placement procedure and wherein the rearrangement reduces a nonuniformity of a temperature distribution associated with the array of TEGs; and a computing device comprising: a processor; and a memory that includes instructions executable by the processor for causing the processor to perform operations comprising: assigning, for each TEG in an initial state of the array of TEGs, a number based on a location of each TEG within the array; and determining the rearrangement of the array of TEGs, wherein the rearrangement of the array comprises TEGs with unique assigned numbers within each row or each column.

9. The system of claim 8, wherein at least two TEGs of the array of TEGs are configured to move to new positions in the array.

10. The system of claim 8, wherein, for the initial state of the array of TEGs, each TEG in a column is electrically connected in series with at least one other TEG in the column, and wherein at least one column in the TEG is electrically connected in parallel with at least one other column of the array of TEGs.

11. The system of claim 9, wherein at least two TEGs of the array of TEGs are configured to move to new positions in the array while maintaining original electrical connections of the array.

12. The system of claim 8, wherein, for the initial state of the array of TEGs, each TEG in a row is electrically connected in series with at least one other TEG inthe row, and wherein at least one row in the TEG is electrically connected in parallel with at least one other row of the array of TEGs.

13. The system of claim 8, wherein the operation of assigning the number is based in part on a nonuniform temperature distribution of the initial state of the array.

14. The system of claim 8, wherein the rearrangement of the array comprises submatrices with m rows and n columns, wherein each submatrix comprises TEGs with unique assigned numbers.

15. A non-transitory computer-readable medium comprising instructions that are executable by a processor for causing the processor to perform operations comprising: assigning for each thermoelectric generator (TEG) in an initial state of an array of TEGs, a number based on a location of each TEG within the array, wherein the array comprises M rows and N columns; and determining a rearrangement of the array of TEGs, the rearrangement consistent with constraints of a combinatorial number placement procedure, wherein the rearrangement reduces a nonuniformity of a temperature distribution associated with the array of TEGs, and wherein each of the M rows and each of the N columns of the rearrangement comprises TEGs with unique assigned numbers within each row or each column.

16. The non-transitory computer-readable medium of claim 15, wherein, for the initial state of the array of TEGs, each TEG in a column is electrically connected in series with at least one other TEG in the column, and wherein at least one column in the TEG is electrically connected in parallel with at least one other column of the array of TEGs.

17. The non-transitory computer-readable medium of claim 15, wherein, for the initial state of the array of TEGs, each TEG in a row is electrically connected in series with at least one other TEG in the row, and wherein at least one row in the TEG is electrically connected in parallel with at least one other row of the array of TEGs.

18. The non-transitory computer-readable medium of claim 15, wherein the operation of assigning the number is based in part on a nonuniform temperature distribution of the initial state of the array.

19. The non-transitory computer-readable medium of claim 15, wherein the rearrangement of the array comprises submatrices with m rows and n columns, wherein each submatrix comprises TEGs with unique assigned numbers.

20. The non-transitory computer-readable medium of claim 15, wherein the operation of determining the rearrangement comprises identifying at least two TEGs of the array of TEGs to move to new positions in the array.

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