Light-emitting element and light-emitting device

Abstract

Provided in the present application are a light-emitting element and a light-emitting device, the light-emitting element comprising: an epitaxial layer, which comprises a first electrically conductive semiconductor layer, an active layer and a second electrically conductive semiconductor layer, and comprises a plurality of pixel unit areas arranged in an array, each pixel unit area comprising a first sub-pixel area, a second sub-pixel area, a third sub-pixel area and a dummy structure area; a first electrode bonding pad, a second electrode bonding pad and a third electrode bonding pad, which are respectively located on the sides of the first sub-pixel area, the second sub-pixel area and the third sub-pixel area that face away from a substrate, and are electrically conductively connected to the second electrically conductive semiconductor layer; and a common-electrode bonding pad, which is located on the side of the dummy structure area that faces away from the substrate and is electrically conductively connected to the first electrically conductive semiconductor layer.

Description

Light-emitting elements and light-emitting devices

[0001] Related applications

[0002] This application claims priority to the following patent applications: Chinese patent application No. 202410485158.6, filed on April 22, 2024, entitled "Light-emitting element and light-emitting device"; Chinese patent application No. 202411808990.1, filed on December 10, 2024, entitled "A light-emitting device package and a method for preparing the same"; and Chinese patent application No. 202510131274.2, filed on February 6, 2025, entitled "Light-emitting structure and a method for preparing the same", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of semiconductor technology, and more specifically to a light-emitting element and a light-emitting device. Background Technology

[0004] Micro LED (Micro Light Emitting Diode) displays are the next-generation display technology following liquid crystal displays and OLED (Organic Light Emitting Diode) displays. Micro LED displays offer numerous advantages such as self-illumination, high efficiency, long lifespan, and ultra-high resolution, making them widely applicable in AR / VR near-eye display devices, wearable devices, and other fields. However, the structural design of the light-emitting element in these technologies limits their further development and application. Summary of the Invention

[0005] In view of the above, this application provides a light-emitting element and a light-emitting device to solve at least one problem existing in the background art.

[0006] In a first aspect, embodiments of this application provide a light-emitting element, the light-emitting element comprising: a substrate, including a first surface and a second surface opposite to each other; an epitaxial layer, located on the first surface of the substrate, including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer sequentially stacked along a direction away from the substrate; the epitaxial layer is patterned and divided into pixel unit regions comprising a plurality of arrayed pixel unit regions, each pixel unit region comprising a first sub-pixel region, a second sub-pixel region, a third sub-pixel region, and a dummy structure region; the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region are distributed at different positions of the pixel unit regions and respectively extend to the boundary of the pixel unit regions; The dummy structure region is located inside the pixel unit region or extends to the boundary of the pixel unit region; the first electrode pad, the second electrode pad, the third electrode pad, and the common electrode pad are respectively located on the side of the first sub-pixel region, the second sub-pixel region, the third sub-pixel region, and the dummy structure region away from the substrate; the first electrode pad, the second electrode pad, and the third electrode pad are electrically connected to the second conductive semiconductor layer in the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region, respectively; the common electrode pad is electrically connected to the first conductive semiconductor layer in the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region.

[0007] In conjunction with the first aspect of this application, in an optional embodiment, the dummy structure region extends to the boundary of the pixel unit region; the projections of the first sub-pixel region, the second sub-pixel region, the third sub-pixel region, and the dummy structure region onto the plane of the substrate are respectively located at the four vertices of the first quadrilateral region.

[0008] In conjunction with the first aspect of this application, in an optional embodiment, the first sub-pixel area is the luminous area of ​​a red sub-pixel, the second sub-pixel area is the luminous area of ​​a green sub-pixel, and the third sub-pixel area is the luminous area of ​​a blue sub-pixel; the second sub-pixel area is arranged adjacent to the dummy structure area; the dummy structure area and the third sub-pixel area are arranged along the diagonal of the first quadrilateral area.

[0009] In conjunction with the first aspect of this application, in an optional embodiment, the light-emitting element further includes: a first pixel groove, a second pixel groove, and a third pixel groove, all extending from the second surface of the substrate toward the epitaxial layer, and corresponding to the positions of the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region, respectively; and an optical material located in the first pixel groove and the second pixel groove; wherein the optical material located in the first pixel groove includes a red light conversion material, and the optical material located in the second pixel groove includes a green light conversion material.

[0010] In conjunction with the first aspect of this application, in an optional embodiment, the light-emitting element further includes: a second pixel groove extension extending from the second surface of the substrate toward the epitaxial layer and corresponding to the position of the dummy structure region; the second pixel groove extension communicates with the second pixel groove, and the green light conversion material is also located in the second pixel groove extension.

[0011] In conjunction with the first aspect of this application, in an optional embodiment, the sum of the projected areas of the second pixel groove and the second pixel groove extension on the plane where the substrate is located is greater than the projected area of ​​the first pixel groove on the plane where the substrate is located.

[0012] In conjunction with the first aspect of this application, in an optional embodiment, on the plane where the substrate is located, the projected area of ​​the third pixel groove is smaller than the projected area of ​​the first pixel groove and smaller than the projected area of ​​the second pixel groove.

[0013] In conjunction with the first aspect of this application, in an optional embodiment, on the plane where the substrate is located, the projected area of ​​the third sub-pixel region is smaller than the projected area of ​​the first sub-pixel region and smaller than the projected area of ​​the second sub-pixel region; the projected area of ​​the dummy structure region is smaller than the projected area of ​​the first sub-pixel region and smaller than the projected area of ​​the second sub-pixel region.

[0014] In conjunction with the first aspect of this application, in an optional embodiment, the ratio of the maximum width of the first pixel slot along the first direction to the maximum width of the second pixel slot along the first direction is 0.4:0.6 to 0.6:0.4; the first direction is the direction of the line connecting the farthest ends of the first pixel slot and the second pixel slot relative to each other.

[0015] In conjunction with a first aspect of this application, in an optional embodiment, the projections of the first pixel slot, the second pixel slot, the second pixel slot extension, and the third pixel slot onto the plane of the substrate are located in a second quadrilateral region; the first pixel slot extends to a first side and a second side of the second quadrilateral region, the first side and the second side intersecting each other; the second pixel slot extends to a third side and a fourth side of the second quadrilateral region, the third side and the fourth side intersecting each other; the third pixel slot extends to a second side and a third side of the second quadrilateral region; the second pixel slot extension extends to a first side and a fourth side of the second quadrilateral region; along the extension direction of the first side, the maximum slot width of the first pixel slot is greater than half the length of the first side; along the extension direction of the second side, the maximum slot width of the first pixel slot is greater than half the length of the second side; along the extension direction of the third side, the maximum slot width of the second pixel slot is greater than half the length of the third side; along the extension direction of the fourth side, the maximum slot width of the through slot formed by the second pixel slot extension and the second pixel slot intersecting each other is equal to the length of the fourth side.

[0016] In conjunction with the first aspect of this application, in an optional embodiment, the projection of the first pixel slot onto the plane of the substrate is composed of a first rectangle and a first right-angled trapezoid, the lower base of the first right-angled trapezoid coinciding with one side of the first rectangle; the projection of the through slot formed by the mutual penetration of the second pixel slot and the extension of the second pixel slot onto the plane of the substrate is composed of a second rectangle, a third rectangle, and a second right-angled trapezoid, the upper and lower bases of the second right-angled trapezoid coinciding with one side of the second rectangle and the third rectangle, respectively; the sloping sides of the second right-angled trapezoid and the sloping sides of the first right-angled trapezoid are adjacent and parallel to each other; the projection of the third pixel slot onto the plane of the substrate is a rectangle.

[0017] In conjunction with the first aspect of this application, in an optional embodiment, the green light conversion material comprises quantum dots; the optical material is located in the second pixel slot and the extension of the second pixel slot, and the optical material further comprises a light diffusion material located between the green light conversion material and the epitaxial layer.

[0018] In conjunction with the first aspect of this application, in an optional embodiment, the light-emitting element further includes: an isolation barrier comprising a first sub-segment, a second sub-segment, a third sub-segment, and a fourth sub-segment; wherein the first sub-segment is formed by a substrate located between the first pixel groove and the third pixel groove, the second sub-segment is formed by a substrate located between the second pixel groove and the third pixel groove, the third sub-segment is formed by a substrate located between the first pixel groove and the second pixel groove, and the fourth sub-segment is formed by a substrate located between the extension of the second pixel groove and the first pixel groove; one end of the third sub-segment is connected to the first sub-segment and the second sub-segment, and the other end of the third sub-segment is connected to the fourth sub-segment; the substrate is the growth substrate of the epitaxial layer.

[0019] In conjunction with the first aspect of this application, in an optional embodiment, the light-emitting element further includes: an isolation channel, comprising a first sub-channel, a second sub-channel, a third sub-channel, and a fourth sub-channel; wherein the first sub-channel is located between the first sub-pixel area and the third sub-pixel area; the second sub-channel is located between the second sub-pixel area and the third sub-pixel area; the third sub-channel is located between the first sub-pixel area and the second sub-pixel area; the fourth sub-channel is located between the first sub-pixel area and the dummy structure area; one end of the third sub-channel is connected to the first sub-channel. The third sub-channel is connected to the fourth sub-channel at one end, and the second sub-channel is connected to the third sub-channel at the other end. On the plane where the substrate is located, the projection shapes of the first sub-segment, the second sub-segment, the third sub-segment, and the fourth sub-segment in the isolation barrier are consistent with the projection shapes of the first sub-channel, the second sub-channel, the third sub-channel, and the fourth sub-channel in the isolation channel, and the projections of the first sub-channel, the second sub-channel, the third sub-channel, and the fourth sub-channel fall within the projections of the first sub-segment, the second sub-segment, the third sub-segment, and the fourth sub-segment, respectively.

[0020] In conjunction with the first aspect of this application, in an optional embodiment, the light-emitting element further includes: a first pixel groove, a second pixel groove, and a third pixel groove, all extending from the second surface of the substrate toward the epitaxial layer, and respectively corresponding to the positions of the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region; wherein, on the plane where the substrate is located, the projections of the active layer in the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region fall within the projections of the first pixel groove, the second pixel groove, and the third pixel groove, respectively.

[0021] In conjunction with the first aspect of this application, in an optional embodiment, the light-emitting element further includes: an isolation channel, including a fifth sub-channel, the fifth sub-channel being located between the second sub-pixel region and the dummy structure region; the fifth sub-channel extending from the epitaxial layer toward the substrate through the second conductive semiconductor layer and the active layer, but not through the first conductive semiconductor layer.

[0022] In conjunction with the first aspect of this application, in an optional embodiment, the light-emitting element further includes: a first upper reflective electrode, a second upper reflective electrode, and a third upper reflective electrode; the first upper reflective electrode is located between a second conductive semiconductor layer and a first electrode pad in the first sub-pixel region; the second upper reflective electrode is located between a second conductive semiconductor layer and a second electrode pad in the second sub-pixel region; the third upper reflective electrode is located between a second conductive semiconductor layer and a third electrode pad in the third sub-pixel region; an insulating layer including a first insulating portion, a second insulating portion, and a third insulating portion; wherein the first insulating portion covers a portion of the sidewall of the first sub-pixel region and extends to the first upper reflective electrode; the second insulating portion covers a portion of the sidewall of the second sub-pixel region and extends to the second upper reflective electrode; the third ... third insulating portion covers a portion of the sidewall of the second sub-pixel region and extends to the second upper reflective The third sub-pixel region has a partial sidewall that extends to the third upper reflective electrode; a first lower reflective electrode, a second lower reflective electrode, and a third lower reflective electrode; the first lower reflective electrode covers the sidewall of the first sub-pixel region that is not covered by the first insulating portion and extends to the first insulating portion; the second lower reflective electrode covers the sidewall of the second sub-pixel region that is not covered by the second insulating portion and extends to the second insulating portion; the third lower reflective electrode covers the sidewall of the third sub-pixel region that is not covered by the third insulating portion and extends to the third insulating portion; wherein, in the substrate thickness direction, the first lower reflective electrode partially overlaps with the first upper reflective electrode, the second lower reflective electrode partially overlaps with the second upper reflective electrode, and the third lower reflective electrode partially overlaps with the third upper reflective electrode.

[0023] In conjunction with the first aspect of this application, in an optional embodiment, the light-emitting element further includes: a first filter layer, a second filter layer, and a third filter layer, all located on the second surface of the substrate; wherein the first filter layer covers the first pixel groove, the second filter layer covers the second pixel groove and the extension of the second pixel groove, and the third filter layer covers the third pixel groove; and a protective capping layer covers the first filter layer, the second filter layer, the third filter layer, and the second surface of the substrate.

[0024] In conjunction with the first aspect of this application, in an optional embodiment, the shortest distance at the boundary between the pixel unit region and the light-emitting element is half the distance between two adjacent pixel unit regions.

[0025] Secondly, embodiments of this application provide a light-emitting device, which includes a plurality of seamlessly spliced ​​light-emitting elements as described in any of the above embodiments.

[0026] The light-emitting element provided in this application embodiment has three sub-pixel areas: a first sub-pixel area, a second sub-pixel area, and a third sub-pixel area, distributed at different positions within a pixel unit area and extending to the boundary of the pixel unit area. A dummy structure area is located inside the pixel unit area or extends to its boundary. Furthermore, a common electrode pad on the dummy structure area is electrically connected to the first conductive semiconductor layer in the first, second, and third sub-pixel areas. In this way, each sub-pixel area within a pixel unit area shares an electrode, reducing lead arrangement while allowing multiple pixel unit areas to operate independently. This allows for flexible arrangement of multiple pixel unit areas within the light-emitting element, facilitating the combination and splicing of multiple light-emitting elements to obtain larger-sized light-emitting devices.

[0027] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description

[0028] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0029] Figure 1 is a schematic diagram of the arrangement of pixel units at the boundary of the dummy structure region extending to the pixel unit region provided in Embodiment 1;

[0030] Figure 2 is a schematic diagram of the arrangement of pixel units located inside the pixel unit area in Embodiment 1;

[0031] Figure 3 is a schematic diagram of the cross-sectional structure of the pixel unit area provided in Embodiment 1, wherein (a), (b) and (c) are schematic diagrams of the cross-sectional structure along lines A-A', B-B' and C-C' in Figure 1, respectively;

[0032] Figure 4 is a schematic projection of the first semiconductor layer in the first sub-pixel region, second sub-pixel region, third sub-pixel region and dummy structure region provided in Embodiment 1 onto the plane where the substrate is located.

[0033] Figure 5 is a schematic projection of the second semiconductor layer in the first sub-pixel region, the second sub-pixel region, the third sub-pixel region and the dummy structure region provided in Embodiment 1 onto the plane where the substrate is located.

[0034] Figure 6 is a microscope image of the light-emitting element provided in Example 1;

[0035] Figure 7 is a schematic diagram of the projection of the first pixel groove, the second pixel groove, the extension of the second pixel groove and the third pixel groove provided in Embodiment 1 onto the plane where the substrate is located.

[0036] Figure 8 is a cross-sectional structural diagram of the first pixel slot, the second pixel slot, the extension of the second pixel slot and the third pixel slot provided in Embodiment 1. In Figures (a), (b) and (c) are cross-sectional structural diagrams along lines D-D', E-E' and F-F' in Figure 6, respectively.

[0037] Figure 9 is a cross-sectional structural diagram of the pixel unit provided in Embodiment 1, wherein (a), (b) and (c) are cross-sectional structural diagrams along lines D-D', E-E' and F-F' in Figure 6, respectively;

[0038] Figure 10 is a cross-sectional view of the light-emitting device package provided in an optional specific embodiment of Example 4;

[0039] Figure 11 is a schematic cross-sectional view of a conventional light-emitting device package;

[0040] Figure 12 is a schematic diagram of the light-emitting device package provided in an optional specific embodiment of Example 4;

[0041] Figure 13 is a schematic diagram of the support structure corresponding to one of the light-emitting chips in the structure shown in Figure 12;

[0042] Figure 14 is a schematic cross-sectional structure of the chip layer provided in Example 4;

[0043] Figure 15 is a schematic cross-sectional view of the first mask layer provided in Example 4;

[0044] Figure 16 is a schematic cross-sectional view of the second mask layer provided in Example 4;

[0045] Figure 17 is a cross-sectional structural diagram of the support structure provided in an optional specific embodiment of Example 4;

[0046] Figure 18 is a schematic cross-sectional view of a temporary substrate provided in an optional specific embodiment of Example 4;

[0047] Figure 19 is a schematic diagram of the light conversion material filling provided in an optional specific embodiment of Example 4;

[0048] Figure 20 is a schematic diagram of the encapsulation material filling provided in an optional specific embodiment of Example 4;

[0049] Figure 21 is a top view of the light-emitting device package provided in another optional specific embodiment of Example 4;

[0050] Figure 22 is a schematic diagram of the support structure corresponding to one of the light-emitting chips in the structure shown in Figure 21.

[0051] Figure 23 is a cross-sectional structural diagram of the support structure provided in another optional specific embodiment of Example 4;

[0052] Figure 24 is a schematic diagram of the light conversion material filling provided in another optional specific embodiment of Example 4;

[0053] Figure 25 is a schematic diagram of the encapsulation material filling provided in another optional specific embodiment of Example 4;

[0054] Figure 26 is a schematic diagram of the second encapsulation layer provided in another optional specific embodiment of Example 4;

[0055] Figure 27 is a schematic diagram of the packaging and cutting of the light-emitting device provided in another optional specific embodiment of Example 4;

[0056] Figure 28 is a schematic flowchart of the fabrication method of the light-emitting device package provided in Example 5;

[0057] Figure 29 is a schematic flowchart of the method for preparing the light-emitting structure provided in Example 6;

[0058] Figure 30 is a cross-sectional structural diagram of the pixel unit provided in Embodiment 6;

[0059] Figure 31 is a global layout of the structure shown in Figure 30;

[0060] Figure 32 is a schematic diagram of the arrangement of each sub-pixel unit in Figure 30;

[0061] Figure 33 is a schematic cross-sectional view of the pixel groove provided in Embodiment 6;

[0062] Figure 34 is a layout diagram of the structure shown in Figure 33;

[0063] Figure 35 is a cross-sectional structural diagram of the color conversion layer provided in Example 6;

[0064] Figures 36 to 39 are schematic cross-sectional views of the light-emitting structure provided in an optional specific embodiment of Example 6 during the preparation process;

[0065] Figure 40 is a schematic diagram of the exposure pattern on the first filter material layer;

[0066] Figure 41 is a schematic diagram of the exposure pattern on the second filter material layer;

[0067] Figures 42 to 46 are schematic cross-sectional views of the light-emitting structure during the preparation process provided in another optional specific embodiment of Example 6;

[0068] Figure 47 is a global layout of the structures shown in Figures 38 and 45;

[0069] Figure 48 is a schematic flowchart of the fabrication method of the light-emitting device provided in Example 8;

[0070] Figure 49 is a cross-sectional structural diagram of the chip layer provided in Example 8;

[0071] Figure 50 is a schematic diagram of the projection of the pixel unit area on the plane of the substrate provided in Embodiment 8;

[0072] Figure 51 is a schematic diagram of the projection of the pixel unit area on the plane of the substrate provided in Embodiment 8;

[0073] Figure 52 is a cross-sectional structural diagram of the pixel unit area provided in Embodiment 8, wherein (a) and (b) are cross-sectional structural diagrams along the lines A1-A1' and A2-A2' in Figure 50, respectively;

[0074] Figure 53 is a cross-sectional structural diagram of a pixel unit region provided in an optional specific embodiment of Example 8, wherein (a) and (b) are cross-sectional structural diagrams along lines A3-A3' and A4-A4' in Figure 50, respectively;

[0075] Figure 54 is a cross-sectional structural diagram of the pixel unit area provided in another optional specific embodiment of Example 8, wherein (a) and (b) are cross-sectional structural diagrams along lines A3-A3' and A4-A4' in Figure 50, respectively;

[0076] Figure 55 is a cross-sectional structural diagram of the cover layer and each electrode pad provided in Example 8;

[0077] Figure 56 is a cross-sectional structural diagram of the cover layer and each electrode pad provided in an optional specific embodiment of Example 8.

[0078] Figure 57 is a cross-sectional structural diagram of the cover layer and each electrode pad provided in another optional specific embodiment of Example 8.

[0079] Figure 58 is a schematic diagram of the projection of the pixel groove onto the plane of the substrate provided in an optional specific embodiment of Example 8;

[0080] Figure 59 is a schematic diagram of the projection of the pixel groove onto the plane of the substrate provided in another optional specific embodiment of Example 8;

[0081] Figure 60 is a cross-sectional view of the pixel slot provided in Embodiment 8, wherein (a) and (b) are cross-sectional views along lines B1-B1' and B2-B2' in Figure 58, respectively.

[0082] Figure 61 is a cross-sectional view of the pixel slot provided in an optional specific embodiment of Example 8, wherein (a) and (b) are cross-sectional views along lines B3-B3' and B4-B4' in Figure 58, respectively.

[0083] Figure 62 is a cross-sectional view of the pixel slot provided in another optional specific embodiment of Example 8, wherein (a) and (b) are cross-sectional views along lines C3-C3' and C4-C4' in Figure 59, respectively.

[0084] Figure 63 is a cross-sectional structural diagram of the optical material, filter layer and protective cover plate provided in Example 8;

[0085] Figure 64 is a cross-sectional structural diagram of the optical material, filter layer and protective cover provided in an optional specific embodiment of Example 8.

[0086] Figure 65 is a cross-sectional structural diagram of the optical material, filter layer and protective cover provided in another optional specific embodiment of Example 8;

[0087] Figure 66 is a schematic diagram of the projection of each electrode on the plane of the welding substrate provided in Example 8;

[0088] Figure 67 is a cross-sectional view of the welding substrate provided in Example 8, wherein (a) and (b) are cross-sectional views along lines D1-D1' and D2-D2' in Figure 66, respectively.

[0089] Figure 68 is a cross-sectional view of the welding substrate provided in Example 8, wherein (a) and (b) are cross-sectional views along lines D3-D3' and D4-D4' in Figure 66, respectively.

[0090] Figure 69 is a cross-sectional structural diagram of the light-emitting device provided in Example 8;

[0091] Figure 70 is a cross-sectional structural diagram of the light-emitting device provided in an optional specific embodiment of Example 8;

[0092] Figure 71 is a cross-sectional structural diagram of the light-emitting device provided in another optional specific embodiment of Example 8. Detailed Implementation

[0093] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0094] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0095] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0096] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0097] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0098] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0099] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0100] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0101] Figure 1 is a schematic diagram of the arrangement of pixel units extending from the virtual structure region to the boundary of the pixel unit region provided in the embodiment of this application; Figure 2 is a schematic diagram of the arrangement of pixel units located inside the pixel unit region provided in the embodiment of this application; Figure 3 is a schematic diagram of the cross-sectional structure of the pixel unit region provided in the embodiment of this application, wherein (a), (b) and (c) are schematic diagrams of the cross-sectional structure along lines A-A', B-B' and C-C' in Figure 1, respectively.

[0102] This application provides a light-emitting element. Please refer to Figures 1 to 3. The light-emitting element includes:

[0103] The substrate 100 includes a first surface 101 and a second surface 102 that are opposite to each other;

[0104] The epitaxial layer 110, located on the first surface 101 of the substrate 100, includes a first conductive semiconductor layer 111, an active layer 112, and a second conductive semiconductor layer 113 sequentially stacked in a direction away from the substrate 100. The epitaxial layer 110 is patterned and divided into multiple pixel unit regions 120 arranged in an array. Each pixel unit region 120 includes a first sub-pixel region 120a, a second sub-pixel region 120b, a third sub-pixel region 120c, and a dummy structure region 120d. The first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c are distributed at different positions in the pixel unit region 120 and extend to the boundary of the pixel unit region 120, respectively. The dummy structure region 120d is located inside the pixel unit region 120 (as shown in Figure 2) or extends to the boundary of the pixel unit region 120 (as shown in Figure 1).

[0105] The first electrode pad 210a, the second electrode pad 210b, the third electrode pad 210c, and the common electrode pad 220 are located on the side away from the substrate 100 of the first sub-pixel region 120a, the second sub-pixel region 120b, the third sub-pixel region 120c, and the dummy structure region 120d, respectively. The first electrode pad 210a, the second electrode pad 210b, and the third electrode pad 210c are electrically connected to the second conductive semiconductor layer 113 in the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c, respectively. The common electrode pad 220 is electrically connected to the first conductive semiconductor layer 111 in the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c.

[0106] It is understood that the light-emitting element provided in this application embodiment, by setting the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c to be distributed at different positions in the pixel unit region 120 and extending to the boundary of the pixel unit region 120, and the dummy structure region 120d located inside the pixel unit region 120 or extending to the boundary of the pixel unit region 120, and the common electrode pad 220 located on the dummy structure region 120d being electrically connected to the first conductive semiconductor layer 111 in the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c, allows each sub-pixel region in a pixel unit region 120 to share an electrode, which can reduce the wiring arrangement while making multiple pixel unit regions 120 independent of each other. In this way, multiple pixel unit regions 120 in the light-emitting element can be flexibly arranged, which is beneficial for combining and splicing multiple light-emitting elements to obtain a larger size light-emitting device.

[0107] In some embodiments, referring to FIG3, the substrate 100 may be a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, a silicon substrate, or other semiconductor material substrates known in the art. In the embodiments of this application, the substrate 100 may be a silicon substrate.

[0108] It should be noted that the plane on which the first surface 101 and the second surface 102 of the substrate 100 are located, or more precisely, the center plane in the thickness direction of the substrate 100, is defined as the plane on which the substrate 100 is located, and the direction perpendicular to the plane on which the substrate 100 is located is along the thickness direction of the substrate 100.

[0109] In some specific embodiments, referring to FIG3, the substrate 100 can be a growth substrate, and the epitaxial layer 110 is formed on the growth substrate by an epitaxial growth process. The epitaxial layer 110 is patterned (e.g., photolithography, etching, etc.) and divided into pixel unit regions 120 including multiple arrays (as shown in FIG1 and FIG2).

[0110] It should be understood that Figures 1 and 2 only illustrate cases where the projection shape of the pixel unit area 120 onto the plane of the substrate 100 is rectangular or circular, and each pixel unit area 120 includes three sub-pixel areas and one dummy structure area. This application does not exclude cases where the projection shape of the pixel unit area 120 onto the plane of the substrate 100 is triangular, trapezoidal, pentagonal, or other suitable shape. This application also does not exclude cases where the pixel unit area 120 includes four, five, or more sub-pixel areas; and / or, the pixel unit area 120 includes multiple dummy structure areas.

[0111] In some embodiments, the shortest distance between the pixel unit area 120 and the boundary of the light-emitting element is half the distance between two adjacent pixel unit areas 120. Thus, after multiple light-emitting elements are combined and spliced, the distance between two adjacent pixel unit areas on different light-emitting elements is equal to the distance between two adjacent pixel unit areas in a single light-emitting element, which helps improve the display performance, such as display consistency, of the light-emitting device obtained by splicing multiple light-emitting elements.

[0112] In some embodiments, the distance between two adjacent pixel unit areas 120 is greater than the distance between the first sub-pixel area 120a, the second sub-pixel area 120b, the third sub-pixel area 120c and the dummy structure area 120d in the same pixel unit area 120.

[0113] In some embodiments, referring to Figures 1 and 3, the light-emitting element further includes: an isolation channel 230, including a first sub-channel 231, a second sub-channel 232, a third sub-channel 233, and a fourth sub-channel 234; wherein, the first sub-channel 231 is located between the first sub-pixel area 120a and the third sub-pixel area 120c; the second sub-channel 232 is located between the second sub-pixel area 120b and the third sub-pixel area 120c; the third sub-channel 233 is located between the first sub-pixel area 120a and the second sub-pixel area 120b; the fourth sub-channel 234 is located between the first sub-pixel area 120a and the dummy structure area 120d; one end of the third sub-channel 233 is connected to the first sub-channel 231 and the second sub-channel 232, and the other end of the third sub-channel 233 is connected to the fourth sub-channel 234.

[0114] Thus, through the isolation effect of each sub-channel in the isolation channel 230, while ensuring the isolation of each sub-pixel area from each other, each sub-pixel area obtains a more reasonable distribution and a suitable regional outline, which is conducive to adjusting the arrangement of multiple sub-pixels of different colors and the size of the light-emitting area.

[0115] Figure 4 is a schematic projection of the first semiconductor layer in the first sub-pixel area, second sub-pixel area, third sub-pixel area and dummy structure area provided in the embodiment of this application onto the plane where the substrate is located; Figure 5 is a schematic projection of the second semiconductor layer in the first sub-pixel area, second sub-pixel area, third sub-pixel area and dummy structure area provided in the embodiment of this application onto the plane where the substrate is located.

[0116] Specifically, referring to Figures 4 and 5, the first sub-channel 231, the second sub-channel 232, the third sub-channel 233, and the fourth sub-channel 234 extend from the epitaxial layer 110 into the substrate 100, penetrating the second conductive semiconductor layer 113, the active layer 112, and the first conductive semiconductor layer 111. That is, the first conductive semiconductor layer 111, the active layer 112, and the second conductive semiconductor layer 113 located on the first sub-channel 231, the second sub-channel 232, the third sub-channel 233, and the fourth sub-channel 234 are all completely removed. The first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c are mutually isolated. Of course, in some other embodiments, the epitaxial layers located on the first sub-channel 231, the second sub-channel 232, the third sub-channel 233, and the fourth sub-channel 234 may only be partially removed.

[0117] In some embodiments, referring further to Figures 1 and 3, the isolation channel 230 also includes a fifth sub-channel 235, which is located between the second sub-pixel region 120b and the dummy structure region 120d. The fifth sub-channel 235 extends from the epitaxial layer 110 toward the substrate 100 through the second conductive semiconductor layer 113 and the active layer 112, but does not extend through the first conductive semiconductor layer 111. That is, the active layer 112 and the second conductive semiconductor layer 113 located on the fifth sub-channel 235 are completely removed, while only a portion of the first conductive semiconductor layer 111 is removed. The epitaxial layers in the second sub-pixel region 120b and the dummy structure region 120d are not completely isolated. The first conductive semiconductor layer 111 in the dummy structure region 120d and the first conductive semiconductor layer 111 in the second sub-pixel region 120b are connected through the first conductive semiconductor layer 111 located on the fifth sub-channel 235 (as shown in Figure 4); or in other words, the first conductive semiconductor layer 111 in the dummy structure region 120d and the first conductive semiconductor layer 111 in the second sub-pixel region 120b are physically connected.

[0118] In some embodiments, referring to FIG3, the common electrode pad 220 forms an ohmic contact with the first conductive semiconductor layer 111 in the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c, which can provide low series resistance electrical conduction for the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c, thereby achieving uniformity of series resistance.

[0119] It should be noted that the dummy structure region 120d corresponding to the common electrode pad 220 is a structure that provides support for the common electrode pad 220 and is used to adjust the height of the common electrode pad 220. Here, the dummy structure region is not used as a light-emitting region, and the active layer 112 in the dummy structure region 120d will not emit light.

[0120] In this embodiment, along the thickness direction of the substrate 100, the height of the dummy structure region 120d is consistent with the heights of the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c. Thus, along the thickness direction of the substrate 100, the distances between the first electrode pad 210a, the second electrode pad 210b, the third electrode pad 210c, and the common electrode pad 220 and the first surface 101 of the substrate 100 are consistent. This improves the height difference between the electrode pads, thereby reducing the phenomena of poor soldering and over-soldering, further reducing damage to the light-emitting element, improving flip-chip soldering yield, and lowering manufacturing costs.

[0121] In some embodiments, referring to FIG3, the first conductive semiconductor layer 111 can be an N-type conductive semiconductor layer, and the second conductive semiconductor layer 113 can be a P-type conductive semiconductor layer; the active layer 112 can be a multiple quantum well layer. Accordingly, the first electrode pad 210a, the second electrode pad 210b, and the third electrode pad 210c can be P-type electrode pads (P-PADs), and the common electrode pad 220 can be an N-type electrode pad (N-PAD). Here, the first conductive semiconductor layer 111 can also be referred to as the "first semiconductor layer", the second conductive semiconductor layer 113 can also be referred to as the "second semiconductor layer", and the active layer 112 can also be referred to as the "semiconductor light-emitting layer".

[0122] In some specific embodiments, the materials of the first conductive semiconductor layer 111 and the second conductive semiconductor layer 113 may include at least one of gallium nitride (GaN), gallium arsenide nitride (GaNAs), gallium phosphide (GaP), aluminum gallium arsenide (AlGaAs), and indium phosphide (InP). The materials of the first electrode pad 210a, the second electrode pad 210b, the third electrode pad 210c, and the common electrode pad 220 include at least one of titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), silver (Ag), and tin (Sn), or alloys of the above metal materials.

[0123] In some embodiments, referring to FIG2, the dummy structure region 120d is located inside the pixel unit region 120; the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c surround the dummy structure region 120d. The projections of the first sub-pixel region 120a, the second sub-pixel region 120b, the third sub-pixel region 120c, and the dummy structure region 120d onto the plane of the substrate 100 lie in a circular region.

[0124] In some other embodiments, referring to FIG1, the dummy structure region 120d extends to the boundary of the pixel unit region 120; the projections of the first sub-pixel region 120a, the second sub-pixel region 120b, the third sub-pixel region 120c, and the dummy structure region 120d onto the plane of the substrate 100 are respectively located at the four vertices of the first quadrilateral region 121. Thus, when the distance between each pixel unit region 120 is constant, the occupied area of ​​the pixel unit region 120 can be further increased, thereby increasing the effective light-emitting area of ​​the light-emitting element.

[0125] It should be understood that although Figure 1 only shows that the projections of the first sub-pixel area 120a, the second sub-pixel area 120b, the third sub-pixel area 120c, and the dummy structure area 120d on the plane of the substrate 100 are located at the four vertices of the rectangular area, this application does not exclude the possibility that the projections of the first sub-pixel area 120a, the second sub-pixel area 120b, the third sub-pixel area 120c, and the dummy structure area 120d are located at the four vertices of the trapezoidal, parallelogram, rhomboid, or other quadrilateral areas.

[0126] In some specific embodiments, the projected shapes of the first sub-pixel region 120a, the second sub-pixel region 120b, the third sub-pixel region 120c, and the dummy structure region 120d on the plane of the substrate 100 can be rectangular, trapezoidal, circular, triangular, or other suitable shapes; the projected shapes of the first sub-pixel region 120a, the second sub-pixel region 120b, the third sub-pixel region 120c, and the dummy structure region 120d can be the same or different. This application does not impose specific limitations on this.

[0127] In some embodiments, referring to FIG1, the first sub-pixel area 120a is the light-emitting area of ​​the red sub-pixel, the second sub-pixel area 120b is the light-emitting area of ​​the green sub-pixel, and the third sub-pixel area 120c is the light-emitting area of ​​the blue sub-pixel; the second sub-pixel area 120b is arranged adjacent to the dummy structure area 120d; the dummy structure area 120d and the third sub-pixel area 120c are arranged along the diagonal of the first quadrilateral area 121.

[0128] It is understandable that red, green, and blue sub-pixels can constitute a single light-emitting pixel unit (full-color LED chip), emitting red, green, and blue light. This arrangement allows the red and green sub-pixels to be arranged diagonally, and the blue sub-pixel to be diagonally arranged with the common electrode area (i.e., the area containing the dummy structure region 120d), providing more space for the red and green sub-pixels. This helps to increase the light-emitting area of ​​the red and green sub-pixels, reduces the difficulty of filling the light conversion material within them, and consequently reduces the blue light radiation intensity per unit area of ​​the light conversion material, thus increasing its lifespan.

[0129] It should be noted that the sub-pixel area is also called the "light-emitting core," and the pixel unit area is also called the "light-emitting chip." The light-emitting chip can be a blue light chip or an ultraviolet light chip; the light-emitting chip can be a Micro LED (micro light-emitting diode) chip. The red, green, and blue sub-pixels use the same light-emitting chip, and the materials and light-emitting characteristics of the light-emitting areas of each sub-pixel are highly consistent, which is beneficial to improving the display effect and long-term stability of the light-emitting element (full-color LED wafer).

[0130] In this embodiment of the application, please refer to FIG1. ​​On the plane where the substrate 100 is located, the projected area of ​​the third sub-pixel region 120c is smaller than the projected area of ​​the first sub-pixel region 120a and smaller than the projected area of ​​the second sub-pixel region 120b; the projected area of ​​the dummy structure region 120d is smaller than the projected area of ​​the first sub-pixel region 120a and smaller than the projected area of ​​the second sub-pixel region 120b.

[0131] In some specific embodiments, please refer to Figure 1. The first sub-pixel area 120a and the second sub-pixel area 120b can be located at the upper right corner and the lower left corner of the first quadrilateral area 121, respectively; the third sub-pixel area 120c and the dummy structure area 120d can be located at the lower right corner and the upper left corner of the first quadrilateral area 121, respectively.

[0132] Of course, in some other embodiments, the first sub-pixel area 120a and the second sub-pixel area 120b can be located at the lower left corner and the upper right corner of the first quadrilateral area 121, respectively; the third sub-pixel area 120c and the dummy structure area 120d can be located at the lower right corner and the upper left corner of the first quadrilateral area 121, respectively, or they can be located at the upper left corner and the lower right corner of the first quadrilateral area 121, respectively.

[0133] Figure 6 is a microscope image of the light-emitting element provided in the embodiment of this application; Figure 7 is a schematic projection of the first pixel groove, the second pixel groove, the extension of the second pixel groove and the third pixel groove provided in the embodiment of this application onto the plane where the substrate is located; Figure 8 is a schematic cross-sectional structure of the first pixel groove, the second pixel groove, the extension of the second pixel groove and the third pixel groove provided in the embodiment of this application, wherein (a), (b) and (c) are schematic cross-sectional structures along lines D-D', E-E' and F-F' in Figure 6, respectively.

[0134] In some embodiments, referring to Figures 6 to 8, the light-emitting element further includes a first pixel groove 130a, a second pixel groove 130b, and a third pixel groove 130c, all extending from the second surface 102 of the substrate 100 toward the epitaxial layer 110, and corresponding to the positions of the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c, respectively.

[0135] It should be noted that in actual fabrication, the fabricated pixel unit region 120 needs to be flip-chip bonded to a temporary carrier plate so that the first pixel groove 130a, the second pixel groove 130b, and the third pixel groove 130c can be fabricated on the second surface 102 of the substrate 100 through processes such as photolithography and etching. Therefore, it can be understood that Figures 6 and 7 are schematic diagrams showing the pixel unit region 120 flip-chip bonded to the temporary carrier plate, with the first pixel groove 130a, the second pixel groove 130b, and the third pixel groove 130c located above the pixel unit region 120.

[0136] In some specific embodiments, the first pixel groove 130a, the second pixel groove 130b and the third pixel groove 130c can penetrate the substrate 100 to expose the surface of the epitaxial layer 110 in contact with the substrate 100; when the substrate 100 has good light transmittance, each pixel groove can also extend only into the substrate 100.

[0137] In this embodiment of the application, please refer to FIG8. The first pixel groove 130a, the second pixel groove 130b and the third pixel groove 130c all penetrate the substrate 100. Along the thickness direction of the substrate 100, the depth of the first pixel groove 130a, the second pixel groove 130b and the third pixel groove 130c is equal to the thickness of the substrate 100.

[0138] In some embodiments, the projected shapes of the first pixel slot 130a, the second pixel slot 130b, and the third pixel slot 130c on the plane of the substrate 100 can be rectangular, trapezoidal, circular, triangular, or other suitable shapes; the projected shapes of the first pixel slot 130a, the second pixel slot 130b, and the third pixel slot 130c can be the same or different.

[0139] In some specific embodiments, referring to Figure 7, the projected shapes of the first pixel slot 130a, the second pixel slot 130b, and the third pixel slot 130c are the same as the projected shapes of the corresponding first sub-pixel areas 120a, 120b, and 120c. Of course, in some other embodiments, the projected shapes of the first pixel slot 130a, the second pixel slot 130b, and the third pixel slot 130c may not be the same as the projected shapes of the corresponding first sub-pixel areas 120a, 120b, and 120c. This application does not impose specific limitations in this regard.

[0140] In some embodiments, referring to FIG8, on the plane where the substrate 100 is located, the projections of the first pixel groove 130a, the second pixel groove 130b and the third pixel groove 130c fall into the projections of the first conductive semiconductor layer 111 of the first sub-pixel region 120a, the second sub-pixel region 120b and the third sub-pixel region 120c, respectively.

[0141] In some embodiments, referring to FIG8, on the plane of the substrate 100, the projections of the active layer 112 in the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c fall within the projections of the first pixel slot 130a, the second pixel slot 130b, and the third pixel slot 130c, respectively. Thus, the active layer 112 has a smaller area, which is beneficial for increasing the current density of the light-emitting element, enabling the light-emitting element to operate at a higher current density, thereby improving light output efficiency.

[0142] Figure 9 is a cross-sectional structural diagram of the pixel unit provided in the embodiment of this application, wherein (a), (b) and (c) are cross-sectional structural diagrams along lines D-D', E-E' and F-F' in Figure 6, respectively.

[0143] In some embodiments, referring to FIG9, the light-emitting element further includes: optical materials located in the first pixel slot 130a and the second pixel slot 130b; wherein the optical material located in the first pixel slot 130a includes red light conversion material 150a, and the optical material located in the second pixel slot 130b includes green light conversion material 150b.

[0144] In some specific embodiments, the red light conversion material 150a and the green light conversion material 150b may include phosphors or quantum dots. When excited by external energy, both phosphors and quantum dots undergo electron transitions, releasing energy in the form of light. Furthermore, by adjusting the composition and size of the phosphors and quantum dots, the emitted color can be controlled, allowing each pixel slot to emit light of different colors. Here, the light conversion material is also referred to as a "color conversion material" or "color conversion layer." It should be noted that this embodiment is not limited to filling the first pixel slot 130a with red light conversion material and the second pixel slot 130b with green light conversion material; those skilled in the art can adjust the filled light conversion material according to actual conditions.

[0145] In actual fabrication, please refer to Figure 9. When both the red light conversion material 150a and the green light conversion material 150b include quantum dots, the optical materials located in the first pixel groove 130a and the second pixel groove 130b also include a light diffusion material 140. The light diffusion material 140 is located between the red light conversion material 150a and the epitaxial layer 110, and between the green light conversion material 150b and the epitaxial layer 110.

[0146] Here, the light-diffusing material 140 is set, which is conducive to the quantum dot receiving uniform light irradiation, thereby effectively reducing the light intensity at the center of the quantum dot, greatly improving the light stability of the quantum dot, and improving the situation where local quantum dots are prone to light quenching due to excessive light intensity at the center, thus effectively extending the luminescence lifetime.

[0147] The light-diffusing material 140 includes diffusing particles, which can be organic materials, inorganic materials, or organic-inorganic composite materials, such as polystyrene, silicon dioxide, and titanium dioxide. By incorporating the light-diffusing particles into the interior or surface of a matrix, the light-diffusing properties are achieved through the reflection and refraction of light between the diffusing particles. The light-diffusing material 140 is also known as a "light-diffusing layer".

[0148] In some embodiments, the optical material may also be located in the third pixel slot 130c. Specifically, when the light emitted by the first sub-pixel area 120a, the second sub-pixel area 120b, and the third sub-pixel area 120c is blue light, the optical material located in the third pixel slot 130c includes a light-diffusing material 140 (as shown in Figure 9(a)); when the light emitted by the first sub-pixel area 120a, the second sub-pixel area 120b, and the third sub-pixel area 120c is ultraviolet light, the optical material located in the third pixel slot 130c may include a blue light conversion material and a light-diffusing material located between the blue light conversion material and the epitaxial layer 110.

[0149] In some embodiments, referring to FIG7, on the plane of the substrate 100, the projected area of ​​the third pixel groove 130c is smaller than the projected area of ​​the first pixel groove 130a and smaller than the projected area of ​​the second pixel groove 130b. This is beneficial to increasing the filling area of ​​the red light conversion material 150a and the green light conversion material 150b, reducing the filling difficulty of the red light conversion material 150a and the green light conversion material 150b, and reducing the blue light radiation intensity per unit area of ​​the red light conversion material 150a and the green light conversion material 150b, thereby improving the service life of the red light conversion material 150a and the green light conversion material 150b.

[0150] In some embodiments, referring to FIG7, the ratio of the maximum slot width D1 of the first pixel slot 130a along the first direction X and the maximum slot width D2 of the second pixel slot 130b along the first direction X is 0.4:0.6 to 0.6:0.4; the first direction X is the direction of the line connecting the farthest ends of the first pixel slot 130a and the second pixel slot 130b relative to each other.

[0151] Understandably, if the ratio of D1 to D2 is too low or too high, the width of the first pixel slot 130a or the second pixel slot 130b along the first direction X will be too small, thus affecting the efficiency of filling optical material in the first pixel slot 130a and the second pixel slot 130b. Therefore, a ratio of D1 to D2 of 0.4:0.6 to 0.6:0.4 is beneficial to reducing the difficulty of filling optical material in the first pixel slot 130a or the second pixel slot 130b and improving production efficiency.

[0152] In some embodiments, referring to Figures 7 and 8, the light-emitting element further includes: a second pixel groove extension 130b' extending from the second surface 102 of the substrate 100 toward the epitaxial layer 110 and corresponding to the position of the dummy structure region 120d; the second pixel groove extension 130b' communicates with the second pixel groove 130b, and the green light conversion material 150b is also located in the second pixel groove extension 130b'.

[0153] It should be noted that, since the first conductive semiconductor layer 111 in the dummy structure region 120d and the first conductive semiconductor layer 111 in the third sub-pixel region 120c are connected by the first conductive semiconductor layer 111 located on the fifth sub-channel 235, when the second pixel groove extension 130b' and the second pixel groove 130b are interconnected, the first conductive semiconductor layer 111 located on the fifth sub-channel 235 can provide support for the green light conversion material 150b.

[0154] In some specific embodiments, the depth of the second pixel groove extension 130b' along the thickness direction of the substrate 100 is consistent with the depth of the second pixel groove 130b.

[0155] It is understandable that the second pixel slot extension 130b' and the second pixel slot 130b are interconnected to form a through slot, which expands the pixel slot filled with green light conversion material 150b to the area where the dummy structure area 120d is located. The area of ​​the pixel slot corresponding to the green sub-pixel is further increased, which is beneficial to the filling of green light conversion material 150b and the reduction of blue light radiation intensity of green light conversion material 150b, thereby improving the service life of green light conversion material 150b.

[0156] In some embodiments, referring to FIG7, the sum of the projected areas of the second pixel slot 130b and the second pixel slot extension 130b' on the plane of the substrate 100 is greater than the projected area of ​​the first pixel slot 130a on the plane of the substrate 100. This is beneficial for the pixel unit to emit white light. Specifically, the ratio of the areas of the first pixel slot 130a, the through slot, and the third pixel slot 130c is 3:6:1.

[0157] In some embodiments, referring to FIG9, the green light conversion material 150b includes quantum dots; the optical material is located in the second pixel slot 130b and the second pixel slot extension 130b', and the optical material further includes a light diffusion material 140 located between the green light conversion material 150b and the epitaxial layer 110.

[0158] It is understandable that when the active layer 112 of the dummy structure region 120d does not emit light, by providing a light diffusion material 140 at the bottom of the second pixel slot 130b and the second pixel slot extension 130b', the light emitted by the second sub-pixel region 120b can be diffused into the second pixel slot extension 130b', thereby making the green sub-pixel emit uniform green light.

[0159] In some embodiments, referring to FIG7, the projections of the first pixel groove 130a, the second pixel groove 130b, the second pixel groove extension 130b', and the third pixel groove 130c onto the plane of the substrate 100 are located in the second quadrilateral region 122; the first pixel groove 130a extends to the first side S1 and the second side S2 of the second quadrilateral region 122, and the first side S1 and the second side S2 intersect each other; the second pixel groove 130b extends to the third side S3 and the fourth side S4 of the second quadrilateral region 122, and the third side S3 and the fourth side S4 intersect each other; the third pixel groove 130c extends to the second side S2 and the third side S3 of the second quadrilateral region 122; the second pixel groove 130a extends to the second side S2 and the third side S3 of the second quadrilateral region 122; the second pixel groove 130a extends to the second side S2 and the third side S3 of the second quadrilateral region 122; the second pixel groove 130a extends to the second side S2 and the third side S3 of the second quadrilateral region 122; the second pixel groove 130a extends to the second side S2 and the third side S3 of the second quadrilateral region 122; the second pixel groove 130a extends to the second side S3 and the third side S4 of the second quadrilateral region 122; the second pixel groove 130a extends to the second side S2 and the third side S3 ... The pixel groove extension 130b' extends to the first side S1 and the fourth side S4 of the second quadrilateral region 122; along the extension direction of the first side S1, the maximum groove width D3 of the first pixel groove 130a is greater than half the length of the first side S1; along the extension direction of the second side S2, the maximum groove width D4 of the first pixel groove 130a is greater than half the length of the second side S2; along the extension direction of the third side S3, the maximum groove width D5 of the second pixel groove 130b is greater than half the length of the third side S3; along the extension direction of the fourth side S4, the maximum groove width D6 of the through groove formed by the mutual penetration of the second pixel groove extension 130b' and the second pixel groove 130b is equal to the length of the fourth side S4.

[0160] In this way, the area of ​​the pixel slots corresponding to the red and green sub-pixels can be further increased, which is beneficial to the filling of red light conversion material 150a and green light conversion material 150b, reduces the blue light radiation intensity of red light conversion material 150a and green light conversion material 150b, and improves the service life of red light conversion material 150a and green light conversion material 150b.

[0161] In some specific embodiments, please refer to FIG7. The projection of the first pixel groove 130a onto the plane of the substrate 100 is composed of a first rectangle R1 and a first right trapezoid T1, the lower base of the first right trapezoid T1 coincides with one side of the first rectangle R1; the projection of the through groove formed by the mutual penetration of the second pixel groove 130b and the second pixel groove extension 130b' onto the plane of the substrate 100 is composed of a second rectangle R2, a third rectangle R3 and a second right trapezoid T2, the upper base and the lower base of the second right trapezoid T2 coincide with one side of the second rectangle R2 and the third rectangle R3 respectively; the sloping sides of the second right trapezoid T2 and the sloping sides of the first right trapezoid T1 are adjacent and parallel to each other; the projection of the third pixel groove 130c onto the plane of the substrate 100 is a rectangle.

[0162] This maximizes the area of ​​the pixel slots corresponding to the red and green sub-pixels, which is beneficial for filling the red light conversion material 150a and the green light conversion material 150b, reducing the blue light radiation intensity of the red light conversion material 150a and the green light conversion material 150b, and improving the service life of the red light conversion material 150a and the green light conversion material 150b.

[0163] It should be noted that in actual fabrication, the corners and edges of the first pixel groove 130a, the through groove, and the third pixel groove 130c need to be chamfered to create a rounded transition between the sharp protruding parts of these three grooves. Therefore, the rectangles and trapezoids mentioned above refer to shapes whose general outlines are the same as those of rectangles and trapezoids.

[0164] Specifically, the vertex corners of the projected shape of the first pixel groove 130a, which is composed of the first rectangle R1 and the first right trapezoid T1, are chamfered; the vertex corners of the projected shape of the through groove, which is composed of the second rectangle R2, the third rectangle R3, and the second right trapezoid T2, are chamfered; and the vertex corners of the rectangle obtained by projecting the third pixel groove 130c onto the plane of the substrate 100 are chamfered.

[0165] In some embodiments, the sidewalls of the first pixel slot 130a, the through slot, and the third pixel slot 130c are further provided with an optically insulating reflective layer (not shown in the figure) to improve the optical crosstalk phenomenon between sub-pixels. The optically insulating reflective layer can be a metal reflective layer, and the material of the metal reflective layer includes, for example, chromium (Cr) and aluminum (Al); the optically insulating reflective layer can also be a DBR reflective layer (Bragg reflective layer), and the material of the DBR reflective layer includes, for example, silicon oxide (SiO2) and titanium oxide (TiO2).

[0166] In some embodiments, referring to Figures 7 and 8, the light-emitting element further includes:

[0167] The isolation barrier 160 includes a first sub-segment 160a, a second sub-segment 160b, a third sub-segment 160c, and a fourth sub-segment 160d. The first sub-segment 160a is formed by a substrate 100 located between a first pixel groove 130a and a third pixel groove 130c; the second sub-segment 160b is formed by a substrate 100 located between a second pixel groove 130b and a third pixel groove 130c; the third sub-segment 160c is formed by a substrate 100 located between a first pixel groove 130a and a second pixel groove 130b; and the fourth sub-segment 160d is formed by a substrate 100 located between a second pixel groove extension 130b' and a first pixel groove 130a. One end of the third sub-segment 160c is connected to the first sub-segment 160a and the second sub-segment 160b, and the other end of the third sub-segment 160c is connected to the fourth sub-segment 160d. The substrate 100 is the growth substrate of the epitaxial layer 110.

[0168] Understandably, when it is necessary to maximize the size of the first pixel slot 130a, the through slot, and the third pixel slot 130c, a smaller width of the isolation barrier 160 may result in poor structural stability of the light-emitting element. Therefore, using the growth substrate of the epitaxial layer 110 (i.e., substrate 100) as the isolation barrier 160 is beneficial to improving the support strength of the isolation barrier 160 and enhancing the structural stability of the light-emitting element.

[0169] In some embodiments, the material of the isolation barrier 160 includes an opaque colloidal material, which effectively prevents interference from some light emitted by a sub-pixel entering adjacent sub-pixels. It also increases refraction within the same sub-pixel area, improving light utilization efficiency, and avoids re-excitation between different sub-pixel areas. The isolation barrier 160 is used to isolate the first pixel slot 130a, the second pixel slot 130b, the through slot, and the third pixel slot 130c. In this embodiment, the substrate 100 is a silicon substrate, and the material of the isolation barrier 160 is silicon; the isolation barrier is also referred to as a "silicon wall."

[0170] In some embodiments, referring to Figures 1 and 7, on the plane of the substrate 100, the projected shapes of the first sub-segment 160a, the second sub-segment 160b, the third sub-segment 160c, and the fourth sub-segment 160d in the isolation barrier 160 are consistent with the projected shapes of the first sub-channel 231, the second sub-channel 232, the third sub-channel 233, and the fourth sub-channel 234 in the isolation channel 230, and the projections of the first sub-channel 231, the second sub-channel 232, the third sub-channel 233, and the fourth sub-channel 234 fall within the projections of the first sub-segment 160a, the second sub-segment 160b, the third sub-segment 160c, and the fourth sub-segment 160d, respectively. It can be seen that the linewidth of the isolation barrier 160 is greater than the linewidth of the isolation channel 230; thus, it is beneficial to further improve the structural strength of the light-emitting element.

[0171] In some embodiments, referring to Figure 3, the light-emitting element further includes:

[0172] A first upper reflective electrode 240a, a second upper reflective electrode 240b, and a third upper reflective electrode 240c; the first upper reflective electrode 240a is located between the second conductive semiconductor layer 113 and the first electrode pad 210a in the first sub-pixel region 120a; the second upper reflective electrode 240b is located between the second conductive semiconductor layer 113 and the second electrode pad 210b in the second sub-pixel region 120b; and the third upper reflective electrode 240c is located between the second conductive semiconductor layer 113 and the third electrode pad 210c in the third sub-pixel region 120c.

[0173] An insulating layer includes a first insulating portion 250a, a second insulating portion 250b, and a third insulating portion 250c; wherein the first insulating portion 250a covers a portion of the sidewall of the first sub-pixel region 120a and extends to the first upper reflective electrode 240a; the second insulating portion 250b covers a portion of the sidewall of the second sub-pixel region 120b and extends to the second upper reflective electrode 240b; and the third insulating portion 250c covers a portion of the sidewall of the third sub-pixel region 120c and extends to the third upper reflective electrode 240c.

[0174] A first lower reflective electrode 260a, a second lower reflective electrode 260b, and a third lower reflective electrode 260c; the first lower reflective electrode 260a covers the sidewall of the first sub-pixel region 120a not covered by the first insulating portion 250a and extends onto the first insulating portion 250a; the second lower reflective electrode 260b covers the sidewall of the second sub-pixel region 120b not covered by the second insulating portion 250b and extends onto the second insulating portion 250b; the third lower reflective electrode 260c covers the sidewall of the third sub-pixel region 120c not covered by the third insulating portion 250c and extends onto the third insulating portion 250c; wherein,

[0175] In the thickness direction of the substrate 100, the first lower reflective electrode 260a and the first upper reflective electrode 240a partially overlap, the second lower reflective electrode 260b and the second upper reflective electrode 240b partially overlap, and the third lower reflective electrode 260c and the third upper reflective electrode 240c partially overlap.

[0176] Understandably, on the one hand, by setting multiple lower reflective electrodes as optical isolation reflective layers, optical isolation between each sub-pixel region can be achieved, and optical crosstalk between each sub-pixel can be prevented; on the other hand, multiple upper reflective electrodes partially overlap with their corresponding lower reflective electrodes (the upper reflective electrodes and the lower reflective electrodes overlap in the vertical direction), which can reflect all the emitted light from the active layer 112 to the first light-emitting surface (the side of the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c that is close to the first surface 101 of the substrate 100).

[0177] In some specific embodiments, the first upper reflective electrode 240a, the second upper reflective electrode 240b, and the third upper reflective electrode 240c are respectively electrically connected to at least a portion of the second conductive semiconductor layer 113 in the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c to form ohmic contacts; and the first upper reflective electrode 240a, the second upper reflective electrode 240b, and the third upper reflective electrode 240c are respectively electrically connected to at least a portion of the first electrode pad 210a, the second electrode pad 210b, and the third electrode pad 210c to form ohmic contacts.

[0178] The first lower reflective electrode 260a, the second lower reflective electrode 260b, and the third lower reflective electrode 260c are respectively electrically connected to at least a portion of the first conductive semiconductor layer 111 in the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c to form ohmic contacts.

[0179] The first upper reflective electrode 240a, the second upper reflective electrode 240b, and the third upper reflective electrode 240c can be P-ohm contact electrodes, and the first lower reflective electrode 260a, the second lower reflective electrode 260b, and the third lower reflective electrode 260c can be N-ohm contact electrodes.

[0180] In some embodiments, referring to FIG3, the light-emitting element further includes a conductive connection portion 270, which covers the isolation channel 230, the sidewalls of the dummy structure region 120d, and extends to the surface of the dummy structure region 120d away from the substrate 100. The first lower reflective electrode 260a, the second lower reflective electrode 260b, and the third lower reflective electrode 260c are electrically connected to the common electrode pad 220 through the conductive connection portion 270 to form an ohmic contact.

[0181] In some specific embodiments, the conductive connection portion 270 is integrally formed with the first lower reflective electrode 260a, the second lower reflective electrode 260b, and the third lower reflective electrode 260c.

[0182] In some embodiments, referring to FIG3, the light-emitting element further includes an isolation layer 280 covering the first lower reflective electrode 260a, the second lower reflective electrode 260b, the third lower reflective electrode 260c, and the conductive connection portion 270. The isolation layer 280 electrically isolates the first upper reflective electrode 240a and the first lower reflective electrode 260a from each other, electrically isolates the second upper reflective electrode 240b and the second lower reflective electrode 260b from each other, and electrically isolates the third upper reflective electrode 240c and the third lower reflective electrode 260c from each other.

[0183] In actual fabrication, the materials of the first upper reflective electrode 240a, the second upper reflective electrode 240b, and the third upper reflective electrode 240c may include at least one of titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and silver (Ag); the materials of the first lower reflective electrode 260a, the second lower reflective electrode 260b, and the third lower reflective electrode 260c may include at least one of titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and silver (Ag); and the materials of the insulating layer and the isolation layer 280 include, but are not limited to, silicon oxide and silicon nitride.

[0184] In some embodiments, referring to FIG9, the light-emitting element further includes:

[0185] The first filter layer 170a, the second filter layer 170b, and the third filter layer 170c are all located on the second surface 102 of the substrate 100. The first filter layer 170a covers the first pixel slot 130a, the second filter layer 170b covers the second pixel slot 130b and the second pixel slot extension 130b', and the third filter layer 170c covers the third pixel slot 130c. This facilitates further improvement in the color purity of the red, green, and blue sub-pixels, enabling more precise control of the displayed colors. Furthermore, it improves the blackness of the light-emitting elements, reducing reflection of ambient light and thus enhancing contrast.

[0186] In some specific embodiments, the filter layer can be a color filter (CF) that only allows light within a specific wavelength range to pass through. The type of filter can be set according to the desired color of the emitted light. For example, a red filter layer (CF-R) can cover the first pixel slot 130a, a green filter layer (CF-G) can cover the through slot, and a blue filter layer (CF-B) can cover the third pixel slot 130c.

[0187] In actual fabrication, when the light emitted by each sub-pixel region is blue light, the red and green filter layers can be filter materials used to filter out blue light that is not absorbed by the light conversion material. The blue filter layer can be a transparent layer or a filter material used to filter wavelengths other than blue light.

[0188] In some embodiments, referring to FIG9, the light-emitting element further includes:

[0189] A protective capping layer 180 covers the first filter layer 170a, the second filter layer 170b, the third filter layer 170c, and the second surface 102 of the substrate 100.

[0190] Understandably, by setting a protective capping layer 180, on the one hand, the structural strength of the light-emitting unit can be improved; on the other hand, it can effectively isolate the optical materials, filter layer and outside air from contact, thus protecting the optical materials and filter layer. For example, when the optical material includes quantum dots, it can reduce the problem of quantum dot particles decaying or even becoming inactive due to water vapor and oxygen in the air, thereby improving the lifespan of the quantum dots.

[0191] In some specific embodiments, the protective capping layer 180 can be formed on the first filter layer 170a, the second filter layer 170b, the third filter layer 170c, and the second surface 102 of the substrate 100 by sputtering or vapor deposition. The material of the protective capping layer 180 can be an insulating material with high light transmittance. For example, the material of the protective capping layer 180 includes inorganic materials such as silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), glass, and sapphire, or transparent polymer materials such as silicone and resin.

[0192] Example 2

[0193] This application provides a light-emitting device, which includes a plurality of seamlessly spliced ​​light-emitting elements as described in Embodiment 1 above.

[0194] Understandably, light-emitting devices obtained by seamlessly splicing multiple light-emitting elements have a large size and are suitable for large-screen display devices, such as LCD TVs, computer monitors, etc.

[0195] Example 3

[0196] Please refer to Figure 1. An embodiment of this application provides a light-emitting element, including:

[0197] The substrate 100 includes a first surface 101 and a second surface 102 that are opposite to each other;

[0198] The epitaxial layer 110 is located on the first surface 101 of the substrate 100 and includes a first conductive semiconductor layer 111, an active layer 112, and a second conductive semiconductor layer 113 stacked sequentially in a direction away from the substrate 100. The epitaxial layer 110 is patterned and divided into multiple pixel unit regions 120 arranged in an array. Each pixel unit region 120 includes a first sub-pixel region 120a, a second sub-pixel region 120b, a third sub-pixel region 120c, and a dummy structure region 120d. The first sub-pixel region 120a, the second sub-pixel region 120b, the third sub-pixel region 120c, and the dummy structure region 120d are distributed at different positions in the pixel unit region 120 and extend to the boundary of the pixel unit region 120 respectively.

[0199] The projections of the first sub-pixel area 120a, the second sub-pixel area 120b, the third sub-pixel area 120c, and the dummy structure area 120d onto the plane of the substrate 100 are located at the four vertices of the first quadrilateral region 121, respectively. The second sub-pixel area 120b is arranged adjacent to the dummy structure area 120d. The dummy structure area 120d and the third sub-pixel area 120c are arranged along the diagonal of the first quadrilateral region 121. The first sub-pixel area 120a is the light-emitting area of ​​the red sub-pixel, the second sub-pixel area 120b is the light-emitting area of ​​the green sub-pixel, and the third sub-pixel area 120c is the light-emitting area of ​​the blue sub-pixel.

[0200] It is understood that in this embodiment of the application, the second sub-pixel area 120b is arranged adjacent to the dummy structure area 120d; the dummy structure area 120d and the third sub-pixel area 120c are arranged along the diagonal of the first quadrilateral area 121. This allows the red and green sub-pixels to be arranged diagonally, and the blue sub-pixel to be arranged diagonally with the common electrode area (i.e., the area where the dummy structure area 120d is located), providing more space for the red and green sub-pixels. This helps to increase the area of ​​the red and green sub-pixels, reduces the difficulty of filling the light conversion material in the red and green sub-pixels, thereby reducing the blue light radiation intensity per unit area of ​​the light conversion material and increasing the service life of the light conversion material.

[0201] Example 4

[0202] Please refer to Figures 10 and 23. An embodiment of this application provides a light-emitting device package, including:

[0203] Chip layer 400 includes a third surface 401 and a fourth surface 402 disposed opposite to each other;

[0204] The support structure 300 is disposed on the third surface 401 of the chip layer 400.

[0205] Chip layer 400 includes one or more chips 410, and chip 410 includes one or more light-emitting units 420.

[0206] The support structure 300 includes a cavity 330 and one or more sub-pixel slots 350 disposed below the cavity 330. The sub-pixel slots 350 extend from the third surface 401 of the chip layer 400 toward the cavity 330 along the direction from the fourth surface 402 to the third surface 401.

[0207] In this context, the sub-pixel slot 350 corresponds to the light-emitting unit 420.

[0208] The sub-pixel slot 350 is filled with light conversion material 150, and

[0209] The inner side of the sidewall 310 of the support structure 300 is set as a stepped structure.

[0210] Understandably, in the embodiments of this application, the support structure 300 adopts a stepped structure, which can ensure the strength of the light-emitting device packaging, avoid process damage and abnormalities of the bonding temporary substrate; while ensuring the strength of the light-emitting device packaging, it can also meet the requirements of light conversion material printing, thereby improving the filling efficiency and accuracy of the light conversion material.

[0211] The light-emitting device package includes a chip layer 400, a support structure 300, and a pad 200.

[0212] Chip layer 400 can be used to convert electrical energy into light energy, providing the main light output of the light-emitting device. In some embodiments, chip layer 400 may include one or more chips (e.g., a single chip as shown in FIG. 10 or multiple chips as shown in FIG. 23). Different types of chips can be selected according to the specific application requirements; for example, the chip may be a blue light chip or an ultraviolet light chip; the chip may be a Micro LED (micro light-emitting diode) chip. The chip may be made of semiconductor materials capable of producing light of specific wavelengths, such as gallium nitride (GaN), gallium arsenide (GaAs), or combinations thereof, and its thickness and size may be adjusted according to the specific application. In some embodiments, the chip may include one or more light-emitting units.

[0213] Chip layer 400 has a third surface 401 and a fourth surface 402. The third surface 401 is typically the upper surface of the chip, on which a support structure 300 may be disposed. The fourth surface 402 is the bottom surface of the chip, which contacts other structural layers (e.g., pads 200, adhesive layers, temporary substrates, etc.) and is used to provide mechanical support or electrical connections.

[0214] A support structure 300 is disposed on the third surface 401 of the chip layer 400 to provide mechanical support and protection. The support structure 300 can be a silicon substrate or made of a transparent material, such as sapphire, silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), or other highly transparent media to reduce light absorption loss. The support structure 300 may include sidewalls 310, cavities 330, one or more sub-pixel slots 350, and isolation walls 340. The sidewalls 310 of the support structure 300 may include a first sidewall 311 and a second sidewall 312, with the first sidewall 311 disposed on the second sidewall 312. In some embodiments, in the direction perpendicular to the fourth surface 402 to the third surface 401, the width of the first sidewall 311 is smaller than the width of the second sidewall 312, thereby allowing the inner side of the sidewalls 310 of the support structure 300 to be configured as a stepped structure.

[0215] In some embodiments, the first sidewall 311 and the second sidewall 312 may be made of the same or different materials. In the projection of the light-emitting device along the direction from the fourth surface 402 to the third surface 401, the sidewall 310 of the support structure 300 overlaps with at least a portion of the periphery of one or more chips in the chip layer 400. The first sidewall 311 surrounds and defines a cavity 330, in which one or more encapsulation layers may be disposed.

[0216] The sub-pixel slot 350 can penetrate the bottom surface of the support structure 300 and extend from the third surface 401 of the chip layer 400 to the cavity 330 along the direction from the fourth surface 402 to the third surface 401 of the chip layer 400 (i.e., the thickness direction of the light-emitting device package). The second sidewall 312 is disposed on the third surface 401 of the chip layer 400, providing mechanical support for the light-emitting device package while also controlling the scattering angle of the light emitted from the chip, thereby improving the output directionality of the light.

[0217] The second sidewall 312 surrounds and defines the sub-pixel slot 350. The sub-pixel slot 350 can be used to fill light conversion material. In some embodiments, one or more sub-pixel slots 350 may correspond to one or more chips in the chip layer 400. Specifically, one sub-pixel slot 350 may correspond to one light-emitting unit in the chip. Isolation walls 340 may be provided between the sub-pixel slots 350. The height of the isolation walls 340 is lower than the height of the first sidewall 311. In some embodiments, the material of the isolation walls 340 may be the same as or different from the material of the support structure 300. In some embodiments, the isolation walls 340 may be prepared by the same process as the second sidewall 312, which helps to simplify the process flow and improve manufacturing efficiency. In some embodiments, the filling method of the light conversion material may include spraying, dripping, scraping, printing (e.g., screen printing, inkjet printing, etc.), in-mold injection molding, electrophoretic deposition, vacuum injection, irradiated curing, etc., or combinations thereof.

[0218] Chip layer 400 can be electrically connected to pad 200. The material of pad 200 includes at least one of titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), silver (Ag), tin (Sn), and platinum (Pt), or an alloy of the above metals.

[0219] The description of the above-described light-emitting device package is for illustrative purposes only and is not intended to limit the scope of this application. Those skilled in the art can make various changes and modifications based on the description in this application. For example, a light-reflecting layer can be provided on the inner side of the first sidewall 311 of the light-emitting device package to reflect light emitted by the chip, thereby improving optical efficiency or achieving specific optical effects. Since the height of the isolation wall 340 is lower than the height of the first sidewall 311, the light-reflecting layer can be relatively easily provided (e.g., coated) on the inner side of the first sidewall 311. As another example, a light-absorbing layer can be provided in the cavity 330 to absorb light emitted from the chip layer 400 that has not been converted by the light-converting material. These changes and modifications are still within the scope of protection of this application.

[0220] Integrated packaging technology is an advanced LED packaging technology that integrates multiple LED chips together, avoiding the cumbersome chip packaging process and achieving a higher degree of chip integration. However, conventional integrated packaging requires the transfer of a large number of LED chips, resulting in complex chip packaging processes, low efficiency, and low yield. Figure 11 is a cross-sectional view of a light-emitting device package in related technologies. As shown in Figure 11, a support structure 300 is disposed on the chip layer 400. The support structure 300 may include multiple sidewalls 3101…,…3107 (sidewalls 3102…,…3106 can also be referred to as isolation walls here). The sidewalls 3101…,…3107 surround the cavity 330 (which can also be referred to as a sub-pixel groove here). To prevent wafer warping, the height of the sidewalls and / or isolation walls between the support structure and the sub-pixel grooves of conventional light-emitting devices is usually set to be greater than or equal to 100 micrometers. However, excessively high and steep sidewalls and isolation walls can lead to significant ink droplet adhesion, making it impossible to form light conversion material with the desired thickness and uniformity. However, if the height of the sidewalls and / or isolation walls is reduced to facilitate the filling of light conversion materials, it may cause wafer warping.

[0221] As shown in Figures 10 and 23, to address the aforementioned issues, the first sidewall 311 of the support structure 300 in this application can form a stepped structure with the second sidewall 312. In the direction perpendicular to the fourth surface 402 to the third surface 401 of the chip layer 400, the width of the first sidewall 311 can be smaller than the width of the second sidewall 312. In the direction from the fourth surface 402 to the third surface 401, the height of the first sidewall 311 can be greater than 100 micrometers, while the height of the second sidewall 312 and / or the isolation wall 340 can be less than 20 micrometers. With this configuration, the first sidewall 311 and the second sidewall 312 can provide high support strength for the light-emitting device packaging. Since the heights of the second sidewall 312 and the isolation wall 340 are relatively low, the problem of uneven filling of the light conversion material caused by excessively high heights of the sidewalls 310 and the isolation wall 340 of the support structure 300 is avoided, and the strength of the light-emitting device packaging after thinning is also guaranteed.

[0222] In some embodiments, in the direction from the fourth surface 402 to the third surface 401, the depth of the sub-pixel groove 350 is equal to the thickness of the second sidewall 312; the thickness of the second sidewall 312 is 10 micrometers to 20 micrometers. The depth of the sub-pixel groove 350 can be understood as the thickness of the isolation wall 340. Thus, in the direction from the fourth surface 402 to the third surface 401, the thickness of the isolation wall 340 is equal to the thickness of the second sidewall 312, and the thickness of both the isolation wall 340 and the second sidewall 312 ranges from 10 micrometers to 20 micrometers. This more effectively avoids the excessive thickness of the isolation wall 340 and the second sidewall 312 from affecting the filling of the light conversion material.

[0223] Figure 12 is a schematic diagram of a light-emitting device package provided in an optional specific embodiment.

[0224] As shown in Figure 12, a support structure is disposed on a chip layer, which includes multiple chips, such as chips 411, 412, 413, and 414. The support structure includes sidewalls 310, which include a third sidewall 313 and a fourth sidewall 314. The third sidewall 313 is disposed around chips 411, 412, 413, and 414, and the fourth sidewall 314 is disposed between every two chips 411, 412, 413, and 414. Each chip in the chip layer corresponds to the support structure; that is, in the direction perpendicular to the thickness of the light-emitting device package, the sidewalls of the support structure (the third sidewall 313 and / or the fourth sidewall 314) can surround multiple pixel slots (or multiple light-emitting units in the chip) corresponding to a chip and overlap with the periphery of the chip, thereby providing support for a single chip.

[0225] Figure 13 is a schematic diagram of the support structure corresponding to one of the light-emitting chips in the structure shown in Figure 12.

[0226] As shown in Figures 12 and 13, the support structure 300 includes a sidewall 310, a pixel slot, and an isolation wall. In a direction perpendicular to the thickness of the light-emitting device package, the sidewall 310 overlaps with the periphery of the corresponding chip. The sidewall 310 includes sidewalls 3131, 3132, 3141, and 3142. The pixel slot includes a first sub-pixel slot 351, a second sub-pixel slot 352, and a third sub-pixel slot 353.

[0227] The isolation wall includes a first isolation wall 341, a second isolation wall 342, and a third isolation wall 343. The first isolation wall 341, the second isolation wall 342, and the third isolation wall 343 and / or the sidewall 310 surround and define the first sub-pixel slot 351, the second sub-pixel slot 352, and the third sub-pixel slot 353. Specifically, a first isolation wall 341 is disposed between a first sub-pixel slot 351 and a second sub-pixel slot 352, a second isolation wall 342 is disposed between a first sub-pixel slot 351 and a third sub-pixel slot 353, and a third isolation wall 343 is disposed between a second sub-pixel slot 352 and a third sub-pixel slot 353. Thus, a sub-pixel slot 351 is formed between sidewalls 3131, 3141, 341, and 342; a sub-pixel slot 352 is formed between sidewalls 3141, 3142, 341, and 343; and a sub-pixel slot 353 is formed between sidewalls 3131, 3132, 342, and 343. The placement of the sidewalls 310 and the isolation walls can reduce crosstalk (light overflow) between light-emitting units, enhance the display effect, and improve the contrast and color saturation of the display. It can also prevent electrical interference between different chips, ensuring that each chip operates independently. In addition, since the chip generates heat during operation, the sidewalls 310 and the isolation walls provide additional thermal isolation, which can help dissipate heat in local areas and prevent performance degradation or thermal damage caused by excessive temperature.

[0228] Figure 21 is a schematic diagram of a light-emitting device package provided in another optional embodiment.

[0229] As shown in Figure 21, the light-emitting device package includes a chip layer 400 and a support structure 300. The chip layer 400 includes chips 411, 412, 413, and 414. The sidewall 310 includes a third sidewall 313. The periphery of the chips in the chip layer 400 and the support structure 300 at least partially overlap in a direction perpendicular to the thickness of the light-emitting device package. Unlike the support structure in Figure 3, in this embodiment, a single support structure 300 corresponds to chips 411, 412, 413, and 414. That is, chips 411, 412, 413, and 414 share the support structure 300, meaning that an isolation wall can be provided between adjacent chips, but no sidewall is provided.

[0230] Figure 22 is a schematic diagram of the support structure corresponding to one of the light-emitting chips in the structure shown in Figure 21.

[0231] As shown in Figures 21 and 22, the support structure 300 includes a sidewall 310, a pixel slot, and an isolation wall. In a direction perpendicular to the thickness of the light-emitting device package, the sidewall 310 overlaps with the periphery of the corresponding chip. The sidewall 310 includes sidewalls 3131, 3132, 3141, and 3142. The pixel slot includes a first sub-pixel slot 351, a second sub-pixel slot 352, and a third sub-pixel slot 353.

[0232] The isolation wall includes a first isolation wall 341, a second isolation wall 342, a third isolation wall 343, and a fourth isolation wall 344. The first isolation wall 341, the second isolation wall 342, the third isolation wall 343, the fourth isolation wall 344, and the sidewall 310 surround and define the first sub-pixel slot 351, the second sub-pixel slot 352, and the third sub-pixel slot 353. Specifically, a first isolation wall 341 is disposed between a first sub-pixel slot 351 and a second sub-pixel slot 352, a second isolation wall 342 is disposed between a first sub-pixel slot 351 and a third sub-pixel slot 353, a third isolation wall 343 is disposed between a second sub-pixel slot 352 and a third sub-pixel slot 353, and a fourth isolation wall 344 is disposed between different chips, thereby forming a sub-pixel slot 351 between the sidewall 3131, the first isolation wall 341, the second isolation wall 342, and the fourth isolation wall 344; forming a sub-pixel slot 352 between the first isolation wall 341, the third isolation wall 343, and the fourth isolation wall 344; and forming a sub-pixel slot 353 between the sidewall 3131, the sidewall 3132, the second isolation wall 342, and the third isolation wall 343.

[0233] The chip corresponding to the support structure 300 includes a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit. The first sub-pixel slot 351, the second sub-pixel slot 352, and the third sub-pixel slot 353 correspond to the first, second, and third light-emitting units, respectively. The first, second, and third light-emitting units may include red light-emitting units, green light-emitting units, and blue light-emitting units. The first sub-pixel slot 351, the second sub-pixel slot 352, and the third sub-pixel slot 353 are filled with red light conversion material, green light conversion material, and blue light conversion material, or left unfilled. For example, if the chip is an ultraviolet light-emitting chip, the first sub-pixel slot 351, the second sub-pixel slot 352, and the third sub-pixel slot 353 are filled with red light conversion material, green light conversion material, and blue light conversion material, respectively. As another example, if the chip is a blue light-emitting chip, the first sub-pixel slot 351 and the second sub-pixel slot 352 are filled with red light conversion material and green light conversion material, respectively, while the third sub-pixel slot 353 is left unfilled. It should be noted that this embodiment is not limited to filling the first sub-pixel slot 351 with red light conversion material, filling the second sub-pixel slot 352 with green light conversion material, and filling the third sub-pixel slot 353 with blue light conversion material. Those skilled in the art can adjust the light conversion material filled according to the actual situation.

[0234] Green light conversion materials may include InP quantum dots, CdSe quantum dots, CdSe / ZnS core-shell quantum dots, perovskite CsPbX3 (X = Cl, Br, I) quantum dots, or combinations thereof; Eu 2+ Doping with β-Sialon, Eu 2+ Doping with Li₂CaSiO₄ or combinations thereof. Red light conversion materials may include rare earth ions such as Eu. 2+ Doping with CaAlSiN3, Eu 2+ Doped Ca 0.8 Li 0.2 Al 0.8 Si 1.2 N3, Eu 2+ Doped (Ca, Sr, Ba)₂Si₅N₈:Eu 2+ Medium or combinations thereof; Mn 4+ Doped with K2SiF6 phosphor, Mn 4+ Doped with K2GeF6 phosphor, Mn 4+ Doped with K2TiF6 phosphor or a combination thereof; Pr 3+ Doped YAG phosphor; or any combination of two or three of the above. Blue light conversion materials may include yttrium aluminum garnet (YAG) based phosphors, silicate phosphors (e.g., Sr2SiO4:Eu... 2+), nitride or oxynitride phosphors (e.g., Sr2Si2Al2N8:Eu 2+ CaAlSiN3:Eu 2+ ), sulfide fluorescence (SrS:Eu) 2+ ); CdSe / ZnS quantum dots, cadmium-free quantum dots (e.g., InP / ZnS quantum dots); metal-organic frameworks (MOFs); perovskite nanocrystals (e.g., CsPbBr3); or any combination of two or three of the above.

[0235] It is understandable that red, green, and blue light-emitting units can form a single light-emitting pixel unit (full-color LED chip), emitting light in three colors: red (R), green (G), and blue (B).

[0236] In some embodiments, the cross-sectional view of the light-emitting device package shown in FIG10 may be a cross-sectional view along the G-G' line shown in FIG13.

[0237] It should be understood that Figures 12 and 13 only illustrate cases where the projected shape of the sub-pixel slots in the direction perpendicular to the thickness of the light-emitting device package is rectangular or pentagonal, and each light-emitting unit corresponds to three sub-pixel slots. This application does not exclude cases where the projected shape of the sub-pixel slots in the direction perpendicular to the thickness of the light-emitting device package is triangular, circular, trapezoidal, hexagonal, or other suitable shape. This application also does not exclude cases where there are four, five, or more sub-pixel slots.

[0238] Please refer to Figures 20 and 25. A first encapsulation layer 560 and a second encapsulation layer 570 are provided in the cavity 330, with the second encapsulation layer 570 disposed on the first encapsulation layer 560.

[0239] The first encapsulation layer 560 may include inorganic encapsulation materials. By setting the first encapsulation layer 560, the chip can be protected from external environmental corrosion, the mechanical strength, temperature resistance, and chemical stability of the light-emitting device package can be improved, and electrical isolation can be provided for the chip.

[0240] The second encapsulation layer 570 may include organic encapsulation materials. By setting the second encapsulation layer 570, mechanical support can be provided for the encapsulation of the light-emitting device, protecting the chip and the circuitry of the light-emitting device from external forces, absorbing or dispersing the heat generated by the chip, preventing the intrusion of external moisture, oxygen and corrosive gases (such as water vapor and salt spray), and avoiding circuit oxidation, corrosion or performance degradation. Organic encapsulation materials are relatively inexpensive and can meet the needs of large-scale industrial production without significantly increasing costs.

[0241] In some embodiments, the first encapsulation layer 560 and the second encapsulation layer 570 may be made of the same or different materials. For example, the first encapsulation layer 560 and the second encapsulation layer 570 may be integrally made of the same material.

[0242] The light-emitting device package may further include a light-absorbing layer (not shown in the figure), disposed between the first packaging layer 560 and the second packaging layer 570.

[0243] The function of a light-absorbing layer is to absorb light within a specific wavelength range to achieve efficient utilization of light energy, adjust spectral distribution, improve photoelectric conversion efficiency, or reduce unnecessary light reflection losses. Light-absorbing layers can include blue light-absorbing layers, red light-absorbing layers, and green light-absorbing layers. The type of light-absorbing layer depends on the type of light emitted by the light-emitting unit. For example, if the light emitted by the light-emitting unit is blue light, the light-absorbing layer can absorb the blue light that has not been converted by the green light conversion material and / or the red light conversion material.

[0244] In some embodiments, the light-absorbing layer may include multiple portions. As an example only, the light-absorbing layer may include a first portion, a second portion, and a third portion. The first portion may be disposed on a first sub-pixel slot, the second portion may be disposed on a second sub-pixel slot, and the third portion may be disposed on a third sub-pixel slot, respectively used to absorb light emitted by the light-emitting unit that has not been converted by the light-converting material in each sub-pixel slot and has leaked out.

[0245] In some embodiments, the material of the light-absorbing layer may include semiconductor materials with a specific band gap (e.g., cadmium sulfide, cadmium selenide, or other compound semiconductors), organic dyes (e.g., porphyrins or phthalocyanine compounds), quantum dots (e.g., indium sulfide quantum dots or cadmium telluride quantum dots), or two-dimensional materials (e.g., graphene or transition metal dichalcogenides), or combinations thereof. In some embodiments, the light-absorbing layer may be deposited on top of the light conversion material using physical vapor deposition (PVD), chemical vapor deposition (CVD), solution spin coating, inkjet printing, atomic layer deposition (ALD), or sol-gel processes. Furthermore, the light-absorbing layer may be surface passivated or structurally optimized (e.g., nanopatterning) to further enhance the overall performance of the light-emitting device.

[0246] Example 5

[0247] Figure 28 is a schematic flowchart of a method for fabricating a light-emitting device package according to an embodiment of this application. As shown in the figure, the fabrication method includes:

[0248] Step S501: Provide a support structure;

[0249] Step S502: A chip layer is disposed on the support structure, the chip layer including a third surface and a fourth surface disposed opposite to each other;

[0250] Step S503: Set a first mask layer on the support structure and perform patterning processing on the first mask layer;

[0251] Step S504: Set a second mask layer on the patterned first mask layer, and use the second mask layer as a mask to perform the first etching on the support structure to obtain one or more grooves;

[0252] Step S505: Remove the second mask layer, and use the first mask layer as a mask to perform a second etching on the support structure after the first etching to obtain the cavity of the support structure and one or more sub-pixel grooves; wherein, the sub-pixel grooves extend from the third surface of the chip layer to the cavity in the direction from the fourth surface to the third surface; after the first etching and the second etching, the inner sidewall of the support structure is formed into a stepped structure.

[0253] Understandably, in the embodiments of this application, the support structure adopts a stepped structure, which can ensure the strength of the light-emitting device packaging, avoid process damage and abnormalities of the bonding temporary substrate; while ensuring the strength of the light-emitting device packaging, it can also meet the requirements of light conversion material printing, thereby improving the filling efficiency and accuracy of the light conversion material.

[0254] Please refer to Figure 14 and perform steps S501 and S502: provide a support structure 300; and set a chip layer 400 on the support structure 300.

[0255] In some embodiments, chip layer 400 may include a single chip. Support structure 300 may be a growth substrate for the chip in chip layer 400, and epitaxial structures in the chip are formed on support structure 300 by epitaxial growth along the direction from the third surface 401 to the fourth surface 402 of chip layer 400. Here, chip layer 400 may be referred to as an "epitaxy layer".

[0256] Please refer to Figure 15 and perform step S503 to set a first mask layer 510 on the support structure 300 and perform graphic processing on the first mask layer 510.

[0257] The first mask layer 510 may include an inorganic mask material. The material of the first mask layer 510 may include silicon oxide, amorphous carbon, silicon nitride, aluminum nitride, metal thin films (e.g., chromium, titanium, aluminum, etc.), and metal oxide thin films (e.g., aluminum oxide, zinc oxide, etc.). The fabrication method of the first mask layer 510 may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), solution deposition, thermal evaporation, ion beam deposition (IBD), or other mask layer fabrication methods, which are not specifically limited herein. The pattern of the first mask layer 510 corresponds to the cavity of the support structure 300.

[0258] Please refer to Figure 16 and perform step S504: Set a second mask layer 520 on the patterned first mask layer 510, and use the second mask layer 520 as a mask to perform the first etching on the support structure 300 to obtain one or more grooves 320 of the support structure 300.

[0259] The second mask layer 520 may include, but is not limited to, photoresist. The second mask layer 520 may (e.g., by coating, spin-coating, or spraying) be applied to the patterned first mask layer 510, completely covering the first mask layer 510 and the upper surface of the support structure 300 exposed by the patterned first mask layer 510. The second mask layer 520 may have patterns corresponding to one or more sub-pixel slots.

[0260] Using the second mask layer 520 as a mask, the support structure 300 is etched for the first time to obtain one or more grooves 320, sidewalls 310, and isolation walls 340 between the grooves 320. The first etching may include photolithography. The one or more grooves 320 formed by the first etching can penetrate the support structure 300. The heights of the sidewalls 310 and the isolation walls 340 can be equal. The depth of the grooves 320 formed after the first etching can be 100 micrometers to 120 micrometers. A groove depth of less than 100 micrometers may cause warping of the fabricated wafer, while a groove depth of more than 120 micrometers means that the wafer size is too large, increasing the difficulty of subsequent cutting and polishing processes and increasing production costs.

[0261] Next, step S505 is executed to remove the second mask layer 520. Using the first mask layer 510 as a mask, the support structure 300 after the first etching is etched a second time to obtain the cavity 330 and one or more sub-pixel slots of the support structure 300. The sub-pixel slots extend from the third surface 401 of the chip layer 400 to the cavity 330 in the direction from the fourth surface 402 to the third surface 401. After the first etching and the second etching, the inner side of the sidewall 310 of the support structure 300 is formed into a stepped structure.

[0262] As an optional specific implementation, please refer to Figures 16 and 17. Step S505 includes: removing the second mask layer 520, using the first mask layer 510 as a mask, and performing a second etching on the support structure 300 after the first etching to obtain the cavity 330 and sub-pixel groove 350 of the support structure 300; wherein, the sub-pixel groove 350 extends from the third surface 401 of the chip layer 400 to the cavity 330 in the direction from the fourth surface 402 to the third surface 401; after the first etching and the second etching, the inner side of the sidewall 310 of the support structure 300 is formed into a stepped structure. It should be noted that one sub-pixel groove 350 corresponds to one chip.

[0263] The second etching may include wet etching, dry etching, laser etching, ion beam etching, reactive gas etching, or a combination thereof. In some embodiments, since the first etching forms one or more relatively deep grooves 320 in the support structure 300, the upper surface of the support structure 300 is uneven, making it difficult to uniformly coat the photoresist again. Therefore, the second etching may employ etching processes other than photolithography, thereby avoiding photolithographic deviations caused by uneven photoresist coating and mask pattern differences.

[0264] As another optional specific implementation, please refer to FIG23. Step S504 includes: setting a second mask layer on the patterned first mask layer, and using the second mask layer as a mask to perform a first etching on the support structure 1020 to obtain a plurality of sub-pixel grooves 3501, 3502, 3503, and 3504 of the support structure; the second mask layer may include photoresist, and the first etching includes photolithography; Step S505 includes: removing the second mask layer 520, using the first mask layer 510 as a mask to perform a second etching on the support structure 300 after the first etching, to obtain the stepped structure of the sidewall 310 of the support structure 300 and the cavity 330.

[0265] Multiple sub-pixel slots correspond to multiple chips. For example, sub-pixel slots 3501-1 and 3501-2 in sub-pixel slot 3501 correspond to one chip (i.e., one pixel), sub-pixel slots 3502-1 and 3502-2 in sub-pixel slot 3502 correspond to one chip, sub-pixel slots 3503-1 and 3503-2 in sub-pixel slot 3503 correspond to one chip, and sub-pixel slots 3504-1 and 3504-2 in sub-pixel slot 3504 correspond to one chip.

[0266] Since two or more chips in chip layer 400 share the sidewalls of support structure 300 (i.e., first sidewall 311 and second sidewall 312), referring to FIG. 21, chip layer 400 includes chips 411, 412, 413, and 414. The periphery of the chips in chip layer 400 and support structure 300 at least partially overlap in a direction perpendicular to the thickness of the light-emitting device package. Compared to FIG. 12, the increase in the total cross-sectional area of ​​the sub-pixel trench in this embodiment allows for the second etching to be performed using either planar photoresist mask etching or photolithography.

[0267] After a second etching, the sidewall 310 is further etched into a first sidewall 311 and a second sidewall 312. In the direction perpendicular to the third surface 401 to the fourth surface 402, the width of the first sidewall 311 is smaller than the width of the second sidewall 312. The partition wall 340 between the sidewall 310 of the support structure 300 and the groove 320 is further etched, reducing its height. The first sidewall 311 surrounds and forms the cavity 330, and a sub-pixel groove 350 is formed between the second sidewall 312 and the partition wall 340 and / or between adjacent partition walls 340. Thus, the first sidewall 311 is disposed on the second sidewall 312, and a stepped structure is formed on the inner sides of the first sidewall 311 and the second sidewall 312. The height of the second sidewall 312 can be equal to the height of the partition wall 340 and less than the height of the first sidewall 311.

[0268] In some embodiments, the height of the isolation wall 340 after the second etching can be from 10 micrometers to 20 micrometers, for example, 10 micrometers, 12 micrometers, 14 micrometers, 15 micrometers, 16 micrometers, 18 micrometers, and 20 micrometers. If the height of the isolation wall 340 is greater than 20 micrometers, it may cause the subsequent light conversion material to be difficult to fill or to fill unevenly. If the height of the isolation wall 340 is less than 10 micrometers, it may cause the light conversion material to overflow, reducing the light conversion efficiency. In severe cases, it may cause the light-emitting device to be open-circuited or the yield to be reduced.

[0269] The stepped structure reduces the height of the second sidewall 312 and the isolation wall 340, preventing wall hanging during the light conversion material filling process caused by excessive height of the sidewall 310 and the isolation wall 340 of the support structure 300. At the same time, the size of the sub-pixel slot 350 can be flexibly set according to the size of the chip, thereby improving the applicability of the light-emitting device packaging and reducing the process difficulty of light conversion material filling.

[0270] In some embodiments, referring to FIG18, the fabrication method may include: providing pads 200 on a fourth surface 402 of the chip layer 400; and providing a temporary substrate 540 on the fourth surface 402. The temporary substrate 540 can provide mechanical support for the packaging of the light-emitting device and can withstand the corrosion of high temperature and chemical reactions, thus protecting the chip layer 400. The temporary substrate 540 may be made of rigid or semi-rigid materials, such as metals (e.g., stainless steel, titanium, etc.), ceramic materials, quartz glass, etc. An adhesive layer 530 may be provided between the temporary substrate 540 and the chip layer 400 to improve the bonding strength between the temporary substrate 540 and the chip layer 400. The material of the adhesive layer 530 may include thermoplastic materials, thermosetting resins, or peelable adhesives, or combinations thereof.

[0271] Please refer to Figures 19 and 23. In some embodiments, the preparation method may further include filling the sub-pixel slot with light conversion material 150.

[0272] As shown in Figure 19, the light conversion material 150 can be filled into the sub-pixel slot 350 using a printer 550. The printer 550 may include an inkjet printer, a solution processing printer, a 3D printer, etc. As an example only, the light conversion material 150 can be prepared into an ink with desired flowability and viscosity, and the ink made from the light conversion material can be printed into the sub-pixel slot 350 using an inkjet printer.

[0273] As shown in Figure 19, since the width of the first sidewall 311 in the sidewall 310 is smaller than the width of the second sidewall 312, and after two etching processes, the height of the second sidewall 312 and the isolation wall 340 is further reduced, resulting in a relatively small depth of the sub-pixel groove 350 and an increased cross-sectional area of ​​the cavity 330. This improves the operability of printing the light conversion material and avoids the problem that the light conversion material 150 will accumulate on the first sidewall 311, the second sidewall 312 and the isolation wall 340 during the printing process, thus preventing the acquisition of light conversion material with ideal thickness and uniformity.

[0274] Using printer 550 to print light conversion material 150 into sub-pixel slots 350 allows for precise control of the filling amount of light conversion material 150. Furthermore, the printing process can complete the multiple coating and exposure steps required in traditional light conversion material filling processes, reducing production costs and time. Additionally, by adjusting parameters such as the printer nozzle, solution concentration, and drying temperature, different materials can be printed, further improving manufacturing flexibility. In some embodiments, sub-pixel slots corresponding to multiple chips in chip layer 400, filled with the same light conversion material, can be filled simultaneously or sequentially using the same printer, improving filling efficiency and shortening the process flow.

[0275] As shown in Figure 24, light conversion materials are filled into sub-pixel slots 3501, 3502, 3503, and 3504, respectively. For example, red light conversion material can be filled into sub-pixel slots 3501-1, 3502-1, 3503-1, and 3504-1, respectively, while green light conversion material can be filled into sub-pixel slots 3501-2, 3502-2, 3503-2, and 3504-2, respectively. For details regarding the red and green light conversion materials, please refer to the relevant descriptions in Example 5; further details will not be elaborated upon here.

[0276] Referring to Figures 20 and 25, after printing the light conversion material 150 onto one or more sub-pixel slots 350, the fabrication method may further include: setting one or more encapsulation layers in the cavity 330. As shown, the cavity 330 is filled with a first encapsulation material to form a first encapsulation layer 560.

[0277] In some embodiments, the first encapsulation material may include inorganic encapsulation materials or combinations thereof, such as non-metallic oxide materials (e.g., silicon dioxide, aluminum oxide, titanium oxide, etc.), nitride materials (e.g., silicon nitride, aluminum nitride, etc.), carbide materials (e.g., silicon carbide, boron carbide, etc.), metal oxide materials (e.g., zirconium oxide, magnesium oxide, etc.), metal sulfides and oxynitrides (e.g., zinc sulfide, aluminum oxynitride, etc.).

[0278] The first encapsulating material can be disposed in the cavity 330 in any suitable manner, including but not limited to chemical vapor deposition, physical vapor deposition, atomic layer deposition, sol-gel method, vacuum evaporation, sputtering coating, coating, thermal oxidation, etc. In some embodiments, the first encapsulating material can be filled into the cavity 330 by printing (e.g., inkjet printing). By way of example only, the first encapsulating material can be prepared as an ink with desired flowability and viscosity, and the ink made of the first encapsulating material can be printed into the cavity 330 using an inkjet printer 830, and cured to obtain the first encapsulating layer 560. In some embodiments, the first encapsulating material can be printed using a printer that prints light conversion materials (e.g., printer 550 in FIG. 19).

[0279] The first encapsulation layer 560 can be an inorganic encapsulation layer. By setting the first encapsulation layer 560, the chip can be protected from the corrosion of the external environment, the mechanical strength, temperature resistance and chemical stability of the light-emitting device package can be improved, and electrical isolation can be provided for the chip.

[0280] Furthermore, a second encapsulation material can be filled into the cavity 330 and onto the first encapsulation layer 560 to form a second encapsulation layer 570.

[0281] The second encapsulation material may include, but is not limited to, organic encapsulation materials such as epoxy resin, polyimide, silicone materials, acrylic resin, polyurethane, epoxy resin, liquid crystal polymer, or combinations thereof. The second encapsulation material can be disposed in the cavity 330 in any suitable manner, including but not limited to solution coating, molding, potting, thermoforming, photopolymerization, fused deposition modeling, chemical vapor deposition, roll coating, and electrophoretic deposition. In some embodiments, the second encapsulation material can be filled into the cavity 330 by printing (e.g., inkjet printing). As an example only, the second encapsulation material can be prepared as an ink with desired flowability and viscosity, and the ink prepared from the second encapsulation material can be printed into the cavity 330 using an inkjet printer, followed by curing to obtain the second encapsulation layer 570. In some embodiments, the second encapsulation material can be printed using a printer that prints light conversion materials or a printer that prints the first encapsulation material, thereby efficiently completing the filling of the light conversion material and the encapsulation material, significantly saving material costs and improving production efficiency. In some embodiments, the first encapsulation layer 560 and the second encapsulation layer 570 can be prepared from the same or different materials. For example, the first encapsulation layer 560 and the second encapsulation layer 570 can be integrally fabricated from the same material.

[0282] The second encapsulation layer 570 can be an organic encapsulation layer. By setting the second encapsulation layer 570, mechanical support can be provided for the packaging of the light-emitting device, protecting the chip and its circuitry from external forces, absorbing or dispersing the heat generated by the chip, preventing the intrusion of external moisture, oxygen, and corrosive gases (such as water vapor and salt spray), and avoiding circuit oxidation, corrosion, or performance degradation. Organic encapsulation materials are relatively inexpensive and can meet the needs of large-scale industrial production without significantly increasing costs.

[0283] In some embodiments, a light-absorbing layer may be disposed on the first encapsulation layer 560 before the second encapsulation layer 570 is disposed. The function of the light-absorbing layer is to absorb light within a specific wavelength range to achieve efficient utilization of light energy, adjust the spectral distribution, improve photoelectric conversion efficiency, or reduce unnecessary light reflection loss. The light-absorbing layer may include a blue light-absorbing layer, a red light-absorbing layer, and a green light-absorbing layer. The type of light-absorbing layer is related to the type of light emitted by the light-emitting unit. As an example only, if the light emitted by the light-emitting unit is blue light, the light-absorbing layer may absorb the blue light that has not been converted by the green light conversion material and / or the red light conversion material.

[0284] In some embodiments, the light-absorbing layer may include multiple portions. As an example only, the light-absorbing layer may include a first portion, a second portion, and a third portion. The first portion may be disposed on a first sub-pixel slot, the second portion may be disposed on a second sub-pixel slot, and the third portion may be disposed on a third sub-pixel slot, respectively used to absorb light emitted by the light-emitting unit that has not been converted by the light-converting material in each sub-pixel slot and has leaked out.

[0285] In some embodiments, before the first encapsulation layer 560 and the second encapsulation layer 570 are formed, a reflective layer may be formed on the inner side of the first sidewall 311 to reflect light of a specific wavelength emitted from the chip, thereby improving the light extraction efficiency of the light-emitting device. The material of the light-reflective layer may include metallic reflective materials (e.g., aluminum, silver, gold, platinum, copper, etc.), dielectric reflective materials (e.g., oxides, nitrides, fluorides, etc.), nanostructured materials (e.g., silicon dioxide nanostructures, etc.), or combinations thereof. The reflective layer may be formed on the inner side of the first sidewall 311 by methods such as physical vapor deposition, chemical vapor deposition, solution coating, electroplating / chemical plating, etching, thermal spraying, molecular beam epitaxy, sol-gel method, spin coating, etc.

[0286] In some embodiments, after the light-emitting device is packaged, the package can be polished to reduce its thickness to a desired thickness, such as 100 micrometers to 120 micrometers (e.g., 100 micrometers, 105 micrometers, 110 micrometers, 115 micrometers, 120 micrometers).

[0287] As shown in Figure 26, in another optional embodiment, the fabrication method may further include dividing the second encapsulation layer 570 into multiple sub-encapsulation layers, such as sub-encapsulation layer 571, sub-encapsulation layer 572, sub-encapsulation layer 573, and sub-encapsulation layer 574. The number of sub-encapsulation layers corresponds to the number of chips. In some embodiments, the division method of the second encapsulation layer 570 includes, but is not limited to, laser division, mechanical division, chemical division, plasma division, water jet division, and composite cutting. As an example only, photoresist can be applied to the second encapsulation layer 570, and photolithography can be performed to obtain sub-encapsulation layers 571-574.

[0288] As shown in Figure 27, in another optional embodiment, the fabrication method may further include: cutting the light-emitting device into a package to prepare a single chip package. The cutting method for the light-emitting device package may include, but is not limited to, mechanical cutting, laser cutting, and composite cutting.

[0289] In some embodiments, the edge cutting path of the light-emitting device package can overlap with the first sidewall 311 in the thickness direction of the light-emitting device package. In some embodiments, the edge cutting path can overlap with the second sidewall 312 in the thickness direction of the light-emitting device package, as shown in FIG27. This configuration provides the support structure 310 with high mechanical strength during the fabrication of the light-emitting device; it also meets the strength requirements of the light conversion material filling; and further ensures that the thickness or size of the chip after cutting meets the requirements. In some embodiments, the edge cutting path can overlap with the second sidewall 312 in the thickness direction of the light-emitting device package, thereby ensuring that the single chip package fabricated after cutting is not obstructed by the support structure, further improving the viewing angle of the light-emitting device.

[0290] Example 6

[0291] Figure 29 is a schematic flowchart of a method for preparing a light-emitting structure according to an embodiment of this application. As shown in the figure, the preparation method includes:

[0292] Step S601: Provide a substrate, the substrate including a chip region and a dicing region located on the periphery of the chip region, the substrate including a first surface and a second surface opposite to each other in the thickness direction;

[0293] Step S602: A pixel unit is formed on the chip region from the first surface side. The pixel unit includes a first sub-pixel unit, a second sub-pixel unit, and a third sub-pixel unit that are spaced apart from each other.

[0294] Step S603: Etch the chip region from the second surface side to form pixel trenches exposing pixel units. The pixel trenches include a first pixel trench, a second pixel trench, and a third pixel trench spaced apart from each other. The first pixel trench, the second pixel trench, and the third pixel trench correspond to the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit, respectively. The unremoved portion of the chip region is formed as an isolation barrier. The isolation barrier includes a first isolation barrier and a second isolation barrier. The first isolation barrier is located between any two of the first pixel trench, the second pixel trench, and the third pixel trench. The second isolation barrier is located in the edge region of the chip region. Along the substrate thickness direction, the projection of the second isolation barrier surrounds the projection of the first isolation barrier.

[0295] Step S604: Form a first color conversion layer and a second color conversion layer in the first pixel slot and the second pixel slot respectively;

[0296] Step S605: Form a filter layer covering the pixel groove on the second surface. The filter layer includes a first filter layer and a second filter layer. The first filter layer covers the first pixel groove, and the second filter layer covers the second pixel groove.

[0297] Step S606: Form a matte layer on the isolation barrier.

[0298] Therefore, by setting an matte layer on the isolation barrier, the matte layer absorbs all light and prevents the light hitting the isolation barrier from being reflected, thereby improving the display contrast of the light-emitting structure.

[0299] It should be noted that although the steps in Figure 29 are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise explicitly stated in this document, there is no strict order requirement for the execution of these steps, and they can be executed in other orders.

[0300] First, referring to Figures 30 and 31, perform step S601: provide a substrate 100, which includes a chip region 1010 and a dicing region 1020 located on the periphery of the chip region 1010. The substrate 100 includes a first surface 101 and a second surface 102 that are opposite to each other in the thickness direction.

[0301] The substrate 100 may be a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, a silicon substrate, or other semiconductor material substrates known in the art. In the embodiments of this application, the substrate 100 may be a silicon substrate.

[0302] It should be noted that the plane on which the first surface 101 and the second surface 102 of the substrate 100 are located, or more precisely, the center plane in the thickness direction of the substrate 100, is defined as the plane on which the substrate 100 is located, and the direction perpendicular to the plane on which the substrate 100 is located is along the thickness direction of the substrate 100.

[0303] Along the thickness direction of substrate 100, the projection of the dicing region 1020 surrounds the projection of chip region 1010.

[0304] As shown in Figure 31, in some embodiments, the substrate 100 includes a plurality of chip regions 1010. In this embodiment, the substrate 100 can be understood as a wafer.

[0305] Next, referring to Figures 30 to 32, perform step S602: form a pixel unit 190 on the chip region 1010 from the first surface 101 side. The pixel unit 190 includes a first sub-pixel unit 190a, a second sub-pixel unit 190b and a third sub-pixel unit 190c that are spaced apart from each other.

[0306] It should be noted that Figure 30 is a cross-sectional structural diagram of the pixel unit provided in the embodiment of this application, and Figure 31 is a global layout diagram of the structure shown in Figure 30. Figures (a), (b) and (c) in Figure 30 are cross-sectional structural diagrams along the H-H' line, I-I' line and J-J' line in Figure 31, respectively. Figure 32 is a schematic diagram of the arrangement of each sub-pixel unit in Figure 30, and is also an enlarged schematic diagram of a pixel unit in Figure 31.

[0307] In some embodiments, the substrate 100 can be a growth substrate, and an epitaxial layer (not shown in the figure) is formed on the substrate 100 by an epitaxial growth process; a patterning process (such as photolithography, etching, etc.) is performed on the epitaxial layer to form a pixel unit 190.

[0308] Forming an epitaxial layer on the substrate 100 may include: sequentially growing a first conductive semiconductor layer (not shown in the figure), an active layer (not shown in the figure), and a second conductive semiconductor layer (not shown in the figure) on the epitaxial layer. It should be noted that, regarding the epitaxial layer, please refer to the relevant description of the epitaxial layer in Embodiment 1, which will not be repeated here.

[0309] It should be noted that the pixel unit in the embodiments of this application can also be called a "pixel unit area", and the sub-pixel unit can also be called a "sub-megapixel area". For details about the pixel unit and each sub-pixel unit, please refer to the relevant description of the pixel unit area and sub-megapixel area in Embodiment 1, which will not be repeated here.

[0310] In some embodiments, referring to FIG32, isolation channels are formed between each sub-pixel unit. The isolation channels include a first sub-channel 231, a second sub-channel 232, and a third sub-channel 233. The first sub-channel 231 is located between the first sub-pixel unit 190a and the second sub-pixel unit 190b; the second sub-channel 232 is located between the first sub-pixel unit 190a and the third sub-pixel unit 190c; and the third sub-channel 233 is located between the second sub-pixel unit 190b and the third sub-pixel unit 190c. One end of the first sub-channel 231 connects the second sub-channel 232 and the third sub-channel 233. Thus, through the isolation effect of each sub-channel in the isolation channels, while ensuring that each sub-pixel unit is isolated from each other, each sub-pixel unit obtains a more reasonable distribution and a suitable regional contour, which is beneficial for adjusting the arrangement and luminous area size of multiple sub-pixel units of different colors.

[0311] In some embodiments, before performing step S603, the fabrication method may further include: bonding a temporary carrier plate (not shown) to the first surface 101 side; and flipping the substrate 100. Thus, the substrate 100, having completed the pixel unit 190 fabrication process, is bonded to a temporary carrier plate for subsequent step S603. Specifically, through the support of the temporary carrier plate, the steps of fabricating the first pixel groove 130a, the second pixel groove 130b, and the third pixel groove 130c on the second surface 102 of the substrate 100 using processes such as photolithography and etching are implemented.

[0312] Next, referring to Figure 33, perform step S603: etch the chip region 1010 from the second surface 102 side to form a pixel groove 130 exposing the pixel unit 190. The pixel groove 130 includes a first pixel groove 130a, a second pixel groove 130b, and a third pixel groove 130c that are spaced apart from each other. The first pixel groove 130a, the second pixel groove 130b, and the third pixel groove 130c are respectively connected to the first sub-pixel unit 190a, the second sub-pixel unit 190b, and the third sub-pixel unit. Corresponding to 190c, the unremoved portion of the chip region 1010 is formed as an isolation barrier, which includes a first isolation barrier 161 and a second isolation barrier 162. The first isolation barrier 161 is located between any two of the first pixel groove 130a, the second pixel groove 130b, and the third pixel groove 130c. The second isolation barrier 162 is located at the edge region of the chip region 1010. Along the thickness direction of the substrate 100, the projection of the second isolation barrier 162 surrounds the projection of the first isolation barrier 161.

[0313] It should be noted that Figures (a), (b), and (c) in Figure 33 correspond to Figures (a), (b), and (c) in Figure 30, respectively, and are schematic diagrams of structures formed by further performing the preparation method based on Figures (a), (b), and (c) in Figure 30.

[0314] It should be noted that for details regarding the first pixel slot 130a, the second pixel slot 130b, and the third pixel slot 130c, please refer to the relevant description in Embodiment 1, which will not be elaborated upon here.

[0315] As shown in Figure 34, in the unremoved portion of chip region 1010, the portion of the first pixel slot 130a near the second pixel slot 130b and the third pixel slot 130c forms a first isolation barrier 161, and the portion of the first pixel slot 130a away from the second pixel slot 130b and the third pixel slot 130c forms a second isolation barrier 162; the portion of the second pixel slot 130b near the first pixel slot 130a and the third pixel slot 130c forms a first isolation barrier 161, and the portion of the second pixel slot 130b away from the first pixel slot 130a and the third pixel slot 130c forms a second isolation barrier 162; the portion of the third pixel slot 130c near the first pixel slot 130a and the second pixel slot 130b forms a first isolation barrier 161, and the portion of the third pixel slot 130c away from the first pixel slot 130a and the second pixel slot 130b forms a second isolation barrier 162. The projection of the second isolation barrier 162 onto the plane of the substrate 100 is specifically annular. The outer boundary of the second isolation barrier 162 can be understood as the boundary between the chip area 1010 and the cutting channel area 1020.

[0316] Understandably, in related technologies, after forming the pixel unit 190, an additional isolation barrier is typically fabricated between each sub-pixel unit using deposition and etching processes; alternatively, an isolation barrier, color conversion layer, and other structural layers are fabricated on one substrate, and the pixel unit 190 is fabricated on another substrate, followed by bonding and removal of the substrate. This fabrication process is complex, requires high-precision technology, and has high production costs. Furthermore, the isolation barrier exhibits poor support. Therefore, this application uses the substrate 100 that supports the pixel unit to fabricate the isolation barrier, which is beneficial for improving the support strength of the isolation barrier, enhancing the structural stability of the light-emitting element, and reducing production difficulty and cost. In this embodiment, the substrate 100 is a silicon substrate, and the material of the isolation barrier is silicon; the isolation barrier is also referred to as a "silicon wall."

[0317] In some embodiments, the line width of the isolation barrier is greater than the line width of the isolation trench. This is beneficial for further improving the structural strength and luminous effect of the light-emitting element.

[0318] Next, please refer to Figure 35 and perform step S604: form a first color conversion layer 151 and a second color conversion layer 152 in the first pixel slot 130a and the second pixel slot 130b, respectively.

[0319] It should be noted that Figures (a), (b), and (c) in Figure 35 correspond to Figures (a), (b), and (c) in Figure 33, respectively, and are schematic diagrams of structures formed by further performing the preparation method based on Figures (a), (b), and (c) in Figure 33.

[0320] Optionally, the materials of the first color conversion layer 151 and the second color conversion layer 152 may include phosphors or quantum dots. When excited by external energy, both phosphors and quantum dots undergo electron transitions, releasing energy in the form of light. Furthermore, by adjusting the composition and size of the phosphors and quantum dots, the emitted color can be controlled, allowing each pixel slot to emit light of different colors. Further, both the first color conversion layer 151 and the second color conversion layer 152 are made of quantum dots.

[0321] The first sub-pixel unit 190a and the first color conversion layer 151 can constitute a first sub-pixel, the second sub-pixel unit 190b and the second color conversion layer 152 can constitute a second sub-pixel, and the third sub-pixel unit 190c can constitute a third sub-pixel. In this embodiment, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. The red, green, and blue sub-pixels can constitute a light-emitting pixel unit (full-color LED chip), emitting red, green, and blue light. Therefore, the first color conversion layer 151 can be a red color conversion layer, and the second color conversion layer 152 can be a green color conversion layer.

[0322] It should be noted that a pixel unit can be understood as a "light-emitting chip," and a sub-pixel unit can be understood as a "light-emitting core." The light-emitting chip can be a blue light chip or an ultraviolet light chip; the light-emitting chip can be a Micro LED chip. The red, green, and blue sub-pixels use the same light-emitting chip, and the materials and light-emitting characteristics of the light-emitting areas of each sub-pixel are highly consistent, which is beneficial to improving the display effect and long-term stability of the light-emitting structure (full-color LED wafer).

[0323] In some embodiments, on the plane of the substrate 100, the projected area of ​​the third pixel slot 130c is smaller than the projected area of ​​the first pixel slot 130a and smaller than the projected area of ​​the second pixel slot 130b. This is beneficial for increasing the filling area of ​​the first color conversion layer 151 and the second color conversion layer 152, reducing the filling difficulty of the first color conversion layer 151 and the second color conversion layer 152, reducing the blue light radiation intensity per unit area of ​​the first color conversion layer 151 and the second color conversion layer 152, and improving the service life of the first color conversion layer 151 and the second color conversion layer 152.

[0324] Optionally, the fabrication method may further include: forming an optical material layer 153 in the third pixel groove 130c, wherein the optical material layer 153 may include a third color conversion layer (not shown) and / or a light diffusion layer (not shown).

[0325] In some embodiments, the light emitted by the pixel unit 190 is blue light, and the optical material layer 153 can be a light diffusion layer. Understandably, the material of the light diffusion layer includes diffusion particles, which include organic materials, inorganic materials, and organic-inorganic composite materials, such as polystyrene, silicon dioxide, titanium dioxide, etc. By mixing the light diffusion particles into the interior or surface of the matrix, the light diffusion performance is achieved by utilizing the reflection and refraction of light between the diffusion particles.

[0326] In some other embodiments, the light emitted by the pixel unit 190 is ultraviolet light, and the optical material layer 153 may include a third color conversion layer, or the optical material layer may include a third color conversion layer and a light diffusion layer, with the light diffusion layer located between the third color conversion layer and the third sub-pixel unit 190c; wherein, the third color conversion layer is a blue color conversion layer.

[0327] Optionally, before performing step S604, the fabrication method may include: forming a light diffusion layer (not shown in the figure) in the first pixel groove 130a and the second pixel groove 130b; the thickness of the light diffusion layer is less than the depth of the first pixel groove 130a and the second pixel groove 130b in the thickness direction of the substrate 100. The light diffusion layer facilitates uniform light irradiation of the quantum dot, thereby effectively reducing the light intensity at the center of the quantum dot, greatly improving the light stability of the quantum dot, and mitigating the situation where local quantum dots are prone to light quenching due to excessively high central light intensity, thus effectively extending the luminescence lifetime.

[0328] Understandably, in actual fabrication, the light diffusion layers in the first pixel slot 130a, the second pixel slot 130b, and the third pixel slot 130c can be fabricated in the same process.

[0329] Next, referring to Figures 37 and 43, perform step S605: Form a filter layer covering the pixel slots on the second surface 102. The filter layer includes a first filter layer 170a and a second filter layer 170b. The first filter layer 170a covers the first pixel slot 130a, and the second filter layer 170b covers the second pixel slot 130b. Understandably, color conversion materials cannot completely absorb all the light incident on the pixel unit. Adding a corresponding filter layer to the color conversion layer absorbs the residual light, which helps to further improve the color purity of the light emitted by each sub-pixel, allowing for more precise control of the displayed color. Furthermore, it helps to improve the blackness of the light-emitting structure, reducing the reflection of ambient light by the light-emitting element, thereby improving contrast.

[0330] Optionally, the filter layer also includes a third filter layer (not shown in the figure), which covers the third pixel slot 130c.

[0331] In some specific embodiments, the filter layer can be a color filter (CF) that only allows light within a specific wavelength range to pass through. The type of filter can be set according to the desired color of emitted light. In this embodiment, the first filter layer 170a can be a red filter layer (CF-R), the second filter layer 170b can be a green filter layer (CF-G), and the third filter layer can be a blue filter layer (CF-B). When the light emitted by each sub-pixel area is blue light, the red and green filter layers can be filter materials used to filter out blue light that is not absorbed by the light conversion material, and the blue filter layer can be a transparent layer or a filter material used to filter wavelengths other than blue light.

[0332] Please refer to Figures 37 and 44, and perform step S606: form an matting layer 600 on the isolation barrier. Understandably, in this embodiment, the isolation barrier is fabricated using a substrate 100. Conventional substrate materials have a certain reflectivity; under ambient light, the top surface of the isolation barrier reflects ambient light, causing the non-light-emitting area of ​​the light-emitting structure (the area where the isolation barrier is located) to also emit light, significantly affecting the display contrast of the light-emitting structure. Therefore, this application improves contrast by setting an matting layer 600 on the isolation barrier, which absorbs incident ambient light, increases the blackness of the light-emitting structure, and reduces the reflection of ambient light by the light-emitting element.

[0333] In some embodiments, referring to Figures 37, 44, and 47, the substrate 100 includes a plurality of chip regions 1010; an matting layer 600 on an adjacent second isolation barrier 162 defines a dicing window 1021, which exposes the dicing region 1020. In this application, the matting layer 600 includes a first portion and a second portion, the first portion being the portion of the matting layer 600 located on the first isolation barrier 161, and the second portion being the portion of the matting layer 600 located on the second isolation barrier 162, the first portion and the second portion being connected to each other.

[0334] Understandably, the second isolation barrier 162 is located at the edge of the chip region 1010. The outer boundary of the second isolation barrier 162 can be understood as the boundary of the chip region 1010, and also the boundary of the dicing region 1020. The outer wall of the second portion of the matte layer 600 corresponds to the boundary of the second isolation barrier 162; in other words, the outer wall of the second portion of the matte layer 600 corresponds to the boundary of the dicing region 1020. Therefore, for two adjacent chip regions 1010 and the dicing region 1020 between them, the window formed between the outer walls of the two adjacent second portions exposes the dicing region 1020.

[0335] Understandably, in the current field, it is common practice to form markings on the dicing area 1020 during the fabrication process. Before dicing the wafer, an image of the wafer surface morphology is acquired using equipment to locate the markings and determine the position of the dicing area 1020. During this process, the equipment emits light onto the wafer surface and generates a wafer surface morphology image based on the reflected light. However, both the isolation barrier and the dicing area 1020 reflect the incident light from the equipment, resulting in low contrast in the wafer surface morphology image, making it difficult to accurately locate the markings and thus affecting dicing and causing waste. Therefore, this application provides an matting layer 600 on the isolation barrier and exposes the dicing area 1020 through a dicing window 1021 defined by the pattern of the matting layer 600. When the equipment illuminates the wafer surface, the isolation barrier does not reflect light, while the dicing area 1020 does. This results in high contrast of the light-emitting structure and a strong contrast in the image acquired by the equipment, making it easier and more accurate to determine the position of the dicing area.

[0336] On the plane of substrate 100, the projection of the second isolation barrier 162 is annular, and the projection of the dicing area 1020 is also annular. The side of the second isolation barrier 162 away from the pixel slot is the dicing area 1020, and the projection of the dicing area 1020 surrounds the projection of the second isolation barrier 162. In some embodiments, on the plane of substrate 100, the projection shape of the second portion is the same as the projection shape of the second isolation barrier 162, and the projection area of ​​the second portion is smaller than the projection area of ​​the second isolation barrier 162. In this embodiment, the linewidth of the dicing window 1021 is greater than the linewidth of the dicing area 1020. This provides more space for dicing and makes it easier to identify the position of the dicing area 1020 before dicing.

[0337] In other embodiments, the projection of the second portion overlaps with the projection of the second isolation barrier 162 on the plane of the substrate 100. In this embodiment, the linewidth of the dicing window 1021 is equal to the linewidth of the dicing region 1020. This avoids the absence of an extinction layer 600 in certain areas of the chip region 1010, which could affect the contrast of the light-emitting structure.

[0338] In an optional specific implementation, referring to Figures 36 and 37, steps S605 and S606 include:

[0339] A first filter material layer 171 covering the pixel groove 130 and the substrate 100 is formed on the second surface 102;

[0340] A first patterning process is performed on the first filter material layer 171 to expose the second pixel groove 130b, the third pixel groove 130c and the cutting channel area 1020, and the first filter material layer 171 on the first pixel groove 130a is formed as the first filter layer 170a.

[0341] A second filter material layer 172 covering the pixel groove 130 and the substrate 100 is formed on the second surface 102;

[0342] A second patterning process is performed on the second filter material layer 172 to expose the first pixel groove 130a, the third pixel groove 130c and the cutting channel area 1020. The second filter material layer 172 on the second pixel groove 130b is formed as a second filter layer 170b. The stacked structure of the first filter material layer 171 and the second filter material layer 172 on the isolation barrier is formed as an matting layer 600. The first filter material layer 171 and the second filter material layer 172 filter light of different colors.

[0343] Therefore, steps S605 and S606 are performed in the same process. When preparing the first filter layer 170a and the second filter layer 170b, the matting layer 600 is formed simultaneously, reducing the number of processes and improving production efficiency.

[0344] It should be noted that Figures (a), (b), and (c) in each of Figures 36 and 37 correspond to Figures (a), (b), and (c) in Figure 35, respectively. They are schematic diagrams of structures formed by sequentially performing the preparation methods based on Figures (a), (b), and (c) in Figure 35.

[0345] Optionally, the materials of the first filter material layer 171 and the second filter material layer 172 include colored photoresist; the first patterning process and the second patterning process include photolithography.

[0346] Specifically, referring to Figure 40, during the first photolithography, the first exposed area 1711 includes the portion of the first filter material layer 171 corresponding to the first pixel groove 130a and the portion corresponding to the isolation barrier; the first non-exposed area 1712 includes the portion of the first filter material layer 171 corresponding to the second pixel groove 130b, the portion corresponding to the third pixel groove 130c, and the portion corresponding to the cutting channel area 1020. The first filter material layer 171 is a negative resist. The first filter material layer 171 of the first exposed area 1711 is retained, while the first filter material layer 171 of the first non-exposed area 1712 is removed. Referring to Figure 41, during the second photolithography process, the second exposed area 1721 includes the portion of the second filter material layer 172 corresponding to the second pixel groove 130b and the portion corresponding to the isolation barrier; the second non-exposed area 1722 includes the portion of the second filter material layer 172 corresponding to the first pixel groove 130a, the portion corresponding to the third pixel groove 130c, and the portion corresponding to the cutting channel area 1020. The second filter material layer 172 is a negative resist. The second filter material layer 172 in the second exposed area 1721 is retained, while the second filter material layer 172 in the second non-exposed area 1722 is removed. Understandably, in related technologies, the first filter layer 170a and the second filter layer 170b are typically obtained through two photolithography processes. This application simultaneously forms the matting layer 600 without increasing the number of exposures, resulting in minimal improvement to the manufacturing process.

[0347] Since the first filter material layer 171 and the second filter material layer 172 only allow the corresponding color spectrum to pass through, after the two filter material layers are stacked, the light emitted after passing through the second filter material layer 172 cannot pass through the first filter material layer 171, and vice versa, achieving an extinction effect. Thus, all visible light maintains low transmittance, and the isolation barrier achieves a low reflectance effect. In this embodiment, the stacked structure composed of the first filter material layer 171 and the second filter material layer 172 can also be called a "CF stacked structure". The first filter material layer 171 is specifically a red filter material layer, such as a red photoresist layer, and the second filter material layer 172 is specifically a green filter material layer, such as a green photoresist layer.

[0348] It should be noted that Figures 36 and 37 only schematically show the preparation sequence of forming the first filter material layer 171 first and then the second filter material layer 172. However, this application does not exclude the preparation sequence of forming the second filter material layer 172 first and then the first filter material layer 171. This application does not limit this.

[0349] In some embodiments, the fabrication method further includes: forming a third filter material layer (not shown) covering the pixel groove 130 and the substrate 100 on the second surface 102; performing a third patterning process on the third filter material layer to expose the first pixel groove 130a, the second pixel groove 130b, and the dicing area 1020; the third filter material layer on the third pixel groove 130c is formed as a third filter layer; the stacked structure consisting of the first filter material layer 171, the second filter material layer 172, and the third filter material layer on the isolation barrier is formed as an extinction layer 600, wherein the first filter material layer 171, the second filter material layer 172, and the third filter material layer filter light of different colors. Specifically, the third filter material layer is a blue filter material layer, such as a blue photoresist layer. It is understood that this application does not limit the order in which the first filter material layer 171, the second filter material layer 172, and the third filter material layer are formed.

[0350] In another optional embodiment, referring to Figures 42 to 44, steps S605 and S606 include:

[0351] A first filter material layer 171 covering the pixel groove 130 and the substrate 100 is formed on the second surface 102;

[0352] A first patterning process is performed on the first filter material layer 171 to expose the second pixel groove 130b, the third pixel groove 130c, the isolation barrier and the cutting channel area 1020, forming a first filter layer 170a covering the first pixel groove 130a.

[0353] A second filter material layer 172 covering the pixel groove 130 and the substrate 100 is formed on the second surface 102;

[0354] A second patterning process is performed on the second filter material layer 172 to expose the first pixel groove 130a, the third pixel groove 130c, the isolation barrier and the cutting channel area 1020, forming a second filter layer 170b covering the second pixel groove 130b.

[0355] An matting material layer (not shown in the figure) covering the pixel groove 130 and the substrate 100 is formed on the second surface 102;

[0356] A third patterning process is performed on the matte material layer to expose the pixel groove 130 and the cutting channel area 1020 in order to form a matte layer 600 on the isolation barrier.

[0357] In this specific embodiment, after step S605 is completed, step S606 is performed through photolithography. In actual fabrication, the photomasks required for the two photolithography processes in step S605 can be photomasks that are already in production. Only one additional photomask needs to be fabricated to perform the photolithography process in step S606. The modification to the photomask is minor and it is easier to adapt to existing production processes.

[0358] It should be noted that Figures (a), (b), and (c) in each of Figures 42 to 44 correspond to Figures (a), (b), and (c) in Figure 35, respectively. They are schematic diagrams of structures formed by sequentially performing the preparation methods based on Figures (a), (b), and (c) in Figure 35.

[0359] Optionally, the matte layer 600 may be made of black photoresist. Black photoresist can absorb most of the light, effectively achieving a blackening effect and improving the contrast of the light-emitting structure.

[0360] Please refer to Figures 37 and 43. Optionally, the filter layer also covers part of the isolation barrier. This reduces the requirements for overlay accuracy during actual fabrication, leaves a margin for patterning processes, and prevents each filter layer from forming on other pixel slots, thus affecting the emission of sub-pixels.

[0361] In some embodiments, the linewidth of the portion of the filter layer covering the isolation barrier ranges from 0 μm to 30 μm. Therefore, controlling the linewidth within the range of 0 μm to 30 μm allows for a moderate reduction in overlay accuracy requirements while ensuring that the luminescent area of ​​the light-emitting structure remains largely unchanged. Furthermore, a linewidth range of 1 μm to 5 μm for the portion of the filter layer covering the isolation barrier is even more beneficial for balancing overlay accuracy and luminescence performance.

[0362] Please refer to Figures 38, 45, and 47. After performing step S606, the preparation method further includes: forming a protective capping layer 180, which covers the second surface 102, the filter layer, and the matting layer 600. It should be noted that the protective capping layer 180 is specifically described in Example 1, and will not be elaborated upon here.

[0363] It should be noted that Figure 47 is a layout of the structure shown in Figure 38, and also a layout of the structure shown in Figure 45. Figure 38 is a cross-sectional view of the light-emitting structure provided in an optional embodiment during the fabrication process, and Figure 45 is a cross-sectional view of the light-emitting structure provided in another optional embodiment during the fabrication process. Figures (a), (b), and (c) in Figures 38 and 45 are cross-sectional views along lines K-K', L-L', and M-M' in Figure 47, respectively.

[0364] Please refer to Figures 38 and 39, as well as Figures 45 and 46. After step S606, the fabrication method may further include: dicing along the dicing window 1021 to obtain a chip structure.

[0365] It should be noted that in Figures 38 and 39, Figures (a), (b), and (c) correspond to Figures (a), (b), and (c) in Figure 37, respectively. They are schematic diagrams of structures formed by sequentially performing the preparation methods based on Figures (a), (b), and (c) in Figure 37. Similarly, in Figures 45 and 46, Figures (a), (b), and (c) correspond to Figures (a), (b), and (c) in Figure 44, respectively. They are schematic diagrams of structures formed by sequentially performing the preparation methods based on Figures (a), (b), and (c) in Figure 44.

[0366] Example 7

[0367] This application provides a light-emitting structure. Please refer to Figures 38 and 45. The light-emitting structure includes:

[0368] The substrate 100 includes a chip region 1010 and a dicing region 1020 located on the periphery of the chip region 1010. The substrate 100 includes a first surface 101 and a second surface 102 that are opposite to each other in the thickness direction.

[0369] Pixel unit 190 is located on the first surface 101 side of chip region 1010. Pixel unit 190 includes a first sub-pixel unit 190a, a second sub-pixel unit 190b and a third sub-pixel unit 190c arranged at intervals from each other.

[0370] Pixel slot 130 is located within chip region 1010 and extends from the second surface 102 side to expose pixel unit 190. Pixel slot 130 includes a first pixel slot 130a, a second pixel slot 130b and a third pixel slot 130c that are spaced apart from each other. The first pixel slot 130a, the second pixel slot 130b and the third pixel slot 130c correspond to the first sub-pixel unit 190a, the second sub-pixel unit 190b and the third sub-pixel unit 190c, respectively.

[0371] The isolation barrier includes a first isolation barrier 161 and a second isolation barrier 162. The first isolation barrier 161 is formed by the portion of the chip region 1010 located between any two of the first pixel slot 130a, the second pixel slot 130b and the third pixel slot 130c. The second isolation barrier 162 is formed by the edge region of the chip region 1010. Along the thickness direction of the substrate 100, the projection of the second isolation barrier 162 surrounds the projection of the first isolation barrier 161.

[0372] The first color conversion layer 151 and the second color conversion layer 152 are located in the first pixel slot 130a and the second pixel slot 130b, respectively.

[0373] A filter layer is located on the side of the second surface 102 and covers the pixel slot 130. The filter layer includes a first filter layer 170a and a second filter layer 170b. The first filter layer 170a covers the first pixel slot 130a, and the second filter layer 170b covers the second pixel slot 130b.

[0374] The matte finish 600 is located on the isolation barrier.

[0375] Therefore, by setting an matting layer 600 on the isolation barrier, the matting layer 600 absorbs all light and prevents the light hitting the isolation barrier from being reflected, thereby improving the display contrast of the light-emitting structure.

[0376] Understandably, the first pixel groove 130a extends from the second surface 102 toward the first surface 101 through the substrate 100, and corresponds to the first sub-pixel unit 190a; the second pixel groove 130b extends from the second surface 102 toward the first surface 101 through the substrate 100, and corresponds to the second sub-pixel unit 190b; the third pixel groove 130c extends from the second surface 102 toward the first surface 101 through the substrate 100, and corresponds to the third sub-pixel unit 190c. Along the thickness direction of the substrate 100, the depths of the first pixel groove 130a, the second pixel groove 130b, and the third pixel groove 130c are equal to the thickness of the substrate 100.

[0377] In chip region 1010, the portion of the first pixel slot 130a closest to the second pixel slot 130b and the third pixel slot 130c forms a first isolation barrier 161, and the portion of the first pixel slot 130a furthest from the second pixel slot 130b and the third pixel slot 130c forms a second isolation barrier 162; similarly, the portion of the second pixel slot 130b closest to the first pixel slot 130a and the third pixel slot 130c forms the first isolation barrier 161, and the portion of the second pixel slot 130b furthest from the first pixel slot 130a and the third pixel slot 130c forms the second isolation barrier 162; and the portion of the third pixel slot 130c closest to the first pixel slot 130a and the second pixel slot 130b forms the first isolation barrier 161, and the portion of the third pixel slot 130c furthest from the first pixel slot 130a and the second pixel slot 130b forms the second isolation barrier 162. The projection of the second isolation barrier 162 onto the plane of the substrate 100 is specifically annular. Since the second isolation barrier 162 is formed by the edge region of the chip area 1010, the outer boundary of the second isolation barrier 162 can be understood as the boundary of the chip area 1010, or as the boundary between the cutting channel areas 1020.

[0378] Optionally, the materials of the first color conversion layer 151 and the second color conversion layer 152 may include phosphors or quantum dots. Further, the materials of both the first color conversion layer 151 and the second color conversion layer 152 may be quantum dots.

[0379] The first sub-pixel unit 190a and the first color conversion layer 151 can constitute a first sub-pixel, the first sub-pixel unit 190a and the second color conversion layer 152 can constitute a second sub-pixel, and the third sub-pixel unit 190c can constitute a third sub-pixel. In this embodiment, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. The red, green, and blue sub-pixels can constitute a light-emitting pixel unit (full-color LED chip), emitting red, green, and blue light. Therefore, the first color conversion layer 151 can be a red color conversion layer, and the second color conversion layer 152 can be a green color conversion layer.

[0380] It should be noted that a pixel unit can be understood as a "light-emitting chip," and a sub-pixel unit can be understood as a "light-emitting core." The light-emitting chip can be a blue light chip or an ultraviolet light chip; the light-emitting chip can be a Micro LED chip. The red, green, and blue sub-pixels use the same light-emitting chip, and the materials and light-emitting characteristics of the light-emitting areas of each sub-pixel are highly consistent, which is beneficial to improving the display effect and long-term stability of the light-emitting structure (full-color LED wafer).

[0381] Optionally, an optical material layer 153 is formed in the third pixel slot 130c. The optical material layer 153 may include a third color conversion layer (not shown) and / or a light diffusion layer (not shown). In some embodiments, the light emitted by the pixel unit 190 is blue light, and the optical material layer 153 may be a light diffusion layer. In other embodiments, the light emitted by the pixel unit 190 is ultraviolet light, and the optical material layer 153 may include a third color conversion layer, or the optical material layer may include a third color conversion layer and a light diffusion layer, with the light diffusion layer located between the third color conversion layer and the third sub-pixel unit 190c; wherein the third color conversion layer is a blue color conversion layer.

[0382] Optionally, a light diffusion layer (not shown in the figure) is further formed between the first color conversion layer 151 and the first sub-pixel unit 190a, and a light diffusion layer (not shown in the figure) is further formed between the second color conversion layer 152 and the second sub-pixel unit 190b. This is beneficial for extending the luminescence lifetime.

[0383] Optionally, the substrate 100 includes a plurality of chip regions 1010; the matting layer 600 on the adjacent second isolation barrier 162 defines a dicing window 1021, which exposes the dicing region 1020. Thus, the position of the dicing region 1020 can be obtained relatively easily and accurately.

[0384] In an optional embodiment, referring to Figure 38, the extinction layer 600 includes a first filter material layer 171 and a second filter material layer 172 stacked sequentially. The first filter material layer 171 and the second filter material layer 172 filter different colors of light. The first filter material layer 171 and the first filter layer 170a are the same material layer, and the second filter material layer 172 and the second filter layer 170b are the same material layer. Since the first filter material layer 171 and the second filter material layer 172 only allow the corresponding color spectrum to pass through, after the two filter material layers are stacked, the outgoing light after passing through the second filter material layer 172 cannot pass through the first filter material layer 171, and vice versa, achieving an extinction effect. Thus, all visible light maintains low transmittance, and the isolation barrier achieves a low reflectance effect. In this embodiment, the stacked structure composed of the first filter material layer 171 and the second filter material layer 172 can also be called a "CF stacked structure".

[0385] Optionally, the materials of the first filter material layer 171 and the second filter material layer 172 include colored photoresist. In this embodiment, the first filter material layer 171 is specifically a red filter material layer, such as a red photoresist layer, and the second filter material layer 172 is specifically a green filter material layer, such as a green photoresist layer.

[0386] Furthermore, the first filter material layer 171 and the first filter layer 170a are made of the same material layer, and the second filter material layer 172 and the second filter layer 170b are also made of the same material layer. In actual fabrication, the first filter material layer 171 and the second filter material layer 172 can be formed simultaneously with the fabrication of the first filter layer 170a and the second filter layer 170b, resulting in a laminated structure. This reduces production steps and improves production efficiency.

[0387] Optionally, the filter layer includes a color filter (CF). A color filter allows light to pass through only within a specific wavelength range. Further, the material of the filter layer includes colored photoresist.

[0388] In another optional embodiment, referring to Figure 45, the matting layer 600 is made of black photoresist. Black photoresist can absorb most of the light, effectively achieving a blackening effect and improving the contrast of the light-emitting structure.

[0389] Optionally, the filter layer also covers part of the isolation barrier. This reduces the requirements for overlay precision during actual fabrication, leaves a margin for the photolithography process, and prevents the filter layers from forming on other pixel slots, thus affecting the light-emitting area of ​​the sub-pixels.

[0390] Optionally, the linewidth of the portion of the filter layer covering the isolation barrier ranges from 1μm to 5μm. Therefore, controlling the linewidth within the range of 1μm to 5μm allows for a moderate reduction in overlay precision requirements while ensuring that the luminescent area of ​​the light-emitting structure remains largely unchanged.

[0391] Please refer to Figures 38 and 45. The light-emitting structure also includes: a protective capping layer 180, covering the second surface 102, a filter layer, and an matting layer 600. This can improve the structural strength of the light-emitting structure and effectively isolate the color conversion layer, filter layer, and other structures from contact with the outside air.

[0392] Example 8

[0393] Figure 48 is a schematic flowchart of a method for fabricating a light-emitting device according to an embodiment of this application. As shown in the figure, the fabrication method includes:

[0394] Step S801: Provide a substrate, the substrate including a first surface and a second surface opposite to each other in the thickness direction;

[0395] Step S802: Form a chip layer on the first surface side;

[0396] Step S803: Perform a patterning process from the first surface side to form an isolation channel. The chip layer is divided into pixel unit regions including at least two sub-pixel regions by the isolation channel. The isolation channel includes a pixel sub-channel located between any two sub-pixel regions. The pixel sub-channel extends from the side of the chip layer away from the substrate, penetrates the chip layer, and extends into the interior of the substrate.

[0397] Step S804: Form electrode pads on the side of each sub-pixel region away from the substrate;

[0398] Step S805: Provide a welding substrate, on which welding electrodes are formed;

[0399] Step S806: Weld the electrode pads to the welding electrodes using welding material; wherein, the pixel channel is used to contain the welding material during the welding process.

[0400] Therefore, by setting a sub-channel between any two sub-pixel areas that extends from the side of the chip layer away from the substrate, penetrates the chip layer, and extends into the substrate, the sub-pixel areas are isolated from each other, while the space between the sub-pixel areas is increased. The portion of the solder material that escapes during the soldering process can be contained by the sub-channel, avoiding contact between the portions of the solder material that escape at different locations, thereby reducing the probability of short-circuit failure of the device.

[0401] First, referring to Figure 49, perform step S801 to provide a substrate 100, which includes a first surface 101 and a second surface 102 that are opposite to each other in the thickness direction.

[0402] The substrate 100 may be a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, a silicon substrate, or other semiconductor material substrates known in the art. In the embodiments of this application, the substrate 100 may be a silicon substrate.

[0403] It should be noted that the plane containing the first surface 101 and the second surface 102 of the substrate, or more precisely, the center plane in the thickness direction of the substrate, is defined as the plane in which the substrate is located, and the direction perpendicular to the plane in which the substrate is located is along the thickness direction of the substrate.

[0404] Please continue to refer to Figure 49 and perform step S802 to form a chip layer 400 on the first surface 101 side.

[0405] In some embodiments, the substrate 100 can be a growth substrate, on which a chip layer 400 is formed by an epitaxial growth process. Here, the chip layer 400 can also be referred to as an "epitaxy layer".

[0406] In some embodiments, the chip layer 400 may include a first conductive semiconductor layer 111, an active layer 112, and a second conductive semiconductor layer 113 sequentially stacked along a direction away from the substrate 100. It should be noted that the specific details regarding the first conductive semiconductor layer 111, the active layer 112, and the second conductive semiconductor layer 113 can be found in the relevant description in Embodiment 1, and will not be repeated here.

[0407] Next, referring to Figures 50 and 52, perform step S803, perform a patterning process from the first surface 101 side to form an isolation channel 230. The chip layer 400 is divided by the isolation channel 230 into pixel unit regions 120 including at least two sub-pixel regions. The isolation channel 230 includes a pixel sub-channel 2310 located between any two sub-pixel regions. The pixel sub-channel 2310 extends from the side of the chip layer 400 away from the substrate 100, penetrates the chip layer 400, and extends into the interior of the substrate 100. Therefore, by setting a pixel sub-channel 2310 between any two sub-pixel areas, extending from the side of the chip layer 400 away from the substrate 100, penetrating the chip layer 400 and extending into the interior of the substrate 100, the sub-pixel areas are isolated from each other, while the space between the sub-pixel areas is increased. The portion of the solder material that escapes during the soldering process can be accommodated by the pixel sub-channel 2310, avoiding contact between the portions of the solder material that escape at different locations, thereby reducing the probability of short-circuit failure of the device.

[0408] In some embodiments, referring to FIG50, the pixel unit area 120 includes a first sub-pixel area 120a, a second sub-pixel area 120b, and a third sub-pixel area 120c.

[0409] It should be understood that Figure 50 only illustrates the case where the projection shape of the pixel unit area 120 on the plane of the substrate 100 is rectangular, and the pixel unit area 120 includes three sub-pixel areas. This application does not exclude the possibility that the projection shape of the pixel unit area 120 on the plane of the substrate 100 is triangular, trapezoidal, pentagonal, or other suitable shape. Referring to Figure 51, in some embodiments, the projection shape of the pixel unit area 120 on the plane of the substrate 100 is circular. This application also does not exclude the possibility that the pixel unit area 120 includes four, five, or more sub-pixel areas. Of course, in some specific embodiments, on the plane of the substrate 100, the projection shapes of the first sub-pixel area 120a, the second sub-pixel area 120b, and the third sub-pixel area 120c can be rectangular, trapezoidal, circular, triangular, or other suitable shapes; the projection shapes of the first sub-pixel area 120a, the second sub-pixel area 120b, and the third sub-pixel area 120c can be the same or different. This application does not impose specific limitations in this regard.

[0410] It should be understood that Figure 50 only schematically illustrates the case of a single pixel unit region 120. This application does not exclude the possibility that the chip layer 400, after being patterned, is divided into multiple arrayed pixel unit regions 120. This application does not limit this.

[0411] In some embodiments, the first sub-pixel area 120a is the light-emitting area for the red sub-pixel, the second sub-pixel area 120b is the light-emitting area for the green sub-pixel, and the third sub-pixel area 120c is the light-emitting area for the blue sub-pixel. It can be understood that the red, green, and blue sub-pixels can constitute a single light-emitting pixel unit (full-color LED chip), emitting red, green, and blue light. It should be noted that the sub-pixel area is also called a "light-emitting core," and the pixel unit area is also called a "light-emitting chip." The light-emitting chip can be a blue light chip or an ultraviolet light chip; the light-emitting chip can be a Micro LED (micro light-emitting diode) chip. The use of the same light-emitting chip for the red, green, and blue sub-pixels, and the highly consistent material and light-emitting characteristics of each sub-pixel, are beneficial for improving the display effect and long-term stability of the light-emitting device.

[0412] Referring to Figure 50, the pixel sub-channel 2310 includes a first pixel sub-channel 2311, a second pixel sub-channel 2312, and a third pixel sub-channel 2313. The first pixel sub-channel 2311 is located between the first sub-pixel area 120a and the third sub-pixel area 120c; the second pixel sub-channel 2312 is located between the second sub-pixel area 120b and the third sub-pixel area 120c; and the third pixel sub-channel 2313 is located between the first sub-pixel area 120a and the second sub-pixel area 120b. One end of the third pixel sub-channel 2313 connects to the first pixel sub-channel 2311 and the second pixel sub-channel 2312. Thus, through the isolation effect of each sub-channel in the isolation channel 230, while ensuring the isolation of each sub-pixel area from each other, each sub-pixel area achieves a more reasonable distribution and suitable regional outline, which is beneficial for adjusting the arrangement and luminous area size of multiple sub-pixels of different colors. In the embodiments of this application, the first pixel sub-channel can also be referred to as the "first sub-channel", the second pixel sub-channel can also be referred to as the "second sub-channel", and the third pixel sub-channel can also be referred to as the "third sub-channel".

[0413] Referring to Figure 52, in some embodiments, the pixel channel 2310 includes a first channel portion 2301 extending from the first surface 101 of the substrate 100 into the interior of the substrate 100; in the thickness direction of the substrate 100, the depth h1 of the first channel portion 2301 is greater than or equal to 2 μm. Understandably, the greater the depth h1 of the first channel portion 2301, the greater the depth of the pixel channel 2310 and the larger the space. Therefore, during the soldering process, it can better accommodate the escaped portions of the soldering material, more effectively prevent contact between the escaped portions of the soldering material at different locations, and reduce the probability of device short-circuit failure.

[0414] Referring to Figure 52, in some embodiments, the pixel sub-channel 2310 includes a second channel portion 2302 extending from the side of the chip layer 110 away from the substrate 100 to a first surface 101 of the substrate 100, and a first channel portion 2301 extending from the first surface 101 of the substrate 100 into the interior of the substrate 100, the first channel portion 2301 being connected to the second channel portion 2302; in the thickness direction of the substrate 100, the projected area of ​​the second channel portion 2302 is larger than the projected area of ​​the first channel portion 2301. This increases the space of the pixel sub-channel 2310, allowing it to accommodate more soldering material.

[0415] Furthermore, the bottom groove width d1 of the first channel portion 2301 is greater than or equal to 2 μm, and the bottom end of the first channel portion 2301 is the end of the first channel portion 2301 that is closer to the second surface 102; and / or, the top groove width d2 of the second channel portion 2302 is greater than or equal to 15 μm, and the top end of the second channel portion 2302 is the end of the second channel portion 2302 that is farther away from the second surface 102. Understandably, during the welding process, the escaping portion of the welding material will laterally disperse at the top of the second channel portion 2302 and longitudinally accumulate from the top of the second channel portion 2302 to the bottom of the first channel portion 2301. By controlling the top groove width d2 of the second channel portion 2302 to be greater than or equal to 15μm, the path length of the lateral dispersion of the welding material is increased. By controlling the bottom groove width d1 of the first channel portion 2301 to be greater than or equal to 2μm, contact is avoided after the welding material accumulates longitudinally. Thus, contact after the welding material escapes from different locations can be more effectively avoided.

[0416] In some embodiments, please continue to refer to FIG52, the second channel portion 2302 includes a first sub-portion 2302-1 and a second sub-portion 2302-2 that are connected. The first sub-portion 2302-1 extends from the side of the chip layer 400 away from the substrate 100, through the second conductive semiconductor layer 113 and the active layer 112 and into the interior of the first conductive semiconductor layer 111. The second sub-portion 2302-2 extends from the bottom end of the first sub-portion 2302-1 to the first surface 101 of the substrate 100. The bottom end of the first sub-portion 2302-1 is the end of the first sub-portion 2302-1 that is close to the second surface 102. In some specific examples, the projected area of ​​the first sub-part 2302-1 is larger than the projected area of ​​the second sub-part 2302-2 along the thickness direction of the substrate. As a result, the first conductive semiconductor layer 111 is formed to have a first step portion and a second step portion, with the second step portion located below the first step portion. The sidewalls of the first step portion, the active layer 112, and the second conductive semiconductor layer 113 define the sidewalls of the first sub-part 2302-1, and the sidewalls of the second step portion define the sidewalls of the second sub-part 2302-2.

[0417] In some embodiments, the angle between the surface of the second step portion away from the active layer 112 and the sidewall of the second step portion is an acute angle. This reduces the difficulty of fabricating the lower reflective electrode in subsequent steps, achieves good coverage of the sidewall of the isolation channel, and facilitates the reflection of light emitted from the active layer 112, thereby improving light extraction efficiency. The angle between the side of the second step portion away from the active layer 112 and the sidewall of the second step portion can be understood as the angle between the surface of the first conductive semiconductor layer 111 away from the active layer 112 and the sidewall of the second sub-part 2302-2. Furthermore, the angle between the side of the second step portion away from the active layer 112 and the sidewall of the second step portion is less than or equal to 60°, which is more conducive to achieving the desired effect.

[0418] In some embodiments, the sidewall of the second sub-part 2302-2 forms a flat plane with the sidewall of the first channel portion 2301.

[0419] In some embodiments, referring to Figures 50, 53, and 54, the chip layer 400 includes a first conductive semiconductor layer 111, an active layer 112, and a second conductive semiconductor layer 113 stacked sequentially along a direction away from the substrate 100; the pixel unit region 120 also includes a dummy structure region 120d, wherein a first sub-pixel region 120a, a second sub-pixel region 120b, and a third sub-pixel region 120c are distributed at different positions in the pixel unit region 120 and extend to the boundary of the pixel unit region 120, and the dummy structure region 120d is located inside the pixel unit region 120 or at the boundary of the pixel unit region 120; the isolation channel 230 also includes a first virtual sub-channel 2320 located between the first sub-pixel region 120a and the dummy structure region 120d, and a second virtual sub-channel 2320 located between the second sub-pixel region 120b and the dummy structure region 120d. The second virtual sub-channel 2330 between 0d; both the first virtual sub-channel 2320 and the second virtual sub-channel 2330 include a first sub-section 2302-1, which extends from the side of the chip layer 400 away from the substrate 100, through the second conductive semiconductor layer 113 and the active layer 112 and into the interior of the first conductive semiconductor layer 111. The first virtual sub-channel 2320 also includes a second sub-section 2302-2 that communicates with the first sub-section 2302-1. The second sub-section 2302-2 extends from the bottom end of the first sub-section 2302-1 to the first surface 101 of the substrate 100. The bottom end of the first sub-section 2302-1 is the end of the first sub-section 2302-1 that is close to the second surface 102. The first sub-section 2302-1 and the second sub-section 2302-2 constitute the second channel portion 2302.

[0420] Therefore, the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c are distributed at different positions in the pixel unit region 120 and extend to the boundary of the pixel unit region 120. The dummy structure region 120d is located inside the pixel unit region 120 or at the boundary of the pixel unit region 120. Subsequently, a common electrode pad located on the dummy structure region 120d is connected to the first conductive semiconductor layer 111 in the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c. Conductive connection allows each sub-pixel area in a pixel unit area 120 to share an electrode, reducing lead arrangement. The chip composed of a single pixel unit area 120 can be independently controlled, which is beneficial for combining and splicing multiple chips to obtain a larger size light-emitting device. A virtual sub-channel is set between the sub-pixel area and the virtual structure area 120d, so that the part of the welding material that escapes during the welding process can be contained by the pixel sub-channel and the virtual sub-channel, avoiding contact between the parts of the welding material that escape at different locations, thereby reducing the probability of short circuit failure of the device.

[0421] It should be noted that, here, the dummy structure region 120d is not used as the light-emitting region, and the active layer 112 in the dummy structure region 120d will not emit light.

[0422] In this embodiment, along the thickness direction of the substrate 100, the height of the dummy structure region 120d is consistent with the heights of the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c. Thus, along the thickness direction of the substrate 100, the distances between the subsequently fabricated first electrode pads, second electrode pads, third electrode pads, and common electrode pads and the first surface 101 of the substrate 100 are consistent. This improves the height difference between the electrode pads, thereby reducing the phenomena of incomplete soldering and over-soldering, further reducing damage to the light-emitting element, improving flip-chip soldering yield, and lowering manufacturing costs.

[0423] It should be noted that, in the embodiments of this application, the first virtual subchannel 2320 can also be referred to as the "fourth subchannel", and the second virtual subchannel 2330 can also be referred to as the "fifth subchannel".

[0424] In some embodiments, referring to FIG50, the dummy structure region 120d is located inside the pixel unit region 120; the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c surround the dummy structure region 120d. The projections of the first sub-pixel region 120a, the second sub-pixel region 120b, the third sub-pixel region 120c, and the dummy structure region 120d onto the plane of the substrate 100 lie in a circular region. The dummy structure region 120d being located inside the pixel unit region 120 can be understood as meaning that no part of the dummy structure region 120d extends to the boundary of the pixel unit region 120, but rather the entire dummy structure region 120 is located inside the pixel unit region 120.

[0425] In some embodiments, referring to FIG51, the dummy structure region 120d is located at the boundary of the pixel unit region 120; the projections of the first sub-pixel region 120a, the second sub-pixel region 120b, the third sub-pixel region 120c, and the dummy structure region 120d onto the plane of the substrate 100 are respectively located at the four vertices of the quadrilateral region. The dummy structure region 120d being located at the boundary of the pixel unit region 120 can be understood as at least a portion of the dummy structure region 120d extending to the boundary of the pixel unit region 120, including both cases where the entire dummy structure region 120d is located at the boundary and cases where a portion is internal and another portion extends to the boundary.

[0426] It should be understood that although Figure 50 only shows that the projections of the first sub-pixel area 120a, the second sub-pixel area 120b, the third sub-pixel area 120c, and the dummy structure area 120d on the plane of the substrate 100 are located at the four vertices of the rectangular area, this application does not exclude the possibility that the projections of the first sub-pixel area 120a, the second sub-pixel area 120b, the third sub-pixel area 120c, and the dummy structure area 120d are located at the four vertices of the trapezoidal, parallelogram, rhomboid, or other quadrilateral areas.

[0427] In some specific embodiments, the projected shapes of the first sub-pixel region 120a, the second sub-pixel region 120b, the third sub-pixel region 120c, and the dummy structure region 120d on the plane of the substrate 100 can be rectangular, trapezoidal, circular, triangular, or other suitable shapes; the projected shapes of the first sub-pixel region 120a, the second sub-pixel region 120b, the third sub-pixel region 120c, and the dummy structure region 120d can be the same or different. This application does not impose specific limitations on this.

[0428] It should be noted that Figure 50 is a schematic diagram of the projection of the pixel unit area onto the plane of the substrate; Figure 53 is a schematic diagram of the cross-sectional structure of the pixel unit area provided in an optional specific embodiment; Figure 54 is a schematic diagram of the cross-sectional structure of the pixel unit area provided in another optional specific embodiment. Figures (a) and (b) in Figures 53 and 54 are schematic diagrams of the cross-sectional structure along lines A3-A3' and A4-A4' in Figure 50, respectively.

[0429] As shown in Figure 50, the isolation channel 230 also includes a first virtual sub-channel 2320 and a second virtual sub-channel 2330; the other end of the third pixel sub-channel 2310 is connected to the first virtual sub-channel 2320 and the second virtual sub-channel 2330.

[0430] As an optional specific implementation, please refer to FIG53. The first virtual sub-channel 2320 and the second virtual sub-channel 2330 both include a first sub-section 2302-1. The first sub-section 2302-1 extends from the side of the chip layer 400 away from the substrate 100, penetrates the second conductive semiconductor layer 113 and the active layer 112, and extends into the interior of the first conductive semiconductor layer 111. The first virtual sub-channel 2320 also includes a second sub-section 2302-2 that communicates with the first sub-section 2302-1. The second sub-section 2302-2 extends from the bottom end of the first sub-section 2302-1 to the first surface 101 of the substrate 100. The bottom end of the first sub-section 2302-1 is the end of the first sub-section 2302-1 that is close to the second surface 102. The first sub-section 2302-1 and the second sub-section 2302-2 constitute the second channel portion 2302.

[0431] In this embodiment, the first virtual sub-channel 2320 includes a second channel portion 2302. The first virtual sub-channel 2320 extends from the side of the chip layer 400 away from the substrate 100 and penetrates the second conductive semiconductor layer 113, the active layer 112 and the first conductive semiconductor layer 111. The dummy structure region 120d and the first sub-pixel region 120a are isolated from each other. The second virtual sub-channel 2330 extends from the side of the chip layer 400 away from the substrate 100 and penetrates the second conductive semiconductor layer 113 and the active layer 112, but does not penetrate the first conductive semiconductor layer 111. The epitaxial layers in the second sub-pixel region 120b and the dummy structure region 120d are not completely isolated. The first conductive semiconductor layer 111 in the dummy structure region 120d and the first conductive semiconductor layer 111 in the second sub-pixel region 120b are connected through the first conductive semiconductor layer 111 located at the second virtual sub-channel 2330. In other words, the first conductive semiconductor layer 111 in the dummy structure region 120d and the first conductive semiconductor layer 111 in the second sub-pixel region 120b are physically connected, which facilitates conductive connection.

[0432] As another optional implementation, both the first virtual sub-channel 2320 and the second virtual sub-channel 2330 include a first sub-section 2302-1. The first sub-section 2302-1 extends from the side of the chip layer 400 away from the substrate 100, penetrates the second conductive semiconductor layer 113 and the active layer 112, and extends into the interior of the first conductive semiconductor layer 111. The first virtual sub-channel 2320 also includes a second sub-section 2302-2 that communicates with the first sub-section 2302-1. The second sub-section 2302-2 extends from the bottom end of the first sub-section 2302-1 to the first surface 101 of the substrate 100. The bottom end of the first sub-part 2302-1 is the end of the first sub-part 2302-1 that is close to the second surface 102. The first sub-part 2302-1 and the second sub-part 2302-2 constitute the second channel portion 2302. The first virtual sub-channel 2320 also includes the first channel portion 2301. And / or, the second virtual sub-channel 2330 also includes the second sub-part 2302-2 and the first channel portion 2301. The first channel portion 2301 extends from the first surface 101 of the substrate 100 into the interior of the substrate 100. The first channel portion 2301 is connected to the second channel portion 2302.

[0433] In this embodiment, the first virtual sub-channel 2320 extends from the side of the chip layer 400 away from the substrate 100, penetrates the chip layer 400, and extends into the interior of the substrate 100. The first virtual sub-channel 2320 includes a first channel portion 2301 and a second channel portion 2302. And / or, the second virtual sub-channel 2330 extends from the side of the chip layer 400 away from the substrate 100, penetrates the chip layer 400, and extends into the interior of the substrate 100. The second virtual sub-channel 2330 includes a first channel portion 2301 and a second channel portion 2302. This is more conducive to accommodating the escaped portion of the soldering material.

[0434] In some embodiments, referring to Figures 55 to 57, after forming the isolation channel 230, the preparation method may further include: forming a cover layer covering the sidewalls and bottom wall of the isolation channel 230, wherein the cover layer does not completely fill the isolation channel 230, so as to form a receiving groove 290 in the isolation channel 230, the receiving groove 290 being used to contain welding material during the welding process; in the thickness direction of the substrate 100, the bottom wall of the receiving groove 290 is located between the first surface 101 and the second surface 102 of the substrate 100. Therefore, the cover layer does not completely fill the isolation channel 230, allowing the isolation channel 230 to still accommodate the escaping portion of the welding material during the welding process. Understandably, the bottom wall of the receiving groove 290 is located between the first surface 101 and the second surface 102 of the substrate 100. That is, the receiving groove 290 extends from the side of the chip layer 400 away from the substrate 100, penetrates the chip layer 400, and extends into the interior of the substrate 100. Even if a cover layer is formed in the isolation channel 230, a large space is still reserved between each sub-pixel unit, effectively preventing the escaping portions of the welding material at different locations from contacting each other.

[0435] As shown in FIG55, in some embodiments, the cover layer may include: an insulating layer including a first insulating portion 250a, a second insulating portion 250b, and a third insulating portion 250c; wherein, the first insulating portion 250a covers the sidewalls of the second conductive semiconductor layer 113 and the active layer 112 in the first sub-pixel region 120a and extends to cover a portion of the sidewalls of the first conductive semiconductor layer 111; the second insulating portion 250b covers the sidewalls of the second conductive semiconductor layer 113 and the active layer 112 in the second sub-pixel region 120b and extends to cover a portion of the sidewalls of the first conductive semiconductor layer 111; the third insulating portion 250c covers the sidewalls of the second conductive semiconductor layer 113 and the active layer 112 in the third sub-pixel region 120c and extends to cover a portion of the sidewalls of the first conductive semiconductor layer 111; and the third insulating portion 250c covers the sidewalls of the second conductive semiconductor layer 113 and the active layer 112 in the third sub-pixel region 120c and extends to cover a portion of the sidewalls of the first conductive semiconductor layer 111. The first conductive semiconductor layer 111 is partially covered by an extension layer; a lower reflective electrode, including a first lower reflective electrode 260a, a second lower reflective electrode 260b, and a third lower reflective electrode 260c; wherein, the first lower reflective electrode 260a covers the sidewall of the first sub-pixel region 120a not covered by the first insulating portion 250a and extends to the bottom wall of the pixel sub-channel 2310; the second lower reflective electrode 260b covers the sidewall of the second sub-pixel region 120b not covered by the second insulating portion 250b and extends to the bottom wall of the pixel sub-channel 2310; the third lower reflective electrode 260c covers the sidewall of the third sub-pixel region 120c not covered by the third insulating portion 250c and extends to the bottom wall of the pixel sub-channel 2310. Thus, by using the lower reflective electrode and the insulating layer as an optical isolation layer, optical isolation between each sub-pixel region can be achieved, and optical crosstalk between sub-pixels can be prevented.

[0436] In some embodiments, the cover layer may further include a conductive connection portion 270, which covers the bottom wall of the pixel sub-channel 2310 and is conductively connected to the lower reflective electrode.

[0437] It should be noted that Figures (a) and (b) in Figure 55 correspond to Figures (a) and (b) in Figure 5, respectively, and are schematic diagrams of structures formed by further performing the preparation method based on Figures (a) and (b) in Figure 52.

[0438] In some embodiments, referring to Figures 56 and 57, the conductive connection portion 270 also extends from the side of the dummy structure region 120d away from the substrate 100 along the sidewall of the dummy structure region 120d toward the second surface 102, covering the bottom walls of the first virtual sub-channel 2320 and the second virtual sub-channel 2330. Thus, the first conductive semiconductor layer 111 of each sub-pixel region is conductively connected to the second conductive semiconductor layer 113 of the dummy structure region 120d via the lower reflective electrode and the conductive connection portion 270.

[0439] It should be noted that Figures (a) and (b) in Figure 56 correspond to Figures (a) and (b) in Figure 53, respectively, and are schematic diagrams of structures formed by further performing the preparation method based on Figures (a) and (b) in Figure 53; Figures (a) and (b) in Figure 57 correspond to Figures (a) and (b) in Figure 54, respectively, and are schematic diagrams of structures formed by further performing the preparation method based on Figures (a) and (b) in Figure 54.

[0440] In some embodiments, the lower reflective electrode and the conductive connection portion 270 are integrally formed.

[0441] The material of the lower reflective electrode may include at least one of titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and silver (Ag). This embodiment does not limit this.

[0442] The materials of the insulating layer include, but are not limited to, silicon oxide and silicon nitride.

[0443] In some embodiments, before forming the cover layer, the fabrication method may further include: forming a first upper reflective electrode 240a on the side of the first sub-pixel region 120a away from the substrate 100, with a first insulating portion 250a extending to cover a portion of the first upper reflective electrode 240a, and a first lower reflective electrode 260a extending onto the first insulating portion 250a, wherein the first upper reflective electrode 240a and the first lower reflective electrode 260a partially overlap in the thickness direction of the substrate 100; forming a second upper reflective electrode 240b on the side of the second sub-pixel region 120b away from the substrate 100, with a second insulating portion 250b extending to cover a portion of the substrate 100. The second upper reflective electrode 240b and the second lower reflective electrode 260b extend onto the second insulating portion 250b. In the thickness direction of the substrate 100, the second upper reflective electrode 240b and the second lower reflective electrode 260b partially overlap. A third upper reflective electrode 240c is formed on the side of the third sub-pixel region 120c away from the substrate 100. The third insulating portion 250c extends to cover a portion of the third upper reflective electrode 240c, and the third lower reflective electrode 260c extends onto the third insulating portion 250c. In the thickness direction of the substrate 100, the third upper reflective electrode 240c and the third lower reflective electrode 260c partially overlap. The overlap of the upper and lower reflective electrodes in the vertical direction allows all the emitted light from the active layer 112 to be reflected to the light-emitting surface (the side of the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c closest to the substrate 100), preventing light leakage from the electrode pad side.

[0444] The materials of the first upper reflective electrode 240a, the second upper reflective electrode 240b, and the third upper reflective electrode 240c may include at least one of titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and silver (Ag). This embodiment does not limit this.

[0445] In some embodiments, the cover layer further includes an isolation layer 280 covering the reflective electrode and the conductive connection portion 270. The material of the isolation layer 280 includes, but is not limited to, silicon oxide, silicon nitride, etc.

[0446] Next, step S804 is performed to form electrode pads on the side of each sub-pixel region away from the substrate 100.

[0447] In some embodiments, referring to FIG55, step S804 includes: forming a first electrode pad 210a, a second electrode pad 210b, and a third electrode pad 210c on the side of the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c away from the substrate 100, respectively; the first electrode pad 210a, the second electrode pad 210b, and the third electrode pad 210c are electrically connected to the second conductive semiconductor layer 113 in the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c, respectively. The materials of the first electrode pad 210a, the second electrode pad 210b, and the third electrode pad 210c include at least one of titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), silver (Ag), and tin (Sn), or alloys of the above metal materials. This embodiment does not limit this.

[0448] In some embodiments, referring to Figures 56 and 57, step S804 may further include: forming a common electrode pad 220 on the side of the dummy structure region 120d away from the substrate 100; the first electrode pad 210a, the second electrode pad 210b, and the third electrode pad 210c being electrically connected to the second conductive semiconductor layer 113 in the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c, respectively; and the common electrode pad 220 being electrically connected to the first conductive semiconductor layer 111 in the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c. Thus, by setting the common electrode pad 220 located on the dummy structure region 120d to be electrically connected to the first conductive semiconductor layer 111 in the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c, a common electrode is achieved for each sub-pixel region in the pixel unit region 120. In some embodiments, the common electrode pad 220 forms an ohmic contact with the first conductive semiconductor layer 111 in the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c through the conductive connection portion 270 and the lower reflective electrode, which can provide low series resistance electrical conduction for the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c, thereby achieving uniformity of series resistance.

[0449] The material of the common electrode pad 220 may include at least one of titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), silver (Ag), and tin (Sn), or an alloy of the above metals. This embodiment does not limit this.

[0450] In some embodiments, the fabrication method may further include: bonding a temporary carrier plate (not shown) to the first surface 101 side; and flipping the substrate 100. This bonds the substrate 100, having undergone the front-side process, to a temporary carrier plate for subsequent steps.

[0451] Next, referring to Figures 58 to 60, the fabrication method may further include: etching the substrate 100 from the second surface 102 side to form pixel trenches. The pixel trenches include a first pixel trench 130a, a second pixel trench 130b, and a third pixel trench 130c, each corresponding one-to-one with the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c. The remaining substrate 100 between the first pixel trench 130a and the third pixel trench 130c constitutes the first segment 160a of the isolation barrier 160, and the remaining substrate 100 between the second pixel trench 130b and the third pixel trench 130c constitutes the third segment 160a of the isolation barrier 160. The second sub-segment 160b; the remaining substrate 100 between the first pixel slot 130a and the second pixel slot 130b constitutes the third sub-segment 160c of the isolation barrier 160, one end of the third sub-segment 160c being connected to the first sub-segment 160a and the second sub-segment 160b; the pixel sub-channel 2310 includes a first channel portion 2301 extending from the first surface 101 of the substrate 100 into the interior of the substrate 100; in the thickness direction of the substrate 100, the projection of the first channel portion 2301 is located inside the projection of the isolation barrier 160, and the boundary of the projection of the first channel portion 2301 and the boundary of the projection of the isolation barrier 160 are spaced apart. Thus, the connection between the isolation barrier 160 and the light-emitting surface can be ensured, the light isolation function of the isolation barrier 160 can be guaranteed, and light leakage can be avoided. Understandably, the first channel portion 2301 is located within the isolation barrier 160. In some embodiments, the sidewall of the first channel portion 2301 is covered with a lower reflective electrode, which can work in conjunction with the isolation barrier 160 to further enhance optical isolation.

[0452] It should be noted that Figure 58 is a projection diagram of the pixel groove on the plane of the substrate provided in an optional specific embodiment; Figure 59 is a projection diagram of the pixel groove on the plane of the substrate provided in another optional specific embodiment; Figure 60 is a cross-sectional structural diagram of the pixel groove provided in the embodiment of this application, wherein (a) and (b) are cross-sectional structural diagrams along lines B1-B1' and B2-B2' in Figure 58, respectively, and (a) and (b) in Figure 60 can also be cross-sectional structural diagrams along lines C1-C1' and C2-C2' in Figure 59, respectively; (a) and (b) in Figure 60 correspond to (a) and (b) in Figure 55, respectively, and are structural schematic diagrams formed by further performing the preparation method on the basis of (a) and (b) in Figure 55.

[0453] It should be noted that for details regarding the first pixel slot 130a, the second pixel slot 130b, and the third pixel slot 130c, please refer to the relevant description in Embodiment 1, which will not be elaborated upon here.

[0454] In an optional embodiment, referring to Figures 58 and 61, the pixel slot further includes a second pixel slot extension 130b', extending from the second surface 102 of the substrate 100 toward the chip layer 400 and corresponding to the position of the dummy structure region 120d; the second pixel slot extension 130b' and the second pixel slot 130b are interconnected. It is understood that the interconnection between the second pixel slot extension 130b' and the second pixel slot 130b forms a through slot, extending the pixel slot filled with light conversion material to the area where the dummy structure region 120d is located, further increasing the pixel slot area corresponding to the second sub-pixel region 120b, which is beneficial for filling the light conversion material and reducing the blue light radiation intensity of the light conversion material, thereby improving the lifespan of the light conversion material.

[0455] It should be noted that Figures (a) and (b) in Figure 61 are schematic cross-sectional views along lines B3-B3' and B4-B4' in Figure 58, respectively; Figures (a) and (b) in Figure 61 correspond to Figures (a) and (b) in Figure 56, respectively, and are schematic structural views formed by further performing the preparation method based on Figures (a) and (b) in Figure 56.

[0456] In some specific embodiments, the depth of the second pixel groove extension 130b' along the thickness direction of the substrate 100 is consistent with the depth of the second pixel groove 130b.

[0457] Please refer to Figure 58. The isolation barrier 160 also includes a fourth sub-segment 160d, which is composed of a substrate 100 located between the second pixel groove extension 130b' and the first pixel groove 130a. The other end of the third sub-segment 160c is connected to the fourth sub-segment 160d.

[0458] In another alternative embodiment, referring to Figures 59 to 62, the portion of the substrate 100 corresponding to the position of the dummy structure region 120d is not etched.

[0459] It should be noted that Figures (a) and (b) in Figure 62 are schematic cross-sectional views along lines B3-B3' and B4-B4' in Figure 59, respectively; Figures (a) and (b) in Figure 62 correspond to Figures (a) and (b) in Figure 57, respectively, and are schematic structural views formed by further performing the preparation method based on Figures (a) and (b) in Figure 57.

[0460] Next, referring to Figures 63 to 65, the preparation method may further include: filling the first pixel slot 130a and the second pixel slot 130b with optical materials; wherein the optical material in the first pixel slot 130a includes a red light conversion material 150a, and the optical material in the second pixel slot 130b includes a green light conversion material 150b. In some specific embodiments, the red light conversion material 150a and the green light conversion material 150b may include phosphors or quantum dots. When phosphors and quantum dots are excited by external energy, they undergo electronic transitions and release energy in the form of light; and by adjusting the composition and size of the phosphors and quantum dots, the emission color can be controlled, thereby making each pixel slot emit light of different colors. Here, the light conversion material is also called a "color conversion material" or a "color conversion layer". It should be noted that this embodiment is not limited to filling the first pixel slot 130a with a red light conversion material and filling the second pixel slot 130b with a green light conversion material. Those skilled in the art can adjust the filled light conversion material according to the actual situation.

[0461] It should be noted that Figures (a) and (b) in Figure 63 correspond to Figures (a) and (b) in Figure 60, respectively, and are schematic diagrams of structures formed by further performing the preparation method based on Figures (a) and (b) in Figure 60; Figures (a) and (b) in Figure 64 correspond to Figures (a) and (b) in Figure 61, respectively, and are schematic diagrams of structures formed by further performing the preparation method based on Figures (a) and (b) in Figure 61; Figures (a) and (b) in Figure 65 correspond to Figures (a) and (b) in Figure 62, respectively, and are schematic diagrams of structures formed by further performing the preparation method based on Figures (a) and (b) in Figure 62.

[0462] In some embodiments, when both the red light conversion material 150a and the green light conversion material 150b comprise quantum dots, the optical materials located in the first pixel slot 130a and the second pixel slot 130b further include a light diffusion material 140. The light diffusion material 140 is located between the red light conversion material 150a and the chip layer 400, and also between the green light conversion material 150b and the chip layer 400. Here, the light diffusion material 140 is provided to facilitate uniform light irradiation of the quantum dots, thereby effectively reducing the light intensity at the center of the quantum dots, greatly improving the light stability of the quantum dots, and mitigating the situation where local quantum dots are prone to light quenching due to excessively high central light intensity, effectively extending the luminescence lifetime. The light diffusion material 140 is also referred to as a "light diffusion layer".

[0463] In some embodiments, the fabrication method may further include filling the third pixel slot 130c with optical material. Specifically, when the light emitted by the first sub-pixel area 120a, the second sub-pixel area 120b, and the third sub-pixel area 120c is blue light, the optical material located in the third pixel slot 130c includes a light-diffusing material 140; when the light emitted by the first sub-pixel area 120a, the second sub-pixel area 120b, and the third sub-pixel area 120c is ultraviolet light, the optical material located in the third pixel slot 130c may include a blue light conversion material and a light-diffusing material 140 located between the blue light conversion material and the chip layer 400.

[0464] In an optional specific embodiment, referring to FIG64, the preparation method may further include: filling the second pixel slot extension 130b' with optical material; wherein, the optical material in the second pixel slot extension 130b' includes green light conversion material 150b. The second pixel slot extension 130b' and the second pixel slot 130b are interconnected to form a through slot, so that the pixel slot filled with green light conversion material 150b extends to the area where the dummy structure area 120d is located, thereby further increasing the pixel slot area corresponding to the second sub-pixel area 120b, which is beneficial to the filling of green light conversion material 150b and the reduction of blue light radiation intensity of green light conversion material 150b, and improving the service life of green light conversion material 150b.

[0465] Furthermore, the optical material in the second pixel slot extension 130b' also includes a light diffusing material 140 located between the green light conversion material 150b and the chip layer 400. It is understood that when the active layer 112 of the dummy structure region 120d does not emit light, by providing the light diffusing material 140 at the bottom of the second pixel slot 130b and the second pixel slot extension 130b', the light emitted from the second sub-pixel region 120b can be diffused into the second pixel slot extension 130b', thereby causing the green sub-pixel to emit uniform green light.

[0466] Please continue referring to Figures 63 to 65. The fabrication method may further include: forming a filter layer covering the pixel slot on the second surface 102. The filter layer includes a first filter layer 170a and a second filter layer 170b. The first filter layer 170a covers the first pixel slot 130a, and the second filter layer 170b covers the second pixel slot 130b. Understandably, light conversion materials cannot completely absorb the light incident on the pixel unit. Adding a corresponding filter layer to the light conversion material absorbs the residual light, which helps to further improve the color purity of the light emitted by each sub-pixel area, allowing for more precise control of the displayed color. Furthermore, it helps to improve the blackness of the light-emitting structure, reducing reflection of ambient light and thus improving contrast.

[0467] In an optional specific embodiment, referring to FIG64, the preparation method may further include: forming a filter layer covering the pixel groove on the second surface 102, the filter layer including a first filter layer 170a and a second filter layer 170b, the first filter layer 170a covering the first pixel groove 130a, and the second filter layer 170b covering the second pixel groove 130b and the second pixel groove extension 130b'.

[0468] In some embodiments, the filter layer may further include a third filter layer 170c, which covers the third pixel slot 130c.

[0469] It should be noted that for details regarding the first filter layer 170a, the second filter layer 170b, and the third filter layer 170c, please refer to the relevant descriptions in Embodiment 1, which will not be elaborated upon here.

[0470] Next, the preparation method may further include: forming a protective capping layer 180, which covers the second surface 102 and the filter layer. It should be noted that, regarding the protective capping layer 180, please refer to the relevant description in Example 1, and will not be elaborated upon here.

[0471] Next, referring to Figures 66 and 67, perform step S805 to provide a welding substrate 700, on which welding electrodes are formed.

[0472] In some embodiments, the welding electrodes include a first electrode 710, a second electrode 720, and a third electrode 730. The welding substrate 700 includes a fifth surface 701 and a sixth surface 702 opposite to each other, and the first electrode 710, the second electrode 720, and the third electrode 730 are formed on the fifth surface 701 side of the welding substrate 700. Understandably, the first electrode 710 corresponds to a first electrode pad 210a, the second electrode 720 corresponds to a second electrode pad 210b, and the third electrode 730 corresponds to a third electrode pad 210c.

[0473] It should be noted that the plane on which the fifth surface 701 and the sixth surface 702 of the welding substrate 700 are located, or strictly speaking, the center plane in the thickness direction of the welding substrate 700, is defined as the plane on which the welding substrate is located.

[0474] In some embodiments, referring to Figures 66 and 68, the welding electrode further includes a common electrode 740. It is understood that the common electrode 740 on the welding substrate 700 corresponds to the common electrode pad 220 on the dummy structure region 120d.

[0475] It should be understood that Figure 66 only illustrates the case where the projected shapes of the first electrode 710, the second electrode 720, the third electrode 730, and the common electrode 740 on the plane of the welding substrate 700 are rectangular. This application does not exclude the possibility that the projected shapes of the first electrode 710, the second electrode 720, the third electrode 730, and the common electrode 740 on the plane of the substrate 100 may be trapezoidal, circular, triangular, or other suitable shapes; the projected shapes of the first electrode 710, the second electrode 720, the third electrode 730, and the common electrode 740 may be the same or different. This application does not impose specific limitations in this regard.

[0476] The preparation method further includes: setting a soldering material 800 on a soldering substrate 700. Specifically, the soldering material 800 can be set on each electrode on the soldering substrate 700. In the embodiments of this application, the soldering material 800 is specifically, for example, solder paste. It should be noted that Figures 67 and 68 only schematically show the positional relationship between the soldering material 800 and each electrode, and do not limit the shape of the soldering material 800.

[0477] Next, step S806 is performed, in which the electrode pads are welded to the corresponding welding electrodes using welding material 800; wherein, the pixel channel 2310 is used to contain the welding material 800 during the welding process.

[0478] In some embodiments, referring to FIG69, step S806 includes: welding the first electrode pad 210a, the second electrode pad 210b, and the third electrode pad 210c to the first electrode 710, the second electrode 720, and the third electrode 730 respectively using welding material 800; wherein, the pixel channel 2310 is used to accommodate the welding material 800 during the welding process. The area where the first electrode 710, the second electrode 720, and the third electrode 730 are located on the welding substrate 700 can be understood as the welding area. In actual fabrication, the first surface 101 and the fifth surface 701 are placed face to face, and after the first electrode pad 210a, the second electrode pad 210b, and the third electrode pad 210c are aligned one-to-one with the first electrode 710, the second electrode 720, and the third electrode 730, a certain force is applied so that each electrode pad contacts the welding material 800 on the welding substrate 700. During this process, a portion of the welding material 800 is squeezed out of the welding area. In related technologies, the escaping portions of the solder material 800 in the soldering area may come into contact, a phenomenon also known as "handshake," causing the device to short-circuit and fail. This embodiment of the application increases the space between each soldering area by providing a pixel sub-channel 2310 that extends from the side of the chip layer 400 away from the substrate 100, penetrates the chip layer 400, and extends into the interior of the substrate 100. This allows the escaping portions of the solder material 800 to accumulate towards the interior of the pixel sub-channel 2310, reducing the probability of the escaping portions of the solder material 800 coming into contact.

[0479] In some embodiments, referring to Figures 70 and 71, step S806 may further include: welding the common electrode pad 220 to the common electrode 740 with welding material 800; wherein the first virtual sub-channel 2320 and the second virtual sub-channel 2330 are used to accommodate the welding material 800 during the welding process.

[0480] It should be noted that Figures (a) and (b) in Figure 69 correspond to Figures (a) and (b) in Figure 63, respectively, and are schematic diagrams of structures formed by further performing the preparation method based on Figures (a) and (b) in Figure 63; Figures (a) and (b) in Figure 70 correspond to Figures (a) and (b) in Figure 64, respectively, and are schematic diagrams of structures formed by further performing the preparation method based on Figures (a) and (b) in Figure 64; Figures (a) and (b) in Figure 71 correspond to Figures (a) and (b) in Figure 65, respectively, and are schematic diagrams of structures formed by further performing the preparation method based on Figures (a) and (b) in Figure 65.

[0481] It should also be noted that, in order to clearly show that the virtual sub-channel 2310, the first virtual sub-channel 2320 and the second virtual sub-channel 2330 can accommodate the escaping portion of the welding material 800 during the welding process, Figures 69, 70 and 71 show the size of the escaping portion of the welding material 800 in an exaggerated manner.

[0482] Example 9

[0483] This application provides a light-emitting device. Please refer to Figure 69. The light-emitting device includes:

[0484] Substrate 100 includes a first surface 101 and a second surface 102 that are opposite to each other in the thickness direction;

[0485] Chip layer 400 is located on the first surface 101 side of substrate 100;

[0486] The isolation channel 230 divides the chip layer 400 into pixel unit regions 120, which include at least two sub-pixel regions. The isolation channel 230 includes a pixel sub-channel 2310 located between any two sub-pixel regions. The pixel sub-channel 2310 extends from the side of the chip layer 400 away from the substrate 100, penetrates the chip layer 400, and extends into the interior of the substrate 100.

[0487] Electrode pads are located on the side of each sub-pixel region away from the substrate 100;

[0488] A welding substrate 700 is located on the first surface 101 side, and welding electrodes are formed on the surface of the welding substrate 700 facing the chip layer 400. The electrode pads are welded to the welding electrodes respectively by welding material 800. The pixel channel 2310 is used to contain the welding material 800 during the welding process.

[0489] Therefore, by setting a pixel sub-channel 2310 between any two sub-pixel areas, extending from the side of the chip layer 400 away from the substrate 100, penetrating the chip layer 400 and extending into the interior of the substrate 100, the sub-pixel areas are isolated from each other, while the space between the sub-pixel areas is increased. The portion of the solder material that escapes during the soldering process can be accommodated by the pixel sub-channel 2310, avoiding contact between the portions of the solder material that escape at different locations, thereby reducing the probability of short-circuit failure of the device.

[0490] In some embodiments, referring to Figures 50, 66, and 69, the pixel unit region 120 includes a first sub-pixel region 120a, a second sub-pixel region 120b, and a third sub-pixel region 120c; the electrode pads include a first electrode pad 210a, a second electrode pad 210b, and a third electrode pad 210c, which are respectively located on the side of the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c away from the substrate 100; the welding electrodes include a first electrode 710, a second electrode 720, and a third electrode 730; the first electrode pad 210a, the second electrode pad 210b, and the third electrode pad 210c are respectively welded to the first electrode 710, the second electrode 720, and the third electrode 730 by welding material 800.

[0491] In some embodiments, referring to Figures 52, 58, and 69, the light-emitting device may further include: a pixel groove located within the substrate 100 and extending from the second surface 102 toward the first surface 101. The pixel groove includes a first pixel groove 130a, a second pixel groove 130b, and a third pixel groove 130c that correspond one-to-one with the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c. The substrate 100 between the first pixel groove 130a and the third pixel groove 130c forms a first segment 160a of the isolation barrier 160, and the substrate 100 between the second pixel groove 130b and the third pixel groove 130c forms a... The second segment 160b of the isolation barrier 160; the substrate 100 between the first pixel slot 130a and the second pixel slot 130b constitutes the third segment 160c of the isolation barrier 160, one end of the third segment 160c being connected to the first segment 160a and the second segment 160b; the pixel sub-channel 2310 includes a first channel portion 2301 extending from the first surface 101 of the substrate 100 into the interior of the substrate 100; in the thickness direction of the substrate 100, the projection of the first channel portion 2301 is located inside the projection of the isolation barrier 160, and the boundary of the projection of the first channel portion 2301 and the boundary of the projection of the isolation barrier 160 are spaced apart. Therefore, the connection between the isolation barrier 160 and the light-emitting surface can be ensured, the light isolation function of the isolation barrier 160 can be guaranteed, and light leakage can be avoided. Understandably, the first channel portion 2301 is located within the isolation barrier 160. In some embodiments, the sidewall of the first channel portion 2301 is covered with a lower reflective electrode, which can work in conjunction with the isolation barrier 160 to further enhance optical isolation.

[0492] In some embodiments, the pixel sub-channel 2310 may include a second channel portion 2302 extending from the side of the chip layer 400 away from the substrate 100 to a first surface 101 of the substrate 100, the first channel portion 2301 being in communication with the second channel portion 2302; in the thickness direction of the substrate 100, the projected area of ​​the second channel portion 2302 is larger than the projected area of ​​the first channel portion 2301. This increases the space of the pixel sub-channel 2310, allowing it to accommodate more solder material 800.

[0493] Further, referring to Figure 52, the bottom groove width d2 of the second channel portion 2302 is greater than or equal to 2μm, and the bottom end of the second channel portion 2302 is the end of the second channel portion 2302 that is closer to the second surface 102; and / or, the top groove width d1 of the first channel portion 2301 is greater than or equal to 15μm, and the top end of the first channel portion 2301 is the end of the first channel portion 2301 that is farther away from the second surface 102. Understandably, during the welding process, the escaping portion of the welding material 800 will laterally disperse at the top of the second channel portion 2302 and longitudinally accumulate from the top of the second channel portion 2302 to the bottom of the first channel portion 2301. By controlling the top groove width d2 of the second channel portion 2302 to be greater than or equal to 15μm, the path length of the lateral dispersion of the welding material 800 is increased. By controlling the bottom groove width d1 of the first channel portion 2301 to be greater than or equal to 2μm, contact is avoided after the welding material 800 accumulates longitudinally. Thus, contact can be more effectively avoided after the welding material 800 escapes from different positions.

[0494] In some embodiments, referring to FIG52, the pixel channel 2310 may include a first channel portion 2301 extending from the first surface 101 of the substrate 100 into the interior of the substrate 100; in the thickness direction of the substrate 100, the depth h1 of the first channel portion 2301 is greater than or equal to 2 μm. It is understood that the greater the depth of the first channel portion 2301, the greater the depth of the pixel channel 2310, and the larger the space. Therefore, during the soldering process, it can better accommodate the escaping portions of the solder material 800, more effectively prevent the escaping portions of the solder material 800 at different locations from contacting each other, and reduce the probability of device short-circuit failure.

[0495] Please refer to Figures 53, 54, 70 and 71. In some embodiments, the chip layer 400 includes a first conductive semiconductor layer 111, an active layer 112 and a second conductive semiconductor layer 113 sequentially stacked along a direction away from the substrate 100.

[0496] The pixel unit area 120 also includes a dummy structure area 120d. The first sub-pixel area 120a, the second sub-pixel area 120b and the third sub-pixel area 120c are distributed at different positions in the pixel unit area 120 and extend to the boundary of the pixel unit area 120 respectively. The dummy structure area 120d is located inside the pixel unit area 120 or at the boundary of the pixel unit area 120.

[0497] The isolation channel 230 also includes a first virtual sub-channel 2320 located between the first sub-pixel region 120a and the dummy structure region 120d, and a second virtual sub-channel 2330 located between the second sub-pixel region 120b and the dummy structure region 120d; both the first virtual sub-channel 2320 and the second virtual sub-channel 2330 include a first sub-section 2302-1, which extends from the side of the chip layer 400 away from the substrate 100 and penetrates the second conductive semiconductor layer 113 and the active layer 1. 12 extends into the interior of the first conductive semiconductor layer 111. The first virtual sub-channel 2320 also includes a second sub-section 2302-2 that communicates with the first sub-section 2302-1. The second sub-section 2302-2 extends from the bottom end of the first sub-section 2302-1 to the first surface 101 of the substrate 100. The bottom end of the first sub-section 2302-1 is the end of the first sub-section 2302-1 that is close to the second surface 102. The first sub-section 2302-1 and the second sub-section 2302-2 constitute the second channel portion 2302.

[0498] The electrode pads also include: a common electrode pad 220, located on the side of the dummy structure region 120d away from the substrate 100; a first electrode pad 210a, a second electrode pad 210b, and a third electrode pad 210c, which are electrically connected to the second conductive semiconductor layer 113 in the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c, respectively; and a common electrode pad 220, which is electrically connected to the first conductive semiconductor layer 111 in the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c.

[0499] The welding electrode also includes a common electrode 740; the common electrode pad 220 and the common electrode 740 are welded together by welding material 800; wherein, the first virtual sub-channel 2320 and the second virtual sub-channel 2330 are used to contain the welding material 800 during the welding process.

[0500] Therefore, the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c are distributed at different positions in the pixel unit region 120 and extend to the boundary of the pixel unit region 120. The dummy structure region 120d is located inside the pixel unit region 120 or at the boundary of the pixel unit region 120. The common electrode pad 220 on the dummy structure region 120d is electrically connected to the first conductive semiconductor layer 111 in the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c. In this way, a single pixel unit... Each sub-pixel region in the sub-region 120 shares an electrode, which can reduce the wiring arrangement and allow the chip composed of a single pixel unit region 120 to be independently controlled. This is beneficial for combining and splicing multiple chips to obtain a larger size light-emitting device. The virtual sub-channel between the sub-pixel region and the virtual structure region 120d not only isolates the sub-pixel region and the virtual structure region 120d, but also accommodates the escaping part of the welding material 800 during the welding process. This is more conducive to avoiding contact between the escaping parts of the welding material 800 at different positions, thereby reducing the probability of short-circuit failure of the device.

[0501] In an optional specific embodiment, referring to FIG53, both the first virtual sub-channel 2320 and the second virtual sub-channel 2330 include a first sub-section 2302-1. The first sub-section 2302-1 extends from the side of the chip layer 400 away from the substrate 100, penetrates the second conductive semiconductor layer 113 and the active layer 112, and extends into the interior of the first conductive semiconductor layer 111. The first virtual sub-channel 2320 also includes a second sub-section 2302-2 communicating with the first sub-section 2302-1. The second sub-section 2302-2 extends from the bottom end of the first sub-section 2302-1 to the first surface 101 of the substrate 100. The bottom end of the first sub-section 2302-1 is the end of the first sub-section 2302-1 close to the second surface 102. The first sub-section 2302-1 and the second sub-section 2302-2 constitute the second channel portion 2302.

[0502] In this embodiment, the first virtual sub-channel 2320 includes a second channel portion 2302. The first virtual sub-channel 2320 extends from the side of the chip layer 400 away from the substrate 100 and penetrates the second conductive semiconductor layer 113, the active layer 112 and the first conductive semiconductor layer 111. The dummy structure region 120d and the first sub-pixel region 120a are isolated from each other. The second virtual sub-channel 2330 extends from the side of the chip layer 400 away from the substrate 100 and penetrates the second conductive semiconductor layer 113 and the active layer 112, but does not penetrate the first conductive semiconductor layer 111. The epitaxial layers in the second sub-pixel region 120b and the dummy structure region 120d are not completely isolated. The first conductive semiconductor layer 111 in the dummy structure region 120d and the first conductive semiconductor layer 111 in the second sub-pixel region 120b are connected through the first conductive semiconductor layer 111 located at the second virtual sub-channel 2330. In other words, the first conductive semiconductor layer 111 in the dummy structure region 120d and the first conductive semiconductor layer 111 in the second sub-pixel region 120b are physically connected, which facilitates conductive connection.

[0503] In another optional embodiment, both the first virtual sub-channel 2320 and the second virtual sub-channel 2330 include a first sub-section 2302-1. The first sub-section 2302-1 extends from the side of the chip layer 400 away from the substrate 100, penetrates the second conductive semiconductor layer 113 and the active layer 112, and extends into the interior of the first conductive semiconductor layer 111. The first virtual sub-channel 2320 also includes a second sub-section 2302-2 communicating with the first sub-section 2302-1. The second sub-section 2302-2 extends from the bottom end of the first sub-section 2302-1 to the first surface 101 of the substrate 100. The bottom end of the first sub-part 2302-1 is the end of the first sub-part 2302-1 near the second surface 102. The first sub-part 2302-1 and the second sub-part 2302-2 constitute the second channel portion 2302. The first virtual sub-channel 2320 also includes the first channel portion 2301. And / or, the second virtual sub-channel 2330 also includes the second sub-part 2302-2 and the first channel portion 2301. The first channel portion 2301 extends from the first surface 101 of the substrate 100 into the interior of the substrate 100. The first channel portion 2301 is connected to the second channel portion 2302.

[0504] In this embodiment, the first virtual sub-channel 2320 extends from the side of the chip layer 400 away from the substrate 100, penetrates the chip layer 400, and extends into the interior of the substrate 100. The first virtual sub-channel 2320 includes a first channel portion 2301 and a second channel portion 2302. And / or, the second virtual sub-channel 2330 extends from the side of the chip layer 400 away from the substrate 100, penetrates the chip layer 400, and extends into the interior of the substrate 100. The second virtual sub-channel 2330 includes a first channel portion 2301 and a second channel portion 2302. This is more conducive to accommodating the escaped portion of the soldering material.

[0505] In some embodiments, the light-emitting device may further include: a cover layer covering the sidewalls and bottom wall of the isolation channel 230, but not filling the isolation channel 230, to form a receiving groove 290 in the isolation channel 230, the receiving groove 290 being used to receive welding material 800 during the welding process; in the thickness direction of the substrate 100, the bottom wall of the receiving groove 290 is located between the first surface 101 and the second surface 102 of the substrate 100. Therefore, the cover layer does not completely fill the isolation channel 230, allowing the isolation channel 230 to still accommodate the escaping portion of the welding material 800 during the welding process. Understandably, the bottom wall of the receiving groove 290 is located between the first surface 101 and the second surface 102 of the substrate 100. That is, the receiving groove 290 extends from the side of the chip layer 400 away from the substrate 100, penetrates the chip layer 400, and extends into the interior of the substrate 100. Even if a cover layer is formed in the isolation channel 230, a large space is still reserved between each sub-pixel unit, effectively preventing the escaping portions of the welding material 800 at different locations from contacting each other.

[0506] In some embodiments, referring to FIG69, the cover layer may include an insulating layer, including a first insulating portion 250a, a second insulating portion 250b, and a third insulating portion 250c; wherein, the first insulating portion 250a covers the sidewalls of the second conductive semiconductor layer 113 and the active layer 112 in the first sub-pixel region 120a and extends to cover a portion of the sidewalls of the first conductive semiconductor layer 111; the second insulating portion 250b covers the sidewalls of the second conductive semiconductor layer 113 and the active layer 112 in the second sub-pixel region 120b and extends to cover a portion of the sidewalls of the first conductive semiconductor layer 111; the third insulating portion 250c covers the sidewalls of the second conductive semiconductor layer 113 and the active layer 112 in the third sub-pixel region 120c and extends to cover a portion of the sidewalls of the first conductive semiconductor layer 111. The body layer 111 has a sidewall; a lower reflective electrode, including a first lower reflective electrode 260a, a second lower reflective electrode 260b, and a third lower reflective electrode 260c; wherein the first lower reflective electrode 260a covers the sidewall of the first sub-pixel region 120a not covered by the first insulating portion 250a and extends to the bottom wall of the pixel sub-channel 2310; the second lower reflective electrode 260b covers the sidewall of the second sub-pixel region 120b not covered by the second insulating portion 250b and extends to the bottom wall of the pixel sub-channel 2310; the third lower reflective electrode 260c covers the sidewall of the third sub-pixel region 120c not covered by the third insulating portion 250c and extends to the bottom wall of the pixel sub-channel 2310; and a conductive connection portion 270 covers the bottom wall of the pixel sub-channel 2310. Therefore, by using the lower reflective electrode and the insulating layer as optical isolation layers, optical isolation between each sub-pixel area can be achieved, and optical crosstalk between each sub-pixel can be prevented.

[0507] In some embodiments, the cover layer may further include a conductive connection portion 270 covering the bottom wall of the pixel sub-channel 2310, the conductive connection portion 270 being conductively connected to the lower reflective electrode.

[0508] In some embodiments, referring to Figures 70 and 71, the conductive connection portion 270 may also extend from the side of the dummy structure region 120d away from the substrate 100 along the sidewall of the dummy structure region 120d toward the second surface 102, covering the bottom walls of the first virtual sub-channel 2320 and the second virtual sub-channel 2330. Thus, the first conductive semiconductor layer 111 of each sub-pixel region is conductively connected to the second conductive semiconductor layer 113 of the dummy structure region 120d via the lower reflective electrode and the conductive connection portion 270.

[0509] In some embodiments, referring to FIG. 69, the light-emitting device may further include: a first upper reflective electrode 240a located on the side of the first sub-pixel region 120a away from the substrate 100, a first insulating portion 250a extending to cover a portion of the first upper reflective electrode 240a, and a first lower reflective electrode 260a extending onto the first insulating portion 250a, wherein the first upper reflective electrode 240a and the first lower reflective electrode 260a partially overlap in the thickness direction of the substrate 100; a second upper reflective electrode 240b located on the side of the second sub-pixel region 120b away from the substrate 100, and a second insulating portion 250b extending to cover a portion of the first upper reflective electrode 240a. The second upper reflective electrode 240b and the second lower reflective electrode 260b extend onto the second insulating portion 250b. In the thickness direction of the substrate 100, the second upper reflective electrode 240b and the second lower reflective electrode 260b partially overlap. The third upper reflective electrode 240c is located on the side of the third sub-pixel region 120c away from the substrate 100. The third insulating portion 250c extends to cover a portion of the third upper reflective electrode 240c, and the third lower reflective electrode 260c extends onto the third insulating portion 250c. In the thickness direction of the substrate 100, the third upper reflective electrode 240c and the third lower reflective electrode 260c partially overlap. The overlap of the upper and lower reflective electrodes in the vertical direction allows all the emitted light from the active layer 112 to be reflected to the light-emitting surface (the side of the first sub-pixel region 120a, the second sub-pixel region 120b, and the third sub-pixel region 120c closest to the substrate 100), preventing light leakage from the electrode pad side.

[0510] In some embodiments, referring to FIG69, the cover layer may further include an isolation layer 280 covering the reflective electrode and the conductive connection portion 270. The material of the isolation layer 280 includes, but is not limited to, silicon oxide, silicon nitride, etc.

[0511] In some embodiments, referring to Figures 69 to 70, the light-emitting device may further include: optical material filling the pixel slots; wherein the optical material in the first pixel slot 130a includes red light conversion material 150a, and the optical material in the second pixel slot 130b includes green light conversion material 150b.

[0512] In some embodiments, when both the red light conversion material 150a and the green light conversion material 150b include quantum dots, the optical materials located in the first pixel slot 130a and the second pixel slot 130b further include a light diffusion material 140, which is located between the red light conversion material 150a and the chip layer 400, and between the green light conversion material 150b and the chip layer 400.

[0513] In some embodiments, when the light emitted by the first sub-pixel area 120a, the second sub-pixel area 120b, and the third sub-pixel area 120c is blue light, the optical material located in the third pixel slot 130c includes a light-diffusing material 140; when the light emitted by the first sub-pixel area 120a, the second sub-pixel area 120b, and the third sub-pixel area 120c is ultraviolet light, the optical material located in the third pixel slot 130c may include a blue light conversion material and a light-diffusing material 140 located between the blue light conversion material and the chip layer 400.

[0514] Referring to Figures 69 and 70, the light-emitting device may further include: a filter layer located on the second surface side and covering the pixel slot. The filter layer includes a first filter layer 170a and a second filter layer 170b. The first filter layer 170a covers the first pixel slot 130a, and the second filter layer 170b covers the second pixel slot 130b. Understandably, light conversion materials cannot completely absorb all the light incident on the pixel unit. Adding a corresponding filter layer to the light conversion material absorbs residual light, which helps to further improve the color purity of the light emitted by each sub-pixel area, allowing for more precise control of the displayed color. Furthermore, it helps to improve the blackness of the light-emitting structure, reducing reflection of ambient light and thus improving contrast. Of course, in some embodiments, the filter layer also includes a third filter layer 170c, which covers the third pixel slot 130c.

[0515] In an optional embodiment, referring to Figures 61 and 70, the pixel slot further includes a second pixel slot extension 130b', extending from the second surface 102 of the substrate 100 toward the chip layer 400 and corresponding to the position of the dummy structure region 120d; the second pixel slot extension 130b' is interconnected with the second pixel slot 130b; the optical material in the second pixel slot extension 130b' includes a green light conversion material 150b; the second filter layer 170b covers the second pixel slot 130b and the second pixel slot extension 130b'. It is understood that the interconnection between the second pixel slot extension 130b' and the second pixel slot 130b forms a through slot, extending the pixel slot filled with the green light conversion material 150b to the area where the dummy structure region 120d is located, further increasing the pixel slot area corresponding to the second sub-pixel region 120b, which is beneficial for filling the green light conversion material 150b and reducing the blue light radiation intensity of the green light conversion material 150b, thereby improving the lifespan of the light conversion material.

[0516] Please refer to Figures 69 and 70. The light-emitting device may also include a protective capping layer 180 covering the second surface 102 and the filter layer. This can improve the structural strength of the light-emitting structure and effectively isolate the light conversion material, filter layer, and other structures from contact with the outside air.

[0517] It should be noted that the various embodiments provided in this application belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict. The above descriptions are merely embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of this application should be included within the scope of the claims of this application.

Claims

1. A light-emitting element, the light-emitting element comprising: The substrate includes a first surface and a second surface that are opposite to each other; An epitaxial layer, located on a first surface of the substrate, comprises a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer sequentially stacked along a direction away from the substrate; the epitaxial layer is patterned and divided into multiple pixel unit regions arranged in an array, each pixel unit region comprising a first sub-pixel region, a second sub-pixel region, a third sub-pixel region, and a dummy structure region; the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region are distributed at different positions in the pixel unit region and extend to the boundary of the pixel unit region respectively; the dummy structure region is located inside the pixel unit region or extends to the boundary of the pixel unit region. The first electrode pad, the second electrode pad, the third electrode pad, and the common electrode pad are located on the side of the first sub-pixel region, the second sub-pixel region, the third sub-pixel region, and the dummy structure region away from the substrate, respectively; the first electrode pad, the second electrode pad, and the third electrode pad are electrically connected to the second conductive semiconductor layer in the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region, respectively; the common electrode pad is electrically connected to the first conductive semiconductor layer in the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region.

2. The light-emitting element according to claim 1, wherein, The virtual structure region extends to the boundary of the pixel unit region; The projections of the first sub-pixel region, the second sub-pixel region, the third sub-pixel region, and the dummy structure region onto the plane of the substrate are respectively located at the four vertices of the first quadrilateral region.

3. The light-emitting element according to claim 2, wherein, The first sub-pixel area is the light-emitting area of ​​the red sub-pixel, the second sub-pixel area is the light-emitting area of ​​the green sub-pixel, and the third sub-pixel area is the light-emitting area of ​​the blue sub-pixel; The second sub-pixel region is arranged adjacent to the virtual structure region; The virtual structure area and the third sub-pixel area are arranged along the diagonal of the first quadrilateral area.

4. The light-emitting element according to any one of claims 1 to 3, wherein, The light-emitting element also includes: The first pixel slot, the second pixel slot, and the third pixel slot all extend from the second surface of the substrate toward the epitaxial layer, and correspond to the positions of the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region, respectively. Optical materials are located in the first pixel slot and the second pixel slot; wherein the optical material located in the first pixel slot includes a red light conversion material, and the optical material located in the second pixel slot includes a green light conversion material.

5. The light-emitting element according to claim 4, wherein, The light-emitting element also includes: The second pixel groove extension extends from the second surface of the substrate toward the epitaxial layer and corresponds to the position of the dummy structure region; the second pixel groove extension is interconnected with the second pixel groove, and the green light conversion material is also located in the second pixel groove extension.

6. The light-emitting element according to claim 5, wherein, The sum of the projected areas of the second pixel slot and the extension of the second pixel slot on the plane of the substrate is greater than the projected area of ​​the first pixel slot on the plane of the substrate.

7. The light-emitting element according to claim 4, wherein, On the plane where the substrate is located, the projected area of ​​the third pixel slot is smaller than the projected area of ​​the first pixel slot and smaller than the projected area of ​​the second pixel slot.

8. The light-emitting element according to claim 1, wherein, On the plane where the substrate is located, the projected area of ​​the third sub-pixel region is smaller than the projected area of ​​the first sub-pixel region and smaller than the projected area of ​​the second sub-pixel region; the projected area of ​​the dummy structure region is smaller than the projected area of ​​the first sub-pixel region and smaller than the projected area of ​​the second sub-pixel region.

9. The light-emitting element according to claim 4, wherein, The ratio of the maximum width of the first pixel slot along the first direction to the maximum width of the second pixel slot along the first direction is 0.4:0.6 to 0.6:0.4; the first direction is the direction of the line connecting the farthest ends of the first pixel slot and the second pixel slot relative to each other.

10. The light-emitting element according to claim 5, wherein, The projections of the first pixel slot, the second pixel slot, the extension of the second pixel slot, and the third pixel slot onto the plane of the substrate are located in the second quadrilateral region. The first pixel slot extends to the first and second sides of the second quadrilateral region, and the first and second sides intersect each other; The second pixel slot extends to the third and fourth sides of the second quadrilateral region, and the third and fourth sides intersect each other; The third pixel slot extends to the second side and the third side of the second quadrilateral region; the second pixel slot extension extends to the first side and the fourth side of the second quadrilateral region; Along the extension direction of the first side, the maximum width of the first pixel slot is greater than half the length of the first side; along the extension direction of the second side, the maximum width of the first pixel slot is greater than half the length of the second side; along the extension direction of the third side, the maximum width of the second pixel slot is greater than half the length of the third side; along the extension direction of the fourth side, the maximum width of the through slot formed by the interconnection between the extension portion of the second pixel slot and the second pixel slot is equal to the length of the fourth side.

11. The light-emitting element according to claim 5, wherein, The projection of the first pixel slot onto the plane of the substrate is composed of a first rectangle and a first right trapezoid, wherein the lower base of the first right trapezoid coincides with one side of the first rectangle; The projection of the through groove formed by the mutual penetration of the second pixel groove and the extension of the second pixel groove on the plane of the substrate is composed of a second rectangle, a third rectangle and a second right trapezoid, wherein the upper base and the lower base of the second right trapezoid coincide with one side of the second rectangle and the third rectangle respectively; The hypotenuse of the second right trapezoid is adjacent to and parallel to the hypotenuse of the first right trapezoid; The projection of the third pixel slot onto the plane of the substrate is rectangular.

12. The light-emitting element according to claim 5, wherein, The green light conversion material includes quantum dots; The optical material is located in the second pixel slot and the extension of the second pixel slot, and the optical material also includes a light diffusion material located between the green light conversion material and the epitaxial layer.

13. The light-emitting element according to claim 5, wherein, The light-emitting element also includes: An isolation barrier includes a first sub-segment, a second sub-segment, a third sub-segment, and a fourth sub-segment; wherein the first sub-segment is formed by a substrate located between the first pixel slot and the third pixel slot; the second sub-segment is formed by a substrate located between the second pixel slot and the third pixel slot; the third sub-segment is formed by a substrate located between the extension of the second pixel slot and the first pixel slot; one end of the third sub-segment is connected to the first sub-segment and the second sub-segment, and the other end of the third sub-segment is connected to the fourth sub-segment; the substrate is the growth substrate of the epitaxial layer.

14. The light-emitting element according to claim 13, wherein, The light-emitting element also includes: An isolation channel includes a first sub-channel, a second sub-channel, a third sub-channel, and a fourth sub-channel; wherein, the first sub-channel is located between the first sub-pixel area and the third sub-pixel area; the second sub-channel is located between the second sub-pixel area and the third sub-pixel area; the third sub-channel is located between the first sub-pixel area and the second sub-pixel area; the fourth sub-channel is located between the first sub-pixel area and the virtual structure area; one end of the third sub-channel connects the first sub-channel and the second sub-channel, and the other end of the third sub-channel connects the fourth sub-channel; On the plane where the substrate is located, the projected shapes of the first sub-segment, the second sub-segment, the third sub-segment, and the fourth sub-segment in the isolation barrier are consistent with the projected shapes of the first sub-channel, the second sub-channel, the third sub-channel, and the fourth sub-channel in the isolation channel, and the projections of the first sub-channel, the second sub-channel, the third sub-channel, and the fourth sub-channel fall within the projections of the first sub-segment, the second sub-segment, the third sub-segment, and the fourth sub-channel, respectively.

15. The light-emitting element according to claim 1, wherein, The light-emitting element also includes: The first pixel slot, the second pixel slot, and the third pixel slot all extend from the second surface of the substrate toward the epitaxial layer, and respectively correspond to the positions of the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region; wherein... On the plane where the substrate is located, the projections of the active layer in the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region fall into the projections of the first pixel slot, the second pixel slot, and the third pixel slot, respectively.

16. The light-emitting element according to claim 1, wherein, The light-emitting element also includes: The isolation channel includes a fifth sub-channel, which is located between the second sub-pixel region and the dummy structure region; the fifth sub-channel extends from the epitaxial layer toward the substrate through the second conductive semiconductor layer and the active layer, but does not extend through the first conductive semiconductor layer.

17. The light-emitting element according to claim 1, wherein, The light-emitting element also includes: A first upper reflective electrode, a second upper reflective electrode, and a third upper reflective electrode; the first upper reflective electrode is located between the second conductive semiconductor layer and the first electrode pad in the first sub-pixel region; the second upper reflective electrode is located between the second conductive semiconductor layer and the second electrode pad in the second sub-pixel region; the third upper reflective electrode is located between the second conductive semiconductor layer and the third electrode pad in the third sub-pixel region; An insulating layer includes a first insulating portion, a second insulating portion, and a third insulating portion; wherein the first insulating portion covers a portion of the sidewall of the first sub-pixel region and extends to the first upper reflective electrode; the second insulating portion covers a portion of the sidewall of the second sub-pixel region and extends to the second upper reflective electrode; and the third insulating portion covers a portion of the sidewall of the third sub-pixel region and extends to the third upper reflective electrode. A first lower reflective electrode, a second lower reflective electrode, and a third lower reflective electrode; the first lower reflective electrode covers the sidewall of the first sub-pixel region not covered by the first insulating portion and extends to the first insulating portion; the second lower reflective electrode covers the sidewall of the second sub-pixel region not covered by the second insulating portion and extends to the second insulating portion; the third lower reflective electrode covers the sidewall of the third sub-pixel region not covered by the third insulating portion and extends to the third insulating portion; wherein... In the substrate thickness direction, the first lower reflective electrode partially overlaps with the first upper reflective electrode, the second lower reflective electrode partially overlaps with the second upper reflective electrode, and the third lower reflective electrode partially overlaps with the third upper reflective electrode.

18. The light-emitting element according to claim 5, wherein, The light-emitting element also includes: The first filter layer, the second filter layer, and the third filter layer are all located on the second surface of the substrate; wherein, the first filter layer covers the first pixel groove, the second filter layer covers the second pixel groove and the extension of the second pixel groove, and the third filter layer covers the third pixel groove; A protective capping layer covers the first filter layer, the second filter layer, the third filter layer, and the second surface of the substrate.

19. The light-emitting element according to claim 1, wherein, The shortest distance between the pixel unit area and the boundary of the light-emitting element is half the distance between two adjacent pixel unit areas.

20. A light-emitting device comprising a plurality of seamlessly joined light-emitting elements as described in any one of claims 1 to 19.

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