Program processing method, compiler, system on chip, electronic device and storage medium

Abstract

Provided in the present disclosure are a program processing method, a compiler, a system on chip, an electronic device and a storage medium. The method comprises: when a program has been compiled by a compiler and starts to run, acquiring performance data of the program collected by a collection tool, wherein the program is composed of instruction sequences of a plurality of functions, and the collection tool is inserted into the program by the compiler during the process of compiling the program; on the basis of the performance data, determining at least one target symbol from a plurality of symbols included in the program; aligning the at least one target symbol with starting addresses of a plurality of cache lines of a processor, so as to determine a target cache line starting address corresponding to the at least one target symbol; and adjusting the spatial layout of the at least one target symbol in a memory, so as to determine a target spatial layout of the at least one target symbol in the memory. The present disclosure solves the technical problem in the relevant art of low execution efficiency of a program caused by the difficulty of a compiler in making rational adjustments to symbols.

Description

Program processing method, compiler, system on chip, electronic device and storage medium TECHNICAL FIELD

[0001] The present disclosure relates to the field of processors, and in particular, to a program processing method, a compiler, a system on chip, an electronic device and a storage medium. BACKGROUND

[0002] At present, the alignment strategy adopted by general compiler products is that the compiler performs static analysis plus a certain degree of symbol classification. Specifically, the symbols are generally classified into function addresses, loop start addresses and jump target addresses. Then, the compiler performs static analysis, for example, analyzes the number of loops, and sets a condition as a threshold. When the threshold is reached, alignment is selected. This alignment strategy is to balance the relationship between code size and performance. If multiple symbols can be aligned according to a certain sub-section, the program size will increase a lot. If multiple symbols are not aligned, the performance will be poor due to the branch predictor and other strategies of the processor architecture. Therefore, the symbol alignment strategy is a trade-off between code size and performance. The alignment strategy adopted by the general compiler products at present has a relatively coarse granularity of classification, and the static analysis has certain limitations, and the effect is not very good, resulting in low execution efficiency of the program.

[0003] At present, no effective solution has been proposed for the above problems. SUMMARY

[0004] Embodiments of the present disclosure provide a program processing method, a compiler, a system on chip, an electronic device and a storage medium to at least solve the technical problem that the compiler is difficult to reasonably adjust the symbols in the related art, thereby resulting in low execution efficiency of the program.

[0005] According to an aspect of an embodiment of the present disclosure, a program processing method is provided, applied to a compiler, including: in a case where a program is compiled by the compiler and starts to run, acquiring performance data of the program collected by a collection tool, wherein the program is composed of instruction sequences of multiple functions, and the collection tool is inserted into the program by the compiler in a process of compiling the program; determining at least one target symbol from multiple symbols included in the program based on the performance data, wherein different symbols are used to represent different functions or different variables in the program, and an access frequency of the at least one target symbol is greater than a preset frequency; aligning the at least one target symbol with start addresses of multiple cache lines of a processor to determine a target cache line start address corresponding to the at least one target symbol; and adjusting a spatial layout of the at least one target symbol in a memory to determine a target spatial layout of the at least one target symbol in the memory.

[0006] According to an aspect of some embodiments of the present disclosure, a program processing method is provided, applied to a compiler, including: in a case where a graphics processing program is compiled by the compiler and starts running, obtaining performance data of the graphics processing program collected by a collection tool, wherein the graphics processing program is composed of instruction sequences of a plurality of functions, and the collection tool is inserted into the graphics processing program by the compiler in a process of compiling the graphics processing program; determining at least one target symbol from a plurality of symbols included in the graphics processing program based on the performance data, wherein different symbols are used to represent different functions or different variables in the program, and the at least one target symbol is used to represent a graphics data structure and a rendering function; aligning the at least one target symbol with starting addresses of a plurality of cache lines of a processor to determine target cache line starting addresses corresponding to the at least one target symbol; and adjusting a spatial layout of the at least one target symbol in a memory to determine a target spatial layout of the at least one target symbol in the memory.

[0007] According to an aspect of some embodiments of the present disclosure, a program processing method is provided, applied to a compiler, including: in a case where a graphics processing program is compiled by the compiler and starts running, obtaining performance data of the graphics processing program collected by a collection tool, wherein the graphics processing program is composed of instruction sequences of a plurality of functions, and the collection tool is inserted into the graphics processing program by the compiler in a process of compiling the graphics processing program; determining at least one target symbol from a plurality of symbols included in the graphics processing program based on the performance data, wherein different symbols are used to represent different functions or different variables in the program, and the at least one target symbol is used to represent a graphics data structure and a rendering function; aligning the at least one target symbol with starting addresses of a plurality of cache lines of a processor to determine target cache line starting addresses corresponding to the at least one target symbol; and adjusting a spatial layout of the at least one target symbol in a memory to determine a target spatial layout of the at least one target symbol in the memory.

[0008] According to an aspect of some embodiments of the present disclosure, a program processing method is provided, applied to a compiler, including: in a case where a graphics processing program is compiled by the compiler and starts running, obtaining performance data of the graphics processing program collected by a collection tool, wherein the graphics processing program is composed of instruction sequences of a plurality of functions, and the collection tool is inserted into the graphics processing program by the compiler in a process of compiling the graphics processing program; determining at least one target symbol from a plurality of symbols included in the graphics processing program based on the performance data, wherein different symbols are used to represent different functions or different variables in the program, and the at least one target symbol is used to represent a graphics data structure and a rendering function; aligning the at least one target symbol with starting addresses of a plurality of cache lines of a processor to determine target cache line starting addresses corresponding to the at least one target symbol; and adjusting a spatial layout of the at least one target symbol in a memory to determine a target spatial layout of the at least one target symbol in the memory.

[0009] According to an aspect of embodiments of the present disclosure, there is provided a system on chip, comprising: the compiler in the above embodiments.

[0010] According to an aspect of embodiments of the present disclosure, there is provided an electronic device, comprising: a memory storing an executable program; and a processor configured to execute the program, wherein the program, when executed, performs the method in any of the above embodiments.

[0011] According to another aspect of embodiments of the present disclosure, there is also provided a computer terminal, comprising: a memory storing an executable program; and a processor configured to execute the program, wherein the program, when executed, performs the method in any of the above embodiments.

[0012] According to another aspect of embodiments of the present disclosure, there is also provided a computer-readable storage medium, comprising a stored executable program, wherein the executable program, when executed, controls a device in which the computer-readable storage medium is located to perform the method in any of the above embodiments.

[0013] According to another aspect of embodiments of the present disclosure, there is also provided a computer program product, comprising a computer program which, when executed by a processor, implements the method in any of the above embodiments.

[0014] According to another aspect of embodiments of the present disclosure, there is also provided a computer program product, comprising a non-volatile computer-readable storage medium storing a computer program which, when executed by a processor, implements the method in any of the above embodiments.

[0015] According to another aspect of embodiments of the present disclosure, there is also provided a computer program which, when executed by a processor, implements the method in any of the above embodiments.

[0016] In the embodiments of the present disclosure, in a case where a program is compiled by a compiler and starts to run, performance data of the program collected by a collection tool is acquired, the program is composed of instruction sequences of a plurality of functions, and the collection tool is inserted into the program by the compiler during compilation of the program; at least one target symbol is determined from a plurality of symbols included in the program based on the performance data, different symbols are used to represent different functions or different variables in the program, and an access frequency of the at least one target symbol is greater than a preset frequency; the at least one target symbol is aligned with starting addresses of a plurality of cache lines of a processor to determine a target cache line starting address corresponding to the at least one target symbol; and a spatial layout of the at least one target symbol in a memory is adjusted to determine a target spatial layout of the at least one target symbol in the memory, so as to achieve the purpose of improving the execution efficiency of the program. It is easy to note that the at least one target symbol with a high access frequency and high importance can be determined through the performance data of the program collected by the collection tool, the number of symbols that need to be subjected to the alignment operation can be reduced through the screening of the plurality of symbols, the at least one target symbol is aligned with the starting addresses of the plurality of cache lines to reduce the conflict of the cache lines, and the access delay of the program is reduced through the adjustment of the spatial layout of the at least one target symbol in the memory, so as to realize the improvement of the program, and thus the technical problem that the compiler is difficult to reasonably adjust the symbols in the related art, thereby causing the low execution efficiency of the program is solved.

[0017] It is easy to note that the above general description and the following detailed description are only for exemplifying and explaining the present disclosure, and do not constitute a limitation on the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings described herein are used to provide further understanding of the present disclosure, constitute a part of the present disclosure, and the illustrative embodiments of the present disclosure and the description thereof are used to explain the present disclosure, and do not constitute an improper limitation on the present disclosure. In the drawings:

[0019] FIG. 1 is a hardware structure block diagram of a RISC-V system for implementing a program processing method according to an embodiment of the present disclosure;

[0020] FIG. 2 is a schematic diagram of a system on chip according to an embodiment 2 of the present disclosure;

[0021] FIG. 3 is a flowchart of a program processing method according to an embodiment 1 of the present disclosure;

[0022] FIG. 4 is a flowchart of a program processing method according to an embodiment of the present disclosure;

[0023] FIG. 5 is a flowchart of a program processing method according to an embodiment 3 of the present disclosure;

[0024] FIG. 6 is a schematic diagram of a compiler according to Embodiment 4 of the present disclosure;

[0025] FIG. 7 is a schematic diagram of a program processing device according to Embodiment 6 of the present disclosure;

[0026] FIG. 8 is a schematic diagram of a program processing device according to Embodiment 7 of the present disclosure;

[0027] FIG. 9 is a schematic diagram of a program processing device according to Embodiment 8 of the present disclosure;

[0028] FIG. 10 is a structural block diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to make the person skilled in the art better understand the present disclosure scheme, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor should be within the scope of protection of the present disclosure.

[0030] It should be noted that the terms "first", "second" and the like in the specification and claims of the present disclosure and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0031] First, some of the nouns or terms that appear in the description of the embodiments of the present disclosure are applicable to the following explanations:

[0032] Program performance improvement: refers to the process of improving program running efficiency by various methods, including improving algorithm, code structure, data structure, etc.

[0033] Symbol alignment scheme: a technique for improving code readability and maintainability by adjusting the position and spacing of symbols to make the code more beautiful and easy to read.

[0034] Profile-Guided Optimization (PGO): A technique for improving program performance by analyzing the execution trace of the program to find performance bottlenecks and make improvements.

[0035] Memory distribution: Refers to the distribution of space allocated by the program in memory, including static memory allocation and dynamic memory allocation, etc.

[0036] Execution efficiency: Refers to the speed of completing tasks in a unit of time.

[0037] Hot symbol: Refers to a symbol in the program that is frequently accessed, which is often a key factor in execution efficiency.

[0038] Cache line conflict: Refers to the situation that multiple threads access the cache at the same time, which may cause cache line conflict and affect the execution efficiency of the program.

[0039] Branch predictor: A method for predicting the execution path of a program, which can improve the execution efficiency and response speed of the program.

[0040] Memory address allocation: Refers to the process of allocating space in memory by the program, including static memory allocation and dynamic memory allocation, etc.

[0041] The current compiler performs static analysis to align the start address of the innermost loop. This method can cover the hot spots of the program to some extent to improve the performance of the program. However, the current compiler has the following two shortcomings. First, the start address of the innermost loop cannot cover all hot code blocks of the program. If the outer loop is also a hot code, or some branch jumps are also hot codes, these hot codes will be difficult to align by this method. Second, there may be many innermost loops in the program, which will cause the program size to expand to some extent.

[0042] PGO is a compile-time improvement technique that can collect runtime data of the program to guide the compiler to make more refined improvements. The symbol alignment method proposed in this disclosure combines the advantages of PGO technology, and achieves more effective symbol alignment by analyzing the runtime data of the program. The symbol alignment is accurately performed without excessive code size expansion, thereby improving the performance of the application program.

[0043] Embodiment 1

[0044] According to an embodiment of the present disclosure, a program processing method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described herein can be executed in an order different from that shown herein.

[0045] The method embodiment provided by the embodiment of the present disclosure can be executed in a RISC-V system, a RISC-V chip or the like. FIG. 1 is a hardware structure block diagram of a RISC-V system for implementing a program processing method according to an embodiment of the present disclosure. As shown in FIG. 1, the RISC-V system 100 can be divided into a reduced instruction set architecture 101 (including a basic instruction set 101-1 and an extended instruction set 101-2), a hardware layer 102 (including a processor 102-1, peripheral hardware circuits 102-2, etc.), an interface layer 103, an operating system layer 104 (supporting multiple operating systems 104-1, 104-2, …, 104-n, such as Linux, FreeSBD, RT-Tread, etc.), a middleware and library layer 105 (including system libraries 105-1, APIs 105-2 and middleware services 105-3) and an application program layer 106 (including multiple user programs and services 106-1, 106-2, …, 106-n) from bottom to top. The RISC-V system 100 further includes a tool chain 107 between the bottom hardware and the application program layer, which can include a compiler and assembler 107-1, a linker 107-2, a debugger 107-3, a simulator and emulator 107-4, an integrated development environment 107-5, a hardware description language tool 107-6, a performance analysis tool 107-7 and a version control system 107-8, etc.

[0046] The instruction set architecture 101 defines the basic operations and instruction sets supported by the processor 102-1, including the basic instruction set and the extended instruction set, wherein the basic instruction set represents the basic integer instruction set, such as RV32I and RV64I, and the extended instruction set can be floating point, atomic operation, compression instruction, etc.

[0047] The interface layer 103 includes the specific design of the processor, such as pipeline design, cache structure, execution unit, branch prediction, etc. This layer is the process of mapping abstract instructions to physical hardware.

[0048] The operating system layer 104 is located at the hardware intelligence, providing a hardware abstraction layer and management mechanism, so that the application can interact with the hardware through system calls. The operating system is responsible for managing processor resources, memory, device drivers, task scheduling, etc.

[0049] The middleware and library layer 105 provides a set of rich services and interfaces to help applications run more efficiently. For example, the standard library provides file operations, mathematical calculations and other functions, while the middleware can provide network communication, graphical user interface and other complex services.

[0050] The application program layer 106 utilizes the functions and services provided by the lower layers to implement specific application logic, which can be command-line tools, graphical interface applications, server-side services, etc.

[0051] The toolchain 107 is a key component that connects the underlying hardware to the upper software. Various tools in the toolchain 107 play a role at different levels to support the entire process from hardware design to software development, ensuring the coherence and effectiveness of the entire system design.

[0052] It should be noted that the hierarchical design of the RISC-V architecture allows decoupling between different levels, so that each layer can be developed and improved independently.

[0053] In an optional embodiment, Figure 2 shows a schematic diagram of a System On Chip (SOC) using the RISC-V architecture shown in Figure 1 described above, Figure 2 is a schematic diagram of a System On Chip according to an embodiment of the present disclosure. As shown in Figure 2, the SOC internally contains at least one RISC-V core 202 (only one is shown in the figure), which is connected to peripheral devices through a bus 204, including but not limited to ROM 206, RAM 208, timer 210, UART (Universal Asynchronous Receiver / Transmitter) 212, GPIO (General Purpose Input / Output) 214, SPI (Serial Peripheral Interface Bus) 216, etc.

[0054] Under the above operating environment, the present disclosure provides a program processing method as shown in Figure 3. Figure 3 is a flowchart of a program processing method according to Embodiment 1 of the present disclosure. As shown in Figure 3, the method comprises:

[0055] Step S302, in the case where the program is compiled by the compiler and starts to run, obtaining the performance data of the program collected by the collection tool;

[0056] Wherein, the program is composed of a plurality of instruction sequences of functions, and the collection tool is inserted into the program by the compiler during the compilation of the program.

[0057] The performance data described above can come from a variety of tools, such as a Profiler, Emulation or actual runtime performance monitoring. These tools can provide detailed information about program execution, including the number of executions of multiple symbols and the number of instructions of multiple basic blocks.

[0058] In the case where the program is compiled by the compiler and starts running, obtaining the performance data of the program collected by the collection tool usually involves the following steps:

[0059] The compiler described above can be a program that converts source code into executable programs, and can convert source code written in a high-level language into machine language or intermediate code.

[0060] The collection tool described above can be a performance analysis tool or a performance monitoring tool, which can collect performance data during program execution. Among them, the collection tool can be a PGO tool, which is a compile-time improvement method that can guide the compiler to make more refined improvements by collecting program runtime data.

[0061] The collection tool described above can be inserted into the program by the compiler during compilation, so as to collect performance-related information such as processor usage, memory usage, function call frequency, etc. during program execution. Among them, the collection tool includes but is not limited to performance analysis tools, debuggers, code coverage tools, etc. The specific type of collection tool is not limited here, and the appropriate collection tool can be selected according to actual needs.

[0062] In programming, a function is a block of code that performs a specific task. A program is usually composed of multiple functions, and different functions can contain a series of instructions. These instruction sequences are commands that can be executed by a computer, and the instruction sequences define the logic and behavior of the program. When the program is compiled, the instruction sequences of these functions will be converted into machine language, and the computer can execute the program according to these instruction sequences.

[0063] In the process of compiling the program by the compiler and starting to run, when the program runs to the collection tool, the collection tool can collect performance data during program execution, so as to understand the running status of the program through the performance data, analyze hot symbols, and improve the performance of the program by adjusting the hot symbols.

[0064] Step S304, determining at least one target symbol from a plurality of symbols included in the program based on the performance data;

[0065] Among them, different symbols are used to represent different functions or different variables in the program, and the access frequency of the at least one target symbol is greater than the preset frequency.

[0066] The performance data described above refers to data about resource utilization and execution efficiency generated during the running of the program, such as memory usage, processor usage, response time, etc.

[0067] The plurality of symbols included in the program refer to the names of different functions or variables used in the program. These symbols can represent different functional modules or data storage units in the program.

[0068] The access frequency of the symbol refers to the number of times the symbol is accessed during the running of the program. For example, the number of times a function is called or the number of times a variable is read and written.

[0069] In an optional embodiment, when determining the target symbol based on the performance data, the performance data of the program can be analyzed to find target symbols with an access frequency greater than a preset frequency. These target symbols can be hot spots in the program, representing critical execution paths or frequently accessed data of the program. Aligning or adjusting the spatial layout of these symbols can improve the overall performance of the program.

[0070] In step S306, at least one target symbol is aligned with the starting addresses of the plurality of cache lines of the processor to determine a target cache line starting address corresponding to the at least one target symbol.

[0071] The target symbol can be assigned a memory address, and at least one target symbol is aligned with the starting addresses of the plurality of cache lines of the processor to obtain a target cache line starting address corresponding to the at least one target symbol, thereby reducing cache line conflicts and improving the performance of the program.

[0072] In the plurality of cache lines of the processor, the size of each cache line is usually fixed, such as 64 bytes. In order to improve the utilization efficiency of the cache, we want to align the address of the target symbol with the starting address of the cache line, so that the space of the cache line can be used to the maximum extent, and the number of cache misses can be reduced.

[0073] The plurality of cache lines of the processor are used to store data and instructions to improve data access speed and performance. The cache line is a cache storage unit in the processor, usually containing a plurality of consecutive memory addresses. The plurality of cache lines of the processor can store multiple data blocks at the same time, so that the required data can be accessed faster when the processor executes instructions. This design can effectively reduce the delay of memory access and improve the running efficiency and performance of the processor.

[0074] In an optional embodiment, the address corresponding to the target symbol can be obtained, and then the address of the target symbol is aligned with the starting address of the cache line. The specific steps of the alignment can be to divide the address of the target symbol by the size of the cache line, take the integer part, and then multiply the size of the cache line to obtain the target cache line starting address corresponding to the target symbol. At least one target symbol can also be aligned with the starting addresses of the plurality of cache lines of the processor in other ways, which are not limited here.

[0075] By aligning the target symbols, the cache hit rate can be improved, and the number of cache invalidations can be reduced, thereby improving the execution efficiency of the program. If the target symbol is aligned with the starting address of the cache line, when accessing data near the target symbol, it is likely that the data is already in the cache and can be obtained directly without reading from the main memory, thereby speeding up the execution of the program.

[0076] In step S308, the spatial layout of at least one target symbol in memory is adjusted to determine the target spatial layout of at least one target symbol in memory.

[0077] In an optional embodiment, the spatial layout of at least one target symbol in memory can be adjusted by adjusting the storage location and allocating space for the target symbol. For example, the storage location of the target symbol can be moved from one location in the heap to another location, or from the stack to the heap. In this way, the storage space of the target symbol in memory can be reallocated, thereby achieving the adjustment of the target spatial layout.

[0078] The spatial layout of the target symbol in memory refers to the allocation and arrangement of variables, functions and other symbols in the program in memory. This includes the address, size, alignment and layout relationship between symbols in memory. During program compilation, the spatial layout of the target symbol is determined and managed by the compiler, taking into account the memory structure and alignment rules of the target platform, to ensure that the program can correctly access and manipulate the memory space of each symbol during runtime.

[0079] By adjusting the spatial layout of at least one target symbol in memory, memory utilization can be improved, and by reallocating the storage space of the target symbol, memory resources can be more effectively utilized, memory fragmentation can be reduced, and memory utilization can be improved. Storing the target symbol closer to the processor can reduce memory access time and improve program execution efficiency. Adjusting the spatial layout of the target symbol can improve memory allocation strategies, making the memory management of the program more efficient and reducing the risk of memory leaks and memory overflow.

[0080] In an optional embodiment, a program that can read code and mark program hot code blocks can be trained by deep learning. The compiler can determine whether a symbol is the starting address of a hot code block by marking, and if so, the symbol needs to be aligned with the starting address.

[0081] The accuracy of the hot spot of program execution obtained by PGO or deep learning is high, the target symbol of the hot spot can be aligned or the spatial layout of the target symbol of the hot spot can be adjusted to improve the accuracy of the target symbol, thereby effectively improving the execution efficiency of the program. In addition, the alignment operation or spatial layout adjustment can not be performed on the other symbols in the plurality of symbols except the target symbol, thereby effectively avoiding the problem of program size expansion. The other symbols in the plurality of targets except the target symbol can be inner loops, but not the symbols of the program execution hot spot. The alignment operation or spatial layout adjustment can not be performed on these symbols.

[0082] In the case that the program is compiled by the compiler and starts to run, the performance data of the program collected by the collection tool is obtained, wherein the program is composed of instruction sequences of a plurality of functions, and the collection tool is inserted into the program by the compiler during the compilation of the program. At least one target symbol is determined from a plurality of symbols included in the program based on the performance data, wherein different symbols are used to represent different functions or different variables in the program, and the access frequency of the at least one target symbol is greater than a preset frequency. The at least one target symbol is aligned with the starting addresses of a plurality of cache lines of the processor to determine the target cache line starting address corresponding to the at least one target symbol. The spatial layout of the at least one target symbol in the memory is adjusted to determine the target spatial layout of the at least one target symbol in the memory, thereby achieving the purpose of improving the execution efficiency of the program. It is easy to note that the at least one target symbol with high access frequency and high importance can be determined by the performance data of the program collected by the collection tool. The number of symbols that need to perform the alignment operation can be reduced by screening the plurality of symbols. The at least one target symbol is aligned with the starting addresses of the plurality of cache lines to reduce the cache line conflict. The access delay of the program is reduced by adjusting the spatial layout of the at least one target symbol in the memory, thereby improving the program, and thereby solving the technical problem that the compiler in the related art is difficult to reasonably adjust the symbol, thereby resulting in low execution efficiency of the program.

[0083] In the above embodiment of the present disclosure, determining at least one target symbol from a plurality of symbols included in the program based on the performance data comprises: determining the access frequencies of the plurality of symbols based on the performance data; sorting the plurality of symbols based on the access frequencies of the plurality of symbols to obtain a sorted symbol sequence; and determining a preset number of symbols at the front of the sorted symbol sequence as the at least one target symbol.

[0084] The access frequency is used to reflect the use of the symbol in the program. The higher the access frequency, the higher the importance of the symbol in the program.

[0085] The preset number can be determined according to actual conditions, and the preset number is not limited herein.

[0086] In an optional embodiment, the access frequencies of the plurality of symbols can be determined according to performance data of the program during running, for example, the number of function calls, running time, etc., the symbols in the program can be sorted according to the access frequencies to obtain a symbol sequence arranged from high to low according to the access frequencies, the symbol sequence can help the user understand the importance and use of each symbol in the program, and a preset number of symbols ranked in the front in the sorted symbol sequence, that is, the at least one target symbol, can be determined, in the sorted symbol sequence, a preset number of symbols with relatively high access frequencies are selected as target symbols, these target symbols have relatively high importance and use frequency in the program, and can be the focus of further improvement and analysis.

[0087] By analyzing the access frequencies of the plurality of symbols, the performance bottleneck and hot area in the program can be found out, so that the program can be improved in a targeted manner to improve the overall performance of the program, the use of each symbol in the program can be understood through code maintenance and reconstruction, which is helpful for code maintenance and reconstruction, and the symbols with relatively high access frequencies can be given priority or the key symbols are retained when the code is improved.

[0088] The symbol alignment strategy can be that the PGO tool is used to collect performance data of the program during running, the access frequencies of the plurality of symbols can be calculated according to the performance data, the symbols ranked in the front can be selected as hot symbols, that is, target symbols, an alignment algorithm is used to determine the cache line start addresses corresponding to the plurality of hot symbols, and a space layout algorithm is used to improve the space layout of the symbols in the memory, and the improved symbol alignment scheme can be applied to the program.

[0089] The symbol alignment strategy described above can be applied to different types of programs, and the strategy can be applied to high-performance programs. For example, for a graphics processing program, the target symbols can be graphics data structures and rendering functions, and the distribution of these symbols in the memory can be improved through the symbol alignment strategy, so as to improve the execution efficiency of the program.

[0090] In the above embodiments of the present disclosure, the aligning the at least one target symbol with the start addresses of the plurality of cache lines of the processor, and determining the target cache line start address corresponding to the at least one target symbol comprises: determining the execution times of any one symbol in the plurality of symbols based on the performance data; obtaining the number of instructions contained in the plurality of basic blocks in the program, wherein any one function in the program is composed of instructions contained in at least one basic block; performing instruction extraction on the program based on the execution times of any one symbol and the number of instructions contained in the plurality of basic blocks, and determining the target instruction sequence corresponding to the at least one target symbol; and aligning the target instruction sequence according to the size of the plurality of cache lines, and determining the target cache line start address corresponding to the at least one target symbol.

[0091] The execution times can be the execution times of any one symbol in the plurality of symbols. By counting the execution times, the activity of each symbol in the program can be understood.

[0092] The number of instructions is the total number of instructions contained in the plurality of basic blocks in the program. The basic block can be a group of continuous instruction sequences in the program. By obtaining the number of instructions contained in the plurality of basic blocks in the program, the complexity and execution path of the program can be understood by the developer, and the program can be improved and debugged. The basic block has the characteristics of no entry or exit point, and a basic block usually contains only sequentially executed instructions except the head and tail.

[0093] The execution times and the number of instructions are important measures of the performance and structure of the program, which can help the user to deeply understand the running of the program, and thus improve the program.

[0094] In an optional embodiment, the execution times of any one symbol in the plurality of symbols can be obtained by analyzing the performance data, so as to determine the importance of any one symbol in the program. The number of instructions contained in the plurality of basic blocks in the program can be obtained, and the execution frequency of the execution sequence corresponding to the plurality of basic blocks can be determined by the number of instructions, so as to determine the target instruction sequence corresponding to the at least one target symbol. It should be noted that the target instruction sequence is a function corresponding to the at least one target symbol, and the function can be aligned according to the size of the plurality of cache lines in the program, so as to determine the target cache line start address corresponding to the at least one target symbol. The target cache line start address corresponding to the target symbol can be determined according to the position of the target symbol in the target instruction sequence and the size of the plurality of cache lines, so as to ensure that the target instruction sequence in which the at least one target symbol is located can be completely loaded into the cache line, and the performance loss caused by cross-cache line access can be avoided.

[0095] The connection between the function and the basic block is that the basic blocks inside the function form the logical structure of the function. A basic block is a continuous piece of code without branch or jump statements, and it is the smallest execution unit of a program. A function is a logical unit that contains a series of basic blocks and can be called and executed. The execution order and control flow of the basic blocks form the execution logic of the function, and the basic blocks inside the function are connected to each other through jump and branch statements, forming the execution path of the function. Therefore, the function and the basic block are closely related, and the execution order of the basic block determines the execution logic of the function.

[0096] In the above embodiment of the present disclosure, based on the execution frequency of any one symbol and the number of instructions contained in the plurality of basic blocks, the instructions of the program are extracted to determine the target instruction sequence corresponding to the at least one target symbol, comprising: determining the dynamic execution instruction quantity of any one function based on the execution frequency of any one symbol and the number of instructions contained in the plurality of basic blocks; based on the dynamic execution instruction quantity of any one function, extracting the instruction sequence that satisfies the preset condition from the instruction sequence of the plurality of functions to obtain the target instruction sequence corresponding to the at least one target symbol.

[0097] The dynamic execution instruction quantity mentioned above refers to the number of instructions actually executed by the program during runtime. During the execution of a computer program, different functions will contain different numbers of instructions, and the execution frequency of different functions will also vary. Therefore, to determine the dynamic execution instruction quantity of any one function, the number of times the function is called and the total number of instructions contained in the function need to be considered.

[0098] For the instruction sequence of the plurality of functions, the number of times different functions are called and the dynamic execution instruction quantity of different functions can be determined by collecting data during program runtime. By analyzing the dynamic execution instruction quantity, the instruction sequence corresponding to the dynamic execution instruction quantity that meets the preset condition can be determined as the target instruction sequence.

[0099] The preset condition mentioned above can be greater than a preset threshold or the number of orders is a preset percentage. Here, the preset condition is not limited, and the preset condition can be adjusted according to the actual application scenario.

[0100] In program improvement and performance analysis, a basic block is an important concept. By dividing the program into basic blocks, the compiler and performance analysis tool can more easily understand and analyze the execution behavior of the program, thereby making more effective improvements and analysis. By calculating the execution frequency of each symbol as described above, it can be determined which symbols are hot symbols, so that the program can be improved accordingly.

[0101] In the above embodiment of the present disclosure, the dynamic execution instruction quantity of the arbitrary function is determined based on the execution quantity of the arbitrary symbol and the instruction quantity contained in the plurality of basic blocks, comprising: determining the dynamic execution instruction quantity of the arbitrary basic block based on the execution quantity of the arbitrary symbol and the instruction quantity contained in the arbitrary basic block; and aggregating the dynamic execution instruction quantities of the at least one basic block corresponding to the arbitrary function to determine the dynamic execution instruction quantity of the arbitrary function.

[0102] The above basic block refers to a continuous code segment in a program without branching or jump statements. The dynamic execution instruction quantity refers to the actual execution instruction quantity of the program at runtime.

[0103] The above aggregation of the dynamic execution instruction quantities of the at least one basic block corresponding to the arbitrary function can add the dynamic execution instruction quantities of the at least one basic block corresponding to the arbitrary function to obtain the dynamic execution instruction quantity of the arbitrary function. By aggregating the dynamic execution instruction quantities of the at least one basic block corresponding to the arbitrary function, the performance and efficiency of the function can be determined, and the actual execution of the code can be understood, thereby providing relevant references for performance improvement and code improvement.

[0104] In an optional embodiment, the execution quantity can be recorded by inserting a counter in the basic block. The counter is incremented by one each time the program executes to a basic block, so that the execution quantities of the plurality of basic blocks can be obtained. The instruction quantity contained in the plurality of basic blocks can be determined by static analysis or instruction-level tracking at runtime. The dynamic execution instruction quantity of the plurality of basic blocks can be obtained by multiplying the execution quantities of the plurality of basic blocks by the instruction quantity contained in the plurality of basic blocks. The dynamic execution instruction quantities of the plurality of basic blocks in the same function can be added to obtain the dynamic execution instruction quantity of the function.

[0105] In the above embodiment of the present disclosure, the target instruction sequence corresponding to the at least one target symbol is obtained by extracting the instruction sequence satisfying the preset condition from the instruction sequences of the plurality of functions based on the dynamic execution instruction quantity of the arbitrary function, comprising: extracting the instruction sequence of a first function from the instruction sequences of the plurality of functions based on the dynamic execution instruction quantity of the arbitrary function, wherein the dynamic execution instruction quantity of the first function is greater than that of other functions in the plurality of functions except the first function, and the proportion of the first function in the plurality of functions is a first preset proportion; and extracting the instruction sequence of a second function from the instruction sequence of the first function based on the size of the first function to obtain the target instruction sequence corresponding to the at least one target symbol, wherein the product of the size of the second function and a second preset proportion is greater than the size of the plurality of cache lines.

[0106] The first function can be a function with a larger number of dynamic execution instructions among the plurality of functions, and a proportion of the first function in the plurality of functions is a first preset proportion.

[0107] In an optional embodiment, after determining the instruction sequence of the first function from the plurality of functions, the instruction sequence of the second function can be extracted from the instruction sequence of the first function according to a size of the first function, that is, the instruction sequence of the second function can be extracted from the first function which is more active. The second function is a function which is more important in the first function, and a product of the size of the second function and a second preset proportion is greater than a size of the plurality of cache lines. Therefore, the size of the second function needs to be large enough to occupy a certain space in the cache line, which indicates that the second function is a function that can affect the performance or behavior of the program.

[0108] In an optional embodiment, the target cache line start address corresponding to the at least one target symbol can be determined by aligning the at least one target symbol with start addresses of the plurality of cache lines of the processor through an alignment algorithm.

[0109] The first preset proportion can be N%, and the second preset proportion can be Y%. The first preset proportion and the second preset proportion can be determined according to an actual application scenario or an actual effect to be achieved.

[0110] The specific implementation process of the alignment algorithm can be as follows: first, the number of executions of a plurality of symbols is obtained according to PGO, and the number of instructions contained in a plurality of basic blocks in a program is calculated in combination with a compiler to calculate the number of instructions dynamically executed by each basic block; the number of instructions dynamically executed by each function can be obtained by adding the number of instructions dynamically executed by the basic blocks in the function; functions with a cumulative number of instructions N% are extracted, the threshold N can be modified through an option, and the default value can be set to 80, which is only an example and is not limited; in the extracted functions, functions with a size of more than Y% of the size of the cache line are extracted, the threshold Y can be modified through an option, and the default value can be set to 80, which is only an example and is not limited; and the extracted functions are aligned according to the size of the cache line.

[0111] The functions with a cumulative number of instructions N% are extracted, the threshold N can be modified through an option, and the default value can be set to 80, which is only an example and is not limited; in the extracted functions, functions with a size of more than Y% of the size of the cache line are extracted, the threshold Y can be modified through an option, and the default value can be set to 80, which is only an example and is not limited; and the extracted functions are aligned according to the size of the cache line.

[0112] In the above embodiments of the present disclosure, the space layout of at least one target symbol in the memory is adjusted, and the target space layout of the at least one target symbol in the memory is determined, including: determining the execution times of any one of the plurality of symbols based on the performance data; obtaining the number of instructions contained in the plurality of basic blocks in the program, wherein the instruction sequence of any one function is composed of the instructions contained in at least one basic block; based on the execution times of any one symbol and the number of instructions contained in the plurality of basic blocks, the basic block extraction is performed on the program to determine the target basic block corresponding to the at least one target symbol; and the starting address of the cache line corresponding to the target basic block is aligned according to the alignment mode of the value and the prediction to determine the target space layout of the at least one target symbol in the memory.

[0113] The above-mentioned alignment mode of the value and the prediction refers to that in the memory, the data is stored in the cache line, and the starting address of the cache line needs to correspond to the value and the prediction mode of the data. The alignment mode of the value and the prediction can be aligned according to the starting address of the cache line corresponding to the target basic block to improve the reading and prediction performance of the data.

[0114] For the starting address of the cache line corresponding to the target basic block, the target space layout of the at least one target symbol in the memory can be determined through the alignment mode of the value and the prediction. For example, if the starting address of a target symbol in the memory is aligned with the starting address of the cache line, the cache line can be more effectively utilized when the data value and the prediction are performed, and the efficiency of data access is improved. The above-mentioned alignment mode of the value and the prediction can help to determine the layout of the data in the memory to improve the value and prediction performance of the data.

[0115] In an optional embodiment, for frequently accessed symbols together, the access delay can be minimized by adjusting the relative position of the symbols in the memory, and specifically, the symbol spacing adjustment can be used. Optionally, the space layout algorithm method can be used to improve the space layout of the symbols in the memory, and the space layout algorithm considers the size, type and access frequency of the symbols, and a better space layout scheme can be found.

[0116] In another optional embodiment, the execution times of a plurality of symbols can be obtained according to PGO, the number of instructions of a plurality of basic blocks can be calculated in combination with the compiler, the dynamic execution instruction number of the plurality of basic blocks can be calculated, the target basic block with the cumulative dynamic execution instruction number of N% can be extracted, the threshold value N can be modified by an option, and the default value can be set to 80, which is only an example and is not limited. Further, the starting address of the extracted target basic block can be aligned according to the alignment mode of the value and the prediction of the processor, and the default value can be set to 8 bytes, which is not limited here.

[0117] In the above embodiments of the present disclosure, the program is subjected to basic block extraction based on the execution frequency of any one symbol and the number of instructions contained in the plurality of basic blocks, and target basic blocks corresponding to at least one target symbol are determined, including: determining the dynamic execution instruction quantity of any one basic block based on the execution frequency of any one symbol and the number of instructions contained in any one basic block; and extracting target basic blocks corresponding to at least one target symbol from the plurality of basic blocks based on the dynamic execution instruction quantity of any one basic block, wherein the dynamic execution instruction quantity of the target basic block is greater than that of other basic blocks in the plurality of basic blocks except the target basic block, and the proportion of the target basic block in the plurality of basic blocks is a third preset proportion.

[0118] The third preset proportion described above can be set according to actual needs, and is not limited here.

[0119] In an optional embodiment, the dynamic execution instruction quantity of any one basic block can be determined according to the execution frequency of any one symbol and the number of instructions contained in any one basic block, so as to determine the execution state of any one basic block in the program according to the dynamic execution instruction quantity of any one basic block. Optionally, at least one target symbol corresponding to a target basic block can be extracted from the plurality of basic blocks according to the dynamic execution instruction quantity of any one basic block, the target basic block is a more important basic block in the plurality of basic blocks, and the target basic block can be a key point for improving the program. Since the target basic block occupies a relatively large proportion in the execution of the program, the execution efficiency of the entire program can be improved by improving these target basic blocks.

[0120] The present disclosure proposes a method for symbol alignment by analyzing the execution trajectory of a program. The memory distribution of symbols can be improved by collecting performance data of the program during runtime, thereby improving the execution efficiency of the program. First, the performance data of the program during runtime can be collected by using the collection tool provided by the compiler, such as function call frequency, branch jump frequency, and variable access mode, etc. These performance data can be used as an important basis for symbol alignment.

[0121] According to the above performance data, the present disclosure designs a symbol alignment method, which can include the following key steps. First, hot symbol, i.e., functions and variables in the plurality of symbols that are frequently accessed during program runtime, can be determined. The plurality of symbols can be analyzed according to the performance data of the program to obtain the hot symbol. The access frequency of different symbols can be calculated by a statistical method, and the plurality of symbols can be sorted. The top N symbols can be selected as the hot symbol.

[0122] For the hotspot symbol, the hotspot symbol can be aligned to the start address of the processor cache line, so as to reduce the conflict of the cache line in the processor. Optionally, the start address of the cache line matched with the hotspot symbol can be determined by an alignment algorithm, so as to determine a more appropriate alignment address for the hotspot symbol. The alignment algorithm considers the size, type and access frequency of the hotspot symbol, so as to obtain a more appropriate start position of the cache line.

[0123] The symbol alignment method proposed in the disclosure can improve the memory distribution of the symbol by collecting the performance data of the program during runtime, thereby improving the execution efficiency of the program. It should be noted that the work of adjusting the memory location and the memory layout is done by the compiler, and the purpose of the adjustment is to improve the execution efficiency of the program. The key point in the disclosure is that the hotspot symbol identification can be performed, the frequently accessed functions and variables in the program are identified by analyzing the PGO data, and the hotspot symbol alignment is performed on the frequently accessed functions and variables. The hotspot symbol can be aligned to the start address of the processor cache line, so as to reduce the conflict of the cache line. For the frequently accessed symbols, the relative position of the symbol in the memory can be adjusted to minimize the access delay.

[0124] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the disclosure are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of the related data need to comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for the user to choose authorization or refusal.

[0125] It should be noted that, for the foregoing method embodiments, in order to simply describe, they are all expressed as a series of action combinations, but those skilled in the art should know that the disclosure is not limited by the order of the described actions, because according to the disclosure, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily essential to the disclosure.

[0126] From the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and the necessary general hardware platform, and of course it can also be realized by hardware. Based on such understanding, the technical solutions of the disclosure can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes a plurality of instructions for making a terminal device (which can be a mobile phone, computer, server or network device) execute the method of each embodiment of the disclosure.

[0127] Embodiment 2

[0128] According to the embodiments of the present disclosure, a program processing method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from here.

[0129] FIG. 4 is a flowchart of a program processing method according to Embodiment 2 of the present disclosure. As shown in FIG. 4, the method comprises:

[0130] In the case where the graphics processing program is compiled by the compiler and starts to run, the performance data of the graphics processing program collected by the collection tool is obtained.

[0131] The graphics processing program is composed of instruction sequences of multiple functions, and the collection tool is inserted into the graphics processing program by the compiler during the compilation of the graphics processing program.

[0132] The graphics processing program described above can be a computer program for processing and operating graphics images. These programs can be used to edit, adjust, transform and process graphics images to achieve different effects and purposes, such as image enhancement, image synthesis, image compression, etc. Graphics processing programs are commonly used in image editing software, computer aided design software, animation production software, etc. They can operate different types of image files, such as photos, illustrations, graphics images, etc.

[0133] At least one target symbol is determined from the multiple symbols contained in the graphics processing program based on the performance data.

[0134] Different symbols are used to represent different functions or different variables in the program, and at least one target symbol is used to represent a graphics data structure and a rendering function.

[0135] The graphics data structure described above can be a data structure for representing graphics information, such as points, lines, polygons, etc. These data structures can be used to describe the shape, color, position, etc. of the graphics.

[0136] The rendering function described above can be a function for converting graphics data structure into visual graphics. The graphics data structure can be converted into pixel-level image, including color, lighting effect, shadow, etc. The rendering function usually uses graphics library or graphics processor to perform graphics rendering.

[0137] Step S406, aligning the at least one target symbol with the starting addresses of the plurality of cache lines of the processor to determine a target cache line starting address corresponding to the at least one target symbol;

[0138] Step S408, adjusting the spatial layout of the at least one target symbol in the memory to determine a target spatial layout of the at least one target symbol in the memory.

[0139] Through the above steps, in the case that the graphics processing program is compiled by the compiler and starts to run, the performance data of the graphics processing program collected by the collection tool is obtained, wherein the graphics processing program is composed of instruction sequences of a plurality of functions, and the collection tool is inserted into the graphics processing program by the compiler during the compilation of the graphics processing program; at least one target symbol is determined from a plurality of symbols included in the graphics processing program based on the performance data, wherein different symbols are used to represent different functions or different variables in the program, and the at least one target symbol is used to represent a graphics data structure and a rendering function; the at least one target symbol is aligned with the starting addresses of the plurality of cache lines of the processor to determine a target cache line starting address corresponding to the at least one target symbol; and the spatial layout of the at least one target symbol in the memory is adjusted to determine a target spatial layout of the at least one target symbol in the memory, thereby achieving the purpose of improving the execution efficiency of the program. It is easy to note that the at least one target symbol with high access frequency and high importance can be determined through the performance data of the program collected by the collection tool, the number of symbols that need to be aligned can be reduced by screening a plurality of symbols, the at least one target symbol is aligned with the starting addresses of the plurality of cache lines to reduce cache line conflicts, and the access delay of the program is reduced by adjusting the spatial layout of the at least one target symbol in the memory, thereby realizing the improvement of the program, and further solving the technical problem that the compiler in the related art is difficult to reasonably adjust the symbols, thereby causing the execution efficiency of the program to be low.

[0140] It should be noted that the preferred embodiments involved in the above embodiments of the present disclosure have the same scheme, application scenario, and implementation process as provided in Embodiment 1, but are not limited to the scheme provided in Embodiment 1.

[0141] Embodiment 3

[0142] According to the embodiments of the present disclosure, a program processing method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that here.

[0143] FIG. 5 is a flowchart of a program processing method according to Embodiment 3 of the present disclosure. As shown in FIG. 5, the method comprises the following steps:

[0144] In step S502, performance data of the program collected by the collection tool is obtained in a case where the program is compiled by the compiler and starts to run.

[0145] The program is composed of instruction sequences of a plurality of functions, and the collection tool is inserted into the program by the compiler during the compilation of the program.

[0146] In step S504, at least one target symbol is determined from a plurality of symbols included in the program based on the performance data.

[0147] Different symbols are used to represent different functions or different variables in the program, and the access frequency of the at least one target symbol is greater than a preset frequency.

[0148] In step S506, the at least one target symbol is aligned with the starting addresses of a plurality of cache lines of the processor to determine a target cache line starting address corresponding to the at least one target symbol.

[0149] In step S508, the spatial layout of the at least one target symbol in the memory is adjusted to determine a target spatial layout of the at least one target symbol in the memory.

[0150] In step S510, the program is recompiled based on the target cache line starting address and the target spatial layout corresponding to the at least one target symbol.

[0151] In an optional embodiment, the program can be recompiled based on the target cache line starting address and the target spatial layout corresponding to the at least one target symbol, so as to improve the performance of the program and improve the running efficiency of the program.

[0152] In the case that the program is compiled by the compiler and starts to run, the performance data of the program collected by the collection tool is obtained, the program is composed of instruction sequences of multiple functions, and the collection tool is inserted into the program by the compiler during the compilation of the program; at least one target symbol is determined from multiple symbols included in the program based on the performance data, different symbols are used to represent different functions or different variables in the program, and the access frequency of the at least one target symbol is greater than a preset frequency; the at least one target symbol is aligned with the starting addresses of multiple cache lines of the processor to determine a target cache line starting address corresponding to the at least one target symbol; the spatial layout of the at least one target symbol in the memory is adjusted to determine a target spatial layout of the at least one target symbol in the memory; and the program is recompiled based on the target cache line starting address corresponding to the at least one target symbol and the target spatial layout, so as to achieve the purpose of improving the execution efficiency of the program. It can be easily noted that the at least one target symbol with high access frequency and high importance can be determined based on the performance data of the program collected by the collection tool, the number of symbols that need to be subjected to the alignment operation can be reduced by screening the multiple symbols, the at least one target symbol is aligned with the starting addresses of the multiple cache lines to reduce the cache line conflict, and the access delay of the program is reduced by adjusting the spatial layout of the at least one target symbol in the memory, so as to improve the program, and thus the technical problem that the compiler in the related art is difficult to reasonably adjust the symbols, thereby causing the low execution efficiency of the program is solved.

[0153] It should be noted that the preferred embodiments involved in the above embodiments of the present disclosure have the same application scenarios and implementation processes as the scheme provided in Embodiment 1, but are not limited to the scheme provided in Embodiment 1.

[0154] Embodiment 4

[0155] According to the embodiments of the present disclosure, a compiler is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that here.

[0156] FIG. 6 is a schematic diagram of a compiler according to Embodiment 4 of the present disclosure, as shown in FIG. 6, the compiler 600 includes a collection tool 602 and a symbol alignment module 604.

[0157] The collecting tool is used to collect performance data of the program in a case where the program is compiled by the compiler and starts to run, the collecting tool is inserted into the program in a process of compiling the program, and the program is composed of instruction sequences of a plurality of functions.

[0158] In the above embodiments of the present disclosure, the compiler further includes a compiling module configured to recompile the program based on the target cache line start address and the target space layout corresponding to the at least one target symbol.

[0159] It should be noted that the preferred embodiments involved in the above embodiments of the present disclosure have the same application scenarios and implementation processes as the scheme provided in Embodiment 1, but are not limited to the scheme provided in Embodiment 1.

[0160] Embodiment 5

[0161] According to the embodiments of the present disclosure, a system on chip is provided, which includes the compiler in the above embodiments.

[0162] Embodiment 6

[0163] According to the embodiments of the present disclosure, a program processing device for implementing the above program processing method is further provided, and FIG. 7 is a schematic diagram of a program processing device according to Embodiment 6 of the present disclosure. As shown in FIG. 7, the device 700 includes an obtaining module 702, a determining module 704, an aligning module 706, and an adjusting module 708.

[0164] The obtaining module is configured to obtain performance data of the program collected by the collecting tool in a case where the program is compiled by the compiler and starts to run, the program is composed of instruction sequences of a plurality of functions, and the collecting tool is inserted into the program by the compiler in a process of compiling the program. The determining module is configured to determine at least one target symbol from a plurality of symbols included in the program based on the performance data, wherein different symbols are used to represent different functions or different variables in the program, and an access frequency of the at least one target symbol is greater than a preset frequency. The aligning module is configured to align the at least one target symbol with start addresses of a plurality of cache lines of a processor, and determine target cache line start addresses corresponding to the at least one target symbol. The adjusting module is configured to adjust a space layout of the at least one target symbol in a memory, and determine a target space layout of the at least one target symbol in the memory.

[0165] It should be noted that the above acquisition module 702, determination module 704, alignment module 706, and adjustment module 708 correspond to steps S302 to S308 in Embodiment 1, and the four modules have the same instances and application scenarios as the corresponding steps, but are not limited to the content disclosed in Embodiment 1. It should be noted that the above modules or units can be hardware components or software components stored in a memory (for example, the memory 104) and processed by one or more processors (for example, the processors 102a, 102b, …, 102n), or can be run in the computer terminal 10 provided in Embodiment 1 as part of the device.

[0166] In the above embodiments of the present disclosure, determining at least one target symbol from a plurality of symbols included in a program based on performance data includes: determining access frequencies of the plurality of symbols based on the performance data; sorting the plurality of symbols based on the access frequencies to obtain a sorted symbol sequence; and determining a preset number of symbols at the front of the sorted symbol sequence as the at least one target symbol.

[0167] In the above embodiments of the present disclosure, the alignment module is configured to determine an execution number of any one of the plurality of symbols based on the performance data; obtain a number of instructions included in a plurality of basic blocks in the program, wherein any one function in the program is composed of instructions included in at least one basic block; perform instruction extraction on the program based on the execution number of any one symbol and the number of instructions included in the plurality of basic blocks to determine a target instruction sequence corresponding to the at least one target symbol; and align the target instruction sequence according to the size of the plurality of cache lines to determine a target cache line start address corresponding to the at least one target symbol.

[0168] In the above embodiments of the present disclosure, the alignment module is configured to determine a dynamic execution instruction number of any one function based on the execution number of any one symbol and the number of instructions included in the plurality of basic blocks; and extract an instruction sequence satisfying a preset condition from instruction sequences of a plurality of functions based on the dynamic execution instruction number of any one function to obtain a target instruction sequence corresponding to the at least one target symbol.

[0169] In the above embodiments of the present disclosure, the alignment module is configured to determine a dynamic execution instruction number of any one basic block based on the execution number of any one symbol and the number of instructions included in any one basic block; and aggregate the dynamic execution instruction numbers of at least one basic block corresponding to any one function to determine a dynamic execution instruction number of any one function.

[0170] In the above embodiments of the present disclosure, the alignment module is configured to extract an instruction sequence of a first function from instruction sequences of a plurality of functions based on a number of instructions dynamically executed by any one function, wherein the number of instructions dynamically executed by the first function is greater than that of other functions in the plurality of functions, and a proportion of the first function in the plurality of functions is a first preset proportion; and extract an instruction sequence of a second function from the instruction sequence of the first function based on a size of the first function, to obtain a target instruction sequence corresponding to at least one target symbol, wherein a product of the size of the second function and a second preset proportion is greater than a size of a plurality of cache lines.

[0171] In the above embodiments of the present disclosure, the adjustment module is configured to adjust a spatial layout of at least one target symbol in a memory, and determine a target spatial layout of the at least one target symbol in the memory, including: determining a number of times of execution of any one symbol in the plurality of symbols based on performance data; obtaining a number of instructions contained in a plurality of basic blocks in a program, wherein an instruction sequence of any one function is composed of instructions contained in at least one basic block; performing basic block extraction on the program based on the number of times of execution of any one symbol and the number of instructions contained in the plurality of basic blocks, to determine a target basic block corresponding to the at least one target symbol; and aligning a cache line start address corresponding to the target basic block according to a value and a predicted alignment manner, to determine the target spatial layout of the at least one target symbol in the memory.

[0172] In the above embodiments of the present disclosure, the adjustment module is further configured to perform basic block extraction on the program based on the number of times of execution of any one symbol and the number of instructions contained in the plurality of basic blocks, to determine a target basic block corresponding to the at least one target symbol, including: determining a number of instructions dynamically executed by any one basic block based on the number of times of execution of any one symbol and the number of instructions contained in any one basic block; and extracting the target basic block corresponding to the at least one target symbol from the plurality of basic blocks based on the number of instructions dynamically executed by any one basic block, wherein the number of instructions dynamically executed by the target basic block is greater than that of other basic blocks in the plurality of basic blocks, and a proportion of the target basic block in the plurality of basic blocks is a third preset proportion.

[0173] It should be noted that the preferred embodiments involved in the above embodiments of the present disclosure have the same application scenarios and implementation processes as the schemes provided in Embodiment 1, but are not limited to the schemes provided in Embodiment 1.

[0174] Embodiment 7

[0175] According to the embodiments of the present disclosure, a program processing device for implementing the above program processing method is further provided, and FIG. 8 is a schematic diagram of a program processing device according to Embodiment 7 of the present disclosure. As shown in FIG. 8, the device 800 includes an obtaining module 802, a determining module 804, an alignment module 806, and an adjustment module 808.

[0176] The obtaining module is configured to obtain performance data of the graphics processing program collected by the collection tool in a case where the graphics processing program is compiled by the compiler and starts running, wherein the graphics processing program is composed of instruction sequences of a plurality of functions, and the collection tool is inserted into the graphics processing program by the compiler in a process of compiling the graphics processing program; the determining module is configured to determine at least one target symbol from a plurality of symbols included in the graphics processing program based on the performance data, wherein different symbols are used to represent different functions or different variables in the program, and the at least one target symbol is used to represent a graphics data structure and a rendering function; the aligning module is configured to align the at least one target symbol with starting addresses of a plurality of cache lines of the processor to determine a target cache line starting address corresponding to the at least one target symbol; and the adjusting module is configured to adjust a spatial layout of the at least one target symbol in the memory to determine a target spatial layout of the at least one target symbol in the memory.

[0177] It should be noted that the obtaining module 802, the determining module 804, the aligning module 806, and the adjusting module 808 correspond to steps S402 to S408 in Embodiment 2, and the four modules have the same instances and application scenarios as the corresponding steps, but are not limited to the solutions provided in Embodiment 1. It should be noted that the modules or units described above can be hardware components or software components stored in the memory (for example, the memory 104) and processed by one or more processors (for example, the processors 102a, 102b,..., 102n), and the modules described above can also be a part of the device and can run in the computer terminal 10 provided in Embodiment 1.

[0178] It should be noted that the preferred embodiments involved in the above embodiments of the present disclosure have the same solutions, application scenarios, and implementation processes as those provided in Embodiment 1, but are not limited to the solutions provided in Embodiment 1.

[0179] Embodiment 8

[0180] According to the embodiments of the present disclosure, a program processing device for implementing the above program processing method is also provided. FIG. 9 is a schematic diagram of a program processing device according to Embodiment 8 of the present disclosure. As shown in FIG. 9, the device 900 includes an obtaining module 902, a determining module 904, an aligning module 906, an adjusting module 908, and a compiling module 910.

[0181] The acquisition module is configured to acquire performance data of a program collected by a collection tool, in a case where the program is compiled by a compiler and starts to run, wherein the program is composed of instruction sequences of a plurality of functions, and the collection tool is inserted into the program by the compiler during compilation of the program.

[0182] It should be noted that the acquisition module 902, the determination module 904, the alignment module 906, the adjustment module 908, and the compilation module 910 correspond to steps S502 to S410 in Embodiment 3, and the five modules have the same instances and application scenarios as the corresponding steps, but are not limited to the content disclosed in Embodiment 1. It should be noted that the above modules or units can be hardware components or software components stored in a memory (for example, the memory 104) and processed by one or more processors (for example, the processors 102a, 102b, …, 102n), and the above modules can also be run in the computer terminal 10 provided in Embodiment 1 as a part of the apparatus.

[0183] It should be noted that the preferred embodiments involved in the above embodiments of the present disclosure have the same scheme, application scenario, and implementation process as those provided in Embodiment 1, but are not limited to the scheme provided in Embodiment 1.

[0184] Embodiment 9

[0185] The embodiments of the present disclosure can provide an electronic device, which can be any one of electronic devices in a group of electronic devices. Alternatively, in the present embodiment, the electronic device can also be replaced by a terminal device such as a mobile terminal.

[0186] Alternatively, in the present embodiment, the electronic device can be located in at least one network device of a plurality of network devices of a computer network.

[0187] In the present embodiment, the computer terminal can execute program codes in the method.

[0188] Optionally, FIG. 10 is a structural block diagram of an electronic device according to an embodiment of the present disclosure. As shown in FIG. 10, the electronic device A can include one or more (only one is shown in FIG. 10) processors 102, a memory 104, a storage controller, and a peripheral interface, wherein the peripheral interface is connected with a radio frequency module, an audio module, and a display.

[0189] The memory can be used to store software programs and modules, such as program instructions / modules corresponding to the methods and apparatuses in the embodiments of the present disclosure. The processor executes various functions and data processing by running the software programs and modules stored in the memory, that is, implements the methods in the above embodiments. The memory can include a high-speed random access memory, and can further include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some examples, the memory can further include a memory remotely arranged with respect to the processor, and the remote memory can be connected to the terminal A through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0190] The processor can call information and applications stored in the memory through the transmission device to perform the following steps: in a case where a program is compiled and run by a compiler, obtaining performance data of the program collected by a collection tool, wherein the program is composed of instruction sequences of multiple functions, and the collection tool is inserted into the program by the compiler during the compilation of the program; determining at least one target symbol from multiple symbols included in the program based on the performance data, wherein different symbols are used to represent different functions or different variables in the program, and an access frequency of the at least one target symbol is greater than a preset frequency; aligning the at least one target symbol with starting addresses of multiple cache lines of the processor to determine target cache line starting addresses corresponding to the at least one target symbol; and adjusting a spatial layout of the at least one target symbol in the memory to determine a target spatial layout of the at least one target symbol in the memory.

[0191] The processor can call information and application programs stored in the memory through the transmission device to perform the following steps: in the case that the graphics processing program is compiled and started to run by the compiler, obtaining performance data of the graphics processing program collected by the collection tool, wherein the graphics processing program is composed of instruction sequences of multiple functions, and the collection tool is inserted into the graphics processing program by the compiler during the compilation of the graphics processing program; determining at least one target symbol from multiple symbols contained in the graphics processing program based on the performance data, wherein different symbols are used to represent different functions or different variables in the program, and the at least one target symbol is used to represent a graphics data structure and a rendering function; aligning the at least one target symbol with the starting addresses of multiple cache lines of the processor to determine target cache line starting addresses corresponding to the at least one target symbol; adjusting the spatial layout of the at least one target symbol in the memory to determine a target spatial layout of the at least one target symbol in the memory.

[0192] The processor can call information and application programs stored in the memory through the transmission device to perform the following steps: in the case that the program is compiled and started to run by the compiler, obtaining performance data of the program collected by the collection tool, wherein the program is composed of instruction sequences of multiple functions, and the collection tool is inserted into the program by the compiler during the compilation of the program; determining at least one target symbol from multiple symbols contained in the program based on the performance data, wherein different symbols are used to represent different functions or different variables in the program, and the access frequency of the at least one target symbol is greater than a preset frequency; aligning the at least one target symbol with the starting addresses of multiple cache lines of the processor to determine target cache line starting addresses corresponding to the at least one target symbol; adjusting the spatial layout of the at least one target symbol in the memory to determine a target spatial layout of the at least one target symbol in the memory; and recompiling the program based on the target cache line starting addresses and the target spatial layout corresponding to the at least one target symbol.

[0193] In the case that the program is compiled by the compiler and starts to run, performance data of the program collected by the collection tool is acquired, the program is composed of instruction sequences of a plurality of functions, and the collection tool is inserted into the program by the compiler during the compilation of the program; at least one target symbol is determined from a plurality of symbols included in the program based on the performance data, different symbols are used to represent different functions or different variables in the program, and an access frequency of the at least one target symbol is greater than a preset frequency; the at least one target symbol is aligned with starting addresses of a plurality of cache lines of the processor to determine a target cache line starting address corresponding to the at least one target symbol; and a spatial layout of the at least one target symbol in the memory is adjusted to determine a target spatial layout of the at least one target symbol in the memory, so that the execution efficiency of the program is improved. It is easy to note that the at least one target symbol with a high access frequency and high importance can be determined based on the performance data of the program collected by the collection tool, the number of symbols that need to be aligned can be reduced by screening the plurality of symbols, the at least one target symbol is aligned with the starting addresses of the plurality of cache lines to reduce cache line conflicts, and the access delay of the program is reduced by adjusting the spatial layout of the at least one target symbol in the memory, so that the program is improved, and thus the technical problem that the compiler in the related art cannot reasonably adjust the symbols, thereby causing the execution efficiency of the program to be low, is solved.

[0194] Those skilled in the art can understand that the structure shown in FIG. 10 is only schematic, and the electronic device can also be a terminal device such as a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a palm computer, a Mobile Internet Device (MID), a PAD, etc. The FIG. 10 does not limit the structure of the above-mentioned electronic device. For example, the electronic device A can further include more or fewer components (such as a network interface, a display device, etc.) than those shown in the figure, or have a different configuration from that shown in the FIG. 10.

[0195] Those skilled in the art can understand that all or part of the steps in the various methods of the above-mentioned embodiments can be completed by instructing the related hardware of the terminal device by a program, and the program can be stored in a computer readable storage medium, which can include a flash disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, etc.

[0196] Embodiment 10

[0197] The embodiments of the present disclosure further provide a computer readable storage medium. Optionally, in the embodiments, the computer readable storage medium can be used to save the program codes executed by the method provided by the above embodiments.

[0198] Optionally, in the embodiments, the storage medium can be located in any one of the electronic devices in the computer network or in any one of the mobile terminals in the mobile terminal group.

[0199] Optionally, in the embodiments, the computer readable storage medium is configured to store program codes for performing the following steps: obtaining performance data of a program collected by a collection tool, in a case that the program is compiled by a compiler and starts to run, wherein the program is composed of instruction sequences of a plurality of functions, and the collection tool is inserted into the program by the compiler during the compilation of the program; determining at least one target symbol from a plurality of symbols included in the program based on the performance data, wherein different symbols are used to represent different functions or different variables in the program, and an access frequency of the at least one target symbol is greater than a preset frequency; aligning the at least one target symbol with starting addresses of a plurality of cache lines of a processor to determine target cache line starting addresses corresponding to the at least one target symbol; and adjusting a spatial layout of the at least one target symbol in a memory to determine a target spatial layout of the at least one target symbol in the memory.

[0200] Optionally, in the embodiments, the computer readable storage medium is configured to store program codes for performing the following steps: obtaining performance data of a graphics processing program collected by a collection tool, in a case that the graphics processing program is compiled by a compiler and starts to run, wherein the graphics processing program is composed of instruction sequences of a plurality of functions, and the collection tool is inserted into the graphics processing program by the compiler during the compilation of the graphics processing program; determining at least one target symbol from a plurality of symbols included in the graphics processing program based on the performance data, wherein different symbols are used to represent different functions or different variables in the program, and the at least one target symbol is used to represent a graphics data structure and a rendering function; aligning the at least one target symbol with starting addresses of a plurality of cache lines of a processor to determine target cache line starting addresses corresponding to the at least one target symbol; and adjusting a spatial layout of the at least one target symbol in a memory to determine a target spatial layout of the at least one target symbol in the memory.

[0201] Optionally, in the embodiment, the computer readable storage medium is configured to store program code for performing the following steps: obtaining performance data of a program collected by a collection tool, in a case where the program is compiled by a compiler and starts running, wherein the program is composed of instruction sequences of a plurality of functions, and the collection tool is inserted into the program by the compiler during the compilation of the program; determining at least one target symbol from a plurality of symbols included in the program based on the performance data, wherein different symbols are used to represent different functions or different variables in the program, and an access frequency of the at least one target symbol is greater than a preset frequency; aligning the at least one target symbol with starting addresses of a plurality of cache lines of a processor to determine target cache line starting addresses corresponding to the at least one target symbol; adjusting a spatial layout of the at least one target symbol in memory to determine a target spatial layout of the at least one target symbol in the memory; and recompiling the program based on the target cache line starting addresses corresponding to the at least one target symbol and the target spatial layout.

[0202] With the embodiments of the present disclosure, in a case where the program is compiled by a compiler and starts running, performance data of the program collected by a collection tool is obtained, wherein the program is composed of instruction sequences of a plurality of functions, and the collection tool is inserted into the program by the compiler during the compilation of the program; at least one target symbol is determined from a plurality of symbols included in the program based on the performance data, wherein different symbols are used to represent different functions or different variables in the program, and an access frequency of the at least one target symbol is greater than a preset frequency; the at least one target symbol is aligned with starting addresses of a plurality of cache lines of a processor to determine target cache line starting addresses corresponding to the at least one target symbol; a spatial layout of the at least one target symbol in memory is adjusted to determine a target spatial layout of the at least one target symbol in the memory, thereby achieving the purpose of improving the execution efficiency of the program. It is easy to note that the at least one target symbol with a higher access frequency and being more important can be determined through the performance data of the program collected by the collection tool, the number of symbols that need to be aligned can be reduced through screening of the plurality of symbols, the at least one target symbol is aligned with the starting addresses of the plurality of cache lines to reduce the conflict of the cache lines, and the access delay of the program is reduced through adjustment of the spatial layout of the at least one target symbol in the memory, thereby realizing the improvement of the program, and further solving the technical problem that the compiler in the related art is difficult to reasonably adjust the symbols, thereby resulting in a lower execution efficiency of the program.

[0203] Embodiment 11

[0204] The embodiments of the present disclosure further provide a computer program product. Optionally, in the embodiment, the computer program product can include a computer program, and the computer program, when executed by a processor, implements the method provided by the above-mentioned embodiments.

[0205] Embodiment 12

[0206] Embodiments of the present disclosure further provide a computer program product. Optionally, the computer program product described above can include a nonvolatile computer-readable storage medium, which can be used to store a computer program. The computer program is executed by a processor to implement the method provided by the above embodiments.

[0207] Embodiment 13

[0208] Embodiments of the present disclosure further provide a computer program. Optionally, in the present embodiment, the computer program described above is executed by a processor to implement the method provided by the above embodiments.

[0209] The serial numbers of the embodiments of the present disclosure are only for description, and do not represent the advantages or disadvantages of the embodiments.

[0210] In the above embodiments of the present disclosure, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0211] In several embodiments provided by the present disclosure, it should be understood that the disclosed technology can be implemented in other ways. Of course, the embodiments described above are only schematic. For example, the division of units is only a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, units or modules, and can be electrical or other forms.

[0212] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. According to actual needs, some or all of the units can be selected to achieve the purpose of the present embodiment.

[0213] In addition, each functional unit in each embodiment of the present disclosure can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0214] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present disclosure, essentially or in other words, the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present disclosure. The aforementioned storage medium includes various media that can store program codes, such as a U disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a mobile hard disk, a magnetic disk or an optical disk, etc.

[0215] The above only describes the preferred embodiments of the present disclosure, and it should be pointed out that, for those skilled in the art, without departing from the principles of the present disclosure, a number of improvements and refinements can be made, and these improvements and refinements should also be considered as the protection scope of the present disclosure.

Claims

1. A program processing method applied to a compiler, comprising: acquiring performance data of a program collected by a collection tool, in a case that the program is compiled by the compiler and starts running, wherein the program is composed of instruction sequences of a plurality of functions, and the collection tool is inserted into the program by the compiler during compiling the program; determining at least one target symbol from a plurality of symbols included in the program based on the performance data, wherein different symbols are used to represent different functions or different variables in the program, and an access frequency of the at least one target symbol is greater than a preset frequency; aligning the at least one target symbol with starting addresses of a plurality of cache lines of a processor to determine a target cache line starting address corresponding to the at least one target symbol; adjusting a spatial layout of the at least one target symbol in a memory to determine a target spatial layout of the at least one target symbol in the memory.

2. The method of claim 1, wherein, The determining at least one target symbol from a plurality of symbols included in the program based on the performance data comprises: determining access frequencies of the plurality of symbols based on the performance data; sorting the plurality of symbols based on the access frequencies to obtain a sorted symbol sequence; determining a preset number of symbols ranked in front in the sorted symbol sequence as the at least one target symbol.

3. The method of claim 1, wherein, The aligning the at least one target symbol with starting addresses of a plurality of cache lines of a processor to determine a target cache line starting address corresponding to the at least one target symbol comprises: determining an execution number of any one symbol in the plurality of symbols based on the performance data; acquiring a number of instructions included in a plurality of basic blocks in the program, wherein any one function in the program is composed of instructions included in at least one basic block; performing instruction extraction on the program based on the execution number of the any one symbol and the number of instructions included in the plurality of basic blocks to determine a target instruction sequence corresponding to the at least one target symbol; aligning the target instruction sequence according to sizes of the plurality of cache lines to determine the target cache line starting address corresponding to the at least one target symbol.

4. The method of claim 3, wherein, The performing instruction extraction on the program based on the execution number of the any one symbol and the number of instructions included in the plurality of basic blocks to determine a target instruction sequence corresponding to the at least one target symbol comprises: determining a dynamic execution instruction number of the any one function based on the execution number of the any one symbol and the number of instructions included in the plurality of basic blocks; extracting an instruction sequence satisfying a preset condition from the instruction sequences of the plurality of functions based on the dynamic execution instruction number of the any one function to obtain the target instruction sequence corresponding to the at least one target symbol.

5. The method of claim 4, wherein, The determining a dynamic execution instruction number of the any one function based on the execution number of the any one symbol and the number of instructions included in the plurality of basic blocks comprises: determining a dynamic execution instruction number of the any one basic block based on the execution number of the any one symbol and the number of instructions included in the any one basic block; The dynamic execution instruction quantity of at least one basic block corresponding to the arbitrary function is aggregated to determine the dynamic execution instruction quantity of the arbitrary function.

6. The method of claim 4, wherein, The target instruction sequence corresponding to the at least one target symbol is obtained by extracting, based on the dynamic execution instruction quantity of the arbitrary function, an instruction sequence of a first function from the instruction sequences of the plurality of functions, wherein the dynamic execution instruction quantity of the first function is greater than that of other functions in the plurality of functions except the first function, and the proportion of the first function in the plurality of functions is a first preset proportion. The target instruction sequence corresponding to the at least one target symbol is obtained by extracting, based on the size of the first function, an instruction sequence of a second function from the instruction sequence of the first function, wherein the product of the size of the second function and a second preset proportion is greater than the size of the plurality of cache lines. The space layout of the at least one target symbol in the memory is adjusted to determine the target space layout of the at least one target symbol in the memory, comprising:

7. The method of claim 1, wherein, Based on the performance data, the execution times of any one symbol in the plurality of symbols are determined. The number of instructions contained in the plurality of basic blocks in the program is obtained, wherein the instruction sequence of any one function is composed of instructions contained in at least one basic block. Based on the execution times of the arbitrary symbol and the number of instructions contained in the plurality of basic blocks, the program is subjected to basic block extraction to determine the target basic block corresponding to the at least one target symbol. The cache line starting address corresponding to the target basic block is aligned according to the value and the predicted alignment mode to determine the target space layout of the at least one target symbol in the memory. Based on the execution times of the arbitrary symbol and the number of instructions contained in the plurality of basic blocks, the program is subjected to basic block extraction to determine the target basic block corresponding to the at least one target symbol, comprising:

8. The method of claim 7, wherein, Based on the execution times of the arbitrary symbol and the number of instructions contained in any one basic block, the dynamic execution instruction quantity of the arbitrary basic block is determined. Based on the dynamic execution instruction quantity of the arbitrary basic block, the target basic block corresponding to the at least one target symbol is extracted from the plurality of basic blocks, wherein the dynamic execution instruction quantity of the target basic block is greater than that of other basic blocks in the plurality of basic blocks except the target basic block, and the proportion of the target basic block in the plurality of basic blocks is a third preset proportion.

9. A program processing method applied to a compiler, comprising: In the case that a graphics processing program is compiled by the compiler and starts to run, performance data of the graphics processing program collected by a collection tool is obtained, wherein the graphics processing program is composed of instruction sequences of a plurality of functions, and the collection tool is inserted into the graphics processing program by the compiler during the compilation of the graphics processing program. ​ determine at least one target symbol from a plurality of symbols included in the program based on the performance data, wherein different symbols are used to represent different functions or different variables in the program, and the at least one target symbol is used to represent a graph data structure and a rendering function; align the at least one target symbol with starting addresses of a plurality of cache lines of a processor to determine a target cache line starting address corresponding to the at least one target symbol; and adjust a spatial layout of the at least one target symbol in a memory to determine a target spatial layout of the at least one target symbol in the memory.

10. A program processing method applied to a compiler, comprising: obtaining performance data of a program collected by a collection tool in a case where the program is compiled by the compiler and starts running, wherein the program is composed of instruction sequences of a plurality of functions, and the collection tool is inserted into the program by the compiler during compilation of the program; determining at least one target symbol from a plurality of symbols included in the program based on the performance data, wherein different symbols are used to represent different functions or different variables in the program, and an access frequency of the at least one target symbol is greater than a preset frequency; aligning the at least one target symbol with starting addresses of a plurality of cache lines of a processor to determine a target cache line starting address corresponding to the at least one target symbol; adjusting a spatial layout of the at least one target symbol in a memory to determine a target spatial layout of the at least one target symbol in the memory; and recompiling the program based on the target cache line starting address and the target spatial layout corresponding to the at least one target symbol.

11. A compiler, comprising: a collection tool configured to collect performance data of a program in a case where the program is compiled by the compiler and starts running, wherein the collection tool is inserted into the program during compilation of the program, and the program is composed of instruction sequences of a plurality of functions; a symbol alignment module configured to determine at least one target symbol from a plurality of symbols included in the program based on the performance data, align the at least one target symbol with starting addresses of a plurality of cache lines of a processor to determine a target cache line starting address corresponding to the at least one target symbol, and adjust a spatial layout of the at least one target symbol in a memory to determine a target spatial layout of the at least one target symbol in the memory, wherein different symbols are used to represent different functions or different variables in the program, and an access frequency of the at least one target symbol is greater than a preset frequency.

12. The compiler of claim 11, wherein, further comprising: a compilation module configured to recompile the program based on the target cache line starting address and the target spatial layout corresponding to the at least one target symbol.

13. A system on a chip comprising: The compiler of claim 11 or 12.

14. An electronic device, comprising: a memory storing an executable program; a processor configured to run the program, wherein the program performs the method of any one of claims 1 to 10 when running. The electronic device of claim 14.

15. A computer readable storage medium comprising a stored executable program, wherein, controlling the device in which the storage medium is located to perform the method of any one of claims 1 to 10 when the executable program is running.

16. A computer program product comprising a computer program which, when executed by a processor, implements the method of any one of claims 1 to 10.

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