Semiconductor sample with reduced preparation time

Abstract

The invention relates to a semiconductor sample comprising a top surface including a milling region to be milled by an ion beam hitting the top surface, and a plurality of protective layers located on the top surface and distributed over the top surface, wherein each protective layer is generated such that it covers a surface area of the top surface. A linear marker is provided on each of the protective layers, wherein at least 2 of the linear markers have a defined positional relationship relative to one another, wherein each of the protective layers is dimensioned such that the surface area has a width perpendicular to a longitudinal direction of the linear marker that is smaller than 10 times a width of the corresponding linear marker.

Description

[0001] Semiconductor sample with reduced preparation time

[0002] Technical Field

[0003] The disclosure relates to a semiconductor sample and to a method for generating a semiconductor sample.

[0004] Background

[0005] Semiconductor structures are amongst the finest man-made structures and suffer from different imperfections. Devices for quantitative 3D-metrology, defect-detection or defect review are looking for these imperfections. Fabricated semiconductor structures are based on prior knowledge. The semiconductor structures are manufactured from a sequence of layers being parallel to a substrate. For example, in a logic type sample, metal lines are running parallel in metal layers or HAR (high aspect ratio) structures and metal vias run perpendicular to the metal layers. The angle between metal lines in different layers is either 0° or 90°. On the other hand, for VNAND type structures it is known that their cross-sections are circular on average.

[0006] A semiconductor wafer has a diameter of 300 mm and consist of a plurality of several sites, so called dies, each comprising at least one integrated circuit pattern such as for example for a memory chip or for a processor chip. During fabrication, semiconductor wafers run through about 1000 process steps, and within the semiconductor wafer, about 100 and more parallel layers are formed, comprising the transistor layers, the layers of the middle of the line, and the interconnect layers and, in memory devices, a plurality of 3D arrays of memory cells. Dimensions, shapes and placements of the semiconductor structures and patterns are subject to several influences. In manufacturing of 3D-Memory devices, the critical processes are currently etching and deposition. Other involved process steps such as the lithography exposure or implantation also have an impact on the properties of the IC-elements.

[0007] One way for defect detection is based on 3D tomographic data. A common way to generate 3D tomographic data from semiconductor samples on nm scale is the so-called slice and image approach elaborated for example by a dual beam device (DBD). One way is via FIB- SEM (Focused Ion Beam- Scanning Electron Microscopy) 3D Tomography. Here, slices are cut into the structure via FIB (i.e. by milling) and subsequently imaged with SEM before continuing with the next slice.

[0008] US 1 ,086,100 B2 discloses a method for measuring the advance of a milling front using linear fiducial marks oriented at an angle relative to each other. Such fiducial marks can be used in FIB-SEM 3D tomography. The preparation of the marks requires depositing a rectangular pad of C, PT or W or other material on top of the wafer surface using a gas injection system combined with either FIB or SEM. The fiducial marks are provided on top of a protective layer, also called pad using FIB. The total time for the pad deposition is considerably long for large a large field of view which are demanded by today's semi-manufacturing customers. The purpose of such a rectangular pad or protective layer is twofold: It provides a homogeneous medium for drawing straight high contrast marks and at the same time reduces the curtaining effect of milling caused by inhomogeneity of the top edge of the milled surface. The preparation time for a rectangular pad of several micrometers is more than one hour and also depends on the exact circumstances. This high preparation time for the semiconductor sample before the actual data acquisition is disadvantageous.

[0009] Accordingly, a need exists to overcome this drawback and to provide a semiconductor sample where the preparation time before the 3D tomography scan is reduced.

[0010] Summary

[0011] This need is met by the features of the independent claims. Further aspects are described in the dependent claims.

[0012] According to a first aspect a semiconductor sample is provided comprising a top surface including a milling region to be milled by an ion beam hitting the top surface. The sample furthermore comprises a plurality of protective layers located on the top surface and distributed over the top surface, wherein each protective layer is generated such that it covers a surface area of the top surface. The semiconductor sample furthermore comprises a linear marker provided on each of the protective layers wherein at least two of the linear markers have a defined and known positional relationship relative to one another, and each of the protective layers is dimensioned such that the surface area has a width perpendicular to a longitudinal direction of the linear marker that is smaller than ten times the width of the corresponding linear marker. Furthermore, the corresponding method for generating the semiconductor sample is provided comprising the steps of provisioning the semiconductor sample having the top surface with the milling region to be milled by the ion beam hitting the top surface. The method comprises furthermore the step of generating a plurality of protective layers located on the top surface in such a way that they are distributed over the top surface and each protective layer is generated such that it covers a surface area of the top surface. Furthermore, on each of the protective layers, a linear marker is provided wherein at least two of the linear markers provided on the different protective layers have a defined positional relationship relative to one another and each the protective layers is dimensioned such that the surface area has a width perpendicular to a longitudinal direction of the linear marker that is smaller than ten times the width of the corresponding linear marker.

[0013] Accordingly, instead of providing a pad or a large area on which different linear markers are provided, different smaller protective layers are generated and the size of each of the protective layers is such that it is only slightly larger than the linear marker provided on top of the protective layer. Instead of using a continuous or connected area where all the linear markers area provided, different non-overlapping protective layers or areas are provided, with the surface of each area being only slightly larger than the linear marker provided on the corresponding surface area. It was found that for many wafer types and many designs of the semiconductor sample, only minor curtaining effects were observed so that it is possible to reduce the surface area of the protective layers wherein the areas are reduced such that it only includes an area around the marker which is only slightly bigger than the marker itself. Especially as the width of the area perpendicular to the longitudinal direction of the marker is smaller than ten times the width of the marker itself, preferably even smaller than five times or smaller than three times the widths of the marker, only a small surface has to be provided and generated on the top surface of the semiconductor sample. This greatly reduces the preparation time of the protective layers on the semiconductor sample which is then ready for the milling process.

[0014] According to another aspect a method for generating a semiconductor sample is provided wherein the method comprises the step of providing a semiconductor sample having a top surface with a milling region to be milled by an ion beam hitting the top surface wherein a plurality of markers are directly provided on the surface of the semiconductor sample and at least 2 of the markers have a defined positional relationship relative to one another. Furthermore, the corresponding semiconductor sample is provided generated by the abovedescribed method.

[0015] In this embodiment the protective layer is completely omitted and the markers are directly deposited on the top surface of the semiconductor sample. This reduces the preparation time of the semiconductor sample even further.

[0016] It should be understood that the features mentioned above or those yet to be explained below may be used not only in the respective combinations indicated, but also in other combinations or in isolation without departing from the scope of the present disclosure.

[0017] Brief Description of the Drawings

[0018] Other features and advantages will be or will become apparent to one with skill in the art upon examination of the following detailed description when read in conjunction with the accompanying drawings in which like reference numerals refer to like elements.

[0019] Figure 1 shows a schematic view of a measurement geometry of a dual beam device with which the semiconductor structures of a sample can be examined.

[0020] Figure 2 shows an example illustration of a geometry for a volume inspection of the sample with a slanted cross-section milling and imaging by the dual beam device.

[0021] Figure 3 shows an example schematic representation of a distribution of the protective layers and the corresponding markers on a top surface of a semiconductor sample according to one embodiment of the invention.

[0022] Figure 4 shows a schematic view of an arrangement of the protective layers and the markers relative to the milling surface and a region of interest.

[0023] Figure 5 shows a further schematic view of linear markers directly provided on a top surface of a wafer and the corresponding milling area incorporating features of the invention. Figure 6 shows a further schematic view of a pair of markers provided on a top surface of a semiconductor sample that can be used to measure the progress of the milling front.

[0024] Figure 7 shows an example representation of a flowchart comprising the steps used to generate and prepare a semiconductor sample for a 3D investigation.

[0025] Figure 8 shows a further example representation of a flowchart comprising the steps used for preparing or generating a semiconductor sample for a 3D examination.

[0026] Detailed Description

[0027] In the following, embodiments of the disclosure will be described in detail with reference to the accompanying drawings. It is to be understood that the following description of embodiments is not to be taken in a limiting sense. The scope of the disclosure is not intended to be limited by the embodiments described hereinafter or by the drawings, which are taken to be illustrative only.

[0028] The drawings are to be regarded as being schematic representations and elements illustrated in the drawings are not necessarily shown to scale. Rather, the various elements are represented such that their function and general purpose become apparent to a person skilled in the art. Any connection or coupling between functional blocks, devices, components, or other physical or functional units shown in the drawings or described herein may also be implemented by an indirect connection or coupling. A coupling between components may also be established over a wireless connection. Functional blocks may be implemented in hardware, firmware, software, or a combination thereof.

[0029] In connection with Fig. 1 a charged particle beam system such as an electron beam imaging system 100 is explained in more detail. The imaging system 100 is configured for a slice and imaging method under wedge cut geometry with a dual beam device 1. For a wafer 20, several measurement sites, comprising measurement sites 21 and 22 are defined in a location map or inspection list generated from an inspection tool or from design information. The wafer 20 is placed on a wafer support table 10. The wafer support table 10 is mounted on a stage 90 with actuators and position control. Actuators and means for precision control for a wafer stage such as Laser interferometers are known in the art. A control unit 80 is configured to control a wafer stage 90 and to adjust a measurement site 21 of the wafer 20 at the intersection point with a FIB optical axis 48 and a charged particle beam (CPB) or scanning electron imaging system 40 with optical axis 42. It should be understood that the wedge could not only be generated by a focused ion beam, but also with the help of a laser or neutral atoms or using mechanical tools ("dimpling”). The charged particle imaging system can generate a focused electron or ion beam 44. At the intersection point 43 of both optical axes of FIB and CPB imaging system, the wafer surface is arranged at a slant angle a to the FIB axis 48. FIB axis 48 and CPB imaging system axis 42 include an angle p, and the CPB imaging system axis forms an angle GE with normal to the wafer top surface 24. In the coordinate system of figure 1 , the normal to the wafer or top surface 24 is given by the z-axis. The focused ion beam (FIB) 51 is generated by the FIB-generating unit 50 and is impinging under angle a on the surface 24 of the wafer 20. Slanted cross-section surfaces are milled into the wafer by ion beam milling at the inspection or measurement site 21 under approximately the slant or mill angle alpha (a). In the example of Fig. 1 , the incidence angle alpha (a) is approximately 30°. With the charged particle beam imaging system, images of the milled surfaces can be acquired. In the example of Figure 1 , the angle GE is about 15°. However, other arrangements are possible as well, for example with GE = alpha, such that the CPB imaging system optical axis 42 is perpendicular to the FIB axis 48, or GE = 0°, such that the CPB imaging system axis 42 is perpendicular to the wafer top surface 24.

[0030] During imaging, the ion beam 44 of charged particles, ions such as electrons, is scanned by a scanning unit of the charged particle beam imaging system 40 along a scan path over a crosssection surface of the wafer at measurement site 21 using scanning lines, and secondary particles as well as scattered particles are generated. Particle detector 30 collects at least some of the secondary particles and scattered particles and communicates the particle count with a control unit 60, wherein the particle detector can also be provided within system 40. Other detectors for other kinds of interaction products may be present as well. The image is generated based on the scanning lines as known in the art using the back scattered and / or the secondary particles emitted from the sample based on the scanning electron beam. Control unit 60 is in control of the charged particle beam imaging system 40, of FIB generating unit 50 and connected to a further control unit 80 to control the position of the wafer mounted on the wafer support table via the wafer stage 90. Control unit 60 communicates with operation control unit 70, which triggers placement and alignment for example of measurement site 21 of the wafer 20 at the intersection point 43 via wafer stage movement and triggers repeatedly operations of FIB milling, image acquisition and stage movements. An image of the wafer surface can be generated based on particles detected when the ion beam 44, here an electron beam scans the wafer surface, wherein the image may be generated in control unit 60 or any other module of the system 100. Fig. 2 illustrate further details of the slice and imaging method in the wedge cut geometry. By repetition of the slicing and imaging method in wedge-cut geometry, a plurality of J crosssection image slices comprising image slices of cross-section surfaces 52, 53. i...53. J is generated and a 3D volume image of an inspection volume 160 at an inspection site 6.1 of the wafer 20 at measurement site 6.1 is generated. Figure 2 illustrates the wedge cut geometry at the example of a 3D-memory stack. The cross-section surfaces 52, 53.1 ...53. N are milled with the FIB beam 51 at an angle GF of approximately 30° to the wafer surface, but other angles GF, for example between GF = 20° and GF = 60° are possible as well. Figure 2 illustrates the situation, when the surface 52 is the new cross-section surface which was milled last by FIB 51 . The cross-section surface 52 is scanned for example by SEM ion beam 44, which is in the example of Figure 2 arranged at normal incidence to the wafer surface 55, and a high- resolution cross-section image slice is generated.

[0031] For determining a thickness of the generated image slice it is important to correctly determine an advance of a cutting edge 170 where the ion beam used for milling is hitting the top surface of the sample.

[0032] Fig. 3 shows an example view of an arrangement of dedicated layers with linear markers which are used to determine the progress of the cutting edge where the ion beam hits the top surface. The knowledge of the position in three-dimensional space of any cross-sectional milling surface is important to make sure that each slice of a 3D tomography has a desired thickness. Fig. 3 is a top-down view of the semiconductor sample including a plurality of protective layers 210 to 260 located on the wafer surface 55. On each of the protective layers a linear marker 310 to 360 is provided, wherein marker 310, also called fiducial marker, has a defined positional relationship to marker 340. In the same way the position of the marker 350 relative to marker 320 is known etc. Under the assumption that the cutting edge 170 of the milled surface is provided as indicated in Fig. 3, the image generated on the milling surface will include representations 341 of marker 340 and representation 342 of marker 310 and which have a defined distance D. As the positional relationship between the two markers 310 and 340 is known, the distance D between the two marker representations can help to determine an exact position of the cutting edge 170. As the milling progresses the distance between the two representations such as representations 341 and 342 will become smaller under the assumption that the cutting edge 170 continues to move in direction A as shown by the arrow and in the next image the cutting edge 171 may be present cutting the corresponding linear markers 310 and 340 at another location. Based on the position of the cutting edge 170 and 171 it is possible to determine a slice thickness for an image. Further details for the positioning and determination of the slice thickness are disclosed in US 10,886,100, to which reference is made in this respect.

[0033] The protective layer such as protective layer 230 has a width W1 which is larger than the width of the corresponding linear marker 330 located on the corresponding protective layer. The width of the corresponding marker is indicated as W2 and the width perpendicular to the longitudinal direction of the marker330 is now such that W1 is at most ten times the width W2 of the corresponding marker. Furthermore, each of the markers has an extension in the longitudinal direction of L2 whereas the extension in the longitudinal direction of the corresponding layer is L1. Each the protective layers extends over the linear marker by a certain length which is again at most ten times the widths of the linear market itself. As the protective layer extends over the linear marker at both ends, L1-L2 is smaller than 20 times W2, preferably smaller than ten times or even preferably smaller than six times W2.

[0034] Accordingly, as can be deduced from Fig. 3 the surface area of each protective layer is reduced such that it only includes the close vicinity of the linear markers as shown in Fig. 3 where the boundaries of the protective layers are shown with dashed lines and the linear markers themselves with solid lines. Furthermore, different separate non- connected areas are used and for each linear marker one area is used. The widths (in the surface plane of the sample, the x-y Plane in Fig. 1) of the individual protective layers encompassing the individual linear markers can be chosen such that the markers remain inside the protective layers despite of any uncertainty in positioning of the protective layers and of the markers wherein the uncertainty may be due to mechanical- or charging-induced drift during the preparation.

[0035] FIG. 4 shows the relationship between the position of the milled surface 52 and the arrangement of the protective layers as shown in FIG. 3 including the different markers and protective layers and including a region of interest 59 where an object of interest may be located for which the 3D tomography is made. The different protective layers are located in a marking region 280 shown in FIG. 4 and the region of interest 59 is located outside of the area covered by the markers. The protective layers and the cross-sections thereof might introduce a curtaining effect at the milling front in the milled surface depending on the wafer type and the set-up of the FIB. To avoid this curtaining effect it is proposed to offset the region of interest 59 such that the region of interest 59 is not located inside the marking region 280 so that possible curtaining artifacts remain outside the region of interest as shown in FIG. 4. FIG. 5 shows a further aspect in which the preparation time for the linear markers is further reduced. In this situation shown in FIG. 5 the linear markers 410 and 440 may be deposited directly on the wafer surface 55 without the intermediate provision of the protective layer as it was the situation shown in Figs. 3 and 4. The deposition of these markers can be obtained using GIS and FIB or SEM directly on the top of the surface. This further significantly reduces the preparation time of the semiconductor sample.

[0036] FIG. 6 shows a further embodiment which can be used to measure the progress of the cutting edge or milling front with a low preparation time. As indicated above the progress of the cutting or milling front is needed to determine a slice thickness of the removed material. In the situation shown in FIG. 6 an elongated protective layer 510 may be deposited on the surface and in addition an alignment mark 520 is provided. The alignment mark 520 is originally needed for the lateral alignment of the acquired slice images for subsequent 3D reconstruction (generation of 3D data volume). Therefore, the design of the alignment mark is chosen to allow precise determination of its location using, e.g., cross-correlation based techniques. The alignment mark can be generated in two possible ways. The first way includes a two-step process. The first optional step is to deposit a pad of a couple of hundred nm thickness (300- 500 nm). Usually Pt or W are used as materials for the pad". Second, the FIB is used to cut a “v”-shaped groove in the pad which can be easily identified in an SEM image and used for the alignment. Instead of “v”-shape, any other shape can be used which gives optimal localization accuracy (for example a cross or a set of lines and spaces in orthogonal directions). Alternatively, the mark of a chosen shape can be deposited directly on the surface of the wafer using GIS (gas injection system) combined with FIB or SEM. Accordingly, the alignment mark can be generated in a similar or same way as the other linear markers discussed above. As the milling front advances, a distance D between the cross-section of the protective layer 510 and the alignment mark 520 increases proportionally. This distance measured in the respective SEM images could be also used to determine the milling progress or the slice sickness. The material of the protective layer can be chosen to maximize the contrast between the protective layer and the wafer in the SEM images. As described in connection with FIG. 4 the region of interest for the 3D tomography not shown in FIG. 6 may be placed with offset with respect to the layer 510 to avoid possible curtaining caused by the protective layer. FIG. 7 shows example steps of a method used for generating or preparing a semiconductor sample such as wafer 20 of Fig. 1 . In step S71 a semiconductor sample is provided which has a top surface where a milling should be carried out in a milling region by an ion beam. In step S72 a plurality of protective layers is generated on the top surface which are distributed over the top surface as shown inter alia in Figs. 3 and 4 and each of the protective layers covers a certain surface area of the top surface. In step S73 a linear marker is provided on each of the protective layers and the protective layers are dimensioned relative to the markers and the surface area such that the surface area has a width perpendicular to the longitudinal direction of the linear marker that is smaller than ten times, preferably smaller than five times or even more preferably smaller than three times the width of the corresponding marker. With the method of FIG. 7 a conductor sample is provided as shown in Figs. 3 and 4.

[0037] FIG. 8 shows a further method for generating or preparing a semiconductor sample comprising the step of providing the semiconductor sample with a surface where a milling region is located which is to be milled by an ion beam hitting the top surface as shown by step S81. In step S82 the plurality of markers are directly provided on the top surface. These two markers have a defined positional relationship relative to one another. This situation was shown in connection with FIG. 5 or 6, especially FIG. 5 wherein the markers are directly provided on the top surface. The plurality of markers can include two markers having a predefined positional relationship as shown in FIG. 5. It is possible to use an alignment mark 520 and another protective layer 510 and its cutting edge 515. As the milling advances a distance D between a cutting edge 515 and the alignment mark 520 increases.

[0038] Summarizing, with the above-described methods and samples it is possible to determine the progress of the milling front with a low preparation time of the corresponding sample. Based on a position of the milling front it is possible to determine a slice thickness of an image slice generated with the system as shown in FIG. 1 and 2.

[0039] From the above-said some general conclusions can be drawn.

[0040] As discussed in connection with Figs. 3 and 4, each of the protective layers may be dimensioned such that the protective layer has a length in the longitudinal direction of the linear marker beyond the corresponding end of the linear marker that is smaller than ten times the width of the linear marker. As discussed in connection with FIG. 3 the protective layer has a length L1 and the marker has a length L2 and the difference L1-L2 is smaller than 20 times the width W2. Preferably the surface area of the protective layer has a width perpendicular to the longitudinal direction that is smaller than five times the width of the corresponding linear marker, more preferably even smaller than three times the width of the corresponding linear marker.

[0041] Furthermore, the plurality of protective layers can encircle a marking region such as region 280 shown in FIG. 4 on the top surface of the semiconductor sample, and the milling region comprises a region of interest 59. The region of interest is preferable located outside of the marking region.

[0042] For the semiconductor sample where the marker is provided directly on the surface of the sample (e.g., for the purpose of lateral alignment of the slice images as described above) it is possible to use a linear marker that is generated by directly depositing material on the top surface of the semiconductor sample as disclosed in connection with Fig. 5. One of the markers may be a linear marker and the other one may be an alignment marker, and it is possible to determine a distance between the cutting edge where the linear marker is cut by the milling edge, wherein the distance is determined relative to the alignment marker.

[0043] Furthermore the ion beam can hit the top surface for the generation of the milling region at a milling edge, wherein the linear marker is cut at the milling edge at a cutting edge, and a distance between the cutting edge and the alignment marker is determined.

[0044] The application relates to the following clauses:

[0045] Clause 1 : A semiconductor (20) sample comprising:

[0046] - a top surface (24) including a milling region to be milled by an ion beam hitting the top surface,

[0047] - a plurality of protective layers (210-260) located on the top surface and distributed over the top surface, wherein each protective layer is generated such that it covers a surface area of the top surface,

[0048] - a linear marker (310-360)provided on each of the protective layers, wherein at least 2 of the linear markers have a defined positional relationship relative to one another, wherein each of the protective layers is dimensioned such that the surface area has a width perpendicular to a longitudinal direction of the linear marker that is smaller than 10 times a width of the corresponding linear marker.

[0049] Clause 2: The semiconductor sample of clause 1 , wherein the each of the protective layers is dimensioned such that the protective layer has a length, in a longitudinal direction of the linear marker, beyond each end of the linear marker that is smaller than 10 times the width of the linear marker.

[0050] Clause 3: The semiconductor sample of clause 1 or 2, wherein each of the protective layers is dimensioned such that the surface area has a width perpendicular to a longitudinal direction of the linear marker that is smaller than 5 times the width of the corresponding linear marker, preferably 3 times the width of the corresponding linear marker.

[0051] Clause 4: The semiconductor sample of any preceding clause, wherein the plurality of protective layers encircle a marking region on the top surface of the semiconductor sample, wherein the milling region comprises a regio of interest on the top surface, wherein the region of interest is located outside the marking region.

[0052] Clause 5: A method for generating a semiconductor sample, the method comprising:

[0053] - providing the semiconductor sample having a top surface with a milling region to be milled by an ion beam hitting the top surface,

[0054] - generating a plurality of protective layers located on the top surface in such a way that they are distributed over the top surface, wherein each protective layer is generated such that it covers a surface area of the top surface,

[0055] - providing, on each of the protective layers, a linear marker, wherein at least 2 of the linear markers have a defined positional relationship relative to one another, wherein each of the protective layers is dimensioned such that the surface area has a width perpendicular to a longitudinal direction of the linear marker that is smaller than 10 times a width of the corresponding linear marker.

[0056] Clause 6: The method of clause 5, wherein the each of the protective layers is dimensioned such that the protective layer has a length, in a longitudinal direction of the linear marker, beyond each end of the linear marker that is smaller than 10 times the width of the linear marker.

[0057] Clause 7: The method of clause 5 or 6, wherein the plurality of protective layers encircle a marking region on the top surface of the semiconductor sample, wherein the milling region comprises a regio of interest on the top surface, wherein the region of interest is located outside the marking region.

[0058] Clause 8: The method of any of clauses 5 to 7, wherein each of the protective layers is dimensioned such that the surface area has a width perpendicular to a longitudinal direction of the linear marker that is smaller than 5 times the width of the corresponding linear marker, preferably 3 times the width of the corresponding linear marker.

[0059] Clause 9: A method for generating a semiconductor sample, the method comprising

[0060] - providing a semiconductor sample having a top surface with a milling region to be milled by an ion beam hitting the top surface,

[0061] - providing a plurality of markers directly on the top surface of the semiconductor sample.

[0062] Clause 10: The method of clause 9, wherein each of the marker is a linear marker generated by depositing material directly on the top surface of the semiconductor sample.

[0063] Clause 11 : The method of clause 9, wherein one of the plurality of markers is a linear marker and another marker of the plurality of markers is an alignment marker.

[0064] Clause 12: The method of clause 11 , wherein the ion beam hits the top surface for the generation of the milling region at a milling edge, wherein the linear marker is cut at the milling edge at a cutting edge, and a distance between the cutting edge and the alignment marker is determined.

[0065] Clause 13: A semiconductor sample comprising:

[0066] - a top surface with a milling region to be milled by an ion beam hitting the top surface,

[0067] - a plurality of markers directly on the top surface of the semiconductor sample.

[0068] Clause 14: The semiconductor sample of clause 13, wherein each of the marker is a linear marker generated by depositing material directly on the top surface of the semiconductor sample.

[0069] Clause 15: The semiconductor sample of clause 13, wherein one of the plurality of markers is a linear marker and another marker of the plurality of markers is an alignment mark

[0070] List of reference numerals

[0071] 1 dual beam device

[0072] 10 support table

[0073] 20 wafer

[0074] 21 , 22 measurement site

[0075] 24 wafer surface

[0076] 40 imaging system 42 optical axis 44 ion beam

[0077] 48 FIB optical axis

[0078] 50 FIB generating unit

[0079] 51 FIB ion beam

[0080] 52, 53 cross section surface 55 wafer surface

[0081] 59 region of interest

[0082] 60 control unit

[0083] 70 operation control unit

[0084] 80 control unit

[0085] 90 wafer stage

[0086] 100 imaging system

[0087] 160 inspection volume

[0088] 170 cutting edge

[0089] 171 cutting edge

[0090] 210-260 protective layer

[0091] 280 marking region

[0092] 310-360 linear marker

[0093] 341 , 342 representations

[0094] 350 linear marker

[0095] 410 - 440 linear marker

[0096] 510 protective layer

[0097] 515 cutting edge 520 alignment mark

[0098] S71-S73 processing steps S81 , S82 processing steps

Claims

Claims1. A method for generating a semiconductor sample, the method comprising- providing a semiconductor sample having a top surface with a milling region to be milled by an ion beam hitting the top surface,- providing a plurality of markers directly on the top surface of the semiconductor sample.

2. The method of claim 1 , wherein each of the marker is a linear marker generated by depositing material directly on the top surface of the semiconductor sample.

3. The method of claim 1 , wherein one of the plurality of markers is a linear marker and another marker of the plurality of markers is an alignment marker.

4. The method of claim 3, wherein the ion beam hits the top surface for the generation of the milling region at a milling edge, wherein the linear marker is cut at the milling edge at a cutting edge, and a distance between the cutting edge and the alignment marker is determined.

5. The method of claim 4, wherein the determined distance is used to determine a progress of the milling at the milling region.

6. A semiconductor sample comprising:- a top surface with a milling region to be milled by an ion beam hitting the top surface,- a plurality of markers directly on the top surface of the semiconductor sample.

7. The semiconductor sample of claim 6, wherein each of the marker is a linear marker generated by depositing material directly on the top surface of the semiconductor sample.

8. The semiconductor sample of claim 6, wherein one of the plurality of markers is a linear marker and another marker of the plurality of markers is an alignment mark9. A semiconductor (20) sample comprising:- a top surface (24) including a milling region to be milled by an ion beam hitting the top surface,- a plurality of protective layers (210-260) located on the top surface and distributed over the top surface, wherein each protective layer is generated such that it covers a surface area of the top surface,- a linear marker (310-360)provided on each of the protective layers, wherein at least 2 of the linear markers have a defined positional relationship relative to one another, wherein each ofthe protective layers is dimensioned such that the surface area has a width perpendicular to a longitudinal direction of the linear marker that is smaller than 10 times a width of the corresponding linear marker.

10. The semiconductor sample of claim 9, wherein the each of the protective layers is dimensioned such that the protective layer has a length, in a longitudinal direction of the linear marker, beyond each end of the linear marker that is smaller than 10 times the width of the linear marker.

11. The semiconductor sample of claim 9 or 10, wherein each of the protective layers is dimensioned such that the surface area has a width perpendicular to a longitudinal direction of the linear marker that is smaller than 5 times the width of the corresponding linear marker, preferably 3 times the width of the corresponding linear marker.

12. The semiconductor sample of any of claims 9 to 11 , wherein the plurality of protective layers encircle a marking region on the top surface of the semiconductor sample, wherein the milling region comprises a regio of interest on the top surface, wherein the region of interest is located outside the marking region.

13. A method for generating a semiconductor sample, the method comprising:- providing the semiconductor sample having a top surface with a milling region to be milled by an ion beam hitting the top surface,- generating a plurality of protective layers located on the top surface in such a way that they are distributed over the top surface, wherein each protective layer is generated such that it covers a surface area of the top surface,- providing, on each of the protective layers, a linear marker, wherein at least 2 of the linear markers have a defined positional relationship relative to one another, wherein each of the protective layers is dimensioned such that the surface area has a width perpendicular to a longitudinal direction of the linear marker that is smaller than 10 times a width of the corresponding linear marker.

14. The method of claim 13, wherein the each of the protective layers is dimensioned such that the protective layer has a length, in a longitudinal direction of the linear marker, beyond each end of the linear marker that is smaller than 10 times the width of the linear marker.

15. The method of claim 13 or 14, wherein the plurality of protective layers encircle a marking region on the top surface of the semiconductor sample, wherein the milling region comprisesa regio of interest on the top surface, wherein the region of interest is located outside the marking region.

16. The method of any of claims 13 to 15, wherein each of the protective layers is dimensioned such that the surface area has a width perpendicular to a longitudinal direction of the linear marker that is smaller than 5 times the width of the corresponding linear marker, preferably 3 times the width of the corresponding linear marker.

Images