Lossy line molded article, method for producing same, and method for using same

Abstract

[Problem] In digital circuits, problems relating to crosstalk, noise due to signal reflection, electromagnetic compatibility, decoupling of power supply distribution circuits, and parallel transmission of data signals remain unsolved, and it is imperative that these be solved. [Solution] In fig. 1, formed in a region surrounded by a peripheral region of an inner peripheral part of a rectangular region on both sides of a conversion-treated aluminum foil 1a are: conductive stress relaxation films 4a, 4b; semiconductor films 3a, 3b which overlap the conductive stress relaxation films; and conductive paste films 2a, 2b which overlap the semiconductor films. A lossy line chip is formed by cutting at the boundary line of the rectangular region. A lead frame is mounted to the lossy line chip. A hermetic seal is formed in a state with a terminal exposed to form a low impedance lossy line component. A matched impedance lossy line component and a low impedance lossy line component according to the present invention are used as respectively mounted to a signal circuit and a power supply distribution circuit of a multilayer printed circuit board.

Description

Lossy line molding and its manufacturing method and use

[0001] The present invention relates to a lossy line molded product, and more particularly to a lossy line molded product used in a power distribution circuit that supplies DC power to active elements such as semiconductor integrated circuits that function in digital circuits, which are a type of switching mode circuit, and in a signal transmission circuit for active elements such as semiconductor integrated circuits.

[0002] For IT-related equipment that uses digital circuits, active research and development is being conducted to achieve compliance with IEC / CISPR standards regarding electromagnetic interference issues, strengthen power supply decoupling and reduce the impedance of power supply lines on printed wiring boards on which active elements such as semiconductor integrated circuits are mounted, eliminate crosstalk problems in signal circuits on printed wiring boards and in interface cables between multiple printed wiring boards, improve the signal quality of signal circuits on printed wiring boards, and increase the transmission speed (BPS) of data signals.

[0003] The document states that power supply decoupling capacitors on the printed circuit board that mounts the MPU are important for ensuring reliable operation, and that connecting bulk capacitors such as large-capacity aluminum electrolytic capacitors to the power supply lines is effective for dealing with the relatively long, sudden changes in power supply current of the MPU, which occur over a period of 50 ns to 300 ns. It also states that using multiple capacitors totaling 1 mF and 0.01 μF bypass capacitors on the power supply lines near the MPU is effective for dealing with the sudden current fluctuations in the power distribution circuit that accompany high-speed operation of the MPU at 10 ns or less. This guideline set out by semiconductor manufacturers is widely supported and adopted by capacitor manufacturers, digital circuit engineers, and researchers in related fields around the world. (See Non-Patent Document 1.)

[0004] When using bypass or decoupling capacitors on power lines, the ultimate decoupling effect occurs when the power trace and the common ground plane are short-circuited by a via. While this condition cannot be achieved in practice, it can be achieved with transmission lines with a characteristic impedance of 50 ohms, which are commonly used in measurement systems. The measured frequency characteristics of the transmission coefficient S21 in this case are shown in Figure 4.4.b in Chapter 4. This figure can be considered to represent the high-frequency limit of the bypass or decoupling capacitor. In the typical case where a two-terminal decoupling capacitor is connected in parallel to a power line, the transmission line length is zero, so no internal loss, which is a type of transmission loss, occurs. The entire measured transmission coefficient S21 value is the reflection loss occurring between the decoupling capacitor and the power line. Based on the above findings, the calculated frequency characteristics of the transmission coefficient S21 when a 0.1 μF multilayer ceramic capacitor (MLCC) is connected to a parallel-plate line in a power distribution circuit on a typical multilayer printed wiring board with a characteristic impedance of 3 ohms, are shown in Figure 8.23.b in Chapter 8. This figure shows that when a decoupling capacitor is used in the power supply line of a multilayer printed circuit board using the conventional method, the reflection loss is significantly reduced and the decoupling effect is hardly exhibited (see Non-Patent Document 2).

[0005] According to the theory of isolated electromagnetic waves (SEMW) described in Chapter 5, transistors constituting active elements in semiconductor integrated circuits excite SEMWs, and in the case of voltage-source circuits, the electric field waves that constitute the SEMWs form signal voltages. The power supply impedance acts on the SEMWs, affecting the signal voltage waveform integrity (SI). The duration of the SEMWs that form high-speed signal voltages is generally less than 1 nanosecond. According to the definition of modified critical frequency (MSF) described in Section 5.6 of Chapter 5, the reciprocal of the value obtained by multiplying the duration Ts of the SEMW by π is MSF, so the frequency of the SEMWs that form high-speed signal voltages can be said to be 0.3 GHz or higher. The impossibility of using capacitors to lower the impedance of a power distribution circuit in this frequency band is shown as a conventional PCB in Figure 8.23.b of Chapter 8 (see Non-Patent Document 2).

[0006] According to the theory of electromagnetic physics that governs the behavior of digital circuits, electromagnetic waves propagate through signal lines. Electromagnetic waves propagate unidirectionally through the insulators that make up the signal line, but cannot propagate through conductors. In many cases, signal lines are formed using a microstrip line structure on a multilayer printed wiring board. In this case, electromagnetic wave leakage is likely to cause crosstalk interference between adjacent signal lines. According to SEMW theory, even if the excited SEMW significantly attenuates immediately after excitation, it has no effect on the signal voltage. Chapter 7 presents the theory and experimental results of the matched impedance loss line (MILL) technology, which demonstrates that increasing the transmission loss of the signal line significantly attenuates SEMW while maintaining signal integrity. Applying MILL technology to digital signal lines suppresses crosstalk interference and signal voltage bounce due to electromagnetic wave reflection, thereby improving signal integrity (SI). (See Non-Patent Document 2)

[0007] A technology has been disclosed for forming an alternating-deposition type decoupling device in which multiple capacitor elements are stacked and connected in series to suppress leakage of unwanted electromagnetic waves from the power supply terminals of active elements such as semiconductor integrated circuits. The capacitor elements used are large-capacity capacitors using valve metals, such as tantalum capacitors. However, for reasons explained in Non-Patent Document 2, this two-terminal structure decoupling device is unable to exert much of a decoupling effect on the power supply line (see Patent Document 1).

[0008] The transmission line structure is formed by an insulating layer and two conductor layers sandwiching the insulating layer. One conductor layer uses chemically etched aluminum foil, which has etched portions on both sides and a chemically formed oxide film on the surface that acts as an insulator. A functional polymer laminate film is then formed on the etched surface. This creates a large capacitance, but the carbon paste applied to attenuate electromagnetic waves traveling through the transmission line cannot penetrate the etching pits due to its large particles. As a result, there is almost no internal loss within the etching pits, and reflection loss becomes dominant. When used in power lines on a typical multilayer printed wiring board, the transmission coefficient S21 at frequencies below 100 MHz is comparable to that of a high-capacity conductive polymer aluminum solid electrolytic capacitor. Power lines on typical multilayer printed wiring boards often use high-capacity conductive polymer aluminum solid electrolytic capacitors to protect against relatively long-term sudden power current changes (50 ns to 300 ns) and momentary power interruptions at connectors. Therefore, the formation of a functional polymer laminate film within the etching pit, which exhibits effective characteristics below 100 MHz, is completely unnecessary. (See Patent Documents 2 and 3.)

[0009] A two-terminal capacitor cannot act on electromagnetic waves flowing from a semiconductor device into a decoupling circuit for the reasons described in Non-Patent Document 2, and therefore cannot effectively lower the impedance seen from the semiconductor device or achieve high-frequency decoupling effects (see Patent Documents 4 and 5).

[0010] A structure having ground pattern surfaces sandwiched above and below a circuit pattern provided on an inner layer of a multilayer printed wiring board, and having ground pattern surfaces that are perpendicular to and in contact with the ground pattern surfaces of the upper and lower layers so as to sandwich the left and right sides of the circuit pattern, requires additional crosstalk suppression measures to be taken in the connectors and cables for signals input and output to the multilayer printed wiring board, and also increases the power consumption of the signal driving circuit by reducing the circuit impedance (see Patent Document 6).

[0011] However, in digital signal circuits, the electromagnetic waves that cause crosstalk exist only for extremely short periods during the rising and falling portions of the signal voltage, and the period is indefinite, making it virtually impossible to effectively utilize the technology relating to a crosstalk reduction circuit comprising a first generating means for generating a first compensating signal from an input signal, a second generating means for generating a second compensating signal from the output signal, and a combining means for combining the first and second compensating signals with the output signal to generate an output signal in which crosstalk has been reduced and compensated (see Patent Document 7).

[0012] When the relative permittivity of the signal conductor of a multilayer printed circuit board is εr and the relative permeability is μr, it is nearly impossible to achieve the effect of a technique for suppressing crosstalk with adjacent wiring and radiation noise by using a structure in which the signal conductor is surrounded by a first insulator that satisfies μr≧εr, or a technique for suppressing crosstalk by forming a multilayer printed circuit board with a wiring layer that covers the signal line with a coating material made of a magnetic material, in the signal transmission lines of a general digital circuit that operates with a DC voltage source, because the signal voltage is formed by electric field waves that travel through transmission lines with a fixed characteristic impedance, and magnetic field waves that travel through the transmission line cannot be involved in signal formation at all (see Patent Documents 8 to 9).

[0013] A method of having a plurality of pads arranged in a straight line at a predetermined pitch, a plurality of through holes arranged in parallel along the arrangement direction of the pads, and a wiring pattern connecting the pads and the through holes, and arranging the lines connecting the two through holes through which each of a pair of differential signals constituting a differential signal pair passes at an angle to the arrangement direction of the pads, may have a certain effect on a printed wiring board, but unless sufficient crosstalk suppression measures are taken in the input / output connectors and cables of the printed wiring board, the crosstalk suppression effect cannot be achieved in the signal transmission path system (see Patent Document 10).

[0014] JP 2012-142553 JP 2015-198482 JP 3856671 JP 2006-128284 US-20230267256-A1 JP 5-121892 JP 2811622 JP 4130883 JP 5595153 JP 6844035

[0015] “Pentium Processor With Voltage Reduction Technology: Power Supply Design Considerations for Mobile Systems” by Intel, APPLICATION NOTE, AP-519, June 1997. Hirokazu Tohya, “Solitary Electromagnetic Wave Theory and Lossy Line Technologies for Switching Mode Circuit”, 1st ed; BP International, Guest House Road, Street no-1 / 6, Hooghly, West Bengal, India, 2023; Print ISBN: 978-81-19761-09-8, E-ISBN: 978-81-19761-34-0, DOI: 10.9734 / bpi / mono / 978-81-19761-09-8.

[0016] Digital circuits, a type of switching-mode circuit, have the following unresolved problems caused by electromagnetic waves excited by switching elements, preventing the full potential of digital circuits from being realized: Crosstalk on printed wiring boards and cables cannot be suppressed (Problem 1); Bounce noise and spike noise caused by signal reflection cannot be effectively suppressed (Problem 2); Electromagnetic interference to the surrounding area caused by unwanted electromagnetic waves leaking from the power supply terminals of active elements such as semiconductor integrated circuits cannot be effectively suppressed (Problem 3); Power supply impedance seen from the power supply terminals of active elements such as semiconductor integrated circuits cannot be further reduced (Problem 4); and stagnation in digital data signal transmission speeds cannot be overcome (Problem 5).

[0017] The present invention aims to fundamentally solve all of these problems and relates to the commercialization of lossy line technology developed based on the SEMW physics theory shown in Non-Patent Document 2. When the lossy line molded product according to the present invention is used in IT-related devices, including digital devices, in the manner shown in this patent, it solves all five of the above problems, and simultaneously improves the quality and simplifies design and manufacturing.

[0018] In order to solve the above problems, the present invention provides the following means.

[0019] The invention of claim 1 relates to a lossy line molded product used in a switching mode circuit including a digital circuit, characterized in that a first lossy line chip comprises: a first rectangular region formed on both sides of a first chemically converted aluminum foil; a second rectangular region formed in a first peripheral region on the inner periphery of the first rectangular region and having a first horizontal side, a second horizontal side, a first vertical side, and a second vertical side; a first conductive stress relaxation film formed on the surface of the second rectangular region; a first semiconductor film formed on the surface of the first conductive stress relaxation film or a second semiconductor film formed on the surface of the second rectangular region; and a first conductive paste film or a second conductive paste film formed on the surface of the first semiconductor film or the second semiconductor film, and is formed by cutting along the boundary line of the first rectangular region.

[0020] The invention of claim 2 relates to a lossy line molded product, and is characterized in that in the lossy line molded product of claim 1, the second lossy line chip comprises: a third rectangular region formed on one side of the second chemically formed aluminum foil; a fourth rectangular region formed in a second peripheral region on the inner periphery of the third rectangular region and having a third horizontal side, a fourth horizontal side, a third vertical side, and a fourth vertical side; a third conductive stress relaxation film formed on the surface of the fourth rectangular region; a third semiconductor film formed on the surface of the third conductive stress relaxation film; a fourth semiconductor film formed on the other side of the chemically formed aluminum foil; and a fourth conductive paste film or a third conductive paste film formed on the surface of the fourth semiconductor film or the third semiconductor film, respectively, and is formed by cutting along the boundary line of the third rectangular region.

[0021] The invention of claim 3 relates to a loss line molded product, and is characterized in that in the loss line molded product of claims 1 and 2, a first loss line laminated chip is formed by adhering the first conductive paste film or the second conductive paste film of one or more of the first loss line chips to the first conductive paste film or the second conductive paste film on the other side of one or more other of the first loss line chips via a first conductive adhesive film.

[0022] The invention of claim 4 relates to a lossy line molded product, and in the lossy line molded product of claims 1 to 3, the first lossy line component, the second lossy line component, or the third lossy line component comprises a first lead frame having a first ground terminal and a second ground terminal at both ends attached to the first conductive paste film or the second conductive paste film on one surface of the first lossy line chip, or the third conductive paste film or the fourth conductive paste film on one surface of the second lossy line chip, or the first conductive paste film or the second conductive paste film on one surface of the third lossy line laminated chip, and a third conductive adhesive film a second lead frame having a first power supply terminal and a second power supply terminal at both ends is adhered via a third conductive adhesive film to the first conductive paste film or the second conductive paste film on the other side of the first loss-line chip, or the third conductive paste film or the fourth conductive paste film on the other side of the second loss-line chip, or the first conductive paste film or the second conductive paste film on the other side of the third loss-line laminated chip, and the first ground terminal, the second ground terminal, the first power supply terminal, and the second power supply terminal are hermetically sealed while being exposed.

[0023] The invention of claim 5 relates to a lossy line molded product, and in the lossy line molded product of claims 1 to 4, a fourth lossy line component includes a meander wiring section formed by arranging a plurality of meander wirings of the same type in parallel on one surface of a wiring board, a first copper foil island and a second copper foil island formed at both ends of the meander wiring, a fourth copper foil island and a third copper foil island formed adjacent to the second copper foil island and the first copper foil island, a first signal terminal, a second signal terminal, a third ground terminal, and a fourth ground terminal formed on the other surface of the wiring board, and and copper foil islands or vias at the end of the wiring board formed to connect the second signal terminal, the third copper foil island and the third ground terminal, and the fourth copper foil island and the fourth ground terminal, respectively; a first insulating thin film formed on the entire surface of the wiring board on which the meander wiring is formed excluding the fifth copper foil island and the sixth copper foil island; a fifth semiconductor film formed inside the inner peripheral region of the first insulating thin film; and a fifth conductive paste film formed on the fifth semiconductor film, and the wiring board after film formation is hermetically sealed with the other surface of the wiring board exposed.

[0024] The invention of claim 6 relates to a lossy line molded product, and in the lossy line molded product of claims 1 to 5, the first chemically formed aluminum foil and the second chemically formed aluminum foil are formed without necessarily having etching pits, the first semiconductor film, the second semiconductor film, the third semiconductor film, and the fifth semiconductor film are formed by applying a semiconductor-containing liquid having an area resistance of 20 Ω or less, for example, a carbon paste or an aqueous dispersion of graphene, and then heating and drying the applied liquid, and the fourth semiconductor film is formed by applying a carbon paste having an area resistance of 20 Ω or less and then heating and drying the applied liquid, and the first conductive paste film, the second conductive paste film, the third conductive paste film, the fourth conductive paste film, and the fifth conductive paste film are formed by applying a carbon paste having an area resistance of 20 Ω or less and then heating and drying the applied liquid, and the first conductive paste film, the second conductive paste film, the third conductive paste film, the fourth conductive paste film, and the fifth conductive paste film are formed by applying a carbon paste having an area resistance of 20 Ω or less and then heating and drying the applied liquid, ２The first conductive stress relaxation film, the second conductive stress relaxation film, and the third conductive stress relaxation film are formed by applying and drying a conductive paste having a surface resistance of 25.4 μm thick or less or a volume resistance of 0.5 mΩ cm or less, and the first conductive stress relaxation film, the second conductive stress relaxation film, and the third conductive stress relaxation film are formed by applying and drying a conductive polymer solution, for example a polythiophene solution, having a viscosity of 100 mPa s or more and a particle size of 200 nm or more.

[0025] The invention of claim 7 relates to a lossy line molded product, and in the lossy line molded product of claims 1 to 6, the first lossy line component, the second lossy line component, or the third lossy line component connects the second power supply terminal of the first lossy line component, the second lossy line component, or the third lossy line component to an isolated load-side power supply copper foil island to which a power supply terminal of an active element such as a semiconductor integrated circuit formed on a first multilayer printed wiring board is connected, and A first power supply terminal is connected to a first power receiving trace formed by branching off from a first power receiving island formed on the first multilayer printed wiring board, the first power receiving trace is set to the maximum length and the minimum width within a range that satisfies the allowable current value and is compatible with the layout design conditions of the first multilayer printed wiring board, and the first ground terminal and the second ground terminal of the first lossy line component, the second lossy line component, or the third lossy line component are connected to a common ground copper foil island formed on the first multilayer printed wiring board.

[0026] The invention of claim 8 relates to a lossy line molded product, and is characterized in that in the lossy line molded products of claims 1 to 7, the fourth lossy line component is used by connecting the first signal terminal and the second signal terminal of the fourth lossy line component to two ends formed by cutting a first signal trace formed on a second multilayer printed wiring board in order to transmit a signal from a first signal output terminal of an active element such as a semiconductor integrated circuit mounted on the second multilayer printed wiring board, and by connecting the third ground terminal and the fourth ground terminal of the fourth lossy line component to a common ground copper foil island formed on the second multilayer printed wiring board.

[0027] When the first to third lossy-line components of the present invention are applied as low-impedance lossy-line components to a power distribution circuit of a digital circuit, they prevent most of the large amount of unwanted electromagnetic waves leaking from active elements such as conductive integrated circuits into the power distribution circuit from leaking to the power supply, thereby eliminating electromagnetic interference problems. Furthermore, the terminal impedance seen by active elements such as semiconductor integrated circuits is significantly lower than that of MLCCs connected to conventional parallel-plate power lines, thereby significantly improving the operational stability of active elements such as semiconductor integrated circuits. Furthermore, when the fourth lossy-line component of the present invention is applied as a matching-impedance lossy-line component to a signal transmission circuit of a digital circuit, bounce noise and spike noise caused by crosstalk and signal reflection on printed wiring boards and cables are suppressed, improving signal quality. By maximizing the impedance of the signal wiring connected to the output signal terminal of the matching-impedance lossy-line component, it is possible to reduce the signal drive power of active elements such as conductive integrated circuits to a fraction of the original power. Microwave circuit technology, previously required for high-speed signal lines, is no longer necessary, and ultra-high-speed signal lines can be realized using low-frequency or DC circuit technology. Furthermore, ultra-high speed signal transmission of terabytes per second can be easily achieved using unshielded multi-core cables.

[0028] 1 is an example of a cross section of a lossy-line chip. 2 is an example of a lossy-line chip manufacturing process flow. 3 is an example of a lossy-line chip after a conductive paste film has been formed. 4 is an example of a cross section of a lossy-line chip. 5 is an example of a cross section of a lossy-line laminate chip. 6 is an example of a lossy-line chip to which a lead frame has been bonded. 7 is an example of a lossy-line structure. 8 is an example of a lossy-line component after hermetically sealing. 9 is another example of a lossy-line chip to which a lead frame has been bonded. 10 is another example of a lossy-line structure. 11 is another example of a lossy-line component after hermetically sealing. 12 is an example of a method of mounting on a multilayer printed wiring board. 13 is an example of the characteristics of a lossy-line chip and a lossy-line laminate chip. 14 is an example of one surface and an end surface of a ceramic substrate. 15 is an example of the other surface and an end surface of a ceramic. 16 is an example of one surface of a ceramic substrate after an insulating film has been formed. 17 is an example of one surface of a ceramic substrate after a semiconductor film has been formed. 18 is an example of one surface of a ceramic substrate after a conductive paste film has been formed. 19 is an example of a terminal surface of a lossy-line component after hermetically sealing. 19 is an example of the characteristics of a lossy-line component.

[0029] The present invention will be described in detail below with reference to the accompanying drawings. The drawings used in the following description may show characteristic portions enlarged for the sake of clarity, and the dimensional proportions of each component may differ from the actual proportions. Furthermore, the materials, dimensions, etc. exemplified in the following description are merely examples, and the present invention is not limited thereto. Appropriate modifications can be made within the scope of the present invention.

[0030] {Loss Line Chip (Embodiment 1)} The film formation manufacturing process for the loss line chip according to embodiment 1 will be described with reference to FIGS. 1, 2, and 3. In step 6a shown in FIG. 2, a first conductive polymer aqueous solution containing poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) as a main component and having a viscosity of 100 mPa·s or more and a particle size of 200 nm or more is applied to the surface layer of a line region inside the peripheral region of the inner periphery of a rectangular region formed on both sides of an unetched chemically formed aluminum foil or an etched chemically formed aluminum foil, and then heated and dried to form conductive stress relaxation films 4a and 4b shown in FIG. 1. In step 6b shown in FIG. 2, a carbon paste or graphene aqueous dispersion is applied to the surfaces of the conductive stress relaxation films 4a and 4b shown in FIG. 1 and then dried to form semiconductor films 3a and 3b. In step 6c shown in FIG. 2, a first conductive polymer aqueous solution having a viscosity of 5 Pa·s or more and a particle size of 0.1 Ω / cm is applied to the surfaces of the conductive stress relaxation films 4a and 4b shown in FIG. 1. ２ A conductive paste having a surface resistance of 25.4 μm or less is applied and dried to form conductive paste films 2 a and 2 b, completing the film-forming process. In step 6 d shown in FIG. 2 , the formed chemically converted aluminum foil is cut along the boundary lines of the rectangular region to form the lossy line chip according to the first embodiment.

[0031] If it is anticipated that maintaining the insulation of the chemical conversion film near the boundary of the rectangular region of the film-formed chemically converted aluminum foil is difficult, an insulating film is formed around the inner periphery of the rectangular region formed on both sides of the chemically converted aluminum foil piece before proceeding to the step shown in Figure 2. The conductive stress relief films 4a and 4b are used to prevent damage to the chemical conversion film of the chemically converted aluminum foil by the metal particles contained in the carbon paste film, which may expand and contract during the heating and drying process during the carbon paste film formation process in step 6b. Therefore, for example, if a semiconductor film containing carbon paste is formed on a chemically converted aluminum foil with a chemical conversion film formed at approximately 48 V or higher, step 6b shown in Figure 2 is unnecessary. In Figure 3, the rectangular region surrounded by sides 5a and 5b of the conductive paste film 2c on both sides of the chemically converted aluminum foil piece 1b forms a loss line.

[0032] {Loss Line Chip (Embodiment 2)} In Figure 4, the process of forming a conductive stress relaxation film 4c, a semiconductor film 3c, and a conductive paste film 2d on the upper surface of a chemically formed aluminum foil 1c is the same as in Embodiment 1. On the lower surface of the chemically formed aluminum foil piece 1c, a semiconductor film 3d using carbon paste and a conductive paste film 2e are formed over the entire surface in the same manner as in Embodiment 1. The chemically formed aluminum foil that has undergone the above manufacturing process is cut along the boundary line of the rectangular region to form a loss line chip according to Embodiment 2. If a conductive stress relaxation film is not used on the lower surface of the loss line chip, the chemically formed film of the chemically formed aluminum foil will be damaged by the formation of the carbon paste film, resulting in the formation of a loss line only on the upper surface of the loss line chip according to Embodiment 2. Therefore, in Embodiment 2, a chemically formed aluminum foil having a relatively thin chemically formed film at a voltage of approximately 20 V or less is used.

[0033] {Loss-Line Laminated Chip (Embodiment 3)} In Fig. 3, the conductive paste films on one surface of the loss-line chip 7a and the loss-line chip 7b according to embodiment 1 are bonded via a conductive adhesive film 8a to form a loss-line laminated chip according to embodiment 3. In embodiment 3, two loss-line chips are stacked, but it is possible to form the chip by stacking three or more chips within the allowable values ​​of terminal impedance and chip thickness. In the loss-line laminated chip according to embodiment 3, the terminal impedance, rated voltage, and chip thickness increase depending on the number of layers, but there is almost no increase or decrease in the rated current and transmission coefficient S21.

[0034] {Loss-Line Component (Embodiment 4)} In Fig. 6, a loss-line chip 7c, which is a general term for the loss-line chip according to embodiment 1, the loss-line chip according to embodiment 2, or the loss-line laminate chip according to embodiment 3, has a conductive paste film on one surface of the loss-line chip 7c attached to one surface of a lead frame 9a via a conductive adhesive film. In Fig. 7, a loss-line chip 7d has one surface attached to one surface of the lead frame 9c, and a lead frame 9b is attached to the conductive paste film on the other surface of the loss-line chip 7d via a conductive adhesive film 8b. In Fig. 8, the surfaces are separated by an insulating film 16a using a solder resist film, and power terminals 10a and 10b and ground terminals 10c and 10d formed on the other surface of the lead frame 9c are exposed. The lead frame and the loss-line chip are then hermetically sealed with an airtight sealant 11a, forming a loss-line component according to embodiment 4. In Fig. 8, the terminals 10a and 10b can also be located at the ends of the other surface of the lead frame 9c without using the insulating film 16a.

[0035] In Fig. 9, a conductive paste film on one surface of a loss-line chip 7e according to any one of the first to third embodiments is attached to one surface of a lead frame 9d via a conductive adhesive film. In Fig. 10, a lead frame 9d is attached via a conductive adhesive film 8c to the conductive paste film on the other surface of a loss-line chip 7f, one surface of which is attached to a lead frame 9e. In Fig. 11, the lead frame and the loss-line chip are hermetically sealed with a hermetic sealant 11b, with power supply terminals 10e and 10f formed on both ends of the lead frame 9e and ground terminals 10g and 10f formed on both ends of the lead frame 9d exposed, thereby forming a loss-line component according to the fourth embodiment.

[0036] In FIG. 12 , an active component 17a such as a semiconductor integrated circuit, lossy-line components 19a and 19b, and a bulk capacitor 12a such as a conductive polymer aluminum solid electrolytic capacitor are mounted on a multilayer printed wiring board 18a, and the ground terminals of the active component 17a such as a semiconductor integrated circuit and the lossy-line components 19a and 19b are connected to a copper foil island 20a for common grounding by vias, the power supply terminal of the active component 17a such as a semiconductor integrated circuit and one power supply terminal of the lossy-line components 19a and 19b are connected to the copper foil island 20b on the power distribution side by vias, and the other power supply terminal of the lossy-line components 19a and 19b is connected to traces 15a and 15b on the power receiving side by vias. The power receiving side traces 15a, 15b are connected directly or via a power receiving side copper foil island to a DC power supply mounted on the multilayer printed wiring board 18a or to a DC power supply device installed outside the multilayer printed wiring board 18a, and the bulk capacitor 12a is connected to the power receiving side copper foil island or trace and copper foil island 20a via a via. No MLCCs are connected to the power distribution side copper foil island 20b or the power receiving side traces 15a, 15b. In Figure 12, the copper foil size of the power receiving side traces 15a, 15b satisfies the allowable current value and is set to the maximum and minimum values ​​of length and width determined by the layout design of the multilayer printed wiring board. However, if no analog circuit elements are connected to the power distribution side copper foil island 20b, the power supply line will only contain isolated electromagnetic waves equivalent to a sine wave of several tens of gigahertz and an electrostatic field that charges and discharges the line due to the isolated electromagnetic wave effect, so there is no need to consider the current value. Furthermore, it is desirable to make the opposing distance between the traces 15a, 15b and the copper foil island 20a as long as possible to increase the impedance, and it is desirable to make the opposing distance between the copper foil island 20b and the copper foil island 20a as short as possible to decrease the impedance.

[0037] 13, 21a and 22a are examples of the transmission coefficient (S21) characteristics and terminal impedance (Zt) characteristics of an MLCC having a capacitance of 0.1 μF connected to the power supply layer and ground layer of a typical multilayer printed wiring board, 21b and 22b are examples of the characteristics of a lossy-line component incorporating a lossy-line chip according to embodiment 3, 21c and 22c are examples of the S21 characteristics and Zt characteristics of a lossy-line component incorporating a lossy-line chip according to embodiment 2, and 22d and 22d are examples of the S21 characteristics and Zt characteristics of a lossy-line component incorporating a lossy-line chip according to embodiment 1. All of the characteristic examples are based on the assumption that the length of side 5a of the lossy-line chip shown in FIG. 3 is 1.2 mm and the length of side 5b is 5 mm, and that the lossy-line chip is mounted on a multilayer printed wiring board in accordance with the method shown in FIG. The switching time characteristics of the terminal impedance (Zt) in FIG. 13 are obtained by converting the frequency axis of the frequency characteristics obtained according to conventional electromagnetic physics theory into the time axis using f=1 / πt defined in 5.6 MODIFIED SIGNIFICANT FREQUENCY (MSF) (modified effective frequency) of Non-Patent Document 2, where the time t corresponds to the gate delay or the time required for switching of a transistor connected to the power supply layer of the multilayer printed wiring board.

[0038] According to Section 3.1.3 Conclusions in Chapter 3, Discussion of EMI Problems, of Non-Patent Document 2, the transmission coefficient value of a lossy-line component in a power distribution circuit that does not cause EMI problems, i.e., a low-impedance lossy-line component, is estimated to be -40 dB or less. In Figure 13, the transmission coefficient S21 of the lossy-line component incorporating the lossy-line chip according to embodiment 3, shown in 21b, is the largest (or has the lowest decoupling performance), with a maximum value of -45 dB at 20 MHz. Since the transmission coefficient characteristics of the lossy-line chip are known to be bidirectional, it has the same decoupling effect not only on unwanted electromagnetic waves leaking from active components such as semiconductor integrated circuits, but also on unwanted electromagnetic waves entering from the outside. Therefore, using the lossy-line components according to embodiments 1 to 3 in the power distribution circuits of IT-related equipment is likely to resolve EMC problems. The transmission coefficient decreases approximately in proportion to the length of side 5b of the lossy-line chip shown in Figure 3.

[0039] The lower the terminal impedance of the power supply, the better for active elements such as semiconductor integrated circuits. According to the SEMW physics theory described in Non-Patent Document 2, the power supply impedance affects the SEMW excited by active elements such as semiconductor integrated circuits during their switching time, which in turn affects the quality of the signal voltage waveform (SI) formed by the SEMW. According to the ITRS (International Transceiver Standards for Semiconductors), the Ts of high-performance MPUs at the 1999 (180 nm) technology node is 18 ps, and the gate delay (switching time) of active elements such as semiconductor integrated circuits used in current digital circuits is significantly shorter than this value. The power distribution circuit of a high-performance MPU is optimally equipped with a lossy line component incorporating a lossy line chip according to embodiment 2, and its Zt characteristics are shown in Figure 22d. In this case, the Zt value between 10 Ps and 100 Ps is 0.02 Ω or less, more than an order of magnitude lower than the terminal impedance when using an MLCC as shown in Figure 22a. Furthermore, the Zt characteristics of 22b and 22c of loss-line components incorporating the loss-line chip according to embodiment 1 and the loss-line laminated chip according to embodiment 3, which are suitable for active elements operating at a power supply voltage of 12 V or more, are 0.15 Ω when Ts is 0.5 ns, for example, which is half the terminal impedance shown in 22a when an MLCC is used. Therefore, it is estimated that the use of the loss-line component according to embodiment 4 will further improve the stable operation of active elements such as semiconductor integrated circuits.

[0040] The characteristic curve shown in Figure 13 was obtained based on the evaluation results of a prototype, using the calculation formula shown in Non-Patent Document 2 and the calculation conditions shown below. The common calculation conditions for the lossy line are as follows: the chemically formed aluminum foil used is 110LJB23B-11Vf, with a rated voltage of 8V; the dielectric constant of the chemically formed aluminum film is 8.5 and the film thickness is 16.9nm; the conductivity of the conductive stress relaxation film is 7 x 1E3 S / m and the film thickness is 0.5µm; the conductivity of the semiconductor film is 6,670 S / m and the film thickness is 7µm; and the conductivity of the conductive paste film is 2.5 x 1E6 S / m and the film thickness is 10µm. The average thickness of the voids in the laminated film is 20nm; the lengths of the vertical side 5a and horizontal side 5b of the line portion of the lossy line chip shown in Figure 3 are 0.3mm and 5mm, respectively. The common calculation conditions for the printed wiring board on which the low-impedance lossy line component is mounted are as follows: A typical eight-layer board is used, with a layer structure of (mixed power and signal), (signal), (ground), (signal), (signal), (ground), (signal), (mixed power and signal). The insulator thickness between the mixed power and signal layer and the ground layer is 0.257 mm, with a relative dielectric constant of 4.1.

[0041] The individual calculation conditions are as follows: When the lossy-line component according to the fourth embodiment is used in the manner shown in Fig. 12, the power receiving copper foil island is a square of 100 mm on each side, the power distribution copper foil island 20b is a square of 40 mm on each side, and the power receiving traces 15a and 15b connected to the power receiving copper foil island are 3 mm wide and 50 mm long when using a lossy-line component incorporating the lossy-line chip according to the first embodiment and the lossy-line laminated chip according to the third embodiment, and are 5 mm wide and 50 mm long when using a lossy-line component incorporating the lossy-line chip according to the second embodiment. A conductive polymer aluminum solid electrolytic capacitor with a capacitance of 2.2 mF, an ESL of 1.5 nH, and an ESR of 50 milliohms was used as the bulk capacitor and connected to the power receiving copper foil island to which the power receiving traces were connected and to the ground plane. An MLCC with a capacitance of 0.1 μF, an ESL of 1.5 nH, and an ESR of zero ohms was connected to the 200 mm square copper foil island and the ground plane along with active devices such as semiconductor integrated circuits. The ESL of the conductive polymer aluminum solid electrolytic capacitor and the MLCC was determined based on the measured frequency characteristics of the transmission coefficient S21 when a microstrip line was short-circuited with a via, as shown in Figure 4.4.b of Chapter 4 of Non-Patent Document 2, rather than the characteristic curve using a coplanar waveguide provided by the capacitor manufacturer. Since the method of connecting an MLCC to a power distribution circuit with a via is common, the transmission coefficient S21 characteristic when the line is short-circuited is considered to represent the high-frequency limit of the capacitor's characteristics.

[0042] {Lossy Line Component (Embodiment 5)} In this embodiment, a ceramic substrate is used as an example of a wiring substrate. In Fig. 14, one surface of a ceramic substrate 13a is provided with an underwiring portion 14a, which is a 5 μm wide, 11.8 mm long, or 22.5 mm long trace, and 16 rows of meander traces, each 2.1 mm long or 3.8 mm long and 0.152 mm wide. A copper foil island 20c is also provided for connection to the ground plane. Also, 25 traces 15c are provided on both sides of the ceramic substrate 13a. The traces 15c connect both ends of the 16 meander traces on one side of the ceramic substrate 13a to 16 signal terminals on the other side of the ceramic substrate 13a, and also connect nine ground copper foil islands on one side of the ceramic substrate 13a to ground terminals on the other side of the ceramic substrate 13a on the left and right sides. In Fig. 15, the other surface of a ceramic substrate 13b is provided with 16 signal terminals 10m, nine ground terminals 10n, and traces 15d on both sides.

[0043] In Fig. 16, a 2 μm-thick insulating film 16b made of polyimide is formed on one surface of a ceramic substrate 13c in a rectangular region excluding the edges of nine copper foil islands 20d for grounding. In Fig. 17, a semiconductor film 3e is formed inside the inner peripheral region of the insulating film of the ceramic substrate 13d, including the edges of the nine copper foil islands for grounding. In Fig. 18, a conductive paste film 2f is formed on the surface of the semiconductor film of the ceramic substrate 13e. In Fig. 19, five surfaces of the ceramic substrate 13f on which the thin film has been formed are hermetically sealed with a hermetic sealant 11b, leaving the terminal surface on which nine ground terminals 10p and 16 signal terminals 10o are formed exposed, thereby completing the lossy line component.

[0044] FIG. 20 shows an example of the transmission coefficient S21 characteristic and terminal impedance Zt characteristic when the lossy-line component according to the fifth embodiment is mounted on a multilayer printed wiring board as a matching impedance lossy-line component together with an active element such as a semiconductor integrated circuit, the signal terminal of the lossy-line component connected to one end of a meander wiring is connected to the other end of a trace that is formed as short as possible and has one end connected to the signal output terminal of the active element such as a semiconductor integrated circuit, the signal terminal of the lossy-line component connected to the other end of the meander wiring is connected to a trace for signal transmission on the multilayer printed wiring board, and a pair of ground terminals of the lossy-line component are connected to a common ground copper foil island on the multilayer printed wiring board.

[0045] 20, 21e shows the transmission coefficient characteristic of one meander wiring formed by a trace having a width of 5 μm and a length of 11.8 mm that constitutes the meander wiring portion of the lossy-line component according to embodiment 5, 21f shows the transmission coefficient (S21) characteristic of one meander wiring formed by a trace having a width of 5 μm and a length of 22.5 mm, and 21g shows the transmission coefficient (S21) characteristic of one meander wiring formed by a trace having a width of 5 μm and a length of 45 mm. In FIG. 20, 22e shows the terminal impedance (Ts) characteristics when the trace lengths of the meander wiring of the lossy-line component according to embodiment 5 are 11.8 mm, 22.5 mm, and 45 mm.

[0046] The characteristic curve in Figure 20 was obtained based on the evaluation results of a prototype, using the calculation formula for lossy lines shown in Non-Patent Document 2 and the following calculation conditions: The insulating film using a polyimide film has a relative dielectric constant of 1.8 and a film thickness of 2 μm; the semiconductor film using carbon paste has a conductivity of 6,670 S / m and a film thickness of 30 μm; and the conductive paste film using silver paste has a conductivity of 2.5 × 1E6 S / m and a film thickness of 10 μm. The characteristic impedance of the signal trace and signal cable is 76.4 Ω. When mounted on a multilayer printed wiring board, the length of the signal trace connecting the signal output terminal of an active element such as a conductor integrated circuit to the signal terminal at one end of the lossy line component is 10 mm, and the combined length of the signal trace and signal cable connected to the signal terminal at the other end of the lossy line component is 3 m. The characteristics in Figure 20 are shown on the time axis. Figure 20 was obtained by converting the characteristics calculated as a frequency function into a time function using the corrected effective frequency f = 1 / πt defined in Non-Patent Document 2.

[0047] From Chapter 7 of Non-Patent Document 2, 7.4 VERIFICATION OF EFFECT VENESS OF USING FOUR 2M LONG 9-CORE MILL CABLE, it is estimated that if the transmission coefficient value of the lossy line component according to embodiment 7, i.e., the matching impedance lossy line component, is −30 dB or less, crosstalk and bounce can be suppressed. Applying this assumption to Figure 20, the characteristic curve 21e shows that the matching impedance lossy line component functions effectively when the switching time of the signal driving element is 0.21 nanoseconds or less, or the 1-bit transfer rate is 3 gigabytes / second or more, or the bus clock is 1.5 gigahertz or more, while the characteristic curve 21f shows that the matching impedance lossy line component functions effectively when the switching time of the signal driving element is 0.42 nanoseconds or less, or the 1-bit transfer rate is 1.6 gigabytes / second or more, or the bus clock is 0.78 gigahertz or more, and the characteristic curve 21f shows that the matching impedance lossy line component functions effectively when the switching time of the signal driving element is 0.89 nanoseconds or less, or the 1-bit transfer rate is 0.74 gigabytes / second or more, or the bus clock is 0.37 gigahertz or more. The terminal impedance (Zt) characteristics of 22e shown in FIG. 20 are almost independent of the length of the meander wiring and are almost equal to the characteristic impedance of the signal line of a typical multilayer printed wiring board. Therefore, the lossy line component according to embodiment 7 can be considered to be impedance-matched to the signal line of the multilayer printed wiring board.

[0048] When the lossy-line component according to the fifth embodiment is effectively used, SEMW traveling along the signal line is significantly attenuated, eliminating signal degradation due to crosstalk in printed wiring boards, connectors, and cables between the sending and receiving ends of the signal transmission line, as well as bounce noise and spike noise caused by signal reflection. Furthermore, paired ground wires or ground planes for the signal line of the printed wiring board or signal cable are essentially unnecessary, potentially maximizing the impedance of the signal wiring connected to the output signal terminal of the lossy-line component according to the seventh embodiment and potentially reducing the signal drive power of active elements such as conductive integrated circuits to a fraction of the original power. Since electromagnetic waves interfering with the signal line are also attenuated in the same way, cable shielding may also be eliminated. Furthermore, microwave circuit technology, which was previously required for high-speed signal lines, becomes unnecessary, enabling ultra-high-speed signal transmission using low-frequency and DC circuit design techniques based on AC circuit engineering theory. This potentially enables ultra-high-speed signal transmission at terabytes per second even with single-core multicore cables without paired ground wires.

[0049] 1a, 1b, 1c Chemical aluminum foil piece 2a, 2b, 2c, 2d, 2e, 2f Conductive paste film 3a, 3b, 3c, 3d, 3e Semiconductor film 4a, 4b, 4c Conductive stress relaxation film 5a, 5b Side 6a, 6b, 6c, 6d Manufacturing process 7a, 7b, 7c, 7d, 7e, 7f Loss line chip 8a, 8b, 8c Conductive adhesive film 9a, 9b, 9c, 9d, 9e Lead frame 10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h, 10i, 10j, 10k, 10l, 10n, 10n, 10o, 10p Terminal 11a, 11b Hermetic seal 12a bulk capacitor 13a, 13b, 13c, 13d, 13e, 13f: ceramic substrate; 14a: meander wiring portion; 15a, 15b, 15c, 15d: trace; 16a, 16b: insulating film; 17a: active component such as semiconductor integrated circuit; 18a: multilayer printed wiring board; 19a, 19b: lossy line component; 20a, 20b, 20c, 20d: copper foil island; 21a, 21b, 21c, 21d, 21e, 21f, 21g: transmission coefficient characteristic curve; 22a, 22b, 22c, 22d, 22e: terminal impedance characteristic curve

Claims

1. A lossy line molded product used in a switching mode circuit including a digital circuit, characterized in that a first lossy line chip comprises a first rectangular region formed on both sides of a first chemically converted aluminum foil, a second rectangular region formed in a first peripheral region on the inner periphery of the first rectangular region and having a first horizontal side, a second horizontal side, a first vertical side, and a second vertical side, a first conductive stress relaxation film formed on the surface of the second rectangular region, a first semiconductor film formed on the surface of the first conductive stress relaxation film or a second semiconductor film formed on the surface of the second rectangular region, and a first conductive paste film or a second conductive paste film formed on the surface of the first semiconductor film or the second semiconductor film, and is formed by cutting along the boundary line of the first rectangular region.

2. A lossy line molded product according to claim 1, characterized in that the second lossy line chip comprises a third rectangular area formed on one side of the second chemically formed aluminum foil, a fourth rectangular area formed in a second peripheral area on the inner periphery of the third rectangular area and having a third horizontal side, a fourth horizontal side, a third vertical side, and a fourth vertical side, a third conductive stress relaxation film formed on the surface of the fourth rectangular area, a third semiconductor film formed on the surface of the third conductive stress relaxation film, a fourth semiconductor film formed on the other side of the chemically formed aluminum foil, and a fourth conductive paste film or a third conductive paste film formed on the surface of the fourth semiconductor film or the third semiconductor film, respectively, and is formed by cutting along the boundary line of the third rectangular area.

3. A lossy line component according to claims 1 and 2, characterized in that the first lossy line laminated chip is formed by bonding the first conductive paste film or the second conductive paste film of one or more of the first lossy line chips to the first conductive paste film or the second conductive paste film on the other surface of one or more other of the first lossy line chips via a first conductive adhesive film.

4. In the lossy line molded product according to claims 1 to 3, the first lossy line component, the second lossy line component, or the third lossy line component is configured such that a first lead frame having a first ground terminal and a second ground terminal at both ends is bonded via a third conductive adhesive film to the first conductive paste film or the second conductive paste film on one surface of the first lossy line chip, or the third conductive paste film or the fourth conductive paste film on one surface of the second lossy line chip, or the first conductive paste film or the second conductive paste film on one surface of the third lossy line laminated chip, a second lead frame having a first power supply terminal and a second power supply terminal at both ends thereof, which is adhered via a third conductive adhesive film to the first conductive paste film or the second conductive paste film on the other surface of the line chip, or the third conductive paste film or the fourth conductive paste film on the other surface of the second lossy-line chip, or the first conductive paste film or the second conductive paste film on the other surface of the third lossy-line laminated chip, and hermetically sealed with the first ground terminal, the second ground terminal, the first power supply terminal, and the second power supply terminal exposed, to form a lossy-line molded product, 5. In the lossy line molded product according to claims 1 to 4, the fourth lossy line component comprises a meander wiring section formed by arranging a plurality of meander wirings of the same type in parallel on one surface of a wiring board, a first copper foil island and a second copper foil island formed at both ends of the meander wiring, a fourth copper foil island and a third copper foil island formed adjacent to the second copper foil island and the first copper foil island, a first signal terminal, a second signal terminal, a third ground terminal, and a fourth ground terminal formed on the other surface of the wiring board, and a first copper foil island and a second copper foil island and a third copper foil island and a fourth signal terminal formed adjacent to the first copper foil island and the second copper foil island, a copper foil island or an end via on an end surface of the wiring board formed to connect the fifth copper foil island and the third ground terminal, and the fourth copper foil island and the fourth ground terminal, respectively; a first insulating thin film formed on the entire surface of the wiring board on which the meander wiring is formed, excluding the fifth copper foil island and the sixth copper foil island; a fifth semiconductor film formed inside the inner peripheral region of the first insulating thin film; and a fifth conductive paste film formed on the fifth semiconductor film, wherein the wiring board after film formation is hermetically sealed with the other surface of the wiring board exposed.

6. In the lossy line molded product according to claims 1 to 5, the first chemically formed aluminum foil and the second chemically formed aluminum foil are formed without necessarily having etching pits, the first semiconductor film, the second semiconductor film, the third semiconductor film, and the fifth semiconductor film are formed by applying a semiconductor-containing liquid having an area resistance of 20 Ω or less, such as a carbon paste or an aqueous dispersion of graphene, and then heating and drying, the fourth semiconductor film is formed by applying a carbon paste having an area resistance of 20 Ω or less and then heating and drying, and the first conductive paste film, the second conductive paste film, the third conductive paste film, the fourth conductive paste film, and the fifth conductive paste film have a viscosity of 5 Pa s or more and a resistivity of 0.1 Ω / cm ２ a conductive paste having a surface resistance of 25.4 μm or less or a volume resistance of 0.5 mΩ·cm or less, and then heat-drying the coated film; and the first conductive stress relaxation film, the second conductive stress relaxation film, and the third conductive stress relaxation film are each formed by coating and drying a conductive polymer solution, e.g., a polythiophene solution, having a viscosity of 100 mPa·s or more and a particle size of 200 nm or more.

7. In the lossy line molded product according to claims 1 to 6, the first lossy line component, the second lossy line component, or the third lossy line component connects the second power supply terminal of the first lossy line component, the second lossy line component, or the third lossy line component to an isolated load-side power supply copper foil island to which a power supply terminal of an active element such as a semiconductor integrated circuit formed on a first multilayer printed wiring board is connected, and the first power supply terminal of the first lossy line component, the second lossy line component, or the third lossy line component is connected to the first multilayer printed wiring board. a lossy line molded product connected to a first power receiving trace formed by branching off from a first power receiving island formed on a printed wiring board, the first power receiving trace being set to the maximum length and the minimum width within a range that satisfies a current carrying allowable value and is compatible with the layout design conditions of the first multilayer printed wiring board, and the first ground terminal and the second ground terminal of the first lossy line component, the second lossy line component, or the third lossy line component being connected to a common ground copper foil island formed on the first multilayer printed wiring board.

8. A lossy line molded product according to claims 1 to 7, characterized in that the fourth lossy line component is used by connecting the first signal terminal and the second signal terminal of the fourth lossy line component to two ends formed by cutting a first signal trace formed on a second multilayer printed wiring board in order to transmit a signal from a first signal output terminal of an active element such as a semiconductor integrated circuit mounted on the second multilayer printed wiring board, and by connecting the third ground terminal and the fourth ground terminal of the fourth lossy line component to a common ground copper foil island formed on the second multilayer printed wiring board.

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