Photoelectric device based on alignment bonding, and preparation method therefor

Abstract

The present invention relates to a photoelectric device based on alignment bonding, and a preparation method therefor. The photoelectric device comprises a driving wafer and pixel units, wherein a second insulating layer is arranged on the driving wafer, a first insulating layer is arranged between the second insulating layer and a P-type semiconductor layer, through holes filled with anode metal members are provided in both the first insulating layer and the second insulating layer, the through holes in the first insulating layer and the through holes in the second insulating layer correspond to each other on a one-to-one basis, the anode metal members in the through holes are bonded to each other to form a bonding body, the P-type semiconductor layer is electrically connected to the driving wafer by means of the bonding body, and N-type semiconductor layers in all the pixel units are connected by means of a common cathode. Further disclosed in the present invention is a preparation method for a photoelectric device. The present invention can effectively ensure an anode connection effect and better facilitate arrangement and processing, and can also better avoid electric leakage of the pixel units, thereby improving the reliability of the photoelectric device.

Description

Photoelectric device based on alignment bonding and preparation method thereof

[0001] Priority information: This application claims priority to Chinese patent application No. 2024106990174, filed on May 31, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor technology, in particular to a photoelectric device based on alignment bonding and a preparation method thereof. BACKGROUND

[0003] The pixel unit 40 of the existing LED photoelectric device generally includes a P-type semiconductor layer 4013 and an N-type semiconductor layer 4011, as shown in FIG. 1, the P-type semiconductor layer 4013 needs to be electrically connected with the anode contact 101 of the driving wafer 50, the existing pixel unit 40 usually realizes anode connection by bonding the metal bonding layer 10 and the driving wafer 50, but when there is an insulating medium layer 20 between the P-type semiconductor layer 4013 and the metal bonding layer 10, an electrically conductive anode connecting piece 30 needs to be additionally arranged outside the pixel unit 40 to realize anode communication, which leads to a more complex structure of the photoelectric device and is not easy to process, and once the anode connecting piece deforms or is installed with deviation, the short circuit and leakage phenomenon between the P-type semiconductor layer 4013 and the N-type semiconductor layer 4011 is also easy to occur, thereby causing the LED photoelectric device to fail.

[0004] Therefore, the existing LED photoelectric device anode connection structure is complex and not easy to process, which cannot effectively ensure the convenience of anode connection, and is also easy to cause short circuit and leakage phenomenon, thereby cannot guarantee the use reliability of the LED photoelectric device. SUMMARY

[0005] Therefore, the technical problem to be solved by the present application is to overcome the defects in the prior art that the LED photoelectric device cannot effectively ensure the convenience of anode connection and is easy to cause short circuit and leakage, so as to improve the use reliability of the LED photoelectric device.

[0006] To solve the above technical problems, the present application provides a photoelectric device based on alignment bonding,

[0007] a driving wafer, the driving wafer is provided with a second insulating layer, the second insulating layer is provided with a through hole, and the through hole is filled with an anode metal piece;

[0008] a pixel unit, the pixel unit includes a pixel main body;

[0009] the pixel main body includes a P-type semiconductor layer, an active layer and an N-type semiconductor layer arranged in sequence away from the driving wafer;

[0010] The first insulating layer is also provided with a through hole, and the through hole is filled with an anode metal piece.

[0011] The N-type semiconductor layers in all the pixel units are connected through a common cathode.

[0012] The application further discloses a preparation method of the photoelectric device based on the alignment bonding.

[0013] The driving wafer is prepared so that the second insulating layer is arranged on the driving wafer, the second insulating layer is provided with a through hole, and the through hole is filled with an anode metal piece.

[0014] The compound semiconductor comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer and a first insulating layer which are sequentially arranged away from the substrate; a through hole is arranged on the first insulating layer, and the through hole is filled with an anode metal piece; and the through hole of the second insulating layer corresponds to the through hole of the first insulating layer.

[0015] The anode metal piece in the through hole of the first insulating layer and the anode metal piece in the corresponding through hole of the second insulating layer are bonded to form a bonding main body, so that the P-type semiconductor layer is electrically connected to the driving wafer through the bonding main body.

[0016] The compound semiconductor is processed to form pixel units corresponding to the bonding main body; the pixel units comprise pixel main bodies, and each pixel main body comprises a P-type semiconductor layer, an active layer and an N-type semiconductor layer which are sequentially arranged away from the driving wafer.

[0017] The N-type semiconductor layers in the pixel units are connected to a common cathode.

[0018] Compared with the prior art, the above technical scheme of the application has the following advantages:

[0019] The photoelectric device based on alignment bonding and the preparation method thereof, the through hole of the first insulating layer and the through hole of the second insulating layer are aligned one by one, so that the anode metal piece in the first insulating layer through hole and the corresponding anode metal piece in the second insulating layer through hole are bonded with each other to form a conductive bonding body, which can not only effectively ensure the anode current enhancement effect, but also is more convenient for arrangement and processing, and is also beneficial to avoid the leakage phenomenon in the pixel unit; in addition, the N-type semiconductor layer and the P-type semiconductor layer are insulated by the first wall body layer, which can better avoid the short circuit and leakage phenomenon of the pixel unit, and can effectively improve the use reliability of the photoelectric device. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to make the content of the present application more easily understood, the present application will be further described in detail below according to specific embodiments of the present application and in conjunction with the drawings.

[0021] Fig. 1 is a structural schematic diagram of an LED photoelectric device of the prior art;

[0022] Fig. 2 is a structural schematic diagram of a first embodiment of the photoelectric device of the present application;

[0023] Fig. 3 is a structural schematic diagram of a second embodiment of the photoelectric device of the present application;

[0024] Fig. 4 is a structural schematic diagram of a third embodiment of the photoelectric device of the present application;

[0025] Fig. 5 is a structural schematic diagram of a fourth embodiment of the photoelectric device of the present application;

[0026] Fig. 6 is a structural schematic diagram of a driving light circle of the present application;

[0027] Fig. 7 is a structural schematic diagram of one embodiment of a compound semiconductor of the present application;

[0028] Fig. 8 is a structural schematic diagram of another embodiment of a compound semiconductor of the present application;

[0029] Fig. 9 is a flowchart of the preparation of the photoelectric device using the compound semiconductor shown in Fig. 7 in the present application;

[0030] Fig. 10 is a flowchart of the preparation of the photoelectric device using the compound semiconductor shown in Fig. 8 in the present application;

[0031] Fig. 11 is a preparation flowchart of one embodiment of the photoelectric device of the present application (with a metal mesh grid);

[0032] Explanation of reference numerals in the accompanying drawings: 10, Bonding metal layer; 101, Anode contact; 20, Insulating dielectric layer; 30, Anode connector; 40, Pixel unit; 401, Pixel body; 4011, N-type semiconductor layer; 4012, Active layer; 4013, P-type semiconductor layer; 4014, P-type ohmic contact layer; 402, Outer wall; 4021, First wall layer; 40211, Step portion; 4022, Second wall layer; 50, Driver wafer; 60, First insulating layer; 601, Through-hole; 602, Anode metal component; 6021, Body end; 6022, Extension end; 70, Second insulating layer; 80, Bonding body; 90, Third insulating layer; 100, Common cathode; 110, Metal mesh; 120, Compound semiconductor; 1201, Substrate. Detailed Implementation

[0033] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present disclosure or its application or use.

[0034] In the description of this invention, it should be understood that the terms "vertical," "upper," "lower," "top," "side," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0035] This embodiment provides an optoelectronic device based on alignment bonding and its fabrication method, which can conveniently and effectively realize the anode connection of LED optoelectronic devices, avoid short circuit leakage, and thus improve the reliability of LED optoelectronic devices.

[0036] The structure of this embodiment will be further described below with reference to Figures 2-11.

[0037] Example 1

[0038] Referring to FIG2, this embodiment discloses an optoelectronic device based on alignment bonding, including a driving wafer 50 and a pixel unit 40;

[0039] A second insulating layer 70 is provided on the driving wafer 50, and a through hole 601 is provided on the second insulating layer 70. An anode metal part 602 is filled in the through hole 601.

[0040] Pixel unit 40 includes pixel body 401;

[0041] The pixel body 401 includes a P-type semiconductor layer 4013, an active layer 4012 and an N-type semiconductor layer 4011 sequentially disposed along a direction away from the driving wafer 50; wherein, the active layer 4012 is used to emit light;

[0042] The pixel unit 40 may also be provided with an outer edge wall 402. The outer edge wall 402 is disposed on the side wall of the pixel body 401. The outer edge wall 402 includes a first wall layer 4021. The first wall layer 4021 is an insulator and is attached to the side wall of the pixel body 401.

[0043] The N-type semiconductor layer 4011 and the P-type semiconductor layer 4013 in each pixel unit 40 are insulated from each other by a first wall layer 4021.

[0044] A first insulating layer 60 is also provided between the second insulating layer 70 and the P-type semiconductor layer 4013 of the pixel unit 40. A through hole 601 is also provided on the first insulating layer 60. An anode metal element 602 is filled in the through hole 601. The through holes 601 of the first insulating layer 60 and the through holes 601 of the second insulating layer 70 correspond one to one. The anode metal element 602 in the through hole 601 of the first insulating layer 60 and the corresponding anode metal element 602 in the through hole 601 of the second insulating layer 70 are bonded to each other to form a bonding body 80. The P-type semiconductor layer 4013 is electrically connected to the driving wafer 50 through the bonding body 80.

[0045] In this configuration, the N-type semiconductor layers 4011 in all pixel units 40 are connected by a common cathode 100, which is deposited on the outside of the N-type semiconductor layers 4011.

[0046] In the above structure, by respectively setting a first insulating layer 60 and a second insulating layer 70, the through holes 601 of the first insulating layer 60 and the through holes 601 of the second insulating layer 70 are aligned one by one, so that the anode metal part 602 in the through hole 601 of the first insulating layer 60 and the corresponding anode metal part 602 in the through hole 601 of the second insulating layer 70 are bonded to each other to form a bonding body 80. The bonding body 80 is used to realize the electrical connection between the P-type semiconductor and the driving wafer 50, avoiding the need to set an anode connection structure outside the pixel unit 40. The structure is simpler, which can not only effectively ensure the anode current enhancement effect, but also facilitate the arrangement and processing, and also help to avoid leakage inside the pixel unit 40.

[0047] In addition, by providing an outer edge wall 402 on the side wall of the pixel body 401 of the optical element, the N-type semiconductor layer 4011 and the P-type semiconductor layer 4013 are insulated from each other by the first wall layer 4021, which can better avoid short circuit leakage between the N-type semiconductor layer 4011 and the P-type semiconductor layer 4013, thereby effectively ensuring the reliability of the optoelectronic device.

[0048] Specifically, in the above structure, the common cathode 100 can be deposited outside the first insulating layer 60 and the outer edge wall 402. The common cathode 100 at least partially covers the first insulating layer 60, while the outer edge wall 402 and the pixel body 401 are encased inside the common cathode 100. The N-type semiconductor layer 4011 in the pixel body 401 is electrically connected to the common cathode 100 to achieve cathode conduction.

[0049] In some embodiments, the lengths of the anode metal pieces 602 in the first insulating layer 60 and the anode metal pieces 602 in the second insulating layer 70 can be the same or different. For example, the length of one anode metal piece can be greater than the length of the other anode metal piece. For instance, the length of the anode metal piece 602 in the first insulating layer 60 can be set to be less than the length of the anode metal piece 602 in the second insulating layer 70, or the length of the anode metal piece 602 in the first insulating layer 60 can be set to be greater than the length of the anode metal piece 602 in the second insulating layer 70. This ensures the contact area of ​​the two anode metal pieces, reduces the accuracy requirements for alignment and bonding, makes it easier to reliably bond the two anode metal pieces together, and also helps to enhance the anode connection strength and increase the anode current.

[0050] In one embodiment, the length M1 of the through hole 601 is 0.1 to 0.5 times the length L2 of the pixel body 401, so as to better ensure the connection area of ​​the anode metal part 602.

[0051] In one embodiment, as shown in Figures 3-4, the outer wall 402 further includes a second wall layer 4022, which is attached to the outer wall of the first wall layer 4021 so that there is no gap between them.

[0052] Furthermore, the second wall layer 4022 is either a reflective layer or a conductive layer, or a composite layer composed of a reflective layer and a conductive layer, to enhance optical and electrical functions.

[0053] By setting a reflective layer in the second wall layer 4022, the effect of side reflection can be achieved, which is more conducive to the realization of all-round reflection, greatly improving the brightness of the pixel unit 40 and the collimation of light, and obtaining better performance and a smaller divergence angle.

[0054] By providing a conductive layer in the second wall layer 4022, it is easier to make electrical connections between the pixel unit and other components.

[0055] The reflective layer can be deposited using high-reflectivity metals such as aluminum (Al), silver (Ag), gold (Au), rhodium (Rh), or platinum (Pt).

[0056] The conductive layer can be deposited using highly conductive metals such as aluminum (Al), copper (Cu), tungsten (W), and titanium (Ti).

[0057] The second wall layer 4022 can also be a stack of transparent conductive layer and metal layer, such as silver or titanium tungsten film layer superimposed on zinc oxide.

[0058] In one embodiment, as shown in FIG3, a step portion 40211 is formed at one end of the first wall layer 4021 near the driving wafer 50, and a second wall layer 4022 is located on the step portion 40211.

[0059] In another embodiment, as shown in FIG4, the end of the first wall layer 4021 near the driving wafer 50 may also adopt a stepless portion 40211 structure.

[0060] In one embodiment, a P-type ohmic contact layer 4014 is further disposed between the P-type semiconductor layer 4013 and the first insulating layer 60.

[0061] The materials of the aforementioned P-type ohmic contact layer 4014 include single or stacked layers of transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO), or single or stacked layers of metals such as Ni, Cr, Au, Ag, Zn, Be, and Al (nickel, chromium, gold, silver, zinc, beryllium, and aluminum), or alloys, or stacked layers of transparent metal oxides and metals.

[0062] In one embodiment, the angle θ between the pixel body 401 and the first insulating layer 60 is about 90°, specifically 60° to 120°, preferably 75° to 105°.

[0063] In one embodiment, the length L2 of the pixel body 401 is 0.5um to 50um.

[0064] The length direction is perpendicular to the "direction away from the drive unit", as shown in Figure 1.

[0065] In one embodiment, the thickness L1 of the first wall layer 4021 is 50 nm to 1500 nm. This thickness range allows for the maximization of the dielectric layer thickness required for omnidirectional reflective structures that meet different wavelength requirements while achieving ideal insulating coverage.

[0066] In one embodiment, a metal mesh 110 is provided on both sides of each pixel unit 40. The metal mesh 110 is electrically connected to the common cathode 100 so as to enhance the cathode current through the metal mesh 110.

[0067] Furthermore, the common cathode 100 can be one or more of the following combinations: ITO (indium tin oxide), AZO (zinc aluminum oxide), ATO (tin antimony oxide), and FTO (tin dioxide doped with fluorine), or a metal stack formed by depositing thin Al, Au, or Ag on the ITO surface and then annealing it to enhance the current transport capability of the common cathode layer.

[0068] This embodiment also discloses a method for fabricating an optoelectronic device based on alignment bonding, including,

[0069] 1) Prepare a driving wafer 50, as shown in Figure 6, such that a second insulating layer 70 is provided on the driving wafer 50, and the second insulating layer 70 is provided with a through hole 601. The through hole 601 is filled with metal to form an anode metal part 602; this process can be prepared by the damascus process.

[0070] And to prepare a compound semiconductor 120, as shown in FIG7, the compound semiconductor 120 includes a substrate 1201, and an N-type semiconductor layer 4011, an active layer 4012, a P-type semiconductor layer 4013 and a first insulating layer 60 sequentially formed along a direction away from the substrate 1201.

[0071] A through hole 601 is provided on the first insulating layer 60, and the through hole 601 is filled with metal to form an anode metal part 602. The through holes 601 of the second insulating layer 70 correspond one-to-one with the through holes 601 of the first insulating layer 60. This process can be prepared by the damascus process.

[0072] The material of the anode metal part 602 may include one or more of TiN (titanium nitride), Al (aluminum), TaN (tantalum nitride) and Cu (copper).

[0073] 2) As shown in stage a of Figure 9, the anode metal part 602 in the through hole 601 of the first insulating layer 60 and the corresponding anode metal part 602 in the through hole 601 of the second insulating layer 70 are bonded together to form a bonding body 80, so that the P-type semiconductor layer 4013 is electrically connected to the driving wafer 50 through the bonding body 80.

[0074] 3) As shown in stage b of Figure 9, the compound semiconductor 120 is processed to form a pixel unit 40 corresponding to the bonding body 80;

[0075] The pixel unit 40 includes a pixel body 401 and an outer edge wall 402. The outer edge wall 402 is disposed on the side wall of the pixel body 401 and includes a first wall layer 4021, which is an insulator and is attached to the side wall of the pixel body 401. Each pixel body 401 includes a P-type semiconductor layer 4013, an active layer 4012, and an N-type semiconductor layer 4011 arranged sequentially along the direction away from the driving wafer 50. The N-type semiconductor layer 4011 and the P-type semiconductor layer 4013 in each pixel unit 40 are insulated from each other by the first wall layer 4021.

[0076] 4) As shown in stage e of Figure 9, the N-type semiconductor layer 4011 in the pixel unit 40 is connected to the common cathode 100 to realize the connection of the cathode and connect to the outside world through the common cathode 100.

[0077] Specifically, a common cathode 100 can be formed by depositing a transparent conductive film on the N-type semiconductor side of all pixel units 40 through sputtering, evaporation, or other methods.

[0078] In this context, the pixel unit 40 and the bonding body 80 can be in one-to-one correspondence, or multiple bonding bodies 80 can correspond to one pixel unit 40.

[0079] Among them, compound semiconductor 120 usually refers to a compound formed by two or more elements. For example, the compound semiconductor 120 here is mainly a light-emitting diode epitaxial material, such as the InGaN ternary material system or the AlGaInP quaternary material system, etc., whose emission wavelength can cover the entire band from ultraviolet, visible light and infrared.

[0080] Taking the Micro-LED field as an example, some compound materials involved in this embodiment are shown in Table 1 below. In some practical applications, the film layers of the compounds are more complex, or there is cross-use of materials, mainly including P-type semiconductor layer materials, N-type semiconductor layer materials, and active layer (MQW quantum well) sandwiched between the two:

[0081] Table 1. Film Material Table for Each Compound

[0082] In one embodiment, a method for processing the compound semiconductor 120 to form a pixel unit 40 corresponding to the bonding body 80 includes the following steps:

[0083] Step S1) Remove the substrate 1201 of the compound semiconductor 120;

[0084] In one embodiment, after removing the substrate 1201, the compound semiconductor 120 can be thinned to expose the N-type semiconductor layer 4011, so as to facilitate the fabrication of a patterned etching mask on the N-type semiconductor layer 4011.

[0085] Step S2) As shown in stage b of Figure 9, the compound semiconductor 120 is etched by the first etching method. During the etching, the first insulating layer 60 is used as the etching stop layer. After etching, the pixel body 401 corresponding to the bonding body 80 is obtained.

[0086] The first etching method mentioned above is either dry etching or wet etching.

[0087] Step S3) As shown in stage c of Figure 9, a first wall layer 4021 is deposited on the outside of the pixel body 401, and the first wall layer 4021 is etched using a dry etching method. As shown in stage d of Figure 9, after etching, only the first wall layer 4021 located on the side wall of the pixel body 401 is retained.

[0088] In one embodiment, a second wall layer 4022 is also provided outside the first wall layer 4021. In step S3), the second wall layer 4022 can be prepared in the following two ways: one is the overall etching method, and the other is the layered etching method.

[0089] The overall etching method is as follows: In step S3), after depositing the first wall layer 4021 on the outside of the pixel body 401, the second wall layer 4022 needs to be deposited. After all the deposition is completed, the overall structure composed of the first wall layer 4021 and the second wall layer 4022 is etched using a dry etching method. After etching, only the first wall layer 4021 and the second wall layer 4022 located on the side wall of the pixel body 401 are retained.

[0090] In the pixel unit 40 structure obtained by the above preparation method, a step portion 40211 is formed at the end of the first wall layer 4021 near the driving unit, and the second wall layer 4022 is located on the step portion 40211, as shown in Figure 3.

[0091] For example, the ce stage in Figure 10 uses a global etching method. In stages e-f of Figure 10, a mask etching method can be used to etch the top wall layer to expose the N-type semiconductor layer, and then a common cathode 100 can be fabricated so that the common cathode 100 and the N-type semiconductor layer are in contact. Alternatively, in stage e of Figure 10, a maskless method can be used to etch the first wall layer 4021 and the second wall layer 4022 located on the sidewall of the pixel body 401 in one go, with a gap in the middle to expose the N-type semiconductor layer. Then, the common cathode 100 can be fabricated so that the common cathode 100 and the N-type semiconductor layer are in contact.

[0092] The layered etching method is as follows: In step S3), after depositing the first wall layer 4021 on the outside of the pixel body 401, the first wall layer 4021 is first etched using a dry etching method. After etching, only the first wall layer 4021 located on the side wall of the pixel body 401 is retained. Then, a second wall layer 4022 is deposited on the outside of the first wall layer 4021. After the deposition is completed, the second wall layer 4022 is etched using a dry etching method. After etching, only the second wall layer 4022 located on the side wall of the pixel body 401 is retained.

[0093] In the pixel unit 40 structure obtained by the above preparation method, there is no step portion 40211 between the first wall layer 4021 and the second wall layer 40223, as shown in Figure 4.

[0094] The fabrication method of the outer edge wall 402 of the aforementioned pixel unit does not require the use of a photolithography machine during fabrication. Instead, it adopts a dry etching method, which eliminates the need for more advanced photolithography machines and eliminates the need for exposure processes. This avoids the defects caused by patterning failure, large overlay offset, and high production cost caused by using a photolithography machine for patterning etching in the prior art. At the same time, it can effectively ensure the fabrication accuracy and achieve in-situ or self-alignment type accuracy. Submicron accuracy is achieved using micron-level equipment and processes.

[0095] In one embodiment, after the pixel unit 40 is fabricated, a metal mesh 110 is formed on both sides of each pixel unit 40. The metal mesh 110 can be fabricated before the common cathode 100 is fabricated, or it can be fabricated after the common cathode 100 is fabricated.

[0096] In one embodiment, both the first insulating layer 60 and the second insulating layer 70 comprise one or more of silicon oxide, aluminum oxide, silicon nitride, titanium oxide, or niobium oxide.

[0097] In one embodiment, the first wall layer 4021 comprises one or more of silicon oxide, aluminum oxide, silicon nitride, titanium oxide, or niobium oxide.

[0098] Example 2

[0099] As shown in Figure 5, the main difference between this embodiment and Embodiment 1 is that the anode metal member 602 of one of the first insulating layer 60 or the second insulating layer 70 includes a body end 6021 and an extension end 6022. The body end 6021 is located inside the through hole 601, and the extension end 6022 is formed on the body end 6021. The length of the extension end 6022 is greater than the length of the body end 6021. Alternatively, the anode metal member 602 of both the first insulating layer 60 and the second insulating layer 70 includes a body end 6021 and an extension end 6022.

[0100] The length direction is perpendicular to the "direction away from the drive unit", as shown in Figure 5.

[0101] The above structure, through the setting of the extended end 6022, increases the contact area of ​​the anode metal part 602, reduces the accuracy requirements of alignment and bonding, and is easier to implement. It also helps to enhance the anode connection strength and enhance the anode current.

[0102] Preferably, the method of forming through holes 601 on the first insulating layer 60 and / or the second insulating layer 70 and filling them with metal material to form the anode metal part 602 can be a double damask process.

[0103] In one embodiment, the extended end 6022 of the anode metal part 602 in the bonding body 80 is located between the first insulating layer 60 and the second insulating layer 70 to better ensure connection reliability.

[0104] Furthermore, a third insulating layer 90 is provided between the first insulating layer 60 and the second insulating layer 70, and the extended end 6022 is located in the third insulating layer 90.

[0105] In one embodiment, the third insulating layer 90 comprises one or more of silicon oxide, aluminum oxide, silicon nitride, titanium oxide, or niobium oxide.

[0106] The extended end 6022 can serve as a metal reflective layer to ensure bottom surface reflection while maintaining an anode connection, thereby enhancing the reflective effect of the pixel unit 40 and improving its light emission intensity and brightness.

[0107] In one embodiment, the length of the extension end 6022 is M2 and the length of the pixel body 401 is L2, so M2≥0.5*L2, thereby better ensuring the anode connection strength and increasing the anode current.

[0108] Furthermore, the length M1 of the through hole 601 is 0.1 to 0.5 times the length L2 of the pixel body 401, that is, M1 = (0.1 to 0.5) * L2.

[0109] As shown in Figure 10, this embodiment also discloses a method for fabricating an optoelectronic device based on alignment bonding. This method is basically the same as that in Embodiment 1, except that when fabricating the compound semiconductor 120 and / or the driving wafer 50, an anode metal part 602 including a body end 6021 and an extension end 6022 needs to be fabricated. The structure of the compound semiconductor 120 is shown in Figure 8. The fabrication method of this optoelectronic device will not be described in detail here.

[0110] Example 3

[0111] As shown in Figure 11, the main difference between this embodiment and Embodiment 1 is that: each pixel unit 40 is further provided with a metal mesh 110 on both sides, the metal mesh 110 is electrically connected to the common cathode 100, and the metal mesh 110 is located between the common cathode 100 and the first insulating layer 60, so as to facilitate the fabrication and at the same time ensure the reliability of the connection.

[0112] Furthermore, there is a gap between the metal mesh 110 and the adjacent pixel unit 40.

[0113] As shown in stage a of Figure 11, when the metal grid 110 is fabricated, the second wall layer 4022 can be utilized. If the second wall layer 4022 is a conductive layer, then when etching the second wall layer 4022, in addition to retaining the second wall layer 4022 at the sidewall of the pixel body, the portion of the second wall layer 4022 located on the upper part of the first insulating layer 60 and away from the pixel unit 40 can also be retained and used as the metal grid 110. That is, the metal grid 110 is formed on both sides of each pixel unit 40, and there is a gap between the metal grid 110 and the adjacent pixel unit 40. This method can maximize the utilization of the deposited second wall layer 4022 and also simplify the fabrication process of the metal grid 110.

[0114] After the metal mesh 110 is prepared, as shown in stage b of Figure 11, a common cathode 100 is deposited on the outside of the second wall layer 4022, so that the metal mesh 110 is located between the common cathode 100 and the bonding body 80, so as to play the role of electrical enhancement of cathode connection.

[0115] It is understandable that other methods can be used to prepare the metal mesh 110, or the common cathode 100 can be prepared first, and then the metal mesh 110 can be prepared.

[0116] The above embodiments, based on the alignment and bonding optoelectronic devices and their fabrication methods, align the through-holes in the first insulating layer and the second insulating layer one by one. This allows the anode metal components in the through-holes of the first insulating layer and the corresponding anode metal components in the through-holes of the second insulating layer to bond together to form a conductive bonding body. This not only effectively ensures the anode current enhancement effect but also facilitates arrangement and processing. In addition, the N-type semiconductor layer and the P-type semiconductor layer are insulated from each other by the first wall layer, which can better prevent short-circuit leakage in the pixel unit and effectively improve the reliability of the optoelectronic device.

[0117] All the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of the present invention. That is, any number of embodiments can be combined to meet the needs of different application scenarios. All of these are within the protection scope of this application and will not be described in detail here.

[0118] It should be noted that the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. An optoelectronic device based on aligned bonding, characterized by: The pixel unit comprises a pixel body. The pixel body comprises, in sequence from the driving wafer, a P-type semiconductor layer, an active layer, and an N-type semiconductor layer. The first insulating layer and the second insulating layer are provided with anode metal pieces. The anode metal pieces in the first insulating layer and the second insulating layer are bonded to form a bonding body. The N-type semiconductor layers in all the pixel units are connected through a common cathode. The pixel unit further comprises an outer wall body provided on the side wall of the pixel body.

2. The optoelectronic device based on alignment bonding of claim 1, wherein: The first wall body layer is an insulator and is attached to the side wall of the pixel body.

3. The aligned-bonding based optoelectronic device of claim 1, wherein: The anode metal pieces of the first insulating layer and / or the second insulating layer comprise a body end located in the through hole and an extension end formed on the body end.

4. The aligned-bonding based optoelectronic device of claim 3, wherein: The extension end of the anode metal piece in the bonding body is located between the first insulating layer and the second insulating layer.

5. The aligned bonded optoelectronic device of claim 3, wherein: A third insulating layer is provided between the first insulating layer and the second insulating layer, and the extension end is located in the third insulating layer.

6. The aligned-bonding based optoelectronic device of claim 3, wherein: The length of the extension end is not less than 0.5 times the length of the pixel body.

7. The aligned-bonding based optoelectronic device of claim 1, wherein: The length of the through hole is 0.1-0.5 times the length of the pixel body.

8. The aligned-bonding based optoelectronic device of claim 2, wherein: The outer wall body further comprises a second wall body layer attached to the outer wall of the first wall body layer.

9. The aligned-bonding based optoelectronic device of claim 8, wherein: The second wall body layer is one of a reflective layer or a conductive layer, or a composite layer composed of a reflective layer and a conductive layer.

10. The aligned-bonding based optoelectronic device of claim 8, wherein: The first wall body layer is provided with a step portion at one end close to the driving wafer, and the second wall body layer is located on the step portion.

11. The aligned-bonding based optoelectronic device of claim 1, wherein: Each of the pixel units is further provided with a metal mesh grid, and the metal mesh grid is electrically connected to the common cathode.

12. The aligned-bonding based optoelectronic device of claim 11, wherein: The metal mesh grid is located between the common cathode and the first insulating layer.

13. A method of fabricating an optoelectronic device based on aligned bonding, the method comprising: The pixel unit comprises a pixel body. ​ The pixel body comprises, in sequence from the driving wafer, a P-type semiconductor layer, an active layer, and an N-type semiconductor layer. The first insulating layer and the second insulating layer are provided with anode metal pieces. The anode metal pieces in the first insulating layer and the second insulating layer are bonded to form a bonding body. The N-type semiconductor layers in all the pixel units are connected through a common cathode. The anode metal piece in the through hole of the first insulating layer and the corresponding anode metal piece in the through hole of the second insulating layer are bonded to each other to form a bonding body, so that the P-type semiconductor layer is electrically connected to the driving wafer through the bonding body; The compound semiconductor is processed to form a pixel unit corresponding to the bonding body; the pixel unit includes a pixel body, and each pixel body includes, in sequence from the driving wafer, a P-type semiconductor layer, an active layer, and an N-type semiconductor layer; The N-type semiconductor layer in the pixel unit is connected to a common cathode.

14. The production method according to claim 13, characterized by: The pixel unit includes the pixel body and an outer wall body arranged on the side wall of the pixel body, the outer wall body includes a first wall body layer, the first wall body layer is an insulator, and the first wall body layer is attached to the side wall of the pixel body; the N-type semiconductor layer and the P-type semiconductor layer in each pixel unit are insulated from each other by the first wall body layer.

15. The production method according to claim 14, characterized by: A method for processing a compound semiconductor to form a pixel unit corresponding to the bonding body, comprising, Step S1), removing the substrate of the compound semiconductor; Step S2), etching the compound semiconductor by a first etching method, taking the first insulating layer as an etching stop layer, and obtaining a pixel body corresponding to the bonding body after etching; Step S3), depositing a first wall body layer outside the pixel body, and etching the first wall body layer by a dry etching method, and only retaining the first wall body layer located at the side wall of the pixel body after etching.

16. The method of claim 15, wherein: In step S3), after depositing the first wall body layer outside the pixel body, a second wall body layer is also deposited, and after the deposition is completed, the entire structure composed of the first wall body layer and the second wall body layer is etched by a dry etching method, and only the first wall body layer and the second wall body layer located at the side wall of the pixel body are retained after etching. Alternatively, after depositing the first wall body layer outside the pixel body, the first wall body layer is etched by a dry etching method, and only the first wall body layer located at the side wall of the pixel body is retained after etching, and then a second wall body layer is deposited outside the first wall body layer, and after the deposition is completed, the second wall body layer is etched by a dry etching method, and only the second wall body layer located at the side wall of the pixel body is retained after etching.

17. The method of claim 14, wherein: When forming the anode metal piece in the through hole of the first insulating layer during the preparation of the compound semiconductor, the anode metal piece includes a body end and an extension end formed on the body end, the body end is located in the through hole, and the length of the extension end is greater than the length of the body end.

18. The method of claim 16, wherein: When the anode metal piece in the through hole of the first insulating layer and the corresponding anode metal piece in the through hole of the second insulating layer are bonded to each other to form a bonding body, the extension end of the anode metal piece in the bonding body is located between the first insulating layer and the second insulating layer.

19. The method of claim 14, wherein: Before the N-type semiconductor layer in the pixel unit is connected with the common cathode, a metal mesh gate is formed on both sides of each pixel unit, the metal mesh gate is deposited on the first insulating layer, and then a common cathode is prepared outside the pixel unit, and the metal mesh gate is located between the common cathode and the first insulating layer.

20. The method of claim 13, wherein: The first insulating layer and the second insulating layer each include one or more of silicon oxide, aluminum oxide, silicon nitride, titanium oxide or niobium oxide.

Images