Shielding method and device for error-correcting code (ECC) fault of random access memory (RAM)

By detecting and converting the ECC fault address of RAM and masking its index position, the problem of high resource overhead in ECC fault repair in existing technologies is solved, thereby improving stability and cost-effectiveness. It is applicable to various RAMs and chips.

WO2025246624A1PCT designated stage Publication Date: 2025-12-04SANECHIPS TECH CO LTD
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Patent Information

Application Number
PCT/CN2025/086983
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-05-28
Filing Date
2025-04-02
Publication Date
2025-12-04

AI Technical Summary

Technical Problem

Existing technologies require additional hardware and software resources to repair ECC faults, and cannot prevent the recurrence of ECC faults, which affects the normal operation of automotive chips.

Method used

By detecting the RAM, the addresses of ECC faults that can be skipped are recorded, converted into readable and writable addresses, and their locations are calculated based on the RAM's table entry information. If they are in a preset table entry, their index positions are masked to prevent further ECC faults from occurring.

Benefits of technology

It reduces the overhead of hardware and software resources, avoids the recurrence of ECC failures, improves the stability of error correction and reduces costs, and is applicable to different chips and RAMs.

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Abstract

Embodiments of the present invention provide a shielding method and device for an error-correcting code (ECC) fault of a random access memory (RAM), comprising: detecting an RAM, and recording an ECC fault address that can be skipped; converting the ECC fault address into a readable / writable ECC fault address; on the basis of entry information and readable / writable ECC fault address of the RAM, calculating an entry where the readable / writable ECC fault address is present; on the basis of the entry where the readable / writable ECC fault address is present, calculating an index position of the readable / writable ECC fault address; if the readable / writable ECC fault address is in a preset entry, determining the readable / writable ECC fault address as a target ECC fault address; and shielding an index position of the target ECC fault address. The present invention solves the problems that additional resource overhead is required for ECC fault repair and repeated generation of ECC faults cannot be avoided.
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Citation Information

Patent Citations

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