Light-emitting module

Abstract

A light-emitting module. The light-emitting module comprises: a substrate (2), a chip array (3) disposed on the substrate (2), a dam (4) covering the periphery of the chip array (3), a light conversion layer (5) disposed above the chip array (3), and an encapsulation layer (6) covering the periphery of the dam (4), wherein the chip array (3) is provided with a plurality of P electrodes (32) and a plurality of N electrodes (31), and a supporting adhesive (8) is filled between the plurality of P electrodes (32) and the plurality of N electrodes (31).

Description

Light-emitting module

[0001] This application claims priority to the Chinese patent application No. 202410726111.4, filed on June 5, 2024, to the Chinese Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, for example, to a light-emitting module. BACKGROUND

[0003] Digital car light is one of the main technologies in the current automotive industry. Based on digital car light to achieve high-brightness display effect and patterned light effect, the current main method is to realize the display effect of digital car through the digital light processing (DLP) technology of digital micromirror device (DMD).

[0004] Since the DLP technology is a million-level pixel display, it achieves fine lighting partitioning and ultra-high-definition imaging projection effect. Multiple light-emitting chips need to be integrated on the car light, which leads to complex optical structure design of the car light, and the light between multiple light-emitting chips is easy to appear the problem of light mixing, which affects the light efficiency of the digital car light.

[0005] SUMMARY

[0006] The present application provides a light-emitting module, which is based on double-layer packaging and chip array cooperation to simplify the optical structure of the car light, fill the support glue between the plurality of P electrodes and the plurality of N electrodes of the chip array, improve the light output contrast of the chip array, and thus improve the light efficiency of the light-emitting module.

[0007] The present application provides a light-emitting module, which comprises a substrate, a chip array arranged on the substrate, a dam arranged around the chip array, a light conversion layer arranged above the chip array, and a packaging layer arranged around the dam.

[0008] The chip array is provided with a plurality of P electrodes and a plurality of N electrodes, and the plurality of P electrodes and the plurality of N electrodes are filled with support glue.

[0009] In one or more embodiments, the dam is a transparent glue layer, the packaging layer is a black glue layer, or the packaging layer is a white glue layer.

[0010] In one or more embodiments, the height of the dam is h1, the height of the light conversion layer is h2, and the constraint relationship between h1 and h2 is h1≥h2.

[0011] In one or more embodiments, the substrate is a silicon-based circuit board, a driving circuit is arranged on the silicon-based circuit board, and the plurality of light-emitting chips of the chip array are electrically connected to the driving circuit.

[0012] In one or more embodiments, the light-emitting module further comprises a transition carrier plate, the substrate is arranged on the transition carrier plate, and the substrate is electrically connected to an external circuit board based on the transition carrier plate.

[0013] In one or more embodiments, the coefficient of thermal expansion of the transition carrier plate is between the coefficient of thermal expansion of the substrate and the coefficient of thermal expansion of the external circuit board.

[0014] In one or more embodiments, the transition carrier plate is provided with a metal electrode, the substrate is provided with a connecting electrode, and the metal electrode of the transition carrier plate and the connecting electrode on the substrate are electrically connected based on a wire.

[0015] In one or more embodiments, the metal electrode, the connecting electrode, and the wire are contained in the packaging layer.

[0016] In one or more embodiments, the chip array comprises a chip main structure, and the chip main structure comprises, in sequence, a buffer layer, an N-type semiconductor layer, a quantum well layer, a P-type semiconductor layer, and an electrode transition layer.

[0017] The chip main structure is formed with the plurality of P electrodes and the plurality of N electrodes.

[0018] In one or more embodiments, the chip main structure is provided with a plurality of wire grooves, and the chip main structure is formed with a plurality of protrusions arranged in an array based on the wire grooves.

[0019] The array structure of the plurality of protrusions comprises a plurality of N-pole protrusions and a plurality of P-pole protrusions, a P electrode is formed on the P-pole protrusion, the plurality of P electrodes form a P electrode array, an N electrode is formed on the N-pole protrusion, and the plurality of N electrodes are arranged at the outer edge of the P electrode array.

[0020] In one or more embodiments, a transition column is arranged between the P electrode array and the plurality of N electrodes, and the transition column is provided with a plurality of transition electrodes.

[0021] In one or more embodiments, the P electrode, the N electrode, and the transition electrode have the same height.

[0022] In one or more embodiments, the N electrode comprises a first electrode layer disposed on the N pole boss and an N pole soldering point disposed on the first electrode layer, one side of the first electrode layer extending to the bottom of the wire slot along the sidewall of the N pole boss;

[0023] The P electrode comprises a second electrode layer disposed on the P pole boss and a P pole soldering point disposed on the second electrode layer.

[0024] In one or more embodiments, the slotting depth of any of the wire slots extends to the N type semiconductor layer,

[0025] The first electrode layer of the N electrode extends to the N type semiconductor layer, and any of the P electrodes is connected with the N type semiconductor layer and the first electrode layer of the N electrode, forming a light emitting chip structure.

[0026] In one or more embodiments, a transition column is disposed between the P electrode array and the plurality of N electrodes, and a plurality of transition electrodes are disposed on the transition column, the transition column being arranged to separate the P electrode array and the plurality of N electrodes.

[0027] In one or more embodiments, the chip array further comprises a current guiding layer disposed in at least one of the plurality of wire slots. BRIEF DESCRIPTION OF DRAWINGS

[0028] FIG. 1 is a structural schematic diagram of a light emitting module in an embodiment of the present application;

[0029] FIG. 2 is a cross-sectional view of a chip array structure in an embodiment of the present application;

[0030] FIG. 3 is a schematic diagram of a current guiding layer structure in an embodiment of the present application;

[0031] FIG. 4 is a schematic diagram of another structure state of a current guiding layer in an embodiment of the present application;

[0032] FIG. 5 is a schematic diagram of a chip array and substrate connection structure in an embodiment of the present application;

[0033] FIG. 6 is a structural top view of a chip array in an embodiment of the present application;

[0034] FIG. 7 is another structural top view of a chip array in an embodiment of the present application;

[0035] FIG. 8 is yet another structural top view of a chip array in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. The described embodiments are only some of the embodiments of the present application, rather than all the embodiments.

[0037] FIG. 1 shows a structural schematic diagram of a light-emitting module in an embodiment of the present application, which includes a substrate 2, a chip array 3 arranged on the substrate 2, a dam 4 wrapped around the chip array 3, a light conversion layer 5 arranged above the chip array 3, and a packaging layer 6 wrapped around the dam 4. The light conversion layer 5 is arranged to convert the light color of the chip array 3 into another light-emitting wavelength band. Based on the chip array 3 integrating a plurality of light-emitting chip structures, the double-layer packaging structure ensures the structural stability and reliability of the light-emitting module, thereby simplifying the structural design of the light-emitting module.

[0038] For example, the dam 4 is a transparent adhesive layer. In an embodiment of the present application, the dam 4 is formed based on a transparent adhesive layer, which avoids the case that the dam 4 absorbs heat to cause excessive heat accumulation on the light-emitting surface of the light-emitting module when the dam 4 is a black adhesive layer, and avoids the case that the dam 4 reflects the light emitted by the chip array 3 and causes stray light when the dam 4 is a white adhesive layer. That is, the dam 4 formed based on a transparent adhesive layer can support and protect the light conversion layer 5, reduce the influence of the dam 4 on the light emitted by the chip array 3, and ensure that the chip array 3 has good light efficiency.

[0039] In one or more embodiments, the packaging layer 6 can be a black adhesive layer. The black adhesive layer can be an adhesive layer doped with carbon powder, which can protect the reliability of the light-emitting module and improve the contrast of the light emitted by the light-emitting module.

[0040] The packaging layer 6 can be a white adhesive layer, which can improve the reflection effect of the light emitted by the light-emitting module and improve the light efficiency of the light-emitting module.

[0041] The chip array 3 is provided with a plurality of P electrodes 32 and a plurality of N electrodes 31. The plurality of P electrodes 32 and the plurality of N electrodes 31 are filled with a supporting adhesive 8, which can be a black underfill adhesive. Based on the black underfill adhesive, the phenomenon of light interference between the plurality of light-emitting chips in the chip array 3 is avoided, and the light efficiency of the chip array 3 is improved.

[0042] In one or more embodiments, the plurality of P electrodes 32 form a P electrode array, the plurality of N electrodes 31 are arranged outside the P electrode array, and the P electrode array and the plurality of N electrodes 31 are arranged in a common N electrode connection structure, thereby simplifying the electrical connection structure of the light-emitting module.

[0043] The material of the dam 4 can be silica gel, that is, the dam 4 is a transparent silica gel layer, which covers and protects the chip array 3 and the light conversion layer 5, so as to avoid damage to the chip array 3 and the light conversion layer 5.

[0044] In one or more embodiments, the dam layer 4 is arranged above the periphery of the chip array 3, and the P electrode array is located in the enclosed area of the dam layer 4, so as to avoid the dam layer 4 affecting the light efficiency of the chip array 3.

[0045] In one or more embodiments, the material of the dam 4 can also be resin, which has good plastic sealing and curing performance.

[0046] In one or more embodiments, the height of the dam 4 is h1, the height of the light conversion layer 5 is h2, and the constraint relationship between h1 and h2 is h1≥h2, so that the dam 4 can completely cover the sidewall of the chip array 3 and the light conversion layer 5, avoiding direct contact of the light conversion layer 5 and the chip array 3 with the packaging layer 6, avoiding the black packaging layer 6 absorbing heat, and causing the light conversion layer 5 to be damaged by heat.

[0047] In one or more embodiments, the height of the dam 4 can be higher than that of the light conversion layer 5, and the dam 4 can cover the top edge area of the light conversion layer 5, so that the dam 4 can protect the light conversion layer 5, reduce the risk of damage to the light conversion layer 5, and improve the light efficiency of the chip array 3.

[0048] In one or more embodiments, the light conversion layer 5 includes at least one of fluorescent powder, quantum dots, and organic dye.

[0049] For example, in the present embodiment, the light conversion layer 5 is provided with fluorescent powder, which converts the light color of the chip array 3, and the fluorescent powder is Yttrium Aluminum Garnet (YAG) yellow light fluorescent powder or nitride yellow light fluorescent powder. In the present embodiment, the fluorescent powder is Y3Al5O12:Ce, which is used to convert the blue light of the chip array 3 into white light. 12 :Ce 3+

[0050] In one or more embodiments, the substrate 2 is a silicon-based circuit board, which is provided with a driving circuit, and a plurality of light emitting chips of the chip array 3 are electrically connected to the driving circuit. Based on the driving circuit, any light emitting chip in the chip array 3 can be independently driven to realize the lighting control of the chip array 3. The driving circuit includes a connection electrode 21. ​

[0051] In one or more embodiments, the light-emitting module further comprises a transition carrier plate 1, the substrate 2 is arranged on the transition carrier plate 1, and the substrate 2 is electrically connected to an external circuit board 9 based on the transition carrier plate 1, that is, the transition carrier plate 1 is arranged to connect the substrate 2 and the external circuit board. The material of the transition carrier plate 1 can be ceramic, the thermal expansion coefficient of the transition carrier plate 1 is between the thermal expansion coefficient of the substrate 2 and the thermal expansion coefficient of the external circuit board. The transition carrier plate 1 is arranged between the substrate 2 and the external circuit board, so that the thermal expansion coefficients between the external circuit board, the transition carrier plate 1 and the substrate 2 are matched, avoiding direct contact of the substrate 2 with the external circuit board, thereby avoiding the case that the substrate 2 and the external circuit board are cracked due to thermal expansion, and improving the structural stability of the light-emitting module.

[0052] In the embodiment, the material of the transition carrier plate 1 is aluminum nitride (AlN) ceramic material, which has good heat conduction performance and electrical insulation, can meet the installation requirements of the light-emitting module, and improve the heat dissipation efficiency of the light-emitting module.

[0053] In one or more embodiments, the transition carrier plate 1 is provided with a metal electrode 11, the substrate 2 is provided with a connecting electrode 21, and the metal electrode 11 of the transition carrier plate 1 is electrically connected to the connecting electrode 21 of the substrate 2 based on a solder wire 100, that is, the substrate 2 and the transition carrier plate 1 are connected by wire bonding based on the solder wire 100. The bottom of the transition carrier plate 1 is provided with a pin pad, which is correspondingly arranged with the metal electrode 11, and the transition carrier plate 1 can be electrically connected to an external circuit board based on the pin pad.

[0054] In one or more embodiments, the solder wire 100 wire bonding mode of the substrate 2 is converted to the pin pad soldering mode based on the transition carrier plate 1, improving the convenience of integrated packaging of the light-emitting module and the external circuit board.

[0055] In one or more embodiments, the metal electrode 11, the connecting electrode 21 and the solder wire 100 are contained in the packaging layer 6, and the packaging layer 6 can shield and protect the metal electrode 11, the connecting electrode 21 and the solder wire 100, ensuring the reliability of the electrical connection structure between the substrate 2 and the transition carrier plate 1.

[0056] Figure 2 shows a cross-sectional view of a chip array structure according to an embodiment of the present application, and Figure 3 shows a schematic view of a current guide layer structure according to an embodiment of the present application; Figure 4 shows a schematic view of another structure state of a current guide layer according to an embodiment of the present application; the chip array 3 comprises a chip main structure 33, and the chip main structure 33 is formed with the plurality of P electrodes 32 and the plurality of N electrodes 31; the chip main structure 33 comprises, in sequence, a buffer layer 331, an N-type semiconductor layer 332, a quantum well layer 333, a P-type semiconductor layer 334, and an electrode transition layer 335.

[0057] In one or more embodiments, the electrode transition layer 335 can be a single-layer structure or a multi-layer structure, and the multi-layer structure comprises one or more layers of indium tin oxide (ITO) or other conductive oxides, a silver metal layer, to meet the light emission requirements of the light-emitting module.

[0058] In one or more embodiments, the chip main structure 33 is provided with a plurality of line grooves 336, and the chip main structure 33 is formed with a plurality of bosses arranged in an array based on the line grooves 336; the array structure of the plurality of bosses comprises a plurality of N-pole bosses 337 and a plurality of P-pole bosses 338; the P electrodes 32 are formed on the P-pole bosses 338, and the plurality of P electrodes 32 form a P electrode array; the N electrodes 31 are formed on the N-pole bosses 337, and the plurality of N electrodes 31 are arranged at the outer edges of the P electrode array.

[0059] In one or more embodiments, the plurality of P electrodes 32 in the P electrode array are independently distributed, and the plurality of N electrodes 31 are connected in series; any P electrode 32 and the N electrode 31 are connected to form a light-emitting chip, and the chip array 3 is formed with a plurality of light-emitting chips with a common N-pole design; based on the common N-pole design, the electrical connection structure of the chip array 3 can be simplified, and the convenience of electrical connection of the chip array 3 can be improved.

[0060] In one or more embodiments, the chip array further comprises a current guide layer 35, and the current guide layer 35 is arranged in at least one of the plurality of line grooves 336.

[0061] In one or more embodiments, the plurality of N electrodes 31 are arranged on the side edges of at least one side of the P electrode array, i.e., the plurality of N electrodes 31 can be arranged on one or more of the upper side edges, lower side edges, left side edges, and right side edges of the P electrode array; based on the current guide layer 35, the convenience of electrical connection between the P electrodes 32 and the N electrodes 31 can be improved, so that the chip array 3 is arranged in a common N-pole array.

[0062] The arrangement structure of the plurality of N electrodes 31 can be annular arrangement, that is, the plurality of N electrodes 31 are arranged on four sides of the P electrode array to form an annular arrangement structure, so that the current between the P electrodes 32 distributed on the periphery in the P electrode array and the plurality of N electrodes 31 is uniformly distributed, and based on the annular arrangement structure of the plurality of N electrodes 31, the current guiding layer 35 can realize uniform distribution of the current of the plurality of P electrodes 32 in the P electrode array.

[0063] In one or more embodiments, the current guiding layer 35 can be a metal conductive material, such as one or more of gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), and iron (Fe), or the current guiding layer 35 can be an alloy.

[0064] In one or more embodiments, the shape of the current guiding layer 35 can be longitudinal strip, transverse strip, ring, grid, etc.

[0065] In one or more embodiments, the current guiding layer 35 can be a metal grid, and based on the metal grid, the uniformity of current transmission between the plurality of P electrodes and the plurality of N electrodes can be improved.

[0066] In one or more embodiments, when the chip array 3 is prepared, the chip array 3 can be prepared on a substrate 7, the substrate 7 is arranged to support the chip array 3, and the buffer layer 331 is arranged to grow the N-type semiconductor layer 332, so as to avoid the N-type semiconductor layer 332 being directly grown on the substrate 7, thereby reducing the growth defect density of the N-type semiconductor layer 332.

[0067] In one or more embodiments, the substrate 7 can be a sapphire substrate, a silicon substrate, a silicon carbide substrate, etc., which meets the preparation requirements of the chip array 3.

[0068] In one or more embodiments, after the chip array 3 and the substrate 2 are connected by a bonding process, the substrate 7 and the chip array 3 can be separated by a laser stripping method, or the substrate 7 can be stripped by the chemical etching method.

[0069] In one or more embodiments, the stripping method of the substrate 7 can be chemical etching, which can avoid the impact damage of gas generated during laser stripping on the chip array 3.

[0070] In one or more embodiments, the N electrode 31 comprises the N pole boss 337, a first electrode layer 312 disposed on the top surface of the N pole boss 337, and an N pole solder joint 311 disposed on the first electrode layer 312, one side of the first electrode layer 312 extends along the sidewall of the N pole boss 337 to the bottom of the wire slot 336, so that the first electrode layer 312 is connected with the N-type semiconductor layer 332 of the chip body structure 33, thereby realizing the electrical connection between the P electrode 32 and the N electrode 31.

[0071] In one or more embodiments, the N electrode 31 is provided with a first insulating layer 313, the first insulating layer 313 covers the sidewall of the N pole boss 337 and the surface of the first electrode layer 312, a first matching groove is formed on the top surface of the first electrode layer 312, and the N pole solder joint 311 is disposed in the first matching groove.

[0072] In one or more embodiments, the P electrode 32 comprises the P pole boss 338, a second electrode layer 322 disposed on the P pole boss 338, a P pole solder joint 321 disposed on the second electrode layer 322, and a second insulating layer 323 covering the sidewall of the P pole boss 338 and the surface of the second electrode layer 322, a second matching groove is formed on the top of the second electrode layer 322 based on the second insulating layer 323, and the P pole solder joint 321 is disposed in the second matching groove.

[0073] In one or more embodiments, the N pole solder joint 311 and the P pole solder joint 321 are both gold-tin alloy solder joints (Au-Sn solder joints), and the N pole solder joint 311 and the P pole solder joint 321 are arranged to realize the electrical connection between the chip array 3 and the working circuit board, and based on the common N pole structure design, the electrical circuit integration of the driving circuit can be simplified.

[0074] In one or more embodiments, the driving circuit is provided with a plurality of conduction points, the plurality of conduction points are arranged one-to-one corresponding to a plurality of N electrodes 31 and a plurality of P electrodes 32 of the chip array 3, and the plurality of N pole solder joints 311 and the plurality of P pole solder joints 321 are electrically connected one-to-one corresponding to the plurality of conduction points, thereby realizing the electrical connection between the plurality of N pole solder joints 311 and the plurality of P pole solder joints 321 and the substrate 2.

[0075] The P electrode array and the plurality of N electrodes 31 are provided with a transition column 37, and the transition column 37 is provided with a plurality of transition electrodes 34.

[0076] The top surfaces of the P electrode 32, the N electrode 31 and the transition electrode 34 are in the same horizontal plane.

[0077] In one or more embodiments, the several conductive points on the substrate 2 are arranged to avoid the position of the transition electrode 34, so that the transition electrode 34 is in a non-conductive state, avoiding the short circuit between the P electrode 32 and the N electrode 31.

[0078] In one or more embodiments, the substrate 2 is provided with several connection bumps, and the several N electrodes 31, the several P electrodes 32 and the several transition electrodes 34 are connected to the several connection bumps one by one. Based on the connection bumps, the structural height between the several N electrodes 31, the several P electrodes 32 and the several transition electrodes 34 can be ensured to be consistent, thereby ensuring the structural stability of the light-emitting module.

[0079] In one or more embodiments, the several connection bumps are metal connection bumps, so that the electrodes of the chip structure are electrically connected to the connection bumps. The connection bumps corresponding to the positions of the several N electrodes 31 and the several P electrodes 32 on the substrate 2 are electrically connected to the internal driving circuit, forming the several conductive points, so that the several N electrodes 31 and the several P electrodes 32 of the chip array 3 are connected to the driving circuit of the substrate 2. The connection bumps corresponding to the positions of the several transition electrodes 34 on the substrate 2 are arranged in the insulating area of the substrate 2, so that the several transition electrodes 34 are in a non-conductive state, thereby ensuring that the several N electrodes 31 and the P electrode array have sufficient electrical insulation distance, avoiding the short circuit between the N electrode 31 and the P electrode 32.

[0080] FIG. 5 shows a schematic diagram of the connection structure of the chip array and the substrate in the embodiment of the present application; FIG. 6 shows a structural top view of the chip array in the embodiment of the present application, FIG. 7 shows another structural top view of the chip array in the embodiment of the present application, and FIG. 8 shows still another structural top view of the chip array in the embodiment of the present application. The P electrode array and the several N electrodes 31 are provided with a transition column 37, and the transition column 37 is provided with several transition electrodes 34. The transition column 37 is arranged to separate the P electrode array and the several N electrodes 31, so that the N electrode 31 and the P electrode 32 have sufficient electrical protection distance, avoiding the short circuit between the N electrode 31 and the P electrode 32 during the use of the chip array 3.

[0081] In one or more embodiments, the electrode structure of the transition electrode 34 is the same as that of the N electrode 31, and the top surfaces of the P electrode 32, the N electrode 31, and the transition electrode 34 are located on the same horizontal plane, thereby improving the structural stability of the light-emitting module.

[0082] In one or more embodiments, the structure of the transition column 37 is designed such that the sizes of the plurality of line grooves 336 on the chip array 3 are the same, and when the black underfill is applied, the uniformity of the flow of the black underfill in the line grooves 336 can be ensured, so that the black underfill can be uniformly laid between the plurality of N electrodes 31 and the plurality of P electrodes 32 of the chip array 3, avoiding the problems of underfilling and uneven distribution of the black underfill, thereby improving the light-emitting reliability of the chip array 3.

[0083] In one or more embodiments, the depth of any of the line grooves 336 extends to the N-type semiconductor layer 332, and the first electrode layer 312 of the N electrode 31 extends to the N-type semiconductor layer 332, so that after subsequent energization, any of the P electrodes 32 can be connected to the N-type semiconductor layer 332 and the first electrode layer 312 of the N electrode 31, thereby causing the quantum well layer 333 (light-emitting layer) to emit light. Any of the P electrodes 32 is connected to the N-type semiconductor layer 332 and the first electrode layer 312 of the N electrode 31 to form a light-emitting chip structure.

[0084] In one or more embodiments, the line groove 336 is provided with a current guiding layer 35, and a recess is formed in the N-type semiconductor layer 332 at a position corresponding to the plurality of line grooves 336. The current guiding layer 35 is fitted in the recess, and the recess can improve the convenience and accuracy of installation and positioning of the current guiding layer 35.

[0085] In one or more embodiments, the current guiding layer 35 is partially embedded in the N-type semiconductor layer 332, so that the current guiding layer 35 can block light in the N-type semiconductor layer 332, i.e., reduce the risk of cross-light between multiple light-emitting chips in the chip array 3.

[0086] In one or more embodiments, the thickness of the current guiding layer 35 is greater than the depth of the recess, so that part of the current guiding layer 35 is exposed on the N-type semiconductor layer 332, and when the first electrode layer 312 of the N electrode 31 extends to the N-type semiconductor layer 332, it can be connected to the current guiding layer 35, and the current guiding layer 35 can limit the first electrode layer 312, thereby improving the convenience of setting the first electrode layer 312.

[0087] In one or more embodiments, the current guide layer 35 can realize the interconnection path between the N electrode 31 and the P electrode 32, and the current guide layer 35 improves the conductivity of the N-type semiconductor layer 332, thereby improving the current uniformity between the N electrode 31 and the P electrode 32.

[0088] In one or more embodiments, the surface of the current guide layer 35 is covered with a third insulating layer 36, and the third insulating layer 36 is arranged to protect the current guide layer 35 and avoid short circuit between multiple light-emitting chips in the chip array 3.

[0089] The embodiment of the present application provides a light-emitting module, which realizes double-layer packaging of the chip array 3 and the light conversion layer 5 based on the dam 4 and the packaging layer 6 formed by a transparent adhesive layer, improves the light efficiency of the chip array 3, and simplifies the structural design of the vehicle lamp based on the double-layer packaging and the structural cooperation of the chip array 3. By filling the support adhesive 8 between the plurality of P electrodes 32 and the plurality of N electrodes 31 of the chip array 3, the light-emitting module improves the light-emitting contrast of the chip array 3, thereby improving the light-emitting efficiency of the light-emitting module.

Claims

1. A light emitting module, the light emitting module comprising: A substrate, a chip array arranged on the substrate, a dam arranged around the chip array, a light conversion layer arranged above the chip array, and a packaging layer arranged around the dam; The chip array is provided with at least one P electrode and at least one N electrode, and the at least one P electrode and the at least one N electrode are filled with support glue.

2. The light emitting module of claim 1, wherein, The dam is a transparent glue layer, the packaging layer is a black glue layer, or the packaging layer is a white glue layer.

3. The light emitting module of claim 1, wherein, The height of the dam is h1, the height of the light conversion layer is h2, and the constraint relationship between h1 and h2 is h1≥h2.

4. The light emitting module of claim 1, wherein, The substrate is a silicon-based circuit board, the silicon-based circuit board is provided with a driving circuit, and at least one light-emitting chip of the chip array is electrically connected with the driving circuit.

5. The light emitting module of claim 1, wherein, The light-emitting module further comprises a transition carrier plate, the substrate is arranged on the transition carrier plate, and the substrate is electrically connected to an external circuit board based on the transition carrier plate.

6. The light emitting module of claim 5, wherein, The coefficient of thermal expansion of the transition carrier plate is between the coefficient of thermal expansion of the substrate and the coefficient of thermal expansion of the external circuit board.

7. The light emitting module of claim 6, wherein, The transition carrier plate is provided with a metal electrode, the substrate is provided with a connecting electrode, and the metal electrode of the transition carrier plate and the connecting electrode on the substrate are electrically connected based on a solder wire.

8. The light emitting module of claim 7, wherein, The metal electrode, the connecting electrode and the solder wire are contained in the packaging layer.

9. The light emitting module of claim 1, wherein, The chip array comprises a chip main structure, and the chip main structure comprises: a buffer layer, an N-type semiconductor layer, a quantum well layer, a P-type semiconductor layer and an electrode transition layer which are sequentially stacked; The chip main structure is formed with the at least one P electrode and the at least one N electrode.

10. The light emitting module of claim 9, wherein, At least one ridge is formed on the chip main structure based on the wire slot. The array structure of the at least one ridge comprises at least one N-pole ridge and at least one P-pole ridge, the P electrode is formed on the P-pole ridge, the at least one P electrode forms a P electrode array, the N electrode is formed on the N-pole ridge, and the at least one N electrode is arranged at the outer edge of the P electrode array.

11. The light emitting module of claim 10, wherein, The P electrode array and the at least one N electrode are provided with a transition column, and the transition column is provided with at least one transition electrode.

12. The light emitting module of claim 11, wherein, The top surfaces of the P electrode, the N electrode and the transition electrode are in the same horizontal plane.

13. The light emitting module of claim 10, wherein, The N electrode comprises a first electrode layer arranged on the N-pole ridge and an N-pole soldering point arranged on the first electrode layer, and one side of the first electrode layer extends to the bottom of the wire slot along the side wall of the N-pole ridge. The P electrode comprises a second electrode layer arranged on the P-pole ridge and a P-pole soldering point arranged on the second electrode layer.

14. The light emitting module of claim 13, wherein, The slotting depth of any wire slot extends to the N-type semiconductor layer. The first electrode layer of the N electrode extends to the N-type semiconductor layer.

15. The light emitting module of claim 10, wherein, The P electrode array and the at least one N electrode are provided with a transition column, and the transition column is provided with at least one transition electrode, and the transition column is arranged to separate the P electrode array and the at least one N electrode.

16. The light emitting module of claim 10, wherein, The chip array also includes a current steering layer disposed within at least one of the at least one wire slot.

Images